From ef380a4a6a2ff4c90bde90c41296e94f5db70389 Mon Sep 17 00:00:00 2001
From: Sunil Shetye
Date: Mon, 11 Mar 2019 15:57:40 +0530
Subject: Half adder subcircuit filename conflict in Windows

Replaced Half_Adder example with renamed HalfAdder to avoid Windows
case-only filename difference conflict with subcircuit half_adder.

Based on contribution by https://github.com/MaxOLydian/eSim
---
 Examples/HalfAdder/half_adder.cir | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 Examples/HalfAdder/half_adder.cir

(limited to 'Examples/HalfAdder/half_adder.cir')

diff --git a/Examples/HalfAdder/half_adder.cir b/Examples/HalfAdder/half_adder.cir
new file mode 100644
index 00000000..8b2e7e06
--- /dev/null
+++ b/Examples/HalfAdder/half_adder.cir
@@ -0,0 +1,11 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U2  1 4 3 d_xor		
+U3  1 4 2 d_and		
+U1  1 4 3 2 PORT		
+
+.end
-- 
cgit