From ef380a4a6a2ff4c90bde90c41296e94f5db70389 Mon Sep 17 00:00:00 2001
From: Sunil Shetye
Date: Mon, 11 Mar 2019 15:57:40 +0530
Subject: Half adder subcircuit filename conflict in Windows

Replaced Half_Adder example with renamed HalfAdder to avoid Windows
case-only filename difference conflict with subcircuit half_adder.

Based on contribution by https://github.com/MaxOLydian/eSim
---
 Examples/HalfAdder/HalfAdder.cir | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Examples/HalfAdder/HalfAdder.cir

(limited to 'Examples/HalfAdder/HalfAdder.cir')

diff --git a/Examples/HalfAdder/HalfAdder.cir b/Examples/HalfAdder/HalfAdder.cir
new file mode 100644
index 00000000..51b78f4e
--- /dev/null
+++ b/Examples/HalfAdder/HalfAdder.cir
@@ -0,0 +1,21 @@
+* /home/fossee/UpdatedExamples/HalfAdder/HalfAdder.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar  3 21:35:33 2016
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad1_ Net-_U2-Pad2_ half_adder		
+U1  IN1 IN2 Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2		
+U2  Net-_U2-Pad1_ Net-_U2-Pad2_ sum cout dac_bridge_2		
+v1  IN1 GND DC		
+v2  IN2 GND DC		
+R1  sum GND 1k		
+R2  cout GND 1k		
+U3  IN1 plot_v1		
+U4  IN2 plot_v1		
+U5  sum plot_v1		
+U6  cout plot_v1		
+
+.end
-- 
cgit