From d25a2bf2d63442e3585479751f168b635fc5701e Mon Sep 17 00:00:00 2001
From: fossee
Date: Thu, 29 Aug 2019 12:00:06 +0530
Subject: changed Examples

---
 .../FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir

(limited to 'Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir')

diff --git a/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir b/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir
new file mode 100644
index 00000000..4d6657ca
--- /dev/null
+++ b/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir
@@ -0,0 +1,21 @@
+* /home/fossee/UpdatedExamples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar  3 21:30:23 2016
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+x1  GND pulse out2 SCR		
+v1  in1 in2 sine		
+v2  pulse GND pulse		
+D1  in1 out1 D		
+D3  in2 out1 D		
+D2  GND in1 D		
+D4  GND in2 D		
+R1  out1 out2 100		
+U1  in1 in2 plot_v2		
+U3  pulse plot_v1		
+U2  out1 out2 plot_v2		
+
+.end
-- 
cgit