From 5e116a4676854289fabeb6cce57f3d01ae8f5709 Mon Sep 17 00:00:00 2001 From: Sunil Shetye Date: Mon, 11 Mar 2019 12:11:24 +0530 Subject: remove temporary files --- Examples/FullAdder/FullAdder-cache.lib | 116 -------- Examples/FullAdder/FullAdder.bak | 328 ---------------------- Examples/FullAdder/full_adder-cache.lib | 61 ---- Examples/FullAdder/full_adder_Previous_Values.xml | 1 - Examples/FullAdder/half_adder-cache.lib | 63 ----- Examples/FullAdder/half_adder_Previous_Values.xml | 1 - 6 files changed, 570 deletions(-) delete mode 100644 Examples/FullAdder/FullAdder-cache.lib delete mode 100644 Examples/FullAdder/FullAdder.bak delete mode 100644 Examples/FullAdder/full_adder-cache.lib delete mode 100644 Examples/FullAdder/full_adder_Previous_Values.xml delete mode 100644 Examples/FullAdder/half_adder-cache.lib delete mode 100644 Examples/FullAdder/half_adder_Previous_Values.xml (limited to 'Examples/FullAdder') diff --git a/Examples/FullAdder/FullAdder-cache.lib b/Examples/FullAdder/FullAdder-cache.lib deleted file mode 100644 index 5669fdaf..00000000 --- a/Examples/FullAdder/FullAdder-cache.lib +++ /dev/null @@ -1,116 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# DC -# -DEF DC v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "DC" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -250 50 H I C CNN -F1 "GND" 0 -150 50 H V C CNN -F2 "" 0 0 50 H V C CNN -F3 "" 0 0 50 H V C CNN -DRAW -P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N -X GND 1 0 0 0 D 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 50 130 50 H V C CNN -F1 "R" 50 50 50 H V C CNN -F2 "" 50 -20 30 H V C CNN -F3 "" 50 50 30 V V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S 150 10 -50 90 0 1 10 N -X ~ 1 -100 50 50 R 60 60 1 1 P -X ~ 2 200 50 50 L 60 60 1 1 P -ENDDRAW -ENDDEF -# -# adc_bridge_3 -# -DEF adc_bridge_3 U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "adc_bridge_3" 0 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -400 200 350 -200 0 1 0 N -X IN1 1 -600 50 200 R 50 50 1 1 I -X IN2 2 -600 -50 200 R 50 50 1 1 I -X IN3 3 -600 -150 200 R 50 50 1 1 I -X OUT1 4 550 50 200 L 50 50 1 1 O -X OUT2 5 550 -50 200 L 50 50 1 1 O -X OUT3 6 550 -150 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# dac_bridge_2 -# -DEF dac_bridge_2 U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "dac_bridge_2" 50 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -250 200 350 -100 0 1 0 N -X IN1 1 -450 50 200 R 50 50 1 1 I -X IN2 2 -450 -50 200 R 50 50 1 1 I -X OUT1 3 550 50 200 L 50 50 1 1 O -X OUT4 4 550 -50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# full_adder -# -DEF full_adder X 0 40 Y Y 1 F N -F0 "X" 1400 700 60 H V C CNN -F1 "full_adder" 1400 600 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S 800 1150 1950 0 0 1 0 N -X IN1 1 600 950 200 R 50 50 1 1 I -X IN2 2 600 550 200 R 50 50 1 1 I -X CIN 3 600 150 200 R 50 50 1 1 I -X SUM 4 2150 950 200 L 50 50 1 1 O -X COUT 5 2150 150 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# plot_v1 -# -DEF plot_v1 U 0 40 Y Y 1 F N -F0 "U" 0 500 60 H V C CNN -F1 "plot_v1" 200 350 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -C 0 500 100 0 1 0 N -X ~ ~ 0 200 200 U 50 50 1 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/Examples/FullAdder/FullAdder.bak b/Examples/FullAdder/FullAdder.bak deleted file mode 100644 index fb0b6864..00000000 --- a/Examples/FullAdder/FullAdder.bak +++ /dev/null @@ -1,328 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L full_adder X1 -U 1 1 56D58C2E -P 4350 4050 -F 0 "X1" H 5750 4750 60 0000 C CNN -F 1 "full_adder" H 5750 4650 60 0000 C CNN -F 2 "" H 4350 4050 60 0000 C CNN -F 3 "" H 4350 4050 60 0000 C CNN - 1 4350 4050 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 56D58CB2 -P 1300 3550 -F 0 "v1" H 1100 3650 60 0000 C CNN -F 1 "DC" H 1100 3500 60 0000 C CNN -F 2 "R1" H 1000 3550 60 0000 C CNN -F 3 "" H 1300 3550 60 0000 C CNN - 1 1300 3550 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 56D58D3D -P 1950 3950 -F 0 "v2" H 1750 4050 60 0000 C CNN -F 1 "DC" H 1750 3900 60 0000 C CNN -F 2 "R1" H 1650 3950 60 0000 C CNN -F 3 "" H 1950 3950 60 0000 C CNN - 1 1950 3950 - 1 0 0 -1 -$EndComp -$Comp -L DC v3 -U 1 1 56D58D84 -P 2700 4350 -F 0 "v3" H 2500 4450 60 0000 C CNN -F 1 "DC" H 2500 4300 60 0000 C CNN -F 2 "R1" H 2400 4350 60 0000 C CNN -F 3 "" H 2700 4350 60 0000 C CNN - 1 2700 4350 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 56D58F73 -P 8200 3200 -F 0 "R1" H 8250 3330 50 0000 C CNN -F 1 "1k" H 8250 3250 50 0000 C CNN -F 2 "" H 8250 3180 30 0000 C CNN -F 3 "" V 8250 3250 30 0000 C CNN - 1 8200 3200 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 56D58FBB -P 8200 4000 -F 0 "R2" H 8250 4130 50 0000 C CNN -F 1 "1k" H 8250 4050 50 0000 C CNN -F 2 "" H 8250 3980 30 0000 C CNN -F 3 "" V 8250 4050 30 0000 C CNN - 1 8200 4000 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR01 -U 1 1 56D59061 -P 8400 3150 -F 0 "#PWR01" H 8400 2900 50 0001 C CNN -F 1 "GND" H 8400 3000 50 0000 C CNN -F 2 "" H 8400 3150 50 0000 C CNN -F 3 "" H 8400 3150 50 0000 C CNN - 1 8400 3150 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 -U 1 1 56D590A3 -P 8400 3950 -F 0 "#PWR02" H 8400 3700 50 0001 C CNN -F 1 "GND" H 8400 3800 50 0000 C CNN -F 2 "" H 8400 3950 50 0000 C CNN -F 3 "" H 8400 3950 50 0000 C CNN - 1 8400 3950 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 56D590F0 -P 2700 4800 -F 0 "#PWR03" H 2700 4550 50 0001 C CNN -F 1 "GND" H 2700 4650 50 0000 C CNN -F 2 "" H 2700 4800 50 0000 C CNN -F 3 "" H 2700 4800 50 0000 C CNN - 1 2700 4800 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR04 -U 1 1 56D59137 -P 1950 4450 -F 0 "#PWR04" H 1950 4200 50 0001 C CNN -F 1 "GND" H 1950 4300 50 0000 C CNN -F 2 "" H 1950 4450 50 0000 C CNN -F 3 "" H 1950 4450 50 0000 C CNN - 1 1950 4450 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR05 -U 1 1 56D59154 -P 1300 4000 -F 0 "#PWR05" H 1300 3750 50 0001 C CNN -F 1 "GND" H 1300 3850 50 0000 C CNN -F 2 "" H 1300 4000 50 0000 C CNN -F 3 "" H 1300 4000 50 0000 C CNN - 1 1300 4000 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1300 3100 3300 3100 -Wire Wire Line - 1950 3500 3300 3500 -Wire Wire Line - 2700 3900 3300 3900 -$Comp -L plot_v1 U2 -U 1 1 56D59201 -P 2800 3250 -F 0 "U2" H 2800 3750 60 0000 C CNN -F 1 "plot_v1" H 3000 3600 60 0000 C CNN -F 2 "" H 2800 3250 60 0000 C CNN -F 3 "" H 2800 3250 60 0000 C CNN - 1 2800 3250 - 1 0 0 -1 -$EndComp -$Comp -L plot_v1 U1 -U 1 1 56D59261 -P 2700 3700 -F 0 "U1" H 2700 4200 60 0000 C CNN -F 1 "plot_v1" H 2900 4050 60 0000 C CNN -F 2 "" H 2700 3700 60 0000 C CNN -F 3 "" H 2700 3700 60 0000 C CNN - 1 2700 3700 - 1 0 0 -1 -$EndComp -$Comp -L plot_v1 U3 -U 1 1 56D592AF -P 3050 4100 -F 0 "U3" H 3050 4600 60 0000 C CNN -F 1 "plot_v1" H 3250 4450 60 0000 C CNN -F 2 "" H 3050 4100 60 0000 C CNN -F 3 "" H 3050 4100 60 0000 C CNN - 1 3050 4100 - 1 0 0 -1 -$EndComp -Wire Wire Line - 2800 3050 2800 3100 -Connection ~ 2800 3100 -Connection ~ 2700 3500 -Connection ~ 3050 3900 -Wire Wire Line - 7850 3150 8100 3150 -Wire Wire Line - 7850 3950 8100 3950 -$Comp -L plot_v1 U4 -U 1 1 56D59437 -P 7900 3300 -F 0 "U4" H 7900 3800 60 0000 C CNN -F 1 "plot_v1" H 8100 3650 60 0000 C CNN -F 2 "" H 7900 3300 60 0000 C CNN -F 3 "" H 7900 3300 60 0000 C CNN - 1 7900 3300 - 1 0 0 -1 -$EndComp -$Comp -L plot_v1 U5 -U 1 1 56D59491 -P 7950 4100 -F 0 "U5" H 7950 4600 60 0000 C CNN -F 1 "plot_v1" H 8150 4450 60 0000 C CNN -F 2 "" H 7950 4100 60 0000 C CNN -F 3 "" H 7950 4100 60 0000 C CNN - 1 7950 4100 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7950 3900 7950 3950 -Connection ~ 7950 3950 -Text GLabel 1900 3050 1 60 Input ~ 0 -in1 -Text GLabel 2150 3450 1 60 Input ~ 0 -in2 -Text GLabel 2850 3850 1 60 Input ~ 0 -cin -Text GLabel 8050 3200 3 60 Input ~ 0 -sum -Text GLabel 8050 4050 3 60 Input ~ 0 -cout -Wire Wire Line - 8050 3200 8050 3150 -Connection ~ 8050 3150 -Wire Wire Line - 8050 4050 8050 3950 -Connection ~ 8050 3950 -Wire Wire Line - 2850 3850 2850 3900 -Connection ~ 2850 3900 -Wire Wire Line - 2150 3450 2150 3500 -Connection ~ 2150 3500 -Wire Wire Line - 1900 3050 1900 3100 -Connection ~ 1900 3100 -$Comp -L adc_bridge_3 U6 -U 1 1 56D59BD2 -P 3900 3450 -F 0 "U6" H 3900 3450 60 0000 C CNN -F 1 "adc_bridge_3" H 3900 3600 60 0000 C CNN -F 2 "" H 3900 3450 60 0000 C CNN -F 3 "" H 3900 3450 60 0000 C CNN - 1 3900 3450 - 1 0 0 -1 -$EndComp -$Comp -L dac_bridge_2 U7 -U 1 1 56D5AD2F -P 7150 3450 -F 0 "U7" H 7150 3450 60 0000 C CNN -F 1 "dac_bridge_2" H 7200 3600 60 0000 C CNN -F 2 "" H 7150 3450 60 0000 C CNN -F 3 "" H 7150 3450 60 0000 C CNN - 1 7150 3450 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6500 3100 6700 3100 -Wire Wire Line - 6700 3100 6700 3400 -Wire Wire Line - 6500 3900 6700 3900 -Wire Wire Line - 6700 3900 6700 3500 -Wire Wire Line - 7700 3400 7850 3400 -Wire Wire Line - 7850 3400 7850 3150 -Wire Wire Line - 7900 3100 7900 3150 -Connection ~ 7900 3150 -Wire Wire Line - 7700 3500 7850 3500 -Wire Wire Line - 7850 3500 7850 3950 -Wire Wire Line - 3300 3900 3300 3600 -Wire Wire Line - 3300 3100 3300 3400 -Wire Wire Line - 4450 3500 4950 3500 -Wire Wire Line - 4450 3400 4450 3100 -Wire Wire Line - 4450 3100 4950 3100 -Wire Wire Line - 4450 3600 4450 3900 -Wire Wire Line - 4450 3900 4950 3900 -$EndSCHEMATC diff --git a/Examples/FullAdder/full_adder-cache.lib b/Examples/FullAdder/full_adder-cache.lib deleted file mode 100644 index 623a7f41..00000000 --- a/Examples/FullAdder/full_adder-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -ENDDRAW -ENDDEF -# -# d_or -# -DEF d_or U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_or" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# half_adder -# -DEF half_adder X 0 40 Y Y 1 F N -F0 "X" 900 500 60 H V C CNN -F1 "half_adder" 900 400 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S 500 800 1250 0 0 1 0 N -X IN1 1 300 700 200 R 50 50 1 1 I -X IN2 2 300 100 200 R 50 50 1 1 I -X SUM 3 1450 700 200 L 50 50 1 1 O -X COUT 4 1450 100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/Examples/FullAdder/full_adder_Previous_Values.xml b/Examples/FullAdder/full_adder_Previous_Values.xml deleted file mode 100644 index b63184d6..00000000 --- a/Examples/FullAdder/full_adder_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -truefalsefalseHzHzFalseVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_or \ No newline at end of file diff --git a/Examples/FullAdder/half_adder-cache.lib b/Examples/FullAdder/half_adder-cache.lib deleted file mode 100644 index 68785220..00000000 --- a/Examples/FullAdder/half_adder-cache.lib +++ /dev/null @@ -1,63 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_xor -# -DEF d_xor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_xor" 50 100 47 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 150 -50 -200 -50 N -P 2 0 1 0 150 150 -200 150 N -X IN1 1 -450 100 215 R 50 43 1 1 I -X IN2 2 -450 0 215 R 50 43 1 1 I -X OUT 3 450 50 200 L 50 39 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/Examples/FullAdder/half_adder_Previous_Values.xml b/Examples/FullAdder/half_adder_Previous_Values.xml deleted file mode 100644 index b915f0da..00000000 --- a/Examples/FullAdder/half_adder_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -truefalsefalseHzHzFalseVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_xord_and \ No newline at end of file -- cgit From d2b775bde7bde4396c251ddac6685d503d0577d8 Mon Sep 17 00:00:00 2001 From: Sunil Shetye Date: Tue, 12 Mar 2019 14:34:31 +0530 Subject: update files from eSim-Examples --- Examples/FullAdder/full_adder.pro | 12 ++++++------ Examples/FullAdder/half_adder.pro | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) (limited to 'Examples/FullAdder') diff --git a/Examples/FullAdder/full_adder.pro b/Examples/FullAdder/full_adder.pro index c0db0775..0bd0d5af 100644 --- a/Examples/FullAdder/full_adder.pro +++ b/Examples/FullAdder/full_adder.pro @@ -61,9 +61,9 @@ LibName27=opto LibName28=atmel LibName29=contrib LibName30=valves -LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog -LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices -LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital -LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid -LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources -LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt +LibName31=eSim_Analog +LibName32=eSim_Devices +LibName33=eSim_Digital +LibName34=eSim_Hybrid +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/Examples/FullAdder/half_adder.pro b/Examples/FullAdder/half_adder.pro index 695ae0f6..30094fb9 100644 --- a/Examples/FullAdder/half_adder.pro +++ b/Examples/FullAdder/half_adder.pro @@ -61,9 +61,9 @@ LibName27=opto LibName28=atmel LibName29=contrib LibName30=valves -LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog -LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices -LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital -LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid -LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources -LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt +LibName31=eSim_Analog +LibName32=eSim_Devices +LibName33=eSim_Digital +LibName34=eSim_Hybrid +LibName35=eSim_Sources +LibName36=eSim_Subckt -- cgit