From d25a2bf2d63442e3585479751f168b635fc5701e Mon Sep 17 00:00:00 2001
From: fossee
Date: Thu, 29 Aug 2019 12:00:06 +0530
Subject: changed Examples

---
 .../Digitaldecoderusing5554017.cir                 | 47 ++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 Examples/Digitaldecoderusing5554017/Digitaldecoderusing5554017.cir

(limited to 'Examples/Digitaldecoderusing5554017/Digitaldecoderusing5554017.cir')

diff --git a/Examples/Digitaldecoderusing5554017/Digitaldecoderusing5554017.cir b/Examples/Digitaldecoderusing5554017/Digitaldecoderusing5554017.cir
new file mode 100644
index 00000000..f720b60a
--- /dev/null
+++ b/Examples/Digitaldecoderusing5554017/Digitaldecoderusing5554017.cir
@@ -0,0 +1,47 @@
+* C:\Users\HP\eSim-Workspace\as2\as2.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/19 11:52:44
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  GND C out1 Net-_R1-Pad2_ Net-_C1-Pad1_ C Net-_R1-Pad1_ Net-_R1-Pad2_ LM555N		
+C1  Net-_C1-Pad1_ GND 0.01u		
+R3  Net-_R1-Pad1_ C 100k		
+R1  Net-_R1-Pad1_ Net-_R1-Pad2_ 1k		
+v1  Net-_R1-Pad2_ GND DC		
+U2  C IC		
+C2  C GND 50n		
+R2  Net-_R2-Pad1_ out1 1k		
+U1  out1 plot_v1		
+U5  Net-_R2-Pad1_ Net-_U5-Pad2_ adc_bridge_1		
+U4  Net-_R1-Pad2_ Net-_U4-Pad2_ adc_bridge_1		
+U9  Net-_U4-Pad2_ Net-_U9-Pad2_ d_inverter		
+X2  Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U6-Pad3_ Net-_U6-Pad4_ Net-_U6-Pad5_ Net-_U7-Pad1_ Net-_U7-Pad2_ Net-_U7-Pad3_ Net-_U7-Pad4_ Net-_U7-Pad5_ Net-_U9-Pad2_ Net-_U5-Pad2_ bha_4017		
+U6  Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U6-Pad3_ Net-_U6-Pad4_ Net-_U6-Pad5_ O1 O2 O3 O4 O5 dac_bridge_5		
+U7  Net-_U7-Pad1_ Net-_U7-Pad2_ Net-_U7-Pad3_ Net-_U7-Pad4_ Net-_U7-Pad5_ O6 O7 O8 O9 O10 dac_bridge_5		
+U10  O1 plot_v1		
+U8  O2 plot_v1		
+U3  C plot_v1		
+U16  O3 plot_v1		
+U13  O4 plot_v1		
+U17  O5 plot_v1		
+U14  O6 plot_v1		
+U18  O7 plot_v1		
+U11  O8 plot_v1		
+U15  O9 plot_v1		
+U12  O10 plot_v1		
+D1  Net-_D1-Pad1_ O1 LED		
+R4  GND Net-_D1-Pad1_ 1k		
+D2  Net-_D1-Pad1_ O2 LED		
+D3  Net-_D1-Pad1_ O3 LED		
+D4  Net-_D1-Pad1_ O4 LED		
+D5  Net-_D1-Pad1_ O5 LED		
+D6  Net-_D1-Pad1_ O6 LED		
+D7  Net-_D1-Pad1_ O7 LED		
+D8  Net-_D1-Pad1_ O8 LED		
+D9  Net-_D1-Pad1_ O9 LED		
+D10  Net-_D1-Pad1_ O10 LED		
+
+.end
-- 
cgit