From cb55e59de7ee4383c04edfae7c39ad9ae9552b36 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 14 Feb 2020 15:16:35 +0530
Subject: common code for Win and Linux, merged py2 changes

---
 Examples/BJT_Biascircuit/BJT_Biascircuit.cir | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'Examples/BJT_Biascircuit/BJT_Biascircuit.cir')

diff --git a/Examples/BJT_Biascircuit/BJT_Biascircuit.cir b/Examples/BJT_Biascircuit/BJT_Biascircuit.cir
index 1d19ccd8..3fc9f2f5 100644
--- a/Examples/BJT_Biascircuit/BJT_Biascircuit.cir
+++ b/Examples/BJT_Biascircuit/BJT_Biascircuit.cir
@@ -1,16 +1,16 @@
-* /home/fossee/eSim-Workspace/BJT_Biascircuit/BJT_Biascircuit.cir
+* /home/saurabh/Installer_Main_Workshop/eSim-1.1.2/Examples/BJT_Biascircuit/BJT_Biascircuit.cir
 
-* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Feb 29 18:30:20 2016
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Aug 21 12:28:54 2019
 
 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
 * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
 
 * Sheet Name: /
-Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ GND NPN		
 v1  vce GND DC		
 R1  Net-_R1-Pad1_ Net-_Q1-Pad1_ 1k		
 R2  Net-_Q1-Pad2_ ib 1k		
 U1  vce Net-_R1-Pad1_ plot_i2		
 I1  ib GND dc		
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ GND eSim_NPN		
 
 .end
-- 
cgit