From 3aa3c9f7f6b7e30c89dc8a83515044bb74854064 Mon Sep 17 00:00:00 2001
From: saurabhb17
Date: Wed, 18 Mar 2020 18:27:02 +0530
Subject: fixes in Analysis of Digital ICs directory

---
 .../Analysis_Of_Digital_IC/4073_test/3_and.cir.out   | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out

(limited to 'Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out')

diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out
new file mode 100644
index 00000000..e3c96645
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
-- 
cgit