From dc61eab5251234f02c0377ea328b929340b3604c Mon Sep 17 00:00:00 2001
From: saurabhb17
Date: Wed, 11 Mar 2020 14:59:48 +0530
Subject: cleanup part2

---
 Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD

(limited to 'Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD')

diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD
new file mode 100644
index 00000000..b949ae4f
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
-- 
cgit