From d25a2bf2d63442e3585479751f168b635fc5701e Mon Sep 17 00:00:00 2001
From: fossee
Date: Thu, 29 Aug 2019 12:00:06 +0530
Subject: changed Examples

---
 .../Analysis_Of_Digital_IC/4012_test/4012.cir.out  | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out

(limited to 'Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out')

diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out
new file mode 100644
index 00000000..b34bbe45
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out
@@ -0,0 +1,44 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+
+* u8  net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9  net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3  net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
-- 
cgit