From 3aa3c9f7f6b7e30c89dc8a83515044bb74854064 Mon Sep 17 00:00:00 2001
From: saurabhb17
Date: Wed, 18 Mar 2020 18:27:02 +0530
Subject: fixes in Analysis of Digital ICs directory

---
 Examples/Analysis_Of_Digital_IC/4002_test/4002.pro |  88 +--
 .../4002_test/4002_test-cache.lib                  | 143 -----
 .../Analysis_Of_Digital_IC/4002_test/4002_test.pro |  49 +-
 .../Analysis_Of_Digital_IC/4002_test/4002_test.sch | 620 ---------------------
 Examples/Analysis_Of_Digital_IC/4002_test/analysis |   1 +
 .../Analysis_Of_Digital_IC/4002_test/analysis~HEAD |   1 -
 .../4002_test/analysis~fellowship2019-python3      |   1 -
 7 files changed, 46 insertions(+), 857 deletions(-)
 create mode 100644 Examples/Analysis_Of_Digital_IC/4002_test/analysis
 delete mode 100644 Examples/Analysis_Of_Digital_IC/4002_test/analysis~HEAD
 delete mode 100644 Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python3

(limited to 'Examples/Analysis_Of_Digital_IC/4002_test')

diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.pro b/Examples/Analysis_Of_Digital_IC/4002_test/4002.pro
index e7859256..31604370 100644
--- a/Examples/Analysis_Of_Digital_IC/4002_test/4002.pro
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.pro
@@ -1,44 +1,44 @@
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-LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
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-LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
-LibName11=power
+update=Wed Mar 18 18:16:38 2020
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+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
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+version=1
+NetIExt=net
+[eeschema]
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+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
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+LibName2=eSim_Devices
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+LibName5=eSim_Sources
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+LibName7=eSim_Plot
+LibName8=eSim_Miscellaneous
+LibName9=eSim_Hybrid
+LibName10=eSim_Digital
+LibName11=eSim_Analog
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib
index 13935dc6..d2bad06f 100644
--- a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib
@@ -1,145 +1,3 @@
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->>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro
index 9632c383..9de116f6 100644
--- a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro
@@ -1,50 +1,4 @@
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-=======
-update=Wed Mar 11 12:49:35 2020
+update=Wed Mar 18 18:17:16 2020
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 [general]
@@ -89,4 +43,3 @@ LibName9=eSim_Miscellaneous
 LibName10=eSim_Hybrid
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->>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch
index 963cc36a..75c866c5 100644
--- a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch
@@ -1,622 +1,3 @@
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-=======
 EESchema Schematic File Version 2
 LIBS:4002_test-rescue
 LIBS:power
@@ -1236,4 +617,3 @@ Wire Wire Line
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 $EndSCHEMATC
->>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/analysis b/Examples/Analysis_Of_Digital_IC/4002_test/analysis
new file mode 100644
index 00000000..660a46cc
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/analysis
@@ -0,0 +1 @@
+.tran 10e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/analysis~HEAD b/Examples/Analysis_Of_Digital_IC/4002_test/analysis~HEAD
deleted file mode 100644
index 660a46cc..00000000
--- a/Examples/Analysis_Of_Digital_IC/4002_test/analysis~HEAD
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python3
deleted file mode 100644
index 660a46cc..00000000
--- a/Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python3
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-03
\ No newline at end of file
-- 
cgit