From cb55e59de7ee4383c04edfae7c39ad9ae9552b36 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Fri, 14 Feb 2020 15:16:35 +0530 Subject: common code for Win and Linux, merged py2 changes --- Examples/3_Input_NOR_Characteristics/4025.cir.out | 36 ----------------------- 1 file changed, 36 deletions(-) delete mode 100644 Examples/3_Input_NOR_Characteristics/4025.cir.out (limited to 'Examples/3_Input_NOR_Characteristics/4025.cir.out') diff --git a/Examples/3_Input_NOR_Characteristics/4025.cir.out b/Examples/3_Input_NOR_Characteristics/4025.cir.out deleted file mode 100644 index b22d91a3..00000000 --- a/Examples/3_Input_NOR_Characteristics/4025.cir.out +++ /dev/null @@ -1,36 +0,0 @@ -* c:\users\bhargav\esim\src\subcircuitlibrary\4025\4025.cir - -* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or -* u6 net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad6_ d_nor -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port -* u4 net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_or -* u7 net-_u4-pad3_ net-_u1-pad13_ net-_u1-pad10_ d_nor -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or -* u5 net-_u2-pad3_ net-_u1-pad8_ net-_u1-pad9_ d_nor -a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 -a2 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad6_ u6 -a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4 -a4 [net-_u4-pad3_ net-_u1-pad13_ ] net-_u1-pad10_ u7 -a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a6 [net-_u2-pad3_ net-_u1-pad8_ ] net-_u1-pad9_ u5 -* Schematic Name: d_or, NgSpice Name: d_or -.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u5 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end -- cgit