From d9e7a8082c3fa21203e37fe9dc03271a9072cb78 Mon Sep 17 00:00:00 2001 From: AmanShukla111 Date: Sun, 1 Jun 2025 19:53:43 +0530 Subject: Adding 74HC4020-14-Bit Asynchronous Binary Counters --- .../SubcircuitLibrary/74HC4020/74HC4020-cache.lib | 139 +++++ library/SubcircuitLibrary/74HC4020/74HC4020.cir | 28 + .../SubcircuitLibrary/74HC4020/74HC4020.cir.out | 77 +++ library/SubcircuitLibrary/74HC4020/74HC4020.pro | 73 +++ library/SubcircuitLibrary/74HC4020/74HC4020.sch | 630 +++++++++++++++++++++ library/SubcircuitLibrary/74HC4020/74HC4020.sub | 71 +++ .../74HC4020/74HC4020_Previous_Values.xml | 1 + library/SubcircuitLibrary/74HC4020/analysis | 1 + 8 files changed, 1020 insertions(+) create mode 100644 library/SubcircuitLibrary/74HC4020/74HC4020-cache.lib create mode 100644 library/SubcircuitLibrary/74HC4020/74HC4020.cir create mode 100644 library/SubcircuitLibrary/74HC4020/74HC4020.cir.out create mode 100644 library/SubcircuitLibrary/74HC4020/74HC4020.pro create mode 100644 library/SubcircuitLibrary/74HC4020/74HC4020.sch create mode 100644 library/SubcircuitLibrary/74HC4020/74HC4020.sub create mode 100644 library/SubcircuitLibrary/74HC4020/74HC4020_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/74HC4020/analysis diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020-cache.lib b/library/SubcircuitLibrary/74HC4020/74HC4020-cache.lib new file mode 100644 index 00000000..41a77822 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4020/74HC4020-cache.lib @@ -0,0 +1,139 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tff +# +DEF d_tff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_tff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X T 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Out 5 550 350 200 L 50 50 1 1 O +X Nout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020.cir b/library/SubcircuitLibrary/74HC4020/74HC4020.cir new file mode 100644 index 00000000..aed99954 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4020/74HC4020.cir @@ -0,0 +1,28 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\Asynch_counter_sub\Asynch_counter_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 4/20/2025 7:24:35 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U10-Pad1_ Net-_U1-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U3-Pad4_ Net-_U4-Pad6_ d_tff +U6 Net-_U10-Pad1_ Net-_U4-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ ? Net-_U6-Pad6_ d_tff +U8 Net-_U10-Pad1_ Net-_U6-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ ? Net-_U10-Pad2_ d_tff +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U10-Pad6_ d_tff +U12 Net-_U10-Pad1_ Net-_U10-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U12-Pad5_ Net-_U12-Pad6_ d_tff +U14 Net-_U10-Pad1_ Net-_U12-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U14-Pad5_ Net-_U14-Pad6_ d_tff +U16 Net-_U10-Pad1_ Net-_U14-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U16-Pad5_ Net-_U16-Pad6_ d_tff +U5 Net-_U10-Pad1_ Net-_U16-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U3-Pad5_ Net-_U5-Pad6_ d_tff +U7 Net-_U10-Pad1_ Net-_U5-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U3-Pad6_ Net-_U7-Pad6_ d_tff +U9 Net-_U10-Pad1_ Net-_U7-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U3-Pad7_ Net-_U11-Pad2_ d_tff +U11 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ d_tff +U13 Net-_U10-Pad1_ Net-_U11-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U13-Pad5_ Net-_U13-Pad6_ d_tff +U15 Net-_U10-Pad1_ Net-_U13-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U15-Pad5_ Net-_U15-Pad6_ d_tff +U17 Net-_U10-Pad1_ Net-_U15-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U17-Pad5_ ? d_tff +U3 Net-_U10-Pad3_ Net-_U1-Pad1_ Net-_U10-Pad4_ Net-_U3-Pad4_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U10-Pad5_ Net-_U11-Pad5_ Net-_U12-Pad5_ Net-_U13-Pad5_ Net-_U14-Pad5_ Net-_U15-Pad5_ Net-_U16-Pad5_ Net-_U17-Pad5_ PORT +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U2-Pad1_ Net-_U10-Pad1_ adc_bridge_1 +v1 Net-_U2-Pad1_ GND 5 + +.end diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020.cir.out b/library/SubcircuitLibrary/74HC4020/74HC4020.cir.out new file mode 100644 index 00000000..0671778f --- /dev/null +++ b/library/SubcircuitLibrary/74HC4020/74HC4020.cir.out @@ -0,0 +1,77 @@ +* c:\fossee\esim\library\subcircuitlibrary\asynch_counter_sub\asynch_counter_sub.cir + +* u4 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad4_ net-_u4-pad6_ d_tff +* u6 net-_u10-pad1_ net-_u4-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u6-pad6_ d_tff +* u8 net-_u10-pad1_ net-_u6-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u10-pad2_ d_tff +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ d_tff +* u12 net-_u10-pad1_ net-_u10-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u12-pad5_ net-_u12-pad6_ d_tff +* u14 net-_u10-pad1_ net-_u12-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u14-pad5_ net-_u14-pad6_ d_tff +* u16 net-_u10-pad1_ net-_u14-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u16-pad5_ net-_u16-pad6_ d_tff +* u5 net-_u10-pad1_ net-_u16-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad5_ net-_u5-pad6_ d_tff +* u7 net-_u10-pad1_ net-_u5-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad6_ net-_u7-pad6_ d_tff +* u9 net-_u10-pad1_ net-_u7-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad7_ net-_u11-pad2_ d_tff +* u11 net-_u10-pad1_ net-_u11-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u11-pad5_ net-_u11-pad6_ d_tff +* u13 net-_u10-pad1_ net-_u11-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u13-pad5_ net-_u13-pad6_ d_tff +* u15 net-_u10-pad1_ net-_u13-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u15-pad5_ net-_u15-pad6_ d_tff +* u17 net-_u10-pad1_ net-_u15-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u17-pad5_ ? d_tff +* u3 net-_u10-pad3_ net-_u1-pad1_ net-_u10-pad4_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u10-pad5_ net-_u11-pad5_ net-_u12-pad5_ net-_u13-pad5_ net-_u14-pad5_ net-_u15-pad5_ net-_u16-pad5_ net-_u17-pad5_ port +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u2-pad1_ net-_u10-pad1_ adc_bridge_1 +v1 net-_u2-pad1_ gnd 5 +a1 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad4_ net-_u4-pad6_ u4 +a2 net-_u10-pad1_ net-_u4-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u6-pad6_ u6 +a3 net-_u10-pad1_ net-_u6-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u10-pad2_ u8 +a4 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ u10 +a5 net-_u10-pad1_ net-_u10-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u12-pad5_ net-_u12-pad6_ u12 +a6 net-_u10-pad1_ net-_u12-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u14-pad5_ net-_u14-pad6_ u14 +a7 net-_u10-pad1_ net-_u14-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u16-pad5_ net-_u16-pad6_ u16 +a8 net-_u10-pad1_ net-_u16-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad5_ net-_u5-pad6_ u5 +a9 net-_u10-pad1_ net-_u5-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad6_ net-_u7-pad6_ u7 +a10 net-_u10-pad1_ net-_u7-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad7_ net-_u11-pad2_ u9 +a11 net-_u10-pad1_ net-_u11-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u11-pad5_ net-_u11-pad6_ u11 +a12 net-_u10-pad1_ net-_u11-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u13-pad5_ net-_u13-pad6_ u13 +a13 net-_u10-pad1_ net-_u13-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u15-pad5_ net-_u15-pad6_ u15 +a14 net-_u10-pad1_ net-_u15-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u17-pad5_ ? u17 +a15 net-_u1-pad1_ net-_u1-pad2_ u1 +a16 [net-_u2-pad1_ ] [net-_u10-pad1_ ] u2 +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u4 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u6 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u8 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u10 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u12 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u14 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u16 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u5 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u7 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u9 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u11 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u13 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u15 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u17 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020.pro b/library/SubcircuitLibrary/74HC4020/74HC4020.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/74HC4020/74HC4020.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020.sch b/library/SubcircuitLibrary/74HC4020/74HC4020.sch new file mode 100644 index 00000000..1cc3a953 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4020/74HC4020.sch @@ -0,0 +1,630 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:Asynch_counter_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_tff U4 +U 1 1 67FA638A +P 2000 1900 +F 0 "U4" H 2000 1900 60 0000 C CNN +F 1 "d_tff" H 2000 2050 60 0000 C CNN +F 2 "" H 2000 1900 60 0000 C CNN +F 3 "" H 2000 1900 60 0000 C CNN + 1 2000 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U6 +U 1 1 67FA6441 +P 3450 1900 +F 0 "U6" H 3450 1900 60 0000 C CNN +F 1 "d_tff" H 3450 2050 60 0000 C CNN +F 2 "" H 3450 1900 60 0000 C CNN +F 3 "" H 3450 1900 60 0000 C CNN + 1 3450 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U8 +U 1 1 67FA6470 +P 4800 1900 +F 0 "U8" H 4800 1900 60 0000 C CNN +F 1 "d_tff" H 4800 2050 60 0000 C CNN +F 2 "" H 4800 1900 60 0000 C CNN +F 3 "" H 4800 1900 60 0000 C CNN + 1 4800 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U10 +U 1 1 67FA649D +P 6150 1900 +F 0 "U10" H 6150 1900 60 0000 C CNN +F 1 "d_tff" H 6150 2050 60 0000 C CNN +F 2 "" H 6150 1900 60 0000 C CNN +F 3 "" H 6150 1900 60 0000 C CNN + 1 6150 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U12 +U 1 1 67FA64D6 +P 7500 1900 +F 0 "U12" H 7500 1900 60 0000 C CNN +F 1 "d_tff" H 7500 2050 60 0000 C CNN +F 2 "" H 7500 1900 60 0000 C CNN +F 3 "" H 7500 1900 60 0000 C CNN + 1 7500 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U14 +U 1 1 67FA6539 +P 8850 1900 +F 0 "U14" H 8850 1900 60 0000 C CNN +F 1 "d_tff" H 8850 2050 60 0000 C CNN +F 2 "" H 8850 1900 60 0000 C CNN +F 3 "" H 8850 1900 60 0000 C CNN + 1 8850 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U16 +U 1 1 67FA6592 +P 10250 1900 +F 0 "U16" H 10250 1900 60 0000 C CNN +F 1 "d_tff" H 10250 2050 60 0000 C CNN +F 2 "" H 10250 1900 60 0000 C CNN +F 3 "" H 10250 1900 60 0000 C CNN + 1 10250 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U5 +U 1 1 67FA6604 +P 2000 4000 +F 0 "U5" H 2000 4000 60 0000 C CNN +F 1 "d_tff" H 2000 4150 60 0000 C CNN +F 2 "" H 2000 4000 60 0000 C CNN +F 3 "" H 2000 4000 60 0000 C CNN + 1 2000 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U7 +U 1 1 67FA662F +P 3450 4000 +F 0 "U7" H 3450 4000 60 0000 C CNN +F 1 "d_tff" H 3450 4150 60 0000 C CNN +F 2 "" H 3450 4000 60 0000 C CNN +F 3 "" H 3450 4000 60 0000 C CNN + 1 3450 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U9 +U 1 1 67FA6674 +P 4800 4000 +F 0 "U9" H 4800 4000 60 0000 C CNN +F 1 "d_tff" H 4800 4150 60 0000 C CNN +F 2 "" H 4800 4000 60 0000 C CNN +F 3 "" H 4800 4000 60 0000 C CNN + 1 4800 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U11 +U 1 1 67FA66AF +P 6150 4000 +F 0 "U11" H 6150 4000 60 0000 C CNN +F 1 "d_tff" H 6150 4150 60 0000 C CNN +F 2 "" H 6150 4000 60 0000 C CNN +F 3 "" H 6150 4000 60 0000 C CNN + 1 6150 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U13 +U 1 1 67FA6708 +P 7500 4000 +F 0 "U13" H 7500 4000 60 0000 C CNN +F 1 "d_tff" H 7500 4150 60 0000 C CNN +F 2 "" H 7500 4000 60 0000 C CNN +F 3 "" H 7500 4000 60 0000 C CNN + 1 7500 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U15 +U 1 1 67FA6741 +P 8850 4000 +F 0 "U15" H 8850 4000 60 0000 C CNN +F 1 "d_tff" H 8850 4150 60 0000 C CNN +F 2 "" H 8850 4000 60 0000 C CNN +F 3 "" H 8850 4000 60 0000 C CNN + 1 8850 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_tff U17 +U 1 1 67FA678E +P 10250 4000 +F 0 "U17" H 10250 4000 60 0000 C CNN +F 1 "d_tff" H 10250 4150 60 0000 C CNN +F 2 "" H 10250 4000 60 0000 C CNN +F 3 "" H 10250 4000 60 0000 C CNN + 1 10250 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 2 1 67FA6EA5 +P 850 1700 +F 0 "U3" H 900 1800 30 0000 C CNN +F 1 "PORT" H 850 1700 30 0000 C CNN +F 2 "" H 850 1700 60 0000 C CNN +F 3 "" H 850 1700 60 0000 C CNN + 2 850 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 3 1 67FA6F3E +P 850 2650 +F 0 "U3" H 900 2750 30 0000 C CNN +F 1 "PORT" H 850 2650 30 0000 C CNN +F 2 "" H 850 2650 60 0000 C CNN +F 3 "" H 850 2650 60 0000 C CNN + 3 850 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 1 1 67FA704B +P 850 1100 +F 0 "U3" H 900 1200 30 0000 C CNN +F 1 "PORT" H 850 1100 30 0000 C CNN +F 2 "" H 850 1100 60 0000 C CNN +F 3 "" H 850 1100 60 0000 C CNN + 1 850 1100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 67FA79AF +P 800 2200 +F 0 "U1" H 800 2100 60 0000 C CNN +F 1 "d_inverter" H 800 2350 60 0000 C CNN +F 2 "" H 850 2150 60 0000 C CNN +F 3 "" H 850 2150 60 0000 C CNN + 1 800 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 4 1 67FBA3CB +P 2550 1300 +F 0 "U3" H 2600 1400 30 0000 C CNN +F 1 "PORT" H 2550 1300 30 0000 C CNN +F 2 "" H 2550 1300 60 0000 C CNN +F 3 "" H 2550 1300 60 0000 C CNN + 4 2550 1300 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 8 1 67FBA46A +P 6700 1300 +F 0 "U3" H 6750 1400 30 0000 C CNN +F 1 "PORT" H 6700 1300 30 0000 C CNN +F 2 "" H 6700 1300 60 0000 C CNN +F 3 "" H 6700 1300 60 0000 C CNN + 8 6700 1300 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 10 1 67FBA630 +P 8050 1300 +F 0 "U3" H 8100 1400 30 0000 C CNN +F 1 "PORT" H 8050 1300 30 0000 C CNN +F 2 "" H 8050 1300 60 0000 C CNN +F 3 "" H 8050 1300 60 0000 C CNN + 10 8050 1300 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 12 1 67FBA6D5 +P 9400 1300 +F 0 "U3" H 9450 1400 30 0000 C CNN +F 1 "PORT" H 9400 1300 30 0000 C CNN +F 2 "" H 9400 1300 60 0000 C CNN +F 3 "" H 9400 1300 60 0000 C CNN + 12 9400 1300 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 14 1 67FBA754 +P 10800 1300 +F 0 "U3" H 10850 1400 30 0000 C CNN +F 1 "PORT" H 10800 1300 30 0000 C CNN +F 2 "" H 10800 1300 60 0000 C CNN +F 3 "" H 10800 1300 60 0000 C CNN + 14 10800 1300 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 5 1 67FBA85B +P 2550 3400 +F 0 "U3" H 2600 3500 30 0000 C CNN +F 1 "PORT" H 2550 3400 30 0000 C CNN +F 2 "" H 2550 3400 60 0000 C CNN +F 3 "" H 2550 3400 60 0000 C CNN + 5 2550 3400 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 6 1 67FBA904 +P 4000 3400 +F 0 "U3" H 4050 3500 30 0000 C CNN +F 1 "PORT" H 4000 3400 30 0000 C CNN +F 2 "" H 4000 3400 60 0000 C CNN +F 3 "" H 4000 3400 60 0000 C CNN + 6 4000 3400 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 7 1 67FBA981 +P 5350 3400 +F 0 "U3" H 5400 3500 30 0000 C CNN +F 1 "PORT" H 5350 3400 30 0000 C CNN +F 2 "" H 5350 3400 60 0000 C CNN +F 3 "" H 5350 3400 60 0000 C CNN + 7 5350 3400 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 9 1 67FBA9F0 +P 6700 3400 +F 0 "U3" H 6750 3500 30 0000 C CNN +F 1 "PORT" H 6700 3400 30 0000 C CNN +F 2 "" H 6700 3400 60 0000 C CNN +F 3 "" H 6700 3400 60 0000 C CNN + 9 6700 3400 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 11 1 67FBAA8B +P 8050 3400 +F 0 "U3" H 8100 3500 30 0000 C CNN +F 1 "PORT" H 8050 3400 30 0000 C CNN +F 2 "" H 8050 3400 60 0000 C CNN +F 3 "" H 8050 3400 60 0000 C CNN + 11 8050 3400 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 13 1 67FBAC33 +P 9400 3400 +F 0 "U3" H 9450 3500 30 0000 C CNN +F 1 "PORT" H 9400 3400 30 0000 C CNN +F 2 "" H 9400 3400 60 0000 C CNN +F 3 "" H 9400 3400 60 0000 C CNN + 13 9400 3400 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 15 1 67FBACB0 +P 10800 3400 +F 0 "U3" H 10850 3500 30 0000 C CNN +F 1 "PORT" H 10800 3400 30 0000 C CNN +F 2 "" H 10800 3400 60 0000 C CNN +F 3 "" H 10800 3400 60 0000 C CNN + 15 10800 3400 + 0 1 1 0 +$EndComp +$Comp +L adc_bridge_1 U2 +U 1 1 67FBBBF8 +P 800 3700 +F 0 "U2" H 800 3700 60 0000 C CNN +F 1 "adc_bridge_1" H 800 3850 60 0000 C CNN +F 2 "" H 800 3700 60 0000 C CNN +F 3 "" H 800 3700 60 0000 C CNN + 1 800 3700 + 0 -1 -1 0 +$EndComp +$Comp +L pulse v1 +U 1 1 67FBBE65 +P 750 4750 +F 0 "v1" H 550 4850 60 0000 C CNN +F 1 "5" H 550 4700 60 0000 C CNN +F 2 "R1" H 450 4750 60 0000 C CNN +F 3 "" H 750 4750 60 0000 C CNN + 1 750 4750 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 67FBBEE8 +P 750 5200 +F 0 "#PWR01" H 750 4950 50 0001 C CNN +F 1 "GND" H 750 5050 50 0000 C CNN +F 2 "" H 750 5200 50 0001 C CNN +F 3 "" H 750 5200 50 0001 C CNN + 1 750 5200 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 67FBCA70 +P 750 5200 +F 0 "#FLG02" H 750 5275 50 0001 C CNN +F 1 "PWR_FLAG" H 750 5350 50 0000 C CNN +F 2 "" H 750 5200 50 0001 C CNN +F 3 "" H 750 5200 50 0001 C CNN + 1 750 5200 + 0 1 1 0 +$EndComp +Wire Wire Line + 2550 2200 2900 2200 +Wire Wire Line + 4000 2200 4250 2200 +Wire Wire Line + 5350 2200 5600 2200 +Wire Wire Line + 6700 2200 6950 2200 +Wire Wire Line + 8050 2200 8300 2200 +Wire Wire Line + 9700 2200 9400 2200 +Wire Wire Line + 2900 4300 2550 4300 +Wire Wire Line + 4000 4300 4250 4300 +Wire Wire Line + 5600 4300 5350 4300 +Wire Wire Line + 6950 4300 6700 4300 +Wire Wire Line + 10800 2200 10800 3100 +Wire Wire Line + 10800 3100 1100 3100 +Wire Wire Line + 1100 3100 1100 4300 +Wire Wire Line + 1100 4300 1450 4300 +Wire Wire Line + 1100 1100 10250 1100 +Wire Wire Line + 10250 1100 10250 1250 +Wire Wire Line + 8850 1250 8850 1100 +Connection ~ 8850 1100 +Wire Wire Line + 7500 1250 7500 1100 +Connection ~ 7500 1100 +Wire Wire Line + 6150 1250 6150 1100 +Connection ~ 6150 1100 +Wire Wire Line + 4800 1250 4800 1100 +Connection ~ 4800 1100 +Wire Wire Line + 3450 1250 3450 1100 +Connection ~ 3450 1100 +Wire Wire Line + 2000 1250 2000 1100 +Connection ~ 2000 1100 +Wire Wire Line + 1450 2200 1100 2200 +Connection ~ 1250 1100 +Wire Wire Line + 1250 1100 1250 2950 +Wire Wire Line + 1250 2950 10250 2950 +Wire Wire Line + 10250 2950 10250 3350 +Wire Wire Line + 2000 3350 2000 2950 +Connection ~ 2000 2950 +Wire Wire Line + 3450 3350 3450 2950 +Connection ~ 3450 2950 +Wire Wire Line + 4800 3350 4800 2950 +Connection ~ 4800 2950 +Wire Wire Line + 6150 3350 6150 2950 +Connection ~ 6150 2950 +Wire Wire Line + 7500 3350 7500 2950 +Connection ~ 7500 2950 +Wire Wire Line + 8850 3350 8850 2950 +Connection ~ 8850 2950 +Wire Wire Line + 1100 2650 10250 2650 +Wire Wire Line + 10250 2650 10250 2500 +Wire Wire Line + 2000 2500 2000 2650 +Connection ~ 2000 2650 +Wire Wire Line + 3450 2500 3450 2650 +Connection ~ 3450 2650 +Wire Wire Line + 4800 2500 4800 2650 +Connection ~ 4800 2650 +Wire Wire Line + 6150 2500 6150 2650 +Connection ~ 6150 2650 +Wire Wire Line + 7500 2500 7500 2650 +Connection ~ 7500 2650 +Wire Wire Line + 8850 2500 8850 2650 +Connection ~ 8850 2650 +Connection ~ 1200 2650 +Wire Wire Line + 1200 2650 1200 4900 +Wire Wire Line + 1200 4900 10250 4900 +Wire Wire Line + 10250 4900 10250 4600 +Wire Wire Line + 8850 4600 8850 4900 +Connection ~ 8850 4900 +Wire Wire Line + 7500 4600 7500 4900 +Connection ~ 7500 4900 +Wire Wire Line + 6150 4600 6150 4900 +Connection ~ 6150 4900 +Wire Wire Line + 4800 4600 4800 4900 +Connection ~ 4800 4900 +Wire Wire Line + 3450 4600 3450 4900 +Connection ~ 3450 4900 +Wire Wire Line + 2000 4600 2000 4900 +Connection ~ 2000 4900 +Wire Wire Line + 1100 1700 1100 1900 +Wire Wire Line + 1100 1900 500 1900 +Wire Wire Line + 500 1900 500 2200 +Wire Wire Line + 750 2850 9600 2850 +Wire Wire Line + 9600 2850 9600 1550 +Wire Wire Line + 9600 1550 9700 1550 +Wire Wire Line + 8300 1550 8250 1550 +Wire Wire Line + 8250 1550 8250 2850 +Connection ~ 8250 2850 +Wire Wire Line + 6950 1550 6900 1550 +Wire Wire Line + 6900 1550 6900 2850 +Connection ~ 6900 2850 +Wire Wire Line + 5600 1550 5500 1550 +Wire Wire Line + 5500 1550 5500 2850 +Connection ~ 5500 2850 +Wire Wire Line + 4250 1550 4150 1550 +Wire Wire Line + 4150 1550 4150 2850 +Connection ~ 4150 2850 +Wire Wire Line + 2900 1550 2750 1550 +Wire Wire Line + 2750 1550 2750 2850 +Connection ~ 2750 2850 +Wire Wire Line + 1450 1550 1350 1550 +Wire Wire Line + 1350 1550 1350 2850 +Connection ~ 1350 2850 +Wire Wire Line + 1450 3650 1450 2850 +Connection ~ 1450 2850 +Wire Wire Line + 2900 3650 2900 2850 +Connection ~ 2900 2850 +Wire Wire Line + 4250 3650 4250 2850 +Connection ~ 4250 2850 +Wire Wire Line + 5600 3650 5600 2850 +Connection ~ 5600 2850 +Wire Wire Line + 6950 3650 6800 3650 +Wire Wire Line + 6800 3650 6800 2850 +Connection ~ 6800 2850 +Wire Wire Line + 8300 3650 8150 3650 +Wire Wire Line + 8150 3650 8150 2850 +Connection ~ 8150 2850 +Wire Wire Line + 9700 3650 9550 3650 +Wire Wire Line + 9550 3650 9550 2850 +Connection ~ 9550 2850 +Wire Wire Line + 750 3150 750 2850 +Wire Wire Line + 8050 4300 8300 4300 +Wire Wire Line + 9400 4300 9700 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020.sub b/library/SubcircuitLibrary/74HC4020/74HC4020.sub new file mode 100644 index 00000000..f0d95a49 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4020/74HC4020.sub @@ -0,0 +1,71 @@ +* Subcircuit Asynch_counter_sub +.subckt Asynch_counter_sub net-_u10-pad3_ net-_u1-pad1_ net-_u10-pad4_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u10-pad5_ net-_u11-pad5_ net-_u12-pad5_ net-_u13-pad5_ net-_u14-pad5_ net-_u15-pad5_ net-_u16-pad5_ net-_u17-pad5_ +* c:\fossee\esim\library\subcircuitlibrary\asynch_counter_sub\asynch_counter_sub.cir +* u4 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad4_ net-_u4-pad6_ d_tff +* u6 net-_u10-pad1_ net-_u4-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u6-pad6_ d_tff +* u8 net-_u10-pad1_ net-_u6-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u10-pad2_ d_tff +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ d_tff +* u12 net-_u10-pad1_ net-_u10-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u12-pad5_ net-_u12-pad6_ d_tff +* u14 net-_u10-pad1_ net-_u12-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u14-pad5_ net-_u14-pad6_ d_tff +* u16 net-_u10-pad1_ net-_u14-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u16-pad5_ net-_u16-pad6_ d_tff +* u5 net-_u10-pad1_ net-_u16-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad5_ net-_u5-pad6_ d_tff +* u7 net-_u10-pad1_ net-_u5-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad6_ net-_u7-pad6_ d_tff +* u9 net-_u10-pad1_ net-_u7-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad7_ net-_u11-pad2_ d_tff +* u11 net-_u10-pad1_ net-_u11-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u11-pad5_ net-_u11-pad6_ d_tff +* u13 net-_u10-pad1_ net-_u11-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u13-pad5_ net-_u13-pad6_ d_tff +* u15 net-_u10-pad1_ net-_u13-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u15-pad5_ net-_u15-pad6_ d_tff +* u17 net-_u10-pad1_ net-_u15-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u17-pad5_ ? d_tff +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u2-pad1_ net-_u10-pad1_ adc_bridge_1 +v1 net-_u2-pad1_ gnd 5 +a1 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad4_ net-_u4-pad6_ u4 +a2 net-_u10-pad1_ net-_u4-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u6-pad6_ u6 +a3 net-_u10-pad1_ net-_u6-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u10-pad2_ u8 +a4 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ u10 +a5 net-_u10-pad1_ net-_u10-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u12-pad5_ net-_u12-pad6_ u12 +a6 net-_u10-pad1_ net-_u12-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u14-pad5_ net-_u14-pad6_ u14 +a7 net-_u10-pad1_ net-_u14-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u16-pad5_ net-_u16-pad6_ u16 +a8 net-_u10-pad1_ net-_u16-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad5_ net-_u5-pad6_ u5 +a9 net-_u10-pad1_ net-_u5-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad6_ net-_u7-pad6_ u7 +a10 net-_u10-pad1_ net-_u7-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad7_ net-_u11-pad2_ u9 +a11 net-_u10-pad1_ net-_u11-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u11-pad5_ net-_u11-pad6_ u11 +a12 net-_u10-pad1_ net-_u11-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u13-pad5_ net-_u13-pad6_ u13 +a13 net-_u10-pad1_ net-_u13-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u15-pad5_ net-_u15-pad6_ u15 +a14 net-_u10-pad1_ net-_u15-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u17-pad5_ ? u17 +a15 net-_u1-pad1_ net-_u1-pad2_ u1 +a16 [net-_u2-pad1_ ] [net-_u10-pad1_ ] u2 +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u4 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u6 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u8 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u10 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u12 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u14 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u16 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u5 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u7 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u9 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u11 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u13 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u15 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u17 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends Asynch_counter_sub \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020_Previous_Values.xml b/library/SubcircuitLibrary/74HC4020/74HC4020_Previous_Values.xml new file mode 100644 index 00000000..26e2bb93 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4020/74HC4020_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec5d_tffd_tffd_tffd_tffd_tffd_tffd_tffd_tffd_tffd_tffd_tffd_tffd_tffd_tffd_inverteradc_bridge \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC4020/analysis b/library/SubcircuitLibrary/74HC4020/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4020/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit