From b085a3df519debbc99acf4ded7e118a1690d6665 Mon Sep 17 00:00:00 2001 From: nilshah98 Date: Tue, 2 Jul 2019 16:42:20 +0530 Subject: Subcircuit added by ECE fellows 2019 --- .../2bit_upcounter/2bit_upcounter-cache.lib | 62 + .../2bit_upcounter/2bit_upcounter.cir | 13 + .../2bit_upcounter/2bit_upcounter.cir.out | 20 + .../2bit_upcounter/2bit_upcounter.pro | 45 + .../2bit_upcounter/2bit_upcounter.sch | 151 ++ .../2bit_upcounter/2bit_upcounter.sub | 14 + .../2bit_upcounter_Previous_Values.xml | 1 + src/SubcircuitLibrary/2bit_upcounter/analysis | 1 + src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib | 77 + src/SubcircuitLibrary/2bitmul/2bitmul.cir | 17 + src/SubcircuitLibrary/2bitmul/2bitmul.cir.out | 31 + src/SubcircuitLibrary/2bitmul/2bitmul.pro | 74 + src/SubcircuitLibrary/2bitmul/2bitmul.sch | 284 ++++ src/SubcircuitLibrary/2bitmul/2bitmul.sub | 25 + .../2bitmul/2bitmul_Previous_Values.xml | 1 + src/SubcircuitLibrary/2bitmul/analysis | 1 + src/SubcircuitLibrary/2bitmul/half_adder-cache.lib | 63 + src/SubcircuitLibrary/2bitmul/half_adder.cir | 11 + src/SubcircuitLibrary/2bitmul/half_adder.cir.out | 20 + src/SubcircuitLibrary/2bitmul/half_adder.pro | 69 + src/SubcircuitLibrary/2bitmul/half_adder.sch | 152 ++ src/SubcircuitLibrary/2bitmul/half_adder.sub | 14 + .../2bitmul/half_adder_Previous_Values.xml | 1 + src/SubcircuitLibrary/3_and/3_and-cache.lib | 61 + src/SubcircuitLibrary/3_and/3_and.cir | 13 + src/SubcircuitLibrary/3_and/3_and.cir.out | 20 + src/SubcircuitLibrary/3_and/3_and.pro | 44 + src/SubcircuitLibrary/3_and/3_and.sch | 130 ++ src/SubcircuitLibrary/3_and/3_and.sub | 14 + .../3_and/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/3_and/analysis | 1 + src/SubcircuitLibrary/4025/4025-cache.lib | 82 ++ src/SubcircuitLibrary/4025/4025.cir | 17 + src/SubcircuitLibrary/4025/4025.cir.out | 36 + src/SubcircuitLibrary/4025/4025.pro | 45 + src/SubcircuitLibrary/4025/4025.sch | 302 ++++ src/SubcircuitLibrary/4025/4025.sub | 30 + .../4025/4025_Previous_Values.xml | 1 + src/SubcircuitLibrary/4025/analysis | 1 + src/SubcircuitLibrary/4072/4072-cache.lib | 63 + src/SubcircuitLibrary/4072/4072.cir | 17 + src/SubcircuitLibrary/4072/4072.cir.out | 36 + src/SubcircuitLibrary/4072/4072.pro | 45 + src/SubcircuitLibrary/4072/4072.sch | 334 +++++ src/SubcircuitLibrary/4072/4072.sub | 30 + .../4072/4072_Previous_Values.xml | 1 + src/SubcircuitLibrary/4072/analysis | 1 + src/SubcircuitLibrary/4073/3_and-cache.lib | 61 + src/SubcircuitLibrary/4073/3_and.cir | 13 + src/SubcircuitLibrary/4073/3_and.cir.out | 20 + src/SubcircuitLibrary/4073/3_and.pro | 44 + src/SubcircuitLibrary/4073/3_and.sch | 130 ++ src/SubcircuitLibrary/4073/3_and.sub | 14 + .../4073/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/4073/4073-cache.lib | 62 + src/SubcircuitLibrary/4073/4073.cir | 14 + src/SubcircuitLibrary/4073/4073.cir.out | 16 + src/SubcircuitLibrary/4073/4073.pro | 43 + src/SubcircuitLibrary/4073/4073.sch | 263 ++++ src/SubcircuitLibrary/4073/4073.sub | 10 + .../4073/4073_Previous_Values.xml | 1 + src/SubcircuitLibrary/4073/analysis | 1 + src/SubcircuitLibrary/4_OR/4_OR-cache.lib | 63 + src/SubcircuitLibrary/4_OR/4_OR.cir | 14 + src/SubcircuitLibrary/4_OR/4_OR.cir.out | 24 + src/SubcircuitLibrary/4_OR/4_OR.pro | 45 + src/SubcircuitLibrary/4_OR/4_OR.sch | 150 ++ src/SubcircuitLibrary/4_OR/4_OR.sub | 18 + .../4_OR/4_OR_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_OR/analysis | 1 + src/SubcircuitLibrary/4_and/3_and-cache.lib | 61 + src/SubcircuitLibrary/4_and/3_and.cir | 13 + src/SubcircuitLibrary/4_and/3_and.cir.out | 20 + src/SubcircuitLibrary/4_and/3_and.pro | 44 + src/SubcircuitLibrary/4_and/3_and.sch | 130 ++ src/SubcircuitLibrary/4_and/3_and.sub | 14 + .../4_and/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_and/4_and-cache.lib | 79 ++ src/SubcircuitLibrary/4_and/4_and-rescue.lib | 22 + src/SubcircuitLibrary/4_and/4_and.cir | 13 + src/SubcircuitLibrary/4_and/4_and.cir.out | 18 + src/SubcircuitLibrary/4_and/4_and.pro | 58 + src/SubcircuitLibrary/4_and/4_and.sch | 151 ++ src/SubcircuitLibrary/4_and/4_and.sub | 12 + .../4_and/4_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_and/analysis | 1 + src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib | 61 + src/SubcircuitLibrary/4_bit_FA/3_and.cir | 13 + src/SubcircuitLibrary/4_bit_FA/3_and.cir.out | 20 + src/SubcircuitLibrary/4_bit_FA/3_and.pro | 58 + src/SubcircuitLibrary/4_bit_FA/3_and.sch | 121 ++ src/SubcircuitLibrary/4_bit_FA/3_and.sub | 14 + .../4_bit_FA/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib | 63 + src/SubcircuitLibrary/4_bit_FA/4_OR.cir | 14 + src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out | 24 + src/SubcircuitLibrary/4_bit_FA/4_OR.pro | 45 + src/SubcircuitLibrary/4_bit_FA/4_OR.sch | 150 ++ src/SubcircuitLibrary/4_bit_FA/4_OR.sub | 18 + .../4_bit_FA/4_OR_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib | 79 ++ src/SubcircuitLibrary/4_bit_FA/4_and.cir | 13 + src/SubcircuitLibrary/4_bit_FA/4_and.cir.out | 18 + src/SubcircuitLibrary/4_bit_FA/4_and.pro | 57 + src/SubcircuitLibrary/4_bit_FA/4_and.sch | 139 ++ src/SubcircuitLibrary/4_bit_FA/4_and.sub | 12 + .../4_bit_FA/4_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib | 172 +++ src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir | 48 + src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out | 151 ++ src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro | 58 + src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch | 945 +++++++++++++ src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub | 145 ++ .../4_bit_FA/4_bit_FA_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_bit_FA/analysis | 1 + src/SubcircuitLibrary/4to16_demux/3_and-cache.lib | 61 + src/SubcircuitLibrary/4to16_demux/3_and.cir | 13 + src/SubcircuitLibrary/4to16_demux/3_and.cir.out | 20 + src/SubcircuitLibrary/4to16_demux/3_and.pro | 44 + src/SubcircuitLibrary/4to16_demux/3_and.sch | 130 ++ src/SubcircuitLibrary/4to16_demux/3_and.sub | 14 + .../4to16_demux/3_and_Previous_Values.xml | 1 + .../4to16_demux/4to16_demux-cache.lib | 97 ++ src/SubcircuitLibrary/4to16_demux/4to16_demux.cir | 32 + .../4to16_demux/4to16_demux.cir.out | 49 + src/SubcircuitLibrary/4to16_demux/4to16_demux.pro | 43 + src/SubcircuitLibrary/4to16_demux/4to16_demux.sch | 889 ++++++++++++ src/SubcircuitLibrary/4to16_demux/4to16_demux.sub | 43 + .../4to16_demux/4to16_demux_Previous_Values.xml | 1 + src/SubcircuitLibrary/4to16_demux/5_and-cache.lib | 79 ++ src/SubcircuitLibrary/4to16_demux/5_and.cir | 14 + src/SubcircuitLibrary/4to16_demux/5_and.cir.out | 22 + src/SubcircuitLibrary/4to16_demux/5_and.pro | 50 + src/SubcircuitLibrary/4to16_demux/5_and.sch | 171 +++ src/SubcircuitLibrary/4to16_demux/5_and.sub | 16 + .../4to16_demux/5_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib | 78 + src/SubcircuitLibrary/4to16_demux/5_nand.cir | 13 + src/SubcircuitLibrary/4to16_demux/5_nand.cir.out | 18 + src/SubcircuitLibrary/4to16_demux/5_nand.pro | 83 ++ src/SubcircuitLibrary/4to16_demux/5_nand.sch | 175 +++ src/SubcircuitLibrary/4to16_demux/5_nand.sub | 12 + .../4to16_demux/5_nand_Previous_Values.xml | 1 + src/SubcircuitLibrary/4to16_demux/analysis | 1 + src/SubcircuitLibrary/5_and/3_and-cache.lib | 61 + src/SubcircuitLibrary/5_and/3_and.cir | 13 + src/SubcircuitLibrary/5_and/3_and.cir.out | 20 + src/SubcircuitLibrary/5_and/3_and.pro | 44 + src/SubcircuitLibrary/5_and/3_and.sch | 130 ++ src/SubcircuitLibrary/5_and/3_and.sub | 14 + .../5_and/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/5_and/5_and-cache.lib | 79 ++ src/SubcircuitLibrary/5_and/5_and.cir | 14 + src/SubcircuitLibrary/5_and/5_and.cir.out | 22 + src/SubcircuitLibrary/5_and/5_and.pro | 50 + src/SubcircuitLibrary/5_and/5_and.sch | 171 +++ src/SubcircuitLibrary/5_and/5_and.sub | 16 + .../5_and/5_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/5_and/analysis | 1 + src/SubcircuitLibrary/5_nand/3_and-cache.lib | 61 + src/SubcircuitLibrary/5_nand/3_and.cir | 13 + src/SubcircuitLibrary/5_nand/3_and.cir.out | 20 + src/SubcircuitLibrary/5_nand/3_and.pro | 44 + src/SubcircuitLibrary/5_nand/3_and.sch | 130 ++ src/SubcircuitLibrary/5_nand/3_and.sub | 14 + .../5_nand/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/5_nand/5_and-cache.lib | 79 ++ src/SubcircuitLibrary/5_nand/5_and.cir | 14 + src/SubcircuitLibrary/5_nand/5_and.cir.out | 22 + src/SubcircuitLibrary/5_nand/5_and.pro | 50 + src/SubcircuitLibrary/5_nand/5_and.sch | 171 +++ src/SubcircuitLibrary/5_nand/5_and.sub | 16 + .../5_nand/5_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/5_nand/5_nand-cache.lib | 78 + src/SubcircuitLibrary/5_nand/5_nand.cir | 13 + src/SubcircuitLibrary/5_nand/5_nand.cir.out | 18 + src/SubcircuitLibrary/5_nand/5_nand.pro | 83 ++ src/SubcircuitLibrary/5_nand/5_nand.sch | 175 +++ src/SubcircuitLibrary/5_nand/5_nand.sub | 12 + .../5_nand/5_nand_Previous_Values.xml | 1 + src/SubcircuitLibrary/5_nand/analysis | 1 + src/SubcircuitLibrary/5_nor/3_and-cache.lib | 61 + src/SubcircuitLibrary/5_nor/3_and.cir | 13 + src/SubcircuitLibrary/5_nor/3_and.cir.out | 20 + src/SubcircuitLibrary/5_nor/3_and.pro | 44 + src/SubcircuitLibrary/5_nor/3_and.sch | 130 ++ src/SubcircuitLibrary/5_nor/3_and.sub | 14 + .../5_nor/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/5_nor/5_and-cache.lib | 79 ++ src/SubcircuitLibrary/5_nor/5_and.cir | 14 + src/SubcircuitLibrary/5_nor/5_and.cir.out | 22 + src/SubcircuitLibrary/5_nor/5_and.pro | 50 + src/SubcircuitLibrary/5_nor/5_and.sch | 171 +++ src/SubcircuitLibrary/5_nor/5_and.sub | 16 + .../5_nor/5_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/5_nor/5_nor-cache.lib | 95 ++ src/SubcircuitLibrary/5_nor/5_nor.cir | 19 + src/SubcircuitLibrary/5_nor/5_nor.cir.out | 42 + src/SubcircuitLibrary/5_nor/5_nor.pro | 73 + src/SubcircuitLibrary/5_nor/5_nor.sch | 275 ++++ src/SubcircuitLibrary/5_nor/5_nor.sub | 36 + .../5_nor/5_nor_Previous_Values.xml | 1 + src/SubcircuitLibrary/5_nor/analysis | 1 + .../5bit-Ripple_carry_adder-cache.lib | 61 + .../5bit-Ripple_carry_adder.cir | 16 + .../5bit-Ripple_carry_adder.cir.out | 18 + .../5bit-Ripple_carry_adder.pro | 44 + .../5bit-Ripple_carry_adder.sch | 386 +++++ .../5bit-Ripple_carry_adder.sub | 12 + .../5bit-Ripple_carry_adder_Previous_Values.xml | 1 + .../5bit-Ripple_carry_adder/Full-Adder-cache.lib | 100 ++ .../5bit-Ripple_carry_adder/Full-Adder.cir | 16 + .../5bit-Ripple_carry_adder/Full-Adder.cir.out | 32 + .../5bit-Ripple_carry_adder/Full-Adder.pro | 74 + .../5bit-Ripple_carry_adder/Full-Adder.sch | 226 +++ .../5bit-Ripple_carry_adder/Full-Adder.sub | 26 + .../Full-Adder_Previous_Values.xml | 1 + .../5bit-Ripple_carry_adder/analysis | 1 + src/SubcircuitLibrary/74153/3_and-cache.lib | 61 + src/SubcircuitLibrary/74153/3_and.cir | 13 + src/SubcircuitLibrary/74153/3_and.cir.out | 20 + src/SubcircuitLibrary/74153/3_and.pro | 44 + src/SubcircuitLibrary/74153/3_and.sch | 130 ++ src/SubcircuitLibrary/74153/3_and.sub | 14 + .../74153/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/74153/4_OR-cache.lib | 63 + src/SubcircuitLibrary/74153/4_OR.cir | 14 + src/SubcircuitLibrary/74153/4_OR.cir.out | 24 + src/SubcircuitLibrary/74153/4_OR.pro | 45 + src/SubcircuitLibrary/74153/4_OR.sch | 150 ++ src/SubcircuitLibrary/74153/4_OR.sub | 18 + .../74153/4_OR_Previous_Values.xml | 1 + src/SubcircuitLibrary/74153/4_and-cache.lib | 79 ++ src/SubcircuitLibrary/74153/4_and-rescue.lib | 22 + src/SubcircuitLibrary/74153/4_and.cir | 13 + src/SubcircuitLibrary/74153/4_and.cir.out | 18 + src/SubcircuitLibrary/74153/4_and.pro | 58 + src/SubcircuitLibrary/74153/4_and.sch | 151 ++ src/SubcircuitLibrary/74153/4_and.sub | 12 + .../74153/4_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/74153/74153-cache.lib | 98 ++ src/SubcircuitLibrary/74153/74153.cir | 25 + src/SubcircuitLibrary/74153/74153.cir.out | 40 + src/SubcircuitLibrary/74153/74153.pro | 43 + src/SubcircuitLibrary/74153/74153.sch | 576 ++++++++ src/SubcircuitLibrary/74153/74153.sub | 34 + .../74153/74153_Previous_Values.xml | 1 + src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib | 94 ++ src/SubcircuitLibrary/74153/Dual4to1MUX.cir | 45 + src/SubcircuitLibrary/74153/Dual4to1MUX.sch | 814 +++++++++++ src/SubcircuitLibrary/74153/analysis | 1 + src/SubcircuitLibrary/74157/3_and-cache.lib | 61 + src/SubcircuitLibrary/74157/3_and.cir | 13 + src/SubcircuitLibrary/74157/3_and.cir.out | 20 + src/SubcircuitLibrary/74157/3_and.pro | 44 + src/SubcircuitLibrary/74157/3_and.sch | 130 ++ src/SubcircuitLibrary/74157/3_and.sub | 14 + .../74157/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/74157/74157-cache.lib | 95 ++ src/SubcircuitLibrary/74157/74157-rescue.lib | 22 + src/SubcircuitLibrary/74157/74157.cir | 25 + src/SubcircuitLibrary/74157/74157.cir.out | 45 + src/SubcircuitLibrary/74157/74157.pro | 44 + src/SubcircuitLibrary/74157/74157.sch | 560 ++++++++ src/SubcircuitLibrary/74157/74157.sub | 39 + .../74157/74157_Previous_Values.xml | 1 + src/SubcircuitLibrary/74157/analysis | 1 + src/SubcircuitLibrary/7485/3_and-cache.lib | 61 + src/SubcircuitLibrary/7485/3_and.cir | 13 + src/SubcircuitLibrary/7485/3_and.cir.out | 20 + src/SubcircuitLibrary/7485/3_and.pro | 44 + src/SubcircuitLibrary/7485/3_and.sch | 130 ++ src/SubcircuitLibrary/7485/3_and.sub | 14 + .../7485/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/7485/4_and-cache.lib | 79 ++ src/SubcircuitLibrary/7485/4_and-rescue.lib | 22 + src/SubcircuitLibrary/7485/4_and.cir | 13 + src/SubcircuitLibrary/7485/4_and.cir.out | 18 + src/SubcircuitLibrary/7485/4_and.pro | 58 + src/SubcircuitLibrary/7485/4_and.sch | 151 ++ src/SubcircuitLibrary/7485/4_and.sub | 12 + .../7485/4_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/7485/5_and-cache.lib | 79 ++ src/SubcircuitLibrary/7485/5_and.cir | 14 + src/SubcircuitLibrary/7485/5_and.cir.out | 22 + src/SubcircuitLibrary/7485/5_and.pro | 50 + src/SubcircuitLibrary/7485/5_and.sch | 171 +++ src/SubcircuitLibrary/7485/5_and.sub | 16 + .../7485/5_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/7485/5_nor-cache.lib | 95 ++ src/SubcircuitLibrary/7485/5_nor.cir | 19 + src/SubcircuitLibrary/7485/5_nor.cir.out | 42 + src/SubcircuitLibrary/7485/5_nor.pro | 73 + src/SubcircuitLibrary/7485/5_nor.sch | 275 ++++ src/SubcircuitLibrary/7485/5_nor.sub | 36 + .../7485/5_nor_Previous_Values.xml | 1 + src/SubcircuitLibrary/7485/7485-cache.lib | 177 +++ src/SubcircuitLibrary/7485/7485.cir | 42 + src/SubcircuitLibrary/7485/7485.cir.out | 101 ++ src/SubcircuitLibrary/7485/7485.pro | 43 + src/SubcircuitLibrary/7485/7485.sch | 1017 +++++++++++++ src/SubcircuitLibrary/7485/7485.sub | 95 ++ .../7485/7485_Previous_Values.xml | 1 + src/SubcircuitLibrary/7485/7485mod-cache.lib | 175 +++ src/SubcircuitLibrary/7485/7485mod.sch | 1007 +++++++++++++ src/SubcircuitLibrary/7485/analysis | 1 + src/SubcircuitLibrary/7485/c_gate-cache.lib | 95 ++ src/SubcircuitLibrary/7485/c_gate.cir | 19 + src/SubcircuitLibrary/7485/c_gate.cir.out | 42 + src/SubcircuitLibrary/7485/c_gate.pro | 57 + src/SubcircuitLibrary/7485/c_gate.sch | 246 ++++ src/SubcircuitLibrary/7485/c_gate.sub | 36 + .../7485/c_gate_Previous_Values.xml | 1 + .../9bit-Right_shift_register-cache.lib | 112 ++ .../9bit-Right_shift_register.cir | 56 + .../9bit-Right_shift_register.cir.out | 192 +++ .../9bit-Right_shift_register.pro | 85 ++ .../9bit-Right_shift_register.sch | 1495 ++++++++++++++++++++ .../9bit-Right_shift_register.sub | 186 +++ .../9bit-Right_shift_register_Previous_Values.xml | 1 + .../9bit-Right_shift_register/analysis | 1 + src/SubcircuitLibrary/AD620/AD620-cache.lib | 82 ++ src/SubcircuitLibrary/AD620/AD620.cir | 26 + src/SubcircuitLibrary/AD620/AD620.cir.out | 28 + src/SubcircuitLibrary/AD620/AD620.pro | 44 + src/SubcircuitLibrary/AD620/AD620.sch | 424 ++++++ src/SubcircuitLibrary/AD620/AD620.sub | 22 + .../AD620/AD620_Previous_Values.xml | 1 + src/SubcircuitLibrary/AD620/NPN.lib | 4 + src/SubcircuitLibrary/AD620/PNP.lib | 4 + src/SubcircuitLibrary/AD620/analysis | 1 + src/SubcircuitLibrary/AD620/lm_741-cache.lib | 119 ++ src/SubcircuitLibrary/AD620/lm_741.cir | 43 + src/SubcircuitLibrary/AD620/lm_741.cir.out | 46 + src/SubcircuitLibrary/AD620/lm_741.pro | 45 + src/SubcircuitLibrary/AD620/lm_741.sch | 697 +++++++++ src/SubcircuitLibrary/AD620/lm_741.sub | 40 + .../AD620/lm_741_Previous_Values.xml | 1 + src/SubcircuitLibrary/AD620/npn_1.lib | 29 + src/SubcircuitLibrary/AD620/pnp_1.lib | 29 + src/SubcircuitLibrary/CA3096/CA3096-cache.lib | 83 ++ src/SubcircuitLibrary/CA3096/CA3096.cir | 16 + src/SubcircuitLibrary/CA3096/CA3096.cir.out | 19 + src/SubcircuitLibrary/CA3096/CA3096.pro | 82 ++ src/SubcircuitLibrary/CA3096/CA3096.sch | 328 +++++ src/SubcircuitLibrary/CA3096/CA3096.sub | 13 + src/SubcircuitLibrary/CA3096/CA3096.xml | 191 +++ .../CA3096/CA3096_Previous_Values.xml | 1 + src/SubcircuitLibrary/CA3096/D.lib | 2 + src/SubcircuitLibrary/CA3096/NPN.lib | 4 + src/SubcircuitLibrary/CA3096/PNP.lib | 4 + src/SubcircuitLibrary/CA3096/analysis | 1 + .../CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib | 185 +++ .../CSLA_BEC1_logic/CSLA_BEC1_logic.cir | 29 + .../CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out | 56 + .../CSLA_BEC1_logic/CSLA_BEC1_logic.pro | 46 + .../CSLA_BEC1_logic/CSLA_BEC1_logic.sch | 654 +++++++++ .../CSLA_BEC1_logic/CSLA_BEC1_logic.sub | 50 + .../CSLA_BEC1_logic_Previous_Values.xml | 1 + .../CSLA_BEC1_logic/LOGIC_ADDER-cache.lib | 82 ++ .../CSLA_BEC1_logic/LOGIC_ADDER.cir | 16 + .../CSLA_BEC1_logic/LOGIC_ADDER.cir.out | 32 + .../CSLA_BEC1_logic/LOGIC_ADDER.pro | 44 + .../CSLA_BEC1_logic/LOGIC_ADDER.sch | 245 ++++ .../CSLA_BEC1_logic/LOGIC_ADDER.sub | 26 + .../LOGIC_ADDER_Previous_Values.xml | 1 + .../CSLA_BEC1_logic/MUX-cache.lib | 76 + src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir | 15 + src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out | 28 + src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro | 43 + src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch | 172 +++ src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub | 22 + .../CSLA_BEC1_logic/MUX_Previous_Values.xml | 1 + src/SubcircuitLibrary/CSLA_BEC1_logic/analysis | 1 + src/SubcircuitLibrary/IB3858/IB3858-cache.lib | 79 ++ src/SubcircuitLibrary/IB3858/IB3858.cir | 16 + src/SubcircuitLibrary/IB3858/IB3858.cir.out | 17 + src/SubcircuitLibrary/IB3858/IB3858.pro | 73 + src/SubcircuitLibrary/IB3858/IB3858.sch | 157 ++ src/SubcircuitLibrary/IB3858/IB3858.sub | 11 + .../IB3858/IB3858_Previous_Values.xml | 1 + src/SubcircuitLibrary/IB3858/analysis | 1 + src/SubcircuitLibrary/LM108/LM108-cache.lib | 120 ++ src/SubcircuitLibrary/LM108/LM108.cir | 59 + src/SubcircuitLibrary/LM108/LM108.cir.out | 63 + src/SubcircuitLibrary/LM108/LM108.pro | 83 ++ src/SubcircuitLibrary/LM108/LM108.sch | 1013 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| 75 + .../LM565/LM565_Previous_Values.xml | 1 + src/SubcircuitLibrary/LM565/NPN.lib | 4 + src/SubcircuitLibrary/LM565/PNP.lib | 4 + .../LOGIC_ADDER/LOGIC_ADDER-cache.lib | 82 ++ src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir | 16 + .../LOGIC_ADDER/LOGIC_ADDER.cir.out | 32 + src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro | 44 + src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch | 245 ++++ src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub | 26 + .../LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml | 1 + src/SubcircuitLibrary/LOGIC_ADDER/analysis | 1 + src/SubcircuitLibrary/NE566/NE566-cache.lib | 125 ++ src/SubcircuitLibrary/NE566/NE566.cir | 57 + src/SubcircuitLibrary/NE566/NE566.cir.out | 61 + src/SubcircuitLibrary/NE566/NE566.pro | 83 ++ src/SubcircuitLibrary/NE566/NE566.sch | 920 ++++++++++++ src/SubcircuitLibrary/NE566/NE566.sub | 55 + .../NE566/NE566_Previous_Values.xml | 1 + src/SubcircuitLibrary/full_sub/analysis | 1 + src/SubcircuitLibrary/full_sub/full_sub-cache.lib | 79 ++ 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src/SubcircuitLibrary/ujt/ujt-cache.lib create mode 100644 src/SubcircuitLibrary/ujt/ujt.cir create mode 100644 src/SubcircuitLibrary/ujt/ujt.cir.out create mode 100644 src/SubcircuitLibrary/ujt/ujt.pro create mode 100644 src/SubcircuitLibrary/ujt/ujt.sch create mode 100644 src/SubcircuitLibrary/ujt/ujt.sub create mode 100644 src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter-cache.lib b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter-cache.lib new file mode 100644 index 00000000..b3857f54 --- /dev/null +++ b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir new file mode 100644 index 00000000..d5d8760a --- /dev/null +++ b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir @@ -0,0 +1,13 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 22 11:44:38 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U2-Pad1_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ d_dff +U3 Net-_U3-Pad1_ Net-_U2-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U3-Pad1_ d_dff +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out new file mode 100644 index 00000000..4232f26a --- /dev/null +++ b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out @@ -0,0 +1,20 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/2bit_upcounter/2bit_upcounter.cir + +* u2 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ d_dff +* u3 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ d_dff +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ u2 +a2 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ u3 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.pro b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.pro new file mode 100644 index 00000000..7fc2f37d --- /dev/null +++ b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.pro @@ -0,0 +1,45 @@ +update=Sat Jun 22 11:40:56 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User + diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sch b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sch new file mode 100644 index 00000000..45c6e1de --- /dev/null +++ b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:2bit-Up_counter-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U2 +U 1 1 5D0DC6F1 +P 3900 3400 +F 0 "U2" H 3900 3400 60 0000 C CNN +F 1 "d_dff" H 3900 3550 60 0000 C CNN +F 2 "" H 3900 3400 60 0000 C CNN +F 3 "" H 3900 3400 60 0000 C CNN + 1 3900 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U3 +U 1 1 5D0DC6F2 +P 5750 3400 +F 0 "U3" H 5750 3400 60 0000 C CNN +F 1 "d_dff" H 5750 3550 60 0000 C CNN +F 2 "" H 5750 3400 60 0000 C CNN +F 3 "" H 5750 3400 60 0000 C CNN + 1 5750 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 2750 3900 2500 +Wire Wire Line + 3900 2500 5750 2500 +Wire Wire Line + 5750 2500 5750 2750 +Wire Wire Line + 3900 4000 3900 4300 +Wire Wire Line + 3900 4300 5750 4300 +Wire Wire Line + 5750 4300 5750 4000 +Wire Wire Line + 4850 2500 4850 4800 +Connection ~ 4850 4300 +Connection ~ 4850 2500 +Wire Wire Line + 4850 4800 5250 4800 +Wire Wire Line + 3350 3700 2600 3700 +Wire Wire Line + 3350 3050 3150 3050 +Wire Wire Line + 3150 3050 3150 2350 +Wire Wire Line + 3150 2350 4600 2350 +Wire Wire Line + 4600 2350 4600 3700 +Wire Wire Line + 4450 3700 5200 3700 +Connection ~ 4600 3700 +Wire Wire Line + 5000 3050 5200 3050 +Wire Wire Line + 5000 3050 5000 2350 +Wire Wire Line + 5000 2350 6450 2350 +Wire Wire Line + 6450 2350 6450 3700 +Wire Wire Line + 6450 3700 6300 3700 +Wire Wire Line + 4450 3050 4500 3050 +Wire Wire Line + 4500 3050 4500 2600 +Wire Wire Line + 4500 2600 6800 2600 +Wire Wire Line + 6300 3050 7050 3050 +$Comp +L PORT U1 +U 1 1 5D0DC6F3 +P 2350 3700 +F 0 "U1" H 2400 3800 30 0000 C CNN +F 1 "PORT" H 2350 3700 30 0000 C CNN +F 2 "" H 2350 3700 60 0000 C CNN +F 3 "" H 2350 3700 60 0000 C CNN + 1 2350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D0DC6F4 +P 5500 4800 +F 0 "U1" H 5550 4900 30 0000 C CNN +F 1 "PORT" H 5500 4800 30 0000 C CNN +F 2 "" H 5500 4800 60 0000 C CNN +F 3 "" H 5500 4800 60 0000 C CNN + 2 5500 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5D0DC6F5 +P 7050 2600 +F 0 "U1" H 7100 2700 30 0000 C CNN +F 1 "PORT" H 7050 2600 30 0000 C CNN +F 2 "" H 7050 2600 60 0000 C CNN +F 3 "" H 7050 2600 60 0000 C CNN + 3 7050 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5D0DC6F6 +P 7300 3050 +F 0 "U1" H 7350 3150 30 0000 C CNN +F 1 "PORT" H 7300 3050 30 0000 C CNN +F 2 "" H 7300 3050 60 0000 C CNN +F 3 "" H 7300 3050 60 0000 C CNN + 4 7300 3050 + -1 0 0 1 +$EndComp +Text Notes 2650 3650 0 60 ~ 0 +CLK +Text Notes 6600 2550 0 60 ~ 0 +O0 +Text Notes 6800 3000 0 60 ~ 0 +O1 +Text Notes 5050 4750 0 60 ~ 0 +EN\n +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sub b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sub new file mode 100644 index 00000000..f888aa71 --- /dev/null +++ b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sub @@ -0,0 +1,14 @@ +* Subcircuit 2bit_upcounter +.subckt 2bit_upcounter net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/2bit_upcounter/2bit_upcounter.cir +* u2 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ d_dff +* u3 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ d_dff +a1 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ u2 +a2 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ u3 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Control Statements + +.ends 2bit_upcounter \ No newline at end of file diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter_Previous_Values.xml b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter_Previous_Values.xml new file mode 100644 index 00000000..2daa4f78 --- /dev/null +++ b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter_Previous_Values.xml @@ -0,0 +1 @@ +d_dffd_dfftruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/2bit_upcounter/analysis b/src/SubcircuitLibrary/2bit_upcounter/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/2bit_upcounter/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib new file mode 100644 index 00000000..9d70ade9 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib @@ -0,0 +1,77 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir b/src/SubcircuitLibrary/2bitmul/2bitmul.cir new file mode 100644 index 00000000..08e3ccc8 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.cir @@ -0,0 +1,17 @@ +* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and +U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and +U3 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and +U2 Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and +X2 Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder +X1 Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT + +.end diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out new file mode 100644 index 00000000..351629fd --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out @@ -0,0 +1,31 @@ +* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir + +.include half_adder.sub +* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and +x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder +x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.pro b/src/SubcircuitLibrary/2bitmul/2bitmul.pro new file mode 100644 index 00000000..944ec056 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.pro @@ -0,0 +1,74 @@ +update=03/07/19 09:55:40 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sch b/src/SubcircuitLibrary/2bitmul/2bitmul.sch new file mode 100644 index 00000000..2629beec --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.sch @@ -0,0 +1,284 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:2bitmul-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U5 +U 1 1 5C7FC048 +P 8150 2950 +F 0 "U5" H 8150 2950 60 0000 C CNN +F 1 "d_and" H 8200 3050 60 0000 C CNN +F 2 "" H 8150 2950 60 0000 C CNN +F 3 "" H 8150 2950 60 0000 C CNN + 1 8150 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FC0BC +P 7450 2950 +F 0 "U4" H 7450 2950 60 0000 C CNN +F 1 "d_and" H 7500 3050 60 0000 C CNN +F 2 "" H 7450 2950 60 0000 C CNN +F 3 "" H 7450 2950 60 0000 C CNN + 1 7450 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5C7FC0F4 +P 6950 2950 +F 0 "U3" H 6950 2950 60 0000 C CNN +F 1 "d_and" H 7000 3050 60 0000 C CNN +F 2 "" H 6950 2950 60 0000 C CNN +F 3 "" H 6950 2950 60 0000 C CNN + 1 6950 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U2 +U 1 1 5C7FC11D +P 6400 2950 +F 0 "U2" H 6400 2950 60 0000 C CNN +F 1 "d_and" H 6450 3050 60 0000 C CNN +F 2 "" H 6400 2950 60 0000 C CNN +F 3 "" H 6400 2950 60 0000 C CNN + 1 6400 2950 + 0 1 1 0 +$EndComp +Wire Wire Line + 8150 2500 8150 2350 +Wire Wire Line + 8150 2350 7450 2350 +Wire Wire Line + 7450 2100 7450 2500 +Wire Wire Line + 6950 2500 6950 2350 +Wire Wire Line + 6950 2350 6400 2350 +Wire Wire Line + 6400 2350 6400 2500 +Wire Wire Line + 8250 1100 8250 2500 +Wire Wire Line + 8250 2250 7050 2250 +Wire Wire Line + 7050 2250 7050 2500 +Wire Wire Line + 7550 2150 7550 2500 +Wire Wire Line + 7550 2450 6500 2450 +Wire Wire Line + 6500 2450 6500 2500 +$Comp +L half_adder X2 +U 1 1 5C7FC23A +P 7200 3350 +F 0 "X2" H 8100 3850 60 0000 C CNN +F 1 "half_adder" H 8100 3750 60 0000 C CNN +F 2 "" H 7200 3350 60 0000 C CNN +F 3 "" H 7200 3350 60 0000 C CNN + 1 7200 3350 + 0 1 1 0 +$EndComp +$Comp +L half_adder X1 +U 1 1 5C7FC324 +P 6050 3350 +F 0 "X1" H 6950 3850 60 0000 C CNN +F 1 "half_adder" H 6950 3750 60 0000 C CNN +F 2 "" H 6050 3350 60 0000 C CNN +F 3 "" H 6050 3350 60 0000 C CNN + 1 6050 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 7500 3400 7900 3400 +Wire Wire Line + 7900 3400 7900 3650 +Wire Wire Line + 7000 3400 7300 3400 +Wire Wire Line + 7300 3400 7300 3650 +Wire Wire Line + 7300 4800 7050 4800 +Wire Wire Line + 7050 4800 7050 3600 +Wire Wire Line + 7050 3600 6750 3600 +Wire Wire Line + 6750 3600 6750 3650 +Wire Wire Line + 6450 3400 6450 3650 +Wire Wire Line + 6450 3650 6150 3650 +$Comp +L PORT U1 +U 5 1 5C7FC4F8 +P 8200 5300 +F 0 "U1" H 8250 5400 30 0000 C CNN +F 1 "PORT" H 8200 5300 30 0000 C CNN +F 2 "" H 8200 5300 60 0000 C CNN +F 3 "" H 8200 5300 60 0000 C CNN + 5 8200 5300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 5C7FC5D7 +P 7300 5300 +F 0 "U1" H 7350 5400 30 0000 C CNN +F 1 "PORT" H 7300 5300 30 0000 C CNN +F 2 "" H 7300 5300 60 0000 C CNN +F 3 "" H 7300 5300 60 0000 C CNN + 6 7300 5300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C7FC641 +P 6750 5150 +F 0 "U1" H 6800 5250 30 0000 C CNN +F 1 "PORT" H 6750 5150 30 0000 C CNN +F 2 "" H 6750 5150 60 0000 C CNN +F 3 "" H 6750 5150 60 0000 C CNN + 7 6750 5150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C7FC698 +P 6150 5250 +F 0 "U1" H 6200 5350 30 0000 C CNN +F 1 "PORT" H 6150 5250 30 0000 C CNN +F 2 "" H 6150 5250 60 0000 C CNN +F 3 "" H 6150 5250 60 0000 C CNN + 8 6150 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5C7FC6EC +P 8250 850 +F 0 "U1" H 8300 950 30 0000 C CNN +F 1 "PORT" H 8250 850 30 0000 C CNN +F 2 "" H 8250 850 60 0000 C CNN +F 3 "" H 8250 850 60 0000 C CNN + 1 8250 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FC815 +P 7900 850 +F 0 "U1" H 7950 950 30 0000 C CNN +F 1 "PORT" H 7900 850 30 0000 C CNN +F 2 "" H 7900 850 60 0000 C CNN +F 3 "" H 7900 850 60 0000 C CNN + 2 7900 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FC857 +P 7550 850 +F 0 "U1" H 7600 950 30 0000 C CNN +F 1 "PORT" H 7550 850 30 0000 C CNN +F 2 "" H 7550 850 60 0000 C CNN +F 3 "" H 7550 850 60 0000 C CNN + 3 7550 850 + 0 1 1 0 +$EndComp +Connection ~ 8250 2250 +Wire Wire Line + 7900 1100 7900 2150 +Wire Wire Line + 7900 2150 7550 2150 +Connection ~ 7550 2450 +Wire Wire Line + 7550 1100 7550 2100 +Wire Wire Line + 7550 2100 7450 2100 +Connection ~ 7450 2350 +Wire Wire Line + 7200 1050 7200 2100 +Wire Wire Line + 7200 2100 6800 2100 +Wire Wire Line + 6800 2100 6800 2350 +Connection ~ 6800 2350 +Wire Wire Line + 8200 3400 8200 5050 +$Comp +L PORT U1 +U 4 1 5C7FC898 +P 7200 800 +F 0 "U1" H 7250 900 30 0000 C CNN +F 1 "PORT" H 7200 800 30 0000 C CNN +F 2 "" H 7200 800 60 0000 C CNN +F 3 "" H 7200 800 60 0000 C CNN + 4 7200 800 + 0 1 1 0 +$EndComp +Wire Wire Line + 7300 5050 7300 4850 +Wire Wire Line + 7300 4850 7900 4850 +Wire Wire Line + 7900 4850 7900 4800 +Wire Wire Line + 6750 4800 6750 4900 +Wire Wire Line + 6150 4800 6150 5000 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sub b/src/SubcircuitLibrary/2bitmul/2bitmul.sub new file mode 100644 index 00000000..ce0d022d --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.sub @@ -0,0 +1,25 @@ +* Subcircuit 2bitmul +.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir +.include half_adder.sub +* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and +x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder +x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 2bitmul \ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml b/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml new file mode 100644 index 00000000..8a55af97 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_andd_andC:\esim\eSim\src\SubcircuitLibrary\half_adderC:\esim\eSim\src\SubcircuitLibrary\half_addertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/analysis b/src/SubcircuitLibrary/2bitmul/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 \ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib b/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir b/src/SubcircuitLibrary/2bitmul/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir.out b/src/SubcircuitLibrary/2bitmul/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.pro b/src/SubcircuitLibrary/2bitmul/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sch b/src/SubcircuitLibrary/2bitmul/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sub b/src/SubcircuitLibrary/2bitmul/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder \ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHzFalseVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_xord_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/3_and/3_and-cache.lib b/src/SubcircuitLibrary/3_and/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/3_and/3_and.cir b/src/SubcircuitLibrary/3_and/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/3_and/3_and.cir.out b/src/SubcircuitLibrary/3_and/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/3_and/3_and.pro b/src/SubcircuitLibrary/3_and/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/3_and/3_and.sch b/src/SubcircuitLibrary/3_and/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/3_and/3_and.sub b/src/SubcircuitLibrary/3_and/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/3_and/analysis b/src/SubcircuitLibrary/3_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/4025/4025-cache.lib b/src/SubcircuitLibrary/4025/4025-cache.lib new file mode 100644 index 00000000..dd565db9 --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4025/4025.cir b/src/SubcircuitLibrary/4025/4025.cir new file mode 100644 index 00000000..a2431c71 --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4025\4025.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:34:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U6 Net-_U3-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad6_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U4 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U4-Pad3_ d_or +U7 Net-_U4-Pad3_ Net-_U1-Pad13_ Net-_U1-Pad10_ d_nor +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U5 Net-_U2-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad9_ d_nor + +.end diff --git a/src/SubcircuitLibrary/4025/4025.cir.out b/src/SubcircuitLibrary/4025/4025.cir.out new file mode 100644 index 00000000..b22d91a3 --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4025\4025.cir + +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u6 net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad6_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u4 net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_or +* u7 net-_u4-pad3_ net-_u1-pad13_ net-_u1-pad10_ d_nor +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u5 net-_u2-pad3_ net-_u1-pad8_ net-_u1-pad9_ d_nor +a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a2 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad6_ u6 +a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4 +a4 [net-_u4-pad3_ net-_u1-pad13_ ] net-_u1-pad10_ u7 +a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a6 [net-_u2-pad3_ net-_u1-pad8_ ] net-_u1-pad9_ u5 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4025/4025.pro b/src/SubcircuitLibrary/4025/4025.pro new file mode 100644 index 00000000..3c05588e --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025.pro @@ -0,0 +1,45 @@ +update=05/31/19 09:27:16 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog +LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices +LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital +LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid +LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous +LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot +LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power +LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_PSpice +LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources +LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt +LibName12=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/4025/4025.sch b/src/SubcircuitLibrary/4025/4025.sch new file mode 100644 index 00000000..2a0cb4bc --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025.sch @@ -0,0 +1,302 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4025-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U3 +U 1 1 5CEE0A15 +P 4850 3000 +F 0 "U3" H 4850 3000 60 0000 C CNN +F 1 "d_or" H 4850 3100 60 0000 C CNN +F 2 "" H 4850 3000 60 0000 C CNN +F 3 "" H 4850 3000 60 0000 C CNN + 1 4850 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 5CEE0AE8 +P 6100 3050 +F 0 "U6" H 6100 3050 60 0000 C CNN +F 1 "d_nor" H 6150 3150 60 0000 C CNN +F 2 "" H 6100 3050 60 0000 C CNN +F 3 "" H 6100 3050 60 0000 C CNN + 1 6100 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE0B21 +P 3900 2900 +F 0 "U1" H 3950 3000 30 0000 C CNN +F 1 "PORT" H 3900 2900 30 0000 C CNN +F 2 "" H 3900 2900 60 0000 C CNN +F 3 "" H 3900 2900 60 0000 C CNN + 3 3900 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE0B4F +P 3900 3150 +F 0 "U1" H 3950 3250 30 0000 C CNN +F 1 "PORT" H 3900 3150 30 0000 C CNN +F 2 "" H 3900 3150 60 0000 C CNN +F 3 "" H 3900 3150 60 0000 C CNN + 4 3900 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE0B87 +P 5200 4450 +F 0 "U1" H 5250 4550 30 0000 C CNN +F 1 "PORT" H 5200 4450 30 0000 C CNN +F 2 "" H 5200 4450 60 0000 C CNN +F 3 "" H 5200 4450 60 0000 C CNN + 8 5200 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE0BBA +P 3900 3500 +F 0 "U1" H 3950 3600 30 0000 C CNN +F 1 "PORT" H 3900 3500 30 0000 C CNN +F 2 "" H 3900 3500 60 0000 C CNN +F 3 "" H 3900 3500 60 0000 C CNN + 11 3900 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4150 2900 4400 2900 +Wire Wire Line + 4150 3150 4300 3150 +Wire Wire Line + 4300 3150 4300 3000 +Wire Wire Line + 4300 3000 4400 3000 +Wire Wire Line + 5300 2950 5650 2950 +Wire Wire Line + 5500 3150 5650 3150 +Wire Wire Line + 5650 3150 5650 3050 +Wire Wire Line + 6550 3000 6750 3000 +$Comp +L d_or U4 +U 1 1 5CEE1CD2 +P 4850 3600 +F 0 "U4" H 4850 3600 60 0000 C CNN +F 1 "d_or" H 4850 3700 60 0000 C CNN +F 2 "" H 4850 3600 60 0000 C CNN +F 3 "" H 4850 3600 60 0000 C CNN + 1 4850 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 5CEE1CD8 +P 6100 3650 +F 0 "U7" H 6100 3650 60 0000 C CNN +F 1 "d_nor" H 6150 3750 60 0000 C CNN +F 2 "" H 6100 3650 60 0000 C CNN +F 3 "" H 6100 3650 60 0000 C CNN + 1 6100 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE1CDE +P 5250 3150 +F 0 "U1" H 5300 3250 30 0000 C CNN +F 1 "PORT" H 5250 3150 30 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 5 5250 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CEE1CE4 +P 7000 3000 +F 0 "U1" H 7050 3100 30 0000 C CNN +F 1 "PORT" H 7000 3000 30 0000 C CNN +F 2 "" H 7000 3000 60 0000 C CNN +F 3 "" H 7000 3000 60 0000 C CNN + 6 7000 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CEE1CEA +P 6950 4300 +F 0 "U1" H 7000 4400 30 0000 C CNN +F 1 "PORT" H 6950 4300 30 0000 C CNN +F 2 "" H 6950 4300 60 0000 C CNN +F 3 "" H 6950 4300 60 0000 C CNN + 9 6950 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE1CF0 +P 3900 3750 +F 0 "U1" H 3950 3850 30 0000 C CNN +F 1 "PORT" H 3900 3750 30 0000 C CNN +F 2 "" H 3900 3750 60 0000 C CNN +F 3 "" H 3900 3750 60 0000 C CNN + 12 3900 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4150 3500 4400 3500 +Wire Wire Line + 4150 3750 4300 3750 +Wire Wire Line + 4300 3750 4300 3600 +Wire Wire Line + 4300 3600 4400 3600 +Wire Wire Line + 5300 3550 5650 3550 +Wire Wire Line + 5500 3750 5650 3750 +Wire Wire Line + 5650 3750 5650 3650 +Wire Wire Line + 6550 3600 6750 3600 +$Comp +L d_or U2 +U 1 1 5CEE1F80 +P 4800 4300 +F 0 "U2" H 4800 4300 60 0000 C CNN +F 1 "d_or" H 4800 4400 60 0000 C CNN +F 2 "" H 4800 4300 60 0000 C CNN +F 3 "" H 4800 4300 60 0000 C CNN + 1 4800 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U5 +U 1 1 5CEE1F86 +P 6050 4350 +F 0 "U5" H 6050 4350 60 0000 C CNN +F 1 "d_nor" H 6100 4450 60 0000 C CNN +F 2 "" H 6050 4350 60 0000 C CNN +F 3 "" H 6050 4350 60 0000 C CNN + 1 6050 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE1F8C +P 3850 4200 +F 0 "U1" H 3900 4300 30 0000 C CNN +F 1 "PORT" H 3850 4200 30 0000 C CNN +F 2 "" H 3850 4200 60 0000 C CNN +F 3 "" H 3850 4200 60 0000 C CNN + 1 3850 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CEE1F92 +P 3850 4450 +F 0 "U1" H 3900 4550 30 0000 C CNN +F 1 "PORT" H 3850 4450 30 0000 C CNN +F 2 "" H 3850 4450 60 0000 C CNN +F 3 "" H 3850 4450 60 0000 C CNN + 2 3850 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE1F98 +P 8450 3500 +F 0 "U1" H 8500 3600 30 0000 C CNN +F 1 "PORT" H 8450 3500 30 0000 C CNN +F 2 "" H 8450 3500 60 0000 C CNN +F 3 "" H 8450 3500 60 0000 C CNN + 7 8450 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE1F9E +P 7000 3600 +F 0 "U1" H 7050 3700 30 0000 C CNN +F 1 "PORT" H 7000 3600 30 0000 C CNN +F 2 "" H 7000 3600 60 0000 C CNN +F 3 "" H 7000 3600 60 0000 C CNN + 10 7000 3600 + -1 0 0 1 +$EndComp +Wire Wire Line + 4100 4200 4350 4200 +Wire Wire Line + 4100 4450 4250 4450 +Wire Wire Line + 4250 4450 4250 4300 +Wire Wire Line + 4250 4300 4350 4300 +Wire Wire Line + 5250 4250 5600 4250 +Wire Wire Line + 5450 4450 5600 4450 +Wire Wire Line + 5600 4450 5600 4350 +Wire Wire Line + 6500 4300 6700 4300 +Wire Wire Line + 7800 3500 8200 3500 +NoConn ~ 7800 3500 +$Comp +L PORT U1 +U 13 1 5CEE2827 +P 5250 3750 +F 0 "U1" H 5300 3850 30 0000 C CNN +F 1 "PORT" H 5250 3750 30 0000 C CNN +F 2 "" H 5250 3750 60 0000 C CNN +F 3 "" H 5250 3750 60 0000 C CNN + 13 5250 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7800 3850 8200 3850 +NoConn ~ 7800 3850 +$Comp +L PORT U1 +U 14 1 5CEE289D +P 8450 3850 +F 0 "U1" H 8500 3950 30 0000 C CNN +F 1 "PORT" H 8450 3850 30 0000 C CNN +F 2 "" H 8450 3850 60 0000 C CNN +F 3 "" H 8450 3850 60 0000 C CNN + 14 8450 3850 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4025/4025.sub b/src/SubcircuitLibrary/4025/4025.sub new file mode 100644 index 00000000..867617fd --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025.sub @@ -0,0 +1,30 @@ +* Subcircuit 4025 +.subckt 4025 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\bhargav\esim\src\subcircuitlibrary\4025\4025.cir +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u6 net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad6_ d_nor +* u4 net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_or +* u7 net-_u4-pad3_ net-_u1-pad13_ net-_u1-pad10_ d_nor +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u5 net-_u2-pad3_ net-_u1-pad8_ net-_u1-pad9_ d_nor +a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a2 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad6_ u6 +a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4 +a4 [net-_u4-pad3_ net-_u1-pad13_ ] net-_u1-pad10_ u7 +a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a6 [net-_u2-pad3_ net-_u1-pad8_ ] net-_u1-pad9_ u5 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4025 \ No newline at end of file diff --git a/src/SubcircuitLibrary/4025/4025_Previous_Values.xml b/src/SubcircuitLibrary/4025/4025_Previous_Values.xml new file mode 100644 index 00000000..228a19a0 --- /dev/null +++ b/src/SubcircuitLibrary/4025/4025_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_ord_nord_ord_nord_ord_nor \ No newline at end of file diff --git a/src/SubcircuitLibrary/4025/analysis b/src/SubcircuitLibrary/4025/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4025/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/4072/4072-cache.lib b/src/SubcircuitLibrary/4072/4072-cache.lib new file mode 100644 index 00000000..a3c1c972 --- /dev/null +++ b/src/SubcircuitLibrary/4072/4072-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4072/4072.cir b/src/SubcircuitLibrary/4072/4072.cir new file mode 100644 index 00000000..0f2e56f0 --- /dev/null +++ b/src/SubcircuitLibrary/4072/4072.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4072\4072.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 10:17:30 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad5_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or +U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_or +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_or + +.end diff --git a/src/SubcircuitLibrary/4072/4072.cir.out b/src/SubcircuitLibrary/4072/4072.cir.out new file mode 100644 index 00000000..61e8e949 --- /dev/null +++ b/src/SubcircuitLibrary/4072/4072.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4072\4072.cir + +* u2 net-_u1-pad5_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_or +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_or +a1 [net-_u1-pad5_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4072/4072.pro b/src/SubcircuitLibrary/4072/4072.pro new file mode 100644 index 00000000..64662931 --- /dev/null +++ b/src/SubcircuitLibrary/4072/4072.pro @@ -0,0 +1,45 @@ +update=05/31/19 10:11:54 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog +LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices +LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital +LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid +LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous +LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot +LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power +LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_PSpice +LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources +LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt +LibName12=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/4072/4072.sch b/src/SubcircuitLibrary/4072/4072.sch new file mode 100644 index 00000000..782d3e69 --- /dev/null +++ b/src/SubcircuitLibrary/4072/4072.sch @@ -0,0 +1,334 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:4002-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5CF0AF1E +P 4750 2900 +F 0 "U2" H 4750 2900 60 0000 C CNN +F 1 "d_or" H 4750 3000 60 0000 C CNN +F 2 "" H 4750 2900 60 0000 C CNN +F 3 "" H 4750 2900 60 0000 C CNN + 1 4750 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5CF0AF1F +P 4750 3450 +F 0 "U3" H 4750 3450 60 0000 C CNN +F 1 "d_or" H 4750 3550 60 0000 C CNN +F 2 "" H 4750 3450 60 0000 C CNN +F 3 "" H 4750 3450 60 0000 C CNN + 1 4750 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 2850 5400 2850 +Wire Wire Line + 5400 2850 5400 3000 +Wire Wire Line + 5400 3000 5550 3000 +Wire Wire Line + 5200 3400 5400 3400 +Wire Wire Line + 5400 3400 5400 3100 +Wire Wire Line + 5400 3100 5550 3100 +Wire Wire Line + 5650 5350 6050 5350 +Wire Wire Line + 5650 5550 6050 5550 +Wire Wire Line + 5650 5800 6050 5800 +Wire Wire Line + 5650 6000 6050 6000 +NoConn ~ 5650 5350 +NoConn ~ 5650 5550 +NoConn ~ 5650 5800 +NoConn ~ 5650 6000 +$Comp +L PORT U1 +U 5 1 5CF0AF21 +P 3850 2800 +F 0 "U1" H 3900 2900 30 0000 C CNN +F 1 "PORT" H 3850 2800 30 0000 C CNN +F 2 "" H 3850 2800 60 0000 C CNN +F 3 "" H 3850 2800 60 0000 C CNN + 5 3850 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF0AF22 +P 3900 3050 +F 0 "U1" H 3950 3150 30 0000 C CNN +F 1 "PORT" H 3900 3050 30 0000 C CNN +F 2 "" H 3900 3050 60 0000 C CNN +F 3 "" H 3900 3050 60 0000 C CNN + 2 3900 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF0AF23 +P 3900 3250 +F 0 "U1" H 3950 3350 30 0000 C CNN +F 1 "PORT" H 3900 3250 30 0000 C CNN +F 2 "" H 3900 3250 60 0000 C CNN +F 3 "" H 3900 3250 60 0000 C CNN + 3 3900 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF0AF24 +P 3900 3550 +F 0 "U1" H 3950 3650 30 0000 C CNN +F 1 "PORT" H 3900 3550 30 0000 C CNN +F 2 "" H 3900 3550 60 0000 C CNN +F 3 "" H 3900 3550 60 0000 C CNN + 4 3900 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF0AF25 +P 6950 3050 +F 0 "U1" H 7000 3150 30 0000 C CNN +F 1 "PORT" H 6950 3050 30 0000 C CNN +F 2 "" H 6950 3050 60 0000 C CNN +F 3 "" H 6950 3050 60 0000 C CNN + 1 6950 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 4100 2800 4300 2800 +Wire Wire Line + 4150 3050 4150 2900 +Wire Wire Line + 4150 2900 4300 2900 +Wire Wire Line + 4150 3250 4300 3250 +Wire Wire Line + 4300 3250 4300 3350 +Wire Wire Line + 4150 3550 4150 3450 +Wire Wire Line + 4150 3450 4300 3450 +Wire Wire Line + 6700 3050 6450 3050 +$Comp +L d_or U4 +U 1 1 5CF0AF26 +P 4900 4100 +F 0 "U4" H 4900 4100 60 0000 C CNN +F 1 "d_or" H 4900 4200 60 0000 C CNN +F 2 "" H 4900 4100 60 0000 C CNN +F 3 "" H 4900 4100 60 0000 C CNN + 1 4900 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U5 +U 1 1 5CF0AF27 +P 4900 4650 +F 0 "U5" H 4900 4650 60 0000 C CNN +F 1 "d_or" H 4900 4750 60 0000 C CNN +F 2 "" H 4900 4650 60 0000 C CNN +F 3 "" H 4900 4650 60 0000 C CNN + 1 4900 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 4050 5550 4050 +Wire Wire Line + 5550 4050 5550 4200 +Wire Wire Line + 5550 4200 5700 4200 +Wire Wire Line + 5350 4600 5550 4600 +Wire Wire Line + 5550 4600 5550 4300 +Wire Wire Line + 5550 4300 5700 4300 +$Comp +L PORT U1 +U 9 1 5CF0AF29 +P 4000 4000 +F 0 "U1" H 4050 4100 30 0000 C CNN +F 1 "PORT" H 4000 4000 30 0000 C CNN +F 2 "" H 4000 4000 60 0000 C CNN +F 3 "" H 4000 4000 60 0000 C CNN + 9 4000 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF0AF2A +P 4050 4250 +F 0 "U1" H 4100 4350 30 0000 C CNN +F 1 "PORT" H 4050 4250 30 0000 C CNN +F 2 "" H 4050 4250 60 0000 C CNN +F 3 "" H 4050 4250 60 0000 C CNN + 10 4050 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF0AF2B +P 4050 4450 +F 0 "U1" H 4100 4550 30 0000 C CNN +F 1 "PORT" H 4050 4450 30 0000 C CNN +F 2 "" H 4050 4450 60 0000 C CNN +F 3 "" H 4050 4450 60 0000 C CNN + 11 4050 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF0AF2C +P 4050 4750 +F 0 "U1" H 4100 4850 30 0000 C CNN +F 1 "PORT" H 4050 4750 30 0000 C CNN +F 2 "" H 4050 4750 60 0000 C CNN +F 3 "" H 4050 4750 60 0000 C CNN + 12 4050 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF0AF2D +P 7100 4250 +F 0 "U1" H 7150 4350 30 0000 C CNN +F 1 "PORT" H 7100 4250 30 0000 C CNN +F 2 "" H 7100 4250 60 0000 C CNN +F 3 "" H 7100 4250 60 0000 C CNN + 13 7100 4250 + -1 0 0 1 +$EndComp +Wire Wire Line + 4250 4000 4450 4000 +Wire Wire Line + 4300 4250 4300 4100 +Wire Wire Line + 4300 4100 4450 4100 +Wire Wire Line + 4300 4450 4450 4450 +Wire Wire Line + 4450 4450 4450 4550 +Wire Wire Line + 4300 4750 4300 4650 +Wire Wire Line + 4300 4650 4450 4650 +Wire Wire Line + 6850 4250 6600 4250 +$Comp +L PORT U1 +U 6 1 5CF0AF2E +P 6300 5350 +F 0 "U1" H 6350 5450 30 0000 C CNN +F 1 "PORT" H 6300 5350 30 0000 C CNN +F 2 "" H 6300 5350 60 0000 C CNN +F 3 "" H 6300 5350 60 0000 C CNN + 6 6300 5350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CF0AF2F +P 6300 5550 +F 0 "U1" H 6350 5650 30 0000 C CNN +F 1 "PORT" H 6300 5550 30 0000 C CNN +F 2 "" H 6300 5550 60 0000 C CNN +F 3 "" H 6300 5550 60 0000 C CNN + 7 6300 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF0AF30 +P 6300 5800 +F 0 "U1" H 6350 5900 30 0000 C CNN +F 1 "PORT" H 6300 5800 30 0000 C CNN +F 2 "" H 6300 5800 60 0000 C CNN +F 3 "" H 6300 5800 60 0000 C CNN + 8 6300 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF0AF31 +P 6300 6000 +F 0 "U1" H 6350 6100 30 0000 C CNN +F 1 "PORT" H 6300 6000 30 0000 C CNN +F 2 "" H 6300 6000 60 0000 C CNN +F 3 "" H 6300 6000 60 0000 C CNN + 14 6300 6000 + -1 0 0 1 +$EndComp +$Comp +L d_or U6 +U 1 1 5CF0D6D2 +P 6000 3100 +F 0 "U6" H 6000 3100 60 0000 C CNN +F 1 "d_or" H 6000 3200 60 0000 C CNN +F 2 "" H 6000 3100 60 0000 C CNN +F 3 "" H 6000 3100 60 0000 C CNN + 1 6000 3100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U7 +U 1 1 5CF0D73F +P 6150 4300 +F 0 "U7" H 6150 4300 60 0000 C CNN +F 1 "d_or" H 6150 4400 60 0000 C CNN +F 2 "" H 6150 4300 60 0000 C CNN +F 3 "" H 6150 4300 60 0000 C CNN + 1 6150 4300 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4072/4072.sub b/src/SubcircuitLibrary/4072/4072.sub new file mode 100644 index 00000000..174ea00d --- /dev/null +++ b/src/SubcircuitLibrary/4072/4072.sub @@ -0,0 +1,30 @@ +* Subcircuit 4072 +.subckt 4072 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\bhargav\esim\src\subcircuitlibrary\4072\4072.cir +* u2 net-_u1-pad5_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_or +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_or +a1 [net-_u1-pad5_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4072 \ No newline at end of file diff --git a/src/SubcircuitLibrary/4072/4072_Previous_Values.xml b/src/SubcircuitLibrary/4072/4072_Previous_Values.xml new file mode 100644 index 00000000..0ccd120c --- /dev/null +++ b/src/SubcircuitLibrary/4072/4072_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_ord_ord_ord_ord_ord_or \ No newline at end of file diff --git a/src/SubcircuitLibrary/4072/analysis b/src/SubcircuitLibrary/4072/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4072/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/3_and-cache.lib b/src/SubcircuitLibrary/4073/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4073/3_and.cir b/src/SubcircuitLibrary/4073/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4073/3_and.cir.out b/src/SubcircuitLibrary/4073/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4073/3_and.pro b/src/SubcircuitLibrary/4073/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4073/3_and.sch b/src/SubcircuitLibrary/4073/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4073/3_and.sub b/src/SubcircuitLibrary/4073/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/4073-cache.lib b/src/SubcircuitLibrary/4073/4073-cache.lib new file mode 100644 index 00000000..e316d596 --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4073/4073.cir b/src/SubcircuitLibrary/4073/4073.cir new file mode 100644 index 00000000..7afe79fe --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and +X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and + +.end diff --git a/src/SubcircuitLibrary/4073/4073.cir.out b/src/SubcircuitLibrary/4073/4073.cir.out new file mode 100644 index 00000000..d22d0923 --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073.cir.out @@ -0,0 +1,16 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4073/4073.pro b/src/SubcircuitLibrary/4073/4073.pro new file mode 100644 index 00000000..7ed8e96e --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073.pro @@ -0,0 +1,43 @@ +update=05/31/19 16:37:06 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/src/SubcircuitLibrary/4073/4073.sch b/src/SubcircuitLibrary/4073/4073.sch new file mode 100644 index 00000000..ff6d873a --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073.sch @@ -0,0 +1,263 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5CF10AEA +P 4550 2650 +F 0 "X1" H 4650 2600 60 0000 C CNN +F 1 "3_and" H 4700 2800 60 0000 C CNN +F 2 "" H 4550 2650 60 0000 C CNN +F 3 "" H 4550 2650 60 0000 C CNN + 1 4550 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF10B72 +P 3100 2200 +F 0 "U1" H 3150 2300 30 0000 C CNN +F 1 "PORT" H 3100 2200 30 0000 C CNN +F 2 "" H 3100 2200 60 0000 C CNN +F 3 "" H 3100 2200 60 0000 C CNN + 1 3100 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF10BC9 +P 3100 2500 +F 0 "U1" H 3150 2600 30 0000 C CNN +F 1 "PORT" H 3100 2500 30 0000 C CNN +F 2 "" H 3100 2500 60 0000 C CNN +F 3 "" H 3100 2500 60 0000 C CNN + 2 3100 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF10BEA +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 8 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF10C10 +P 6200 2600 +F 0 "U1" H 6250 2700 30 0000 C CNN +F 1 "PORT" H 6200 2600 30 0000 C CNN +F 2 "" H 6200 2600 60 0000 C CNN +F 3 "" H 6200 2600 60 0000 C CNN + 9 6200 2600 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2600 5050 2600 +Wire Wire Line + 4200 2500 4200 2200 +Wire Wire Line + 4200 2200 3350 2200 +Wire Wire Line + 3350 2500 3850 2500 +Wire Wire Line + 3850 2500 3850 2600 +Wire Wire Line + 3850 2600 4200 2600 +Wire Wire Line + 4200 2700 4200 2850 +Wire Wire Line + 4200 2850 3350 2850 +$Comp +L 3_and X3 +U 1 1 5CF10DE5 +P 4600 4100 +F 0 "X3" H 4700 4050 60 0000 C CNN +F 1 "3_and" H 4750 4250 60 0000 C CNN +F 2 "" H 4600 4100 60 0000 C CNN +F 3 "" H 4600 4100 60 0000 C CNN + 1 4600 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF10DEB +P 3150 3650 +F 0 "U1" H 3200 3750 30 0000 C CNN +F 1 "PORT" H 3150 3650 30 0000 C CNN +F 2 "" H 3150 3650 60 0000 C CNN +F 3 "" H 3150 3650 60 0000 C CNN + 3 3150 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF10DF1 +P 3150 3950 +F 0 "U1" H 3200 4050 30 0000 C CNN +F 1 "PORT" H 3150 3950 30 0000 C CNN +F 2 "" H 3150 3950 60 0000 C CNN +F 3 "" H 3150 3950 60 0000 C CNN + 4 3150 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF10DF7 +P 3150 4300 +F 0 "U1" H 3200 4400 30 0000 C CNN +F 1 "PORT" H 3150 4300 30 0000 C CNN +F 2 "" H 3150 4300 60 0000 C CNN +F 3 "" H 3150 4300 60 0000 C CNN + 5 3150 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF10DFD +P 6250 4050 +F 0 "U1" H 6300 4150 30 0000 C CNN +F 1 "PORT" H 6250 4050 30 0000 C CNN +F 2 "" H 6250 4050 60 0000 C CNN +F 3 "" H 6250 4050 60 0000 C CNN + 6 6250 4050 + -1 0 0 1 +$EndComp +Wire Wire Line + 6000 4050 5100 4050 +Wire Wire Line + 4250 3950 4250 3650 +Wire Wire Line + 4250 3650 3400 3650 +Wire Wire Line + 3400 3950 3900 3950 +Wire Wire Line + 3900 3950 3900 4050 +Wire Wire Line + 3900 4050 4250 4050 +Wire Wire Line + 4250 4150 4250 4300 +Wire Wire Line + 4250 4300 3400 4300 +$Comp +L 3_and X2 +U 1 1 5CF10E9C +P 4550 5450 +F 0 "X2" H 4650 5400 60 0000 C CNN +F 1 "3_and" H 4700 5600 60 0000 C CNN +F 2 "" H 4550 5450 60 0000 C CNN +F 3 "" H 4550 5450 60 0000 C CNN + 1 4550 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF10EA2 +P 3100 5000 +F 0 "U1" H 3150 5100 30 0000 C CNN +F 1 "PORT" H 3100 5000 30 0000 C CNN +F 2 "" H 3100 5000 60 0000 C CNN +F 3 "" H 3100 5000 60 0000 C CNN + 11 3100 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF10EA8 +P 3100 5300 +F 0 "U1" H 3150 5400 30 0000 C CNN +F 1 "PORT" H 3100 5300 30 0000 C CNN +F 2 "" H 3100 5300 60 0000 C CNN +F 3 "" H 3100 5300 60 0000 C CNN + 12 3100 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF10EAE +P 3100 5650 +F 0 "U1" H 3150 5750 30 0000 C CNN +F 1 "PORT" H 3100 5650 30 0000 C CNN +F 2 "" H 3100 5650 60 0000 C CNN +F 3 "" H 3100 5650 60 0000 C CNN + 13 3100 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF10EB4 +P 6200 5400 +F 0 "U1" H 6250 5500 30 0000 C CNN +F 1 "PORT" H 6200 5400 30 0000 C CNN +F 2 "" H 6200 5400 60 0000 C CNN +F 3 "" H 6200 5400 60 0000 C CNN + 10 6200 5400 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 5400 5050 5400 +Wire Wire Line + 4200 5300 4200 5000 +Wire Wire Line + 4200 5000 3350 5000 +Wire Wire Line + 3350 5300 3850 5300 +Wire Wire Line + 3850 5300 3850 5400 +Wire Wire Line + 3850 5400 4200 5400 +Wire Wire Line + 4200 5500 4200 5650 +Wire Wire Line + 4200 5650 3350 5650 +$Comp +L PORT U1 +U 7 1 5CF11A2A +P 7500 4100 +F 0 "U1" H 7550 4200 30 0000 C CNN +F 1 "PORT" H 7500 4100 30 0000 C CNN +F 2 "" H 7500 4100 60 0000 C CNN +F 3 "" H 7500 4100 60 0000 C CNN + 7 7500 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF11A8A +P 7550 4600 +F 0 "U1" H 7600 4700 30 0000 C CNN +F 1 "PORT" H 7550 4600 30 0000 C CNN +F 2 "" H 7550 4600 60 0000 C CNN +F 3 "" H 7550 4600 60 0000 C CNN + 14 7550 4600 + -1 0 0 1 +$EndComp +NoConn ~ 7250 4100 +NoConn ~ 7300 4600 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4073/4073.sub b/src/SubcircuitLibrary/4073/4073.sub new file mode 100644 index 00000000..b10679cc --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073.sub @@ -0,0 +1,10 @@ +* Subcircuit 4073 +.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +* Control Statements + +.ends 4073 \ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/4073_Previous_Values.xml b/src/SubcircuitLibrary/4073/4073_Previous_Values.xml new file mode 100644 index 00000000..5acac768 --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/analysis b/src/SubcircuitLibrary/4073/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4073/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib new file mode 100644 index 00000000..a3c1c972 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir b/src/SubcircuitLibrary/4_OR/4_OR.cir new file mode 100644 index 00000000..7adbf177 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir.out b/src/SubcircuitLibrary/4_OR/4_OR.cir.out new file mode 100644 index 00000000..4388b975 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_OR/4_OR.pro b/src/SubcircuitLibrary/4_OR/4_OR.pro new file mode 100644 index 00000000..1e19b3a7 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR.pro @@ -0,0 +1,45 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sch b/src/SubcircuitLibrary/4_OR/4_OR.sch new file mode 100644 index 00000000..2f28896c --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sub b/src/SubcircuitLibrary/4_OR/4_OR.sub new file mode 100644 index 00000000..53fc8b33 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_OR/analysis b/src/SubcircuitLibrary/4_OR/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/3_and-cache.lib b/src/SubcircuitLibrary/4_and/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_and/3_and.cir b/src/SubcircuitLibrary/4_and/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_and/3_and.cir.out b/src/SubcircuitLibrary/4_and/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_and/3_and.pro b/src/SubcircuitLibrary/4_and/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4_and/3_and.sch b/src/SubcircuitLibrary/4_and/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_and/3_and.sub b/src/SubcircuitLibrary/4_and/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/4_and-cache.lib b/src/SubcircuitLibrary/4_and/4_and-cache.lib new file mode 100644 index 00000000..cb84d8f2 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_and/4_and-rescue.lib b/src/SubcircuitLibrary/4_and/4_and-rescue.lib new file mode 100644 index 00000000..6b2c17f7 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_and/4_and.cir b/src/SubcircuitLibrary/4_and/4_and.cir new file mode 100644 index 00000000..35e46097 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_and/4_and.cir.out b/src/SubcircuitLibrary/4_and/4_and.cir.out new file mode 100644 index 00000000..6e35b18a --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_and/4_and.pro b/src/SubcircuitLibrary/4_and/4_and.pro new file mode 100644 index 00000000..814ad76a --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.pro @@ -0,0 +1,58 @@ +update=06/01/19 15:08:42 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/4_and/4_and.sch b/src/SubcircuitLibrary/4_and/4_and.sch new file mode 100644 index 00000000..2d8296d4 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_and/4_and.sub b/src/SubcircuitLibrary/4_and/4_and.sub new file mode 100644 index 00000000..bf20b628 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml b/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/analysis b/src/SubcircuitLibrary/4_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib b/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.cir b/src/SubcircuitLibrary/4_bit_FA/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out b/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.pro b/src/SubcircuitLibrary/4_bit_FA/3_and.pro new file mode 100644 index 00000000..1b535492 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.sch b/src/SubcircuitLibrary/4_bit_FA/3_and.sch new file mode 100644 index 00000000..6c8d3d4a --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.sub b/src/SubcircuitLibrary/4_bit_FA/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib new file mode 100644 index 00000000..a3c1c972 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir new file mode 100644 index 00000000..7adbf177 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out new file mode 100644 index 00000000..4388b975 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.pro b/src/SubcircuitLibrary/4_bit_FA/4_OR.pro new file mode 100644 index 00000000..8bd4bbf5 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.pro @@ -0,0 +1,45 @@ +update=03/28/19 22:43:48 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sch b/src/SubcircuitLibrary/4_bit_FA/4_OR.sch new file mode 100644 index 00000000..2f28896c --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sub b/src/SubcircuitLibrary/4_bit_FA/4_OR.sub new file mode 100644 index 00000000..53fc8b33 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml new file mode 100644 index 00000000..23698d37 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_ord_ord_or \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib new file mode 100644 index 00000000..4cf915be --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.cir b/src/SubcircuitLibrary/4_bit_FA/4_and.cir new file mode 100644 index 00000000..25e839cd --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out new file mode 100644 index 00000000..6e35b18a --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.pro b/src/SubcircuitLibrary/4_bit_FA/4_and.pro new file mode 100644 index 00000000..cc0f1b93 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and.pro @@ -0,0 +1,57 @@ +update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.sch b/src/SubcircuitLibrary/4_bit_FA/4_and.sch new file mode 100644 index 00000000..bcc3cecf --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.sub b/src/SubcircuitLibrary/4_bit_FA/4_and.sub new file mode 100644 index 00000000..bf20b628 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib new file mode 100644 index 00000000..f787854a --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib @@ -0,0 +1,172 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 3900 3050 60 H V C CNN +F1 "4_OR" 3900 3250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900 +A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150 +A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150 +P 2 0 1 0 3550 2900 3900 2900 N +P 2 0 1 0 3550 3400 3900 3400 N +X in1 1 3400 3300 200 R 50 50 1 1 I +X in2 2 3400 3200 200 R 50 50 1 1 I +X in3 3 3400 3100 200 R 50 50 1 1 I +X in4 4 3400 3000 200 R 50 50 1 1 I +X out 5 4300 3150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir new file mode 100644 index 00000000..8fe97f7e --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir @@ -0,0 +1,48 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_bit_FA\4_bit_FA.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:04:20 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U16-Pad2_ d_or +U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U24-Pad2_ d_and +U4 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U17-Pad2_ d_or +U5 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U26-Pad2_ d_and +U6 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U18-Pad2_ d_or +U7 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U10-Pad2_ d_and +U8 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad1_ d_or +U9 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U31-Pad2_ d_and +U16 Net-_U1-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and +U24 Net-_U16-Pad3_ Net-_U24-Pad2_ Net-_U17-Pad1_ d_or +U33 Net-_U23-Pad2_ Net-_U24-Pad2_ Net-_U33-Pad3_ d_or +U23 Net-_U16-Pad2_ Net-_U23-Pad2_ d_inverter +U38 Net-_U1-Pad1_ Net-_U33-Pad3_ Net-_U38-Pad3_ d_xor +U42 Net-_U38-Pad3_ Net-_U1-Pad13_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and +U26 Net-_U17-Pad3_ Net-_U26-Pad2_ Net-_U18-Pad1_ d_or +U34 Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U34-Pad3_ d_or +U25 Net-_U17-Pad2_ Net-_U25-Pad2_ d_inverter +U39 Net-_U17-Pad1_ Net-_U34-Pad3_ Net-_U39-Pad3_ d_xor +U44 Net-_U39-Pad3_ Net-_U1-Pad10_ d_inverter +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +U28 Net-_U18-Pad3_ Net-_U10-Pad2_ Net-_U28-Pad3_ d_or +U35 Net-_U27-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad3_ d_or +U27 Net-_U18-Pad2_ Net-_U27-Pad2_ d_inverter +U40 Net-_U18-Pad1_ Net-_U35-Pad3_ Net-_U40-Pad3_ d_xor +U45 Net-_U40-Pad3_ Net-_U1-Pad11_ d_inverter +U31 Net-_U21-Pad2_ Net-_U31-Pad2_ Net-_U31-Pad3_ d_or +U21 Net-_U10-Pad1_ Net-_U21-Pad2_ d_inverter +U37 Net-_U28-Pad3_ Net-_U31-Pad3_ Net-_U37-Pad3_ d_xor +U43 Net-_U37-Pad3_ Net-_U1-Pad12_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U32 Net-_U1-Pad1_ Net-_U32-Pad2_ Net-_U32-Pad3_ d_and +U41 Net-_U32-Pad3_ Net-_U41-Pad2_ Net-_U1-Pad14_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +X1 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_U16-Pad2_ Net-_U32-Pad2_ 4_and +X4 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U26-Pad2_ Net-_X3-Pad3_ 3_and +X2 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_U24-Pad2_ Net-_X2-Pad5_ 4_and +X3 Net-_U31-Pad2_ Net-_U10-Pad3_ Net-_X3-Pad3_ Net-_X2-Pad5_ Net-_U41-Pad2_ 4_OR + +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out new file mode 100644 index 00000000..4d05d64a --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out @@ -0,0 +1,151 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir + +.include 4_and.sub +.include 3_and.sub +.include 4_OR.sub +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and +* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or +* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and +* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or +* u7 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and +* u8 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or +* u9 net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and +* u16 net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u24 net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or +* u33 net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or +* u23 net-_u16-pad2_ net-_u23-pad2_ d_inverter +* u38 net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor +* u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u26 net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or +* u34 net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or +* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter +* u39 net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor +* u44 net-_u39-pad3_ net-_u1-pad10_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u28 net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or +* u35 net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or +* u27 net-_u18-pad2_ net-_u27-pad2_ d_inverter +* u40 net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor +* u45 net-_u40-pad3_ net-_u1-pad11_ d_inverter +* u31 net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or +* u21 net-_u10-pad1_ net-_u21-pad2_ d_inverter +* u37 net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor +* u43 net-_u37-pad3_ net-_u1-pad12_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u32 net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and +* u41 net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and +x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and +x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and +x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3 +a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4 +a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5 +a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6 +a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7 +a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8 +a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9 +a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24 +a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33 +a12 net-_u16-pad2_ net-_u23-pad2_ u23 +a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38 +a14 net-_u38-pad3_ net-_u1-pad13_ u42 +a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26 +a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34 +a18 net-_u17-pad2_ net-_u25-pad2_ u25 +a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39 +a20 net-_u39-pad3_ net-_u1-pad10_ u44 +a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28 +a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35 +a24 net-_u18-pad2_ net-_u27-pad2_ u27 +a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40 +a26 net-_u40-pad3_ net-_u1-pad11_ u45 +a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31 +a28 net-_u10-pad1_ net-_u21-pad2_ u21 +a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37 +a30 net-_u37-pad3_ net-_u1-pad12_ u43 +a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro new file mode 100644 index 00000000..2d0c38b5 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro @@ -0,0 +1,58 @@ +update=03/28/19 23:02:17 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_User +LibName25=eSim_Subckt diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch new file mode 100644 index 00000000..d3507ac7 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch @@ -0,0 +1,945 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4_bit_FA-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C963B95 +P 3050 3050 +F 0 "U2" H 3050 3050 60 0000 C CNN +F 1 "d_or" H 3050 3150 60 0000 C CNN +F 2 "" H 3050 3050 60 0000 C CNN +F 3 "" H 3050 3050 60 0000 C CNN + 1 3050 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C963C4C +P 3050 3450 +F 0 "U3" H 3050 3450 60 0000 C CNN +F 1 "d_and" H 3100 3550 60 0000 C CNN +F 2 "" H 3050 3450 60 0000 C CNN +F 3 "" H 3050 3450 60 0000 C CNN + 1 3050 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C963CD9 +P 3050 4000 +F 0 "U4" H 3050 4000 60 0000 C CNN +F 1 "d_or" H 3050 4100 60 0000 C CNN +F 2 "" H 3050 4000 60 0000 C CNN +F 3 "" H 3050 4000 60 0000 C CNN + 1 3050 4000 + 1 0 0 -1 +$EndComp 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6100 0 60 ~ 12 +S3 +Text Notes 10050 1450 0 60 ~ 12 +Cout\n +Text Notes 2250 750 0 60 ~ 12 +Cin\n +Text Notes 2050 2950 0 60 ~ 12 +A0\n +Text Notes 2050 3450 0 60 ~ 12 +B0\n +Text Notes 2050 3900 0 60 ~ 12 +A1 +Text Notes 2050 4400 0 60 ~ 12 +B1 +Text Notes 2050 4750 0 60 ~ 12 +A2 +Text Notes 2050 5250 0 60 ~ 12 +B2 +Text Notes 2100 5700 0 60 ~ 12 +A3 +Text Notes 2150 6200 0 60 ~ 12 +B3 +$Comp +L 4_and X1 +U 1 1 5C9D037C +P 4400 2250 +F 0 "X1" H 5900 3300 60 0000 C CNN +F 1 "4_and" H 5950 3450 60 0000 C CNN +F 2 "" H 4400 2250 60 0000 C CNN +F 3 "" H 4400 2250 60 0000 C CNN + 1 4400 2250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 5C9D0A45 +P 5500 2400 +F 0 "X4" H 6400 2700 60 0000 C CNN +F 1 "3_and" H 6450 2900 60 0000 C CNN +F 2 "" H 5500 2400 60 0000 C CNN +F 3 "" H 5500 2400 60 0000 C CNN + 1 5500 2400 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 5C9D0E20 +P 4400 3450 +F 0 "X2" H 5900 4500 60 0000 C CNN +F 1 "4_and" H 5950 4650 60 0000 C CNN +F 2 "" H 4400 3450 60 0000 C CNN +F 3 "" H 4400 3450 60 0000 C CNN + 1 4400 3450 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X3 +U 1 1 5C9D1513 +P 4450 4900 +F 0 "X3" H 8350 7950 60 0000 C CNN +F 1 "4_OR" H 8350 8150 60 0000 C CNN +F 2 "" H 4450 4900 60 0000 C CNN +F 3 "" H 4450 4900 60 0000 C CNN + 1 4450 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8950 1750 8750 1750 +Wire Wire Line + 7150 1500 7850 1500 +Wire Wire Line + 7850 1500 7850 1600 +Wire Wire Line + 7550 1600 7550 1700 +Wire Wire Line + 7550 1700 7850 1700 +Wire Wire Line + 6800 2000 6800 1800 +Wire Wire Line + 6800 1800 7850 1800 +Wire Wire Line + 6350 2350 7850 2350 +Wire Wire Line + 7850 2350 7850 1900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub new file mode 100644 index 00000000..2f2bc4ef --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub @@ -0,0 +1,145 @@ +* Subcircuit 4_bit_FA +.subckt 4_bit_FA net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir +.include 4_and.sub +.include 3_and.sub +.include 4_OR.sub +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and +* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or +* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and +* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or +* u7 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and +* u8 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or +* u9 net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and +* u16 net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u24 net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or +* u33 net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or +* u23 net-_u16-pad2_ net-_u23-pad2_ d_inverter +* u38 net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor +* u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u26 net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or +* u34 net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or +* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter +* u39 net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor +* u44 net-_u39-pad3_ net-_u1-pad10_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u28 net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or +* u35 net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or +* u27 net-_u18-pad2_ net-_u27-pad2_ d_inverter +* u40 net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor +* u45 net-_u40-pad3_ net-_u1-pad11_ d_inverter +* u31 net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or +* u21 net-_u10-pad1_ net-_u21-pad2_ d_inverter +* u37 net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor +* u43 net-_u37-pad3_ net-_u1-pad12_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u32 net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and +* u41 net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or +x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and +x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and +x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and +x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3 +a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4 +a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5 +a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6 +a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7 +a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8 +a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9 +a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24 +a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33 +a12 net-_u16-pad2_ net-_u23-pad2_ u23 +a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38 +a14 net-_u38-pad3_ net-_u1-pad13_ u42 +a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26 +a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34 +a18 net-_u17-pad2_ net-_u25-pad2_ u25 +a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39 +a20 net-_u39-pad3_ net-_u1-pad10_ u44 +a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28 +a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35 +a24 net-_u18-pad2_ net-_u27-pad2_ u27 +a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40 +a26 net-_u40-pad3_ net-_u1-pad11_ u45 +a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31 +a28 net-_u10-pad1_ net-_u21-pad2_ u21 +a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37 +a30 net-_u37-pad3_ net-_u1-pad12_ u43 +a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_bit_FA \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml new file mode 100644 index 00000000..49a53e5c --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_andd_ord_andd_ord_andd_ord_andd_andd_ord_ord_inverterd_xord_inverterd_andd_ord_ord_inverterd_xord_inverterd_andd_ord_ord_inverterd_xord_inverterd_ord_inverterd_xord_inverterd_andd_andd_andd_andd_andd_andd_andd_andd_andd_ord_ord_ord_andd_orC:\Users\malli\eSim\src\SubcircuitLibrary\4_andC:\Users\malli\eSim\src\SubcircuitLibrary\4_ORC:\Users\malli\eSim\src\SubcircuitLibrary\4_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/analysis b/src/SubcircuitLibrary/4_bit_FA/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir b/src/SubcircuitLibrary/4to16_demux/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir.out b/src/SubcircuitLibrary/4to16_demux/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.pro b/src/SubcircuitLibrary/4to16_demux/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sch b/src/SubcircuitLibrary/4to16_demux/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sub b/src/SubcircuitLibrary/4to16_demux/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib b/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib new file mode 100644 index 00000000..898ea926 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_nand +# +DEF 5_nand X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_nand" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir new file mode 100644 index 00000000..c97c2f8b --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir @@ -0,0 +1,32 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 17:01:07 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad23_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad22_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad21_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad20_ Net-_U6-Pad2_ d_inverter +U2 Net-_U1-Pad19_ Net-_U1-Pad18_ Net-_U2-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ ? Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ ? PORT +X1 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad1_ 5_nand +X2 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad2_ 5_nand +X3 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad3_ 5_nand +X4 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad4_ 5_nand +X5 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad5_ 5_nand +X6 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad6_ 5_nand +X7 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad7_ 5_nand +X8 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad8_ 5_nand +X9 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad9_ 5_nand +X10 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad10_ 5_nand +X11 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad11_ 5_nand +X12 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad13_ 5_nand +X13 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad14_ 5_nand +X14 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad15_ 5_nand +X15 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad16_ 5_nand +X16 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad17_ 5_nand + +.end diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out new file mode 100644 index 00000000..eecdfb06 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out @@ -0,0 +1,49 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir + +.include 5_nand.sub +* u3 net-_u1-pad23_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad22_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad21_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad20_ net-_u6-pad2_ d_inverter +* u2 net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? port +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand +x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand +x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand +x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand +x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand +x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand +x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand +x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand +x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand +x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand +x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand +x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand +x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand +x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand +x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand +x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand +a1 net-_u1-pad23_ net-_u3-pad2_ u3 +a2 net-_u1-pad22_ net-_u4-pad2_ u4 +a3 net-_u1-pad21_ net-_u5-pad2_ u5 +a4 net-_u1-pad20_ net-_u6-pad2_ u6 +a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro b/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro new file mode 100644 index 00000000..5a167cd9 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro @@ -0,0 +1,43 @@ +update=Fri Jun 21 16:58:10 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_User +LibName10=eSim_Subckt diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch new file mode 100644 index 00000000..c9142e27 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch @@ -0,0 +1,889 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4to16_demux-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 5CF2315F +P 4700 1900 +F 0 "U3" H 4700 1800 60 0000 C CNN +F 1 "d_inverter" H 4700 2050 60 0000 C CNN +F 2 "" H 4750 1850 60 0000 C CNN +F 3 "" H 4750 1850 60 0000 C CNN + 1 4700 1900 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF231D7 +P 5600 1850 +F 0 "U4" H 5600 1750 60 0000 C CNN +F 1 "d_inverter" H 5600 2000 60 0000 C CNN +F 2 "" H 5650 1800 60 0000 C CNN +F 3 "" H 5650 1800 60 0000 C CNN + 1 5600 1850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5CF23245 +P 6550 1850 +F 0 "U5" H 6550 1750 60 0000 C CNN +F 1 "d_inverter" H 6550 2000 60 0000 C CNN +F 2 "" H 6600 1800 60 0000 C CNN +F 3 "" H 6600 1800 60 0000 C CNN + 1 6550 1850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5CF232B2 +P 7500 1800 +F 0 "U6" H 7500 1700 60 0000 C CNN +F 1 "d_inverter" H 7500 1950 60 0000 C CNN +F 2 "" H 7550 1750 60 0000 C CNN +F 3 "" H 7550 1750 60 0000 C CNN + 1 7500 1800 + 0 1 1 0 +$EndComp +Text Notes 1300 5450 0 60 ~ 0 +~Y0 +Text Notes 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C CNN +F 3 "" H 3800 4850 60 0000 C CNN + 1 3800 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X6 +U 1 1 5D0CCBF6 +P 4350 4850 +F 0 "X6" H 4400 4750 60 0000 C CNN +F 1 "5_nand" H 4450 5000 60 0000 C CNN +F 2 "" H 4350 4850 60 0000 C CNN +F 3 "" H 4350 4850 60 0000 C CNN + 1 4350 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X7 +U 1 1 5D0CCC81 +P 4900 4850 +F 0 "X7" H 4950 4750 60 0000 C CNN +F 1 "5_nand" H 5000 5000 60 0000 C CNN +F 2 "" H 4900 4850 60 0000 C CNN +F 3 "" H 4900 4850 60 0000 C CNN + 1 4900 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X8 +U 1 1 5D0CCD0B +P 5450 4850 +F 0 "X8" H 5500 4750 60 0000 C CNN +F 1 "5_nand" H 5550 5000 60 0000 C CNN +F 2 "" H 5450 4850 60 0000 C CNN +F 3 "" H 5450 4850 60 0000 C CNN + 1 5450 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X9 +U 1 1 5D0CCE34 +P 6000 4850 +F 0 "X9" H 6050 4750 60 0000 C CNN +F 1 "5_nand" H 6100 5000 60 0000 C CNN +F 2 "" H 6000 4850 60 0000 C CNN +F 3 "" H 6000 4850 60 0000 C CNN + 1 6000 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X10 +U 1 1 5D0CCECA +P 6600 4850 +F 0 "X10" H 6650 4750 60 0000 C CNN +F 1 "5_nand" H 6700 5000 60 0000 C CNN +F 2 "" H 6600 4850 60 0000 C CNN +F 3 "" H 6600 4850 60 0000 C CNN + 1 6600 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X11 +U 1 1 5D0CCF63 +P 7150 4850 +F 0 "X11" H 7200 4750 60 0000 C CNN +F 1 "5_nand" H 7250 5000 60 0000 C CNN +F 2 "" H 7150 4850 60 0000 C CNN +F 3 "" H 7150 4850 60 0000 C CNN + 1 7150 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X12 +U 1 1 5D0CD07D +P 7700 4850 +F 0 "X12" H 7750 4750 60 0000 C CNN +F 1 "5_nand" H 7800 5000 60 0000 C CNN +F 2 "" H 7700 4850 60 0000 C CNN +F 3 "" H 7700 4850 60 0000 C CNN + 1 7700 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X13 +U 1 1 5D0CD124 +P 8250 4850 +F 0 "X13" H 8300 4750 60 0000 C CNN +F 1 "5_nand" H 8350 5000 60 0000 C CNN +F 2 "" H 8250 4850 60 0000 C CNN +F 3 "" H 8250 4850 60 0000 C CNN + 1 8250 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X14 +U 1 1 5D0CD1C6 +P 8800 4850 +F 0 "X14" H 8850 4750 60 0000 C CNN +F 1 "5_nand" H 8900 5000 60 0000 C CNN +F 2 "" H 8800 4850 60 0000 C CNN +F 3 "" H 8800 4850 60 0000 C CNN + 1 8800 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X15 +U 1 1 5D0CD348 +P 9350 4850 +F 0 "X15" H 9400 4750 60 0000 C CNN +F 1 "5_nand" H 9450 5000 60 0000 C CNN +F 2 "" H 9350 4850 60 0000 C CNN +F 3 "" H 9350 4850 60 0000 C CNN + 1 9350 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X16 +U 1 1 5D0CD3EE +P 9900 4850 +F 0 "X16" H 9950 4750 60 0000 C CNN +F 1 "5_nand" H 10000 5000 60 0000 C CNN +F 2 "" H 9900 4850 60 0000 C CNN +F 3 "" H 9900 4850 60 0000 C CNN + 1 9900 4850 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub new file mode 100644 index 00000000..4f7595da --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub @@ -0,0 +1,43 @@ +* Subcircuit 4to16_demux +.subckt 4to16_demux net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir +.include 5_nand.sub +* u3 net-_u1-pad23_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad22_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad21_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad20_ net-_u6-pad2_ d_inverter +* u2 net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand +x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand +x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand +x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand +x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand +x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand +x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand +x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand +x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand +x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand +x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand +x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand +x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand +x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand +x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand +x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand +a1 net-_u1-pad23_ net-_u3-pad2_ u3 +a2 net-_u1-pad22_ net-_u4-pad2_ u4 +a3 net-_u1-pad21_ net-_u5-pad2_ u5 +a4 net-_u1-pad20_ net-_u6-pad2_ u6 +a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4to16_demux \ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml new file mode 100644 index 00000000..93c6f25a --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterd_inverterd_inverterd_nor/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nandtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib new file mode 100644 index 00000000..4cf915be --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir b/src/SubcircuitLibrary/4to16_demux/5_and.cir new file mode 100644 index 00000000..ca1199bd --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir.out b/src/SubcircuitLibrary/4to16_demux/5_and.cir.out new file mode 100644 index 00000000..20d3f8a5 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.pro b/src/SubcircuitLibrary/4to16_demux/5_and.pro new file mode 100644 index 00000000..a9d6304f --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sch b/src/SubcircuitLibrary/4to16_demux/5_and.sch new file mode 100644 index 00000000..0d86cdec --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sub b/src/SubcircuitLibrary/4to16_demux/5_and.sub new file mode 100644 index 00000000..9d929fcb --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib b/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib new file mode 100644 index 00000000..cb517be1 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib @@ -0,0 +1,78 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.cir b/src/SubcircuitLibrary/4to16_demux/5_nand.cir new file mode 100644 index 00000000..e833d0f4 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand.cir @@ -0,0 +1,13 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and +U2 Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out b/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out new file mode 100644 index 00000000..164de911 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out @@ -0,0 +1,18 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir + +.include 5_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and +* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 net-_u2-pad1_ net-_u1-pad6_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.pro b/src/SubcircuitLibrary/4to16_demux/5_nand.pro new file mode 100644 index 00000000..b7d23f44 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand.pro @@ -0,0 +1,83 @@ +update=Fri Jun 21 16:46:10 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName41=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName42=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName43=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName44=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName45=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName46=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName47=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName48=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User + diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.sch b/src/SubcircuitLibrary/4to16_demux/5_nand.sch new file mode 100644 index 00000000..86379b08 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand.sch @@ -0,0 +1,175 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5D0CBD44 +P 4150 3700 +F 0 "X1" H 4200 3600 60 0000 C CNN +F 1 "5_and" H 4250 3850 60 0000 C CNN +F 2 "" H 4150 3700 60 0000 C CNN +F 3 "" H 4150 3700 60 0000 C CNN + 1 4150 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5D0CBD97 +P 5150 3700 +F 0 "U2" H 5150 3600 60 0000 C CNN +F 1 "d_inverter" H 5150 3850 60 0000 C CNN +F 2 "" H 5200 3650 60 0000 C CNN +F 3 "" H 5200 3650 60 0000 C CNN + 1 5150 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5D0CBDBE +P 2900 2900 +F 0 "U1" H 2950 3000 30 0000 C CNN +F 1 "PORT" H 2900 2900 30 0000 C CNN +F 2 "" H 2900 2900 60 0000 C CNN +F 3 "" H 2900 2900 60 0000 C CNN + 1 2900 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D0CBDF4 +P 2900 3150 +F 0 "U1" H 2950 3250 30 0000 C CNN +F 1 "PORT" H 2900 3150 30 0000 C CNN +F 2 "" H 2900 3150 60 0000 C CNN +F 3 "" H 2900 3150 60 0000 C CNN + 2 2900 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5D0CBE16 +P 2900 3400 +F 0 "U1" H 2950 3500 30 0000 C CNN +F 1 "PORT" H 2900 3400 30 0000 C CNN +F 2 "" H 2900 3400 60 0000 C CNN +F 3 "" H 2900 3400 60 0000 C CNN + 3 2900 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5D0CBE3F +P 2900 3750 +F 0 "U1" H 2950 3850 30 0000 C CNN +F 1 "PORT" H 2900 3750 30 0000 C CNN +F 2 "" H 2900 3750 60 0000 C CNN +F 3 "" H 2900 3750 60 0000 C CNN + 4 2900 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5D0CBE6B +P 2900 4150 +F 0 "U1" H 2950 4250 30 0000 C CNN +F 1 "PORT" H 2900 4150 30 0000 C CNN +F 2 "" H 2900 4150 60 0000 C CNN +F 3 "" H 2900 4150 60 0000 C CNN + 5 2900 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5D0CBE9C +P 6200 3700 +F 0 "U1" H 6250 3800 30 0000 C CNN +F 1 "PORT" H 6200 3700 30 0000 C CNN +F 2 "" H 6200 3700 60 0000 C CNN +F 3 "" H 6200 3700 60 0000 C CNN + 6 6200 3700 + -1 0 0 1 +$EndComp +Wire Wire Line + 3150 2900 3700 2900 +Wire Wire Line + 3700 2900 3700 3500 +Wire Wire Line + 3700 3600 3500 3600 +Wire Wire Line + 3500 3600 3500 3150 +Wire Wire Line + 3500 3150 3150 3150 +Wire Wire Line + 3150 3400 3350 3400 +Wire Wire Line + 3350 3400 3350 3700 +Wire Wire Line + 3350 3700 3700 3700 +Wire Wire Line + 3700 3800 3250 3800 +Wire Wire Line + 3250 3800 3250 3750 +Wire Wire Line + 3250 3750 3150 3750 +Wire Wire Line + 3150 4150 3350 4150 +Wire Wire Line + 3350 4150 3350 3900 +Wire Wire Line + 3350 3900 3700 3900 +Wire Wire Line + 4700 3700 4850 3700 +Wire Wire Line + 5450 3700 5950 3700 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.sub b/src/SubcircuitLibrary/4to16_demux/5_nand.sub new file mode 100644 index 00000000..c3e041fa --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand.sub @@ -0,0 +1,12 @@ +* Subcircuit 5_nand +.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir +.include 5_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and +* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter +a1 net-_u2-pad1_ net-_u1-pad6_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_nand \ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml new file mode 100644 index 00000000..c4b4cde2 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_inverter/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/analysis b/src/SubcircuitLibrary/4to16_demux/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/3_and-cache.lib b/src/SubcircuitLibrary/5_and/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_and/3_and.cir b/src/SubcircuitLibrary/5_and/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_and/3_and.cir.out b/src/SubcircuitLibrary/5_and/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_and/3_and.pro b/src/SubcircuitLibrary/5_and/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/5_and/3_and.sch b/src/SubcircuitLibrary/5_and/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_and/3_and.sub b/src/SubcircuitLibrary/5_and/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/5_and-cache.lib b/src/SubcircuitLibrary/5_and/5_and-cache.lib new file mode 100644 index 00000000..4cf915be --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_and/5_and.cir b/src/SubcircuitLibrary/5_and/5_and.cir new file mode 100644 index 00000000..ca1199bd --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_and/5_and.cir.out b/src/SubcircuitLibrary/5_and/5_and.cir.out new file mode 100644 index 00000000..20d3f8a5 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_and/5_and.pro b/src/SubcircuitLibrary/5_and/5_and.pro new file mode 100644 index 00000000..a9d6304f --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/5_and/5_and.sch b/src/SubcircuitLibrary/5_and/5_and.sch new file mode 100644 index 00000000..0d86cdec --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_and/5_and.sub b/src/SubcircuitLibrary/5_and/5_and.sub new file mode 100644 index 00000000..9d929fcb --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/analysis b/src/SubcircuitLibrary/5_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/3_and-cache.lib b/src/SubcircuitLibrary/5_nand/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_nand/3_and.cir b/src/SubcircuitLibrary/5_nand/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_nand/3_and.cir.out b/src/SubcircuitLibrary/5_nand/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_nand/3_and.pro b/src/SubcircuitLibrary/5_nand/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/5_nand/3_and.sch b/src/SubcircuitLibrary/5_nand/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_nand/3_and.sub b/src/SubcircuitLibrary/5_nand/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/5_and-cache.lib b/src/SubcircuitLibrary/5_nand/5_and-cache.lib new file mode 100644 index 00000000..4cf915be --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_nand/5_and.cir b/src/SubcircuitLibrary/5_nand/5_and.cir new file mode 100644 index 00000000..ca1199bd --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_nand/5_and.cir.out b/src/SubcircuitLibrary/5_nand/5_and.cir.out new file mode 100644 index 00000000..20d3f8a5 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_nand/5_and.pro b/src/SubcircuitLibrary/5_nand/5_and.pro new file mode 100644 index 00000000..a9d6304f --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/5_nand/5_and.sch b/src/SubcircuitLibrary/5_nand/5_and.sch new file mode 100644 index 00000000..0d86cdec --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_nand/5_and.sub b/src/SubcircuitLibrary/5_nand/5_and.sub new file mode 100644 index 00000000..9d929fcb --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/5_nand-cache.lib b/src/SubcircuitLibrary/5_nand/5_nand-cache.lib new file mode 100644 index 00000000..cb517be1 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_nand-cache.lib @@ -0,0 +1,78 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_nand/5_nand.cir b/src/SubcircuitLibrary/5_nand/5_nand.cir new file mode 100644 index 00000000..e833d0f4 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_nand.cir @@ -0,0 +1,13 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and +U2 Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_nand/5_nand.cir.out b/src/SubcircuitLibrary/5_nand/5_nand.cir.out new file mode 100644 index 00000000..164de911 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_nand.cir.out @@ -0,0 +1,18 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir + +.include 5_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and +* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 net-_u2-pad1_ net-_u1-pad6_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_nand/5_nand.pro b/src/SubcircuitLibrary/5_nand/5_nand.pro new file mode 100644 index 00000000..b7d23f44 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_nand.pro @@ -0,0 +1,83 @@ +update=Fri Jun 21 16:46:10 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName41=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName42=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName43=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName44=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName45=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName46=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName47=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName48=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User + diff --git a/src/SubcircuitLibrary/5_nand/5_nand.sch b/src/SubcircuitLibrary/5_nand/5_nand.sch new file mode 100644 index 00000000..86379b08 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_nand.sch @@ -0,0 +1,175 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5D0CBD44 +P 4150 3700 +F 0 "X1" H 4200 3600 60 0000 C CNN +F 1 "5_and" H 4250 3850 60 0000 C CNN +F 2 "" H 4150 3700 60 0000 C CNN +F 3 "" H 4150 3700 60 0000 C CNN + 1 4150 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5D0CBD97 +P 5150 3700 +F 0 "U2" H 5150 3600 60 0000 C CNN +F 1 "d_inverter" H 5150 3850 60 0000 C CNN +F 2 "" H 5200 3650 60 0000 C CNN +F 3 "" H 5200 3650 60 0000 C CNN + 1 5150 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5D0CBDBE +P 2900 2900 +F 0 "U1" H 2950 3000 30 0000 C CNN +F 1 "PORT" H 2900 2900 30 0000 C CNN +F 2 "" H 2900 2900 60 0000 C CNN +F 3 "" H 2900 2900 60 0000 C CNN + 1 2900 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D0CBDF4 +P 2900 3150 +F 0 "U1" H 2950 3250 30 0000 C CNN +F 1 "PORT" H 2900 3150 30 0000 C CNN +F 2 "" H 2900 3150 60 0000 C CNN +F 3 "" H 2900 3150 60 0000 C CNN + 2 2900 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5D0CBE16 +P 2900 3400 +F 0 "U1" H 2950 3500 30 0000 C CNN +F 1 "PORT" H 2900 3400 30 0000 C CNN +F 2 "" H 2900 3400 60 0000 C CNN +F 3 "" H 2900 3400 60 0000 C CNN + 3 2900 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5D0CBE3F +P 2900 3750 +F 0 "U1" H 2950 3850 30 0000 C CNN +F 1 "PORT" H 2900 3750 30 0000 C CNN +F 2 "" H 2900 3750 60 0000 C CNN +F 3 "" H 2900 3750 60 0000 C CNN + 4 2900 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5D0CBE6B +P 2900 4150 +F 0 "U1" H 2950 4250 30 0000 C CNN +F 1 "PORT" H 2900 4150 30 0000 C CNN +F 2 "" H 2900 4150 60 0000 C CNN +F 3 "" H 2900 4150 60 0000 C CNN + 5 2900 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5D0CBE9C +P 6200 3700 +F 0 "U1" H 6250 3800 30 0000 C CNN +F 1 "PORT" H 6200 3700 30 0000 C CNN +F 2 "" H 6200 3700 60 0000 C CNN +F 3 "" H 6200 3700 60 0000 C CNN + 6 6200 3700 + -1 0 0 1 +$EndComp +Wire Wire Line + 3150 2900 3700 2900 +Wire Wire Line + 3700 2900 3700 3500 +Wire Wire Line + 3700 3600 3500 3600 +Wire Wire Line + 3500 3600 3500 3150 +Wire Wire Line + 3500 3150 3150 3150 +Wire Wire Line + 3150 3400 3350 3400 +Wire Wire Line + 3350 3400 3350 3700 +Wire Wire Line + 3350 3700 3700 3700 +Wire Wire Line + 3700 3800 3250 3800 +Wire Wire Line + 3250 3800 3250 3750 +Wire Wire Line + 3250 3750 3150 3750 +Wire Wire Line + 3150 4150 3350 4150 +Wire Wire Line + 3350 4150 3350 3900 +Wire Wire Line + 3350 3900 3700 3900 +Wire Wire Line + 4700 3700 4850 3700 +Wire Wire Line + 5450 3700 5950 3700 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_nand/5_nand.sub b/src/SubcircuitLibrary/5_nand/5_nand.sub new file mode 100644 index 00000000..c3e041fa --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_nand.sub @@ -0,0 +1,12 @@ +* Subcircuit 5_nand +.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir +.include 5_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and +* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter +a1 net-_u2-pad1_ net-_u1-pad6_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_nand \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml new file mode 100644 index 00000000..c4b4cde2 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_inverter/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/analysis b/src/SubcircuitLibrary/5_nand/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/5_nand/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/3_and-cache.lib b/src/SubcircuitLibrary/5_nor/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_nor/3_and.cir b/src/SubcircuitLibrary/5_nor/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_nor/3_and.cir.out b/src/SubcircuitLibrary/5_nor/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_nor/3_and.pro b/src/SubcircuitLibrary/5_nor/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/5_nor/3_and.sch b/src/SubcircuitLibrary/5_nor/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_nor/3_and.sub b/src/SubcircuitLibrary/5_nor/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nor/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/5_and-cache.lib b/src/SubcircuitLibrary/5_nor/5_and-cache.lib new file mode 100644 index 00000000..4cf915be --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_nor/5_and.cir b/src/SubcircuitLibrary/5_nor/5_and.cir new file mode 100644 index 00000000..ca1199bd --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_nor/5_and.cir.out b/src/SubcircuitLibrary/5_nor/5_and.cir.out new file mode 100644 index 00000000..20d3f8a5 --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_nor/5_and.pro b/src/SubcircuitLibrary/5_nor/5_and.pro new file mode 100644 index 00000000..a9d6304f --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/5_nor/5_and.sch b/src/SubcircuitLibrary/5_nor/5_and.sch new file mode 100644 index 00000000..0d86cdec --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_nor/5_and.sub b/src/SubcircuitLibrary/5_nor/5_and.sub new file mode 100644 index 00000000..9d929fcb --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nor/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/5_nor-cache.lib b/src/SubcircuitLibrary/5_nor/5_nor-cache.lib new file mode 100644 index 00000000..7098010f --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_nor-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_nor/5_nor.cir b/src/SubcircuitLibrary/5_nor/5_nor.cir new file mode 100644 index 00000000..0e4db1ea --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_nor.cir @@ -0,0 +1,19 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor/5_nor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:34:56 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT +X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and + +.end diff --git a/src/SubcircuitLibrary/5_nor/5_nor.cir.out b/src/SubcircuitLibrary/5_nor/5_nor.cir.out new file mode 100644 index 00000000..bc90e004 --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_nor.cir.out @@ -0,0 +1,42 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir + +.include 5_and.sub +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_nor/5_nor.pro b/src/SubcircuitLibrary/5_nor/5_nor.pro new file mode 100644 index 00000000..4716d4ae --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_nor.pro @@ -0,0 +1,73 @@ +update=Tue Jun 25 23:32:34 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User +LibName37=eSim_Plot +LibName38=eSim_PSpice +LibName39=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/5_nor/5_nor.sch b/src/SubcircuitLibrary/5_nor/5_nor.sch new file mode 100644 index 00000000..6bb6fcb8 --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_nor.sch @@ -0,0 +1,275 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:c_gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U8 +U 1 1 5D126275 +P 5600 3300 +F 0 "U8" H 5600 3300 60 0000 C CNN +F 1 "d_and" H 5650 3400 60 0000 C CNN +F 2 "" H 5600 3300 60 0000 C CNN +F 3 "" H 5600 3300 60 0000 C CNN + 1 5600 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3200 5150 2850 +Wire Wire Line + 4150 2650 4150 2350 +Wire Wire Line + 4150 2350 3600 2350 +Wire Wire Line + 4150 2750 4050 2750 +Wire Wire Line + 4050 2750 4050 2550 +Wire Wire Line + 4050 2550 3600 2550 +Wire Wire Line + 4150 2850 3700 2850 +Wire Wire Line + 3700 2850 3700 2750 +Wire Wire Line + 3700 2750 3600 2750 +Wire Wire Line + 4150 2950 3600 2950 +Wire Wire Line + 4150 3050 4150 3150 +Wire Wire Line + 4150 3150 3600 3150 +Wire Wire Line + 5150 3300 3600 3300 +$Comp +L d_inverter U2 +U 1 1 5D126276 +P 3300 2350 +F 0 "U2" H 3300 2250 60 0000 C CNN +F 1 "d_inverter" H 3300 2500 60 0000 C CNN +F 2 "" H 3350 2300 60 0000 C CNN +F 3 "" H 3350 2300 60 0000 C CNN + 1 3300 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5D126277 +P 3300 2550 +F 0 "U3" H 3300 2450 60 0000 C CNN +F 1 "d_inverter" H 3300 2700 60 0000 C CNN +F 2 "" H 3350 2500 60 0000 C CNN +F 3 "" H 3350 2500 60 0000 C CNN + 1 3300 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5D126278 +P 3300 2750 +F 0 "U4" H 3300 2650 60 0000 C CNN +F 1 "d_inverter" H 3300 2900 60 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3300 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5D126279 +P 3300 2950 +F 0 "U5" H 3300 2850 60 0000 C CNN +F 1 "d_inverter" H 3300 3100 60 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 1 3300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5D12627A +P 3300 3150 +F 0 "U6" H 3300 3050 60 0000 C CNN +F 1 "d_inverter" H 3300 3300 60 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 1 3300 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5D12627B +P 3300 3300 +F 0 "U7" H 3300 3200 60 0000 C CNN +F 1 "d_inverter" H 3300 3450 60 0000 C CNN +F 2 "" H 3350 3250 60 0000 C CNN +F 3 "" H 3350 3250 60 0000 C CNN + 1 3300 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2350 2000 2350 +Wire Wire Line + 3000 2550 2000 2550 +Wire Wire Line + 3000 2750 2050 2750 +Wire Wire Line + 3000 2950 2050 2950 +Wire Wire Line + 3000 3150 2050 3150 +Wire Wire Line + 3000 3300 2050 3300 +Wire Wire Line + 6050 3250 6950 3250 +$Comp +L PORT U1 +U 1 1 5D12627C +P 1750 2350 +F 0 "U1" H 1800 2450 30 0000 C CNN +F 1 "PORT" H 1750 2350 30 0000 C CNN +F 2 "" H 1750 2350 60 0000 C CNN +F 3 "" H 1750 2350 60 0000 C CNN + 1 1750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D12627D +P 1750 2550 +F 0 "U1" H 1800 2650 30 0000 C CNN +F 1 "PORT" H 1750 2550 30 0000 C CNN +F 2 "" H 1750 2550 60 0000 C CNN +F 3 "" H 1750 2550 60 0000 C CNN + 2 1750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5D12627E +P 1800 2750 +F 0 "U1" H 1850 2850 30 0000 C CNN +F 1 "PORT" H 1800 2750 30 0000 C CNN +F 2 "" H 1800 2750 60 0000 C CNN +F 3 "" H 1800 2750 60 0000 C CNN + 3 1800 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5D12627F +P 1800 2950 +F 0 "U1" H 1850 3050 30 0000 C CNN +F 1 "PORT" H 1800 2950 30 0000 C CNN +F 2 "" H 1800 2950 60 0000 C CNN +F 3 "" H 1800 2950 60 0000 C CNN + 4 1800 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5D126280 +P 1800 3150 +F 0 "U1" H 1850 3250 30 0000 C CNN +F 1 "PORT" H 1800 3150 30 0000 C CNN +F 2 "" H 1800 3150 60 0000 C CNN +F 3 "" H 1800 3150 60 0000 C CNN + 5 1800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5D126281 +P 1800 3300 +F 0 "U1" H 1850 3400 30 0000 C CNN +F 1 "PORT" H 1800 3300 30 0000 C CNN +F 2 "" H 1800 3300 60 0000 C CNN +F 3 "" H 1800 3300 60 0000 C CNN + 6 1800 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5D126282 +P 7200 3250 +F 0 "U1" H 7250 3350 30 0000 C CNN +F 1 "PORT" H 7200 3250 30 0000 C CNN +F 2 "" H 7200 3250 60 0000 C CNN +F 3 "" H 7200 3250 60 0000 C CNN + 7 7200 3250 + -1 0 0 1 +$EndComp +Text Notes 2400 2350 0 60 ~ 12 +in1 +Text Notes 2400 2550 0 60 ~ 12 +in2 +Text Notes 2400 2750 0 60 ~ 12 +in3 +Text Notes 2400 2950 0 60 ~ 12 +in4 +Text Notes 2400 3150 0 60 ~ 12 +in5 +Text Notes 2400 3300 0 60 ~ 12 +in6 +Text Notes 6350 3250 0 60 ~ 12 +out +$Comp +L 5_and X1 +U 1 1 5D1262D5 +P 4600 2850 +F 0 "X1" H 4650 2750 60 0000 C CNN +F 1 "5_and" H 4700 3000 60 0000 C CNN +F 2 "" H 4600 2850 60 0000 C CNN +F 3 "" H 4600 2850 60 0000 C CNN + 1 4600 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_nor/5_nor.sub b/src/SubcircuitLibrary/5_nor/5_nor.sub new file mode 100644 index 00000000..dbcdb750 --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_nor.sub @@ -0,0 +1,36 @@ +* Subcircuit 5_nor +.subckt 5_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir +.include 5_and.sub +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_nor \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/5_nor_Previous_Values.xml b/src/SubcircuitLibrary/5_nor/5_nor_Previous_Values.xml new file mode 100644 index 00000000..75f5258c --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/5_nor_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_andd_inverterd_inverterd_inverterd_inverterd_inverterd_inverter/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/analysis b/src/SubcircuitLibrary/5_nor/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/5_nor/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib new file mode 100644 index 00000000..b75ae867 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# Full-Adder +# +DEF Full-Adder X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Full-Adder" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 200 300 -200 0 1 0 N +X A 1 -500 150 200 R 50 50 1 1 I +X B 2 -500 0 200 R 50 50 1 1 I +X Cin 3 -500 -150 200 R 50 50 1 1 I +X Out 4 500 100 200 L 50 50 1 1 I +X Cout 5 500 -100 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir new file mode 100644 index 00000000..84b7b723 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir @@ -0,0 +1,16 @@ +* C:\esim\eSim\src\SubcircuitLibrary\5bit-Ripple_carry_adder\5bit-Ripple_carry_adder.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 02:16:47 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X4 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X4-Pad3_ Net-_U1-Pad4_ ? Full-Adder +X5 Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X5-Pad3_ Net-_U1-Pad7_ Net-_X4-Pad3_ Full-Adder +X6 Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X6-Pad3_ Net-_U1-Pad10_ Net-_X5-Pad3_ Full-Adder +X7 Net-_U1-Pad9_ Net-_U1-Pad11_ Net-_X7-Pad3_ Net-_U1-Pad13_ Net-_X6-Pad3_ Full-Adder +X8 Net-_U1-Pad12_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_X7-Pad3_ Full-Adder +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT + +.end diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out new file mode 100644 index 00000000..dfda0a3b --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out @@ -0,0 +1,18 @@ +* c:\esim\esim\src\subcircuitlibrary\5bit-ripple_carry_adder\5bit-ripple_carry_adder.cir + +.include Full-Adder.sub +x4 net-_u1-pad1_ net-_u1-pad2_ net-_x4-pad3_ net-_u1-pad4_ ? Full-Adder +x5 net-_u1-pad3_ net-_u1-pad5_ net-_x5-pad3_ net-_u1-pad7_ net-_x4-pad3_ Full-Adder +x6 net-_u1-pad6_ net-_u1-pad8_ net-_x6-pad3_ net-_u1-pad10_ net-_x5-pad3_ Full-Adder +x7 net-_u1-pad9_ net-_u1-pad11_ net-_x7-pad3_ net-_u1-pad13_ net-_x6-pad3_ Full-Adder +x8 net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x7-pad3_ Full-Adder +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro new file mode 100644 index 00000000..d3bfc6c4 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro @@ -0,0 +1,44 @@ +update=Sat Jun 22 12:25:13 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../eSim-1.1.2/kicadSchematicLibrary +[eeschema/libraries] +LibName1=9bit-BoothMultiplier-cache +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch new file mode 100644 index 00000000..dd2e9165 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch @@ -0,0 +1,386 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5bit-Ripple_carry_adder-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Full-Adder X4 +U 1 1 5C93C7FA +P 3000 3550 +F 0 "X4" H 3000 3550 60 0000 C CNN +F 1 "Full-Adder" H 3000 3550 60 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 1 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L Full-Adder X5 +U 1 1 5C93C84A +P 4350 3550 +F 0 "X5" H 4350 3550 60 0000 C CNN +F 1 "Full-Adder" H 4350 3550 60 0000 C CNN +F 2 "" H 4350 3550 60 0000 C CNN +F 3 "" H 4350 3550 60 0000 C CNN + 1 4350 3550 + 1 0 0 -1 +$EndComp +$Comp +L Full-Adder X6 +U 1 1 5C93C897 +P 5700 3550 +F 0 "X6" H 5700 3550 60 0000 C CNN +F 1 "Full-Adder" H 5700 3550 60 0000 C CNN +F 2 "" H 5700 3550 60 0000 C CNN +F 3 "" H 5700 3550 60 0000 C CNN + 1 5700 3550 + 1 0 0 -1 +$EndComp +$Comp +L Full-Adder X7 +U 1 1 5C93C961 +P 7000 3550 +F 0 "X7" H 7000 3550 60 0000 C CNN +F 1 "Full-Adder" H 7000 3550 60 0000 C CNN +F 2 "" H 7000 3550 60 0000 C CNN +F 3 "" H 7000 3550 60 0000 C CNN + 1 7000 3550 + 1 0 0 -1 +$EndComp +$Comp +L Full-Adder X8 +U 1 1 5C93C9A8 +P 8250 3550 +F 0 "X8" H 8250 3550 60 0000 C CNN +F 1 "Full-Adder" H 8250 3550 60 0000 C CNN +F 2 "" H 8250 3550 60 0000 C CNN +F 3 "" H 8250 3550 60 0000 C CNN + 1 8250 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 3450 3650 3450 +Wire Wire Line + 3650 3450 3650 4800 +Wire Wire Line + 2500 3700 2500 3850 +Wire Wire Line + 2500 3850 4900 3850 +Wire Wire Line + 4900 3850 4900 3650 +Wire Wire Line + 4900 3650 4850 3650 +Wire Wire Line + 4850 3450 4950 3450 +Wire Wire Line + 4950 3450 4950 4800 +Wire Wire Line + 3850 3700 3850 3900 +Wire Wire Line + 3850 3900 6250 3900 +Wire Wire Line + 6250 3900 6250 3650 +Wire Wire Line + 6250 3650 6200 3650 +Wire Wire Line + 5200 3700 5200 3850 +Wire Wire Line + 5200 3850 7550 3850 +Wire Wire Line + 7550 3850 7550 3650 +Wire Wire Line + 7550 3650 7500 3650 +Wire Wire Line + 6500 3900 8750 3900 +Wire Wire Line + 8750 3900 8750 3650 +Wire Wire Line + 8750 3450 8800 3450 +Wire Wire Line + 8800 3450 8800 4950 +Wire Wire Line + 7500 3450 7600 3450 +Wire Wire Line + 7600 3450 7600 4850 +Wire Wire Line + 6200 3450 6300 3450 +Wire Wire Line + 6300 3450 6300 4800 +Wire Wire Line + 7750 3700 7750 3850 +Wire Wire Line + 7750 3850 8000 3850 +Wire Wire Line + 8000 3850 8000 4900 +Wire Wire Line + 2350 3400 2500 3400 +Wire Wire Line + 2350 2200 2350 3400 +Wire Wire Line + 2450 3550 2500 3550 +Wire Wire Line + 2450 2550 2450 3550 +Wire Wire Line + 3650 3400 3850 3400 +Wire Wire Line + 3650 2200 3650 3400 +Wire Wire Line + 7600 3400 7750 3400 +Wire Wire Line + 7600 2200 7600 3400 +Wire Wire Line + 6300 3400 6500 3400 +Wire Wire Line + 6300 2200 6300 3400 +Wire Wire Line + 6400 3550 6500 3550 +Wire Wire Line + 6400 2550 6400 3550 +Wire Wire Line + 4950 3400 5200 3400 +Wire Wire Line + 4950 2200 4950 3400 +Wire Wire Line + 5050 3550 5200 3550 +Wire Wire Line + 5050 2500 5050 3550 +Text Notes 7550 2750 1 60 ~ 0 +A0 +Text Notes 6200 2750 1 60 ~ 0 +A1 +Text Notes 4900 2750 1 60 ~ 0 +A2 +Text Notes 3600 2750 1 60 ~ 0 +A3 +Text Notes 2300 2750 1 60 ~ 0 +A4 +Text Notes 7800 2900 3 60 ~ 0 +B0 +Text Notes 6500 3050 1 60 ~ 0 +B1 +Text Notes 5150 3050 1 60 ~ 0 +B2 +Text Notes 3850 3050 1 60 ~ 0 +B3 +Text Notes 2550 3050 1 60 ~ 0 +B4 +Text Notes 8750 4700 1 60 ~ 0 +O0 +Text Notes 7550 4700 1 60 ~ 0 +O1 +Text Notes 6250 4650 1 60 ~ 0 +O2 +Text Notes 4900 4650 1 60 ~ 0 +O3 +Text Notes 3600 4650 1 60 ~ 0 +O4 +Wire Wire Line + 7700 2550 7700 3550 +Wire Wire Line + 7700 3550 7750 3550 +Wire Wire Line + 3850 3550 3750 3550 +Wire Wire Line + 3750 3550 3750 2550 +Wire Wire Line + 6500 3900 6500 3700 +$Comp +L PORT U1 +U 12 1 5C95CA38 +P 7600 1950 +F 0 "U1" H 7650 2050 30 0000 C CNN +F 1 "PORT" H 7600 1950 30 0000 C CNN +F 2 "" H 7600 1950 60 0000 C CNN +F 3 "" H 7600 1950 60 0000 C CNN + 12 7600 1950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 5C95CAA1 +P 6300 1950 +F 0 "U1" H 6350 2050 30 0000 C CNN +F 1 "PORT" H 6300 1950 30 0000 C CNN +F 2 "" H 6300 1950 60 0000 C CNN +F 3 "" H 6300 1950 60 0000 C CNN + 9 6300 1950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 5C95CAD4 +P 4950 1950 +F 0 "U1" H 5000 2050 30 0000 C CNN +F 1 "PORT" H 4950 1950 30 0000 C CNN +F 2 "" H 4950 1950 60 0000 C CNN +F 3 "" H 4950 1950 60 0000 C CNN + 6 4950 1950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5C95CB01 +P 3650 1950 +F 0 "U1" H 3700 2050 30 0000 C CNN +F 1 "PORT" H 3650 1950 30 0000 C CNN +F 2 "" H 3650 1950 60 0000 C CNN +F 3 "" H 3650 1950 60 0000 C CNN + 3 3650 1950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5C95CB34 +P 2350 1950 +F 0 "U1" H 2400 2050 30 0000 C CNN +F 1 "PORT" H 2350 1950 30 0000 C CNN +F 2 "" H 2350 1950 60 0000 C CNN +F 3 "" H 2350 1950 60 0000 C CNN + 1 2350 1950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 5C95CB65 +P 7700 2300 +F 0 "U1" H 7750 2400 30 0000 C CNN +F 1 "PORT" H 7700 2300 30 0000 C CNN +F 2 "" H 7700 2300 60 0000 C CNN +F 3 "" H 7700 2300 60 0000 C CNN + 14 7700 2300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 5C95CBEC +P 6400 2300 +F 0 "U1" H 6450 2400 30 0000 C CNN +F 1 "PORT" H 6400 2300 30 0000 C CNN +F 2 "" H 6400 2300 60 0000 C CNN +F 3 "" H 6400 2300 60 0000 C CNN + 11 6400 2300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C95CC27 +P 5050 2250 +F 0 "U1" H 5100 2350 30 0000 C CNN +F 1 "PORT" H 5050 2250 30 0000 C CNN +F 2 "" H 5050 2250 60 0000 C CNN +F 3 "" H 5050 2250 60 0000 C CNN + 8 5050 2250 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 5C95CC5E +P 3750 2300 +F 0 "U1" H 3800 2400 30 0000 C CNN +F 1 "PORT" H 3750 2300 30 0000 C CNN +F 2 "" H 3750 2300 60 0000 C CNN +F 3 "" H 3750 2300 60 0000 C CNN + 5 3750 2300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5C95CC9F +P 2450 2300 +F 0 "U1" H 2500 2400 30 0000 C CNN +F 1 "PORT" H 2450 2300 30 0000 C CNN +F 2 "" H 2450 2300 60 0000 C CNN +F 3 "" H 2450 2300 60 0000 C CNN + 2 2450 2300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 5C95D6FB +P 8000 5150 +F 0 "U1" H 8050 5250 30 0000 C CNN +F 1 "PORT" H 8000 5150 30 0000 C CNN +F 2 "" H 8000 5150 60 0000 C CNN +F 3 "" H 8000 5150 60 0000 C CNN + 15 8000 5150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 16 1 5C95D772 +P 8800 5200 +F 0 "U1" H 8850 5300 30 0000 C CNN +F 1 "PORT" H 8800 5200 30 0000 C CNN +F 2 "" H 8800 5200 60 0000 C CNN +F 3 "" H 8800 5200 60 0000 C CNN + 16 8800 5200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 5C95D7ED +P 7600 5100 +F 0 "U1" H 7650 5200 30 0000 C CNN +F 1 "PORT" H 7600 5100 30 0000 C CNN +F 2 "" H 7600 5100 60 0000 C CNN +F 3 "" H 7600 5100 60 0000 C CNN + 13 7600 5100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5C95D844 +P 6300 5050 +F 0 "U1" H 6350 5150 30 0000 C CNN +F 1 "PORT" H 6300 5050 30 0000 C CNN +F 2 "" H 6300 5050 60 0000 C CNN +F 3 "" H 6300 5050 60 0000 C CNN + 10 6300 5050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C95D899 +P 4950 5050 +F 0 "U1" H 5000 5150 30 0000 C CNN +F 1 "PORT" H 4950 5050 30 0000 C CNN +F 2 "" H 4950 5050 60 0000 C CNN +F 3 "" H 4950 5050 60 0000 C CNN + 7 4950 5050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 5C95D8EA +P 3650 5050 +F 0 "U1" H 3700 5150 30 0000 C CNN +F 1 "PORT" H 3650 5050 30 0000 C CNN +F 2 "" H 3650 5050 60 0000 C CNN +F 3 "" H 3650 5050 60 0000 C CNN + 4 3650 5050 + 0 -1 -1 0 +$EndComp +Text Notes 7950 4700 1 60 ~ 0 +Cin +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub new file mode 100644 index 00000000..675975d9 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub @@ -0,0 +1,12 @@ +* Subcircuit 5bit-Ripple_carry_adder +.subckt 5bit-Ripple_carry_adder net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ +* c:\esim\esim\src\subcircuitlibrary\5bit-ripple_carry_adder\5bit-ripple_carry_adder.cir +.include Full-Adder.sub +x4 net-_u1-pad1_ net-_u1-pad2_ net-_x4-pad3_ net-_u1-pad4_ ? Full-Adder +x5 net-_u1-pad3_ net-_u1-pad5_ net-_x5-pad3_ net-_u1-pad7_ net-_x4-pad3_ Full-Adder +x6 net-_u1-pad6_ net-_u1-pad8_ net-_x6-pad3_ net-_u1-pad10_ net-_x5-pad3_ Full-Adder +x7 net-_u1-pad9_ net-_u1-pad11_ net-_x7-pad3_ net-_u1-pad13_ net-_x6-pad3_ Full-Adder +x8 net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x7-pad3_ Full-Adder +* Control Statements + +.ends 5bit-Ripple_carry_adder \ No newline at end of file diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml new file mode 100644 index 00000000..8fbbb417 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\esim\eSim\src\SubcircuitLibrary\Full-AdderC:\esim\eSim\src\SubcircuitLibrary\Full-AdderC:\esim\eSim\src\SubcircuitLibrary\Full-AdderC:\esim\eSim\src\SubcircuitLibrary\Full-AdderC:\esim\eSim\src\SubcircuitLibrary\Full-Adder \ No newline at end of file diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib new file mode 100644 index 00000000..cba68b20 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir new file mode 100644 index 00000000..ea7aed36 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir @@ -0,0 +1,16 @@ +* C:\esim\eSim\src\SubcircuitLibrary\Full-Adder\Full-Adder.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/21/19 17:15:52 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_xor +U5 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_xor +U4 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U3-Pad3_ d_and +U6 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad5_ d_or + +.end diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out new file mode 100644 index 00000000..086d8b71 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out @@ -0,0 +1,32 @@ +* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir + +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor +* u5 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor +* u4 net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and +* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5 +a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3 +a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro new file mode 100644 index 00000000..7089d69d --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro @@ -0,0 +1,74 @@ +update=03/21/19 17:06:42 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User +LibName12=half-adder +LibName13=power +LibName14=device +LibName15=transistors +LibName16=conn +LibName17=linear +LibName18=regul +LibName19=74xx +LibName20=cmos4000 +LibName21=adc-dac +LibName22=memory +LibName23=xilinx +LibName24=microcontrollers +LibName25=dsp +LibName26=microchip +LibName27=analog_switches +LibName28=motorola +LibName29=texas +LibName30=intel +LibName31=audio +LibName32=interface +LibName33=digital-audio +LibName34=philips +LibName35=display +LibName36=cypress +LibName37=siliconi +LibName38=opto +LibName39=atmel +LibName40=contrib +LibName41=valves diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch new file mode 100644 index 00000000..981e7cdb --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch @@ -0,0 +1,226 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:half-adder +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:Full-Adder-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 1 1 5C93775D +P 4100 2800 +F 0 "U1" H 4150 2900 30 0000 C CNN +F 1 "PORT" H 4100 2800 30 0000 C CNN +F 2 "" H 4100 2800 60 0000 C CNN +F 3 "" H 4100 2800 60 0000 C CNN + 1 4100 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9377A8 +P 4100 3100 +F 0 "U1" H 4150 3200 30 0000 C CNN +F 1 "PORT" H 4100 3100 30 0000 C CNN +F 2 "" H 4100 3100 60 0000 C CNN +F 3 "" H 4100 3100 60 0000 C CNN + 2 4100 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9377CD +P 4100 3400 +F 0 "U1" H 4150 3500 30 0000 C CNN +F 1 "PORT" H 4100 3400 30 0000 C CNN +F 2 "" H 4100 3400 60 0000 C CNN +F 3 "" H 4100 3400 60 0000 C CNN + 3 4100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9377F2 +P 8450 2900 +F 0 "U1" H 8500 3000 30 0000 C CNN +F 1 "PORT" H 8450 2900 30 0000 C CNN +F 2 "" H 8450 2900 60 0000 C CNN +F 3 "" H 8450 2900 60 0000 C CNN + 4 8450 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C937851 +P 8450 3200 +F 0 "U1" H 8500 3300 30 0000 C CNN +F 1 "PORT" H 8450 3200 30 0000 C CNN +F 2 "" H 8450 3200 60 0000 C CNN +F 3 "" H 8450 3200 60 0000 C CNN + 5 8450 3200 + -1 0 0 1 +$EndComp +$Comp +L d_xor U2 +U 1 1 5C93788C +P 5150 2900 +F 0 "U2" H 5150 2900 60 0000 C CNN +F 1 "d_xor" H 5200 3000 47 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U5 +U 1 1 5C9378DF +P 6400 2950 +F 0 "U5" H 6400 2950 60 0000 C CNN +F 1 "d_xor" H 6450 3050 47 0000 C CNN +F 2 "" H 6400 2950 60 0000 C CNN +F 3 "" H 6400 2950 60 0000 C CNN + 1 6400 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C937928 +P 6150 3300 +F 0 "U4" H 6150 3300 60 0000 C CNN +F 1 "d_and" H 6200 3400 60 0000 C CNN +F 2 "" H 6150 3300 60 0000 C CNN +F 3 "" H 6150 3300 60 0000 C CNN + 1 6150 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9379CF +P 5200 3500 +F 0 "U3" H 5200 3500 60 0000 C CNN +F 1 "d_and" H 5250 3600 60 0000 C CNN +F 2 "" H 5200 3500 60 0000 C CNN +F 3 "" H 5200 3500 60 0000 C CNN + 1 5200 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 5C937A14 +P 7250 3550 +F 0 "U6" H 7250 3550 60 0000 C CNN +F 1 "d_or" H 7250 3650 60 0000 C CNN +F 2 "" H 7250 3550 60 0000 C CNN +F 3 "" H 7250 3550 60 0000 C CNN + 1 7250 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 2800 4700 2800 +Wire Wire Line + 4350 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Wire Wire Line + 5600 2850 5950 2850 +Wire Wire Line + 4350 3400 4400 3400 +Wire Wire Line + 4400 3400 4400 3150 +Wire Wire Line + 4400 3150 5450 3150 +Wire Wire Line + 5450 3150 5450 2950 +Wire Wire Line + 5450 2950 5950 2950 +Wire Wire Line + 6850 2900 8200 2900 +Wire Wire Line + 4450 2800 4450 3400 +Wire Wire Line + 4450 3400 4750 3400 +Connection ~ 4450 2800 +Wire Wire Line + 4600 3100 4600 3500 +Wire Wire Line + 4600 3500 4750 3500 +Connection ~ 4600 3100 +Wire Wire Line + 5650 3450 6800 3450 +Wire Wire Line + 4400 3300 5700 3300 +Connection ~ 4400 3300 +Wire Wire Line + 5700 3200 5700 2850 +Connection ~ 5700 2850 +Wire Wire Line + 6600 3250 6650 3250 +Wire Wire Line + 6650 3250 6650 3550 +Wire Wire Line + 6650 3550 6800 3550 +Wire Wire Line + 7700 3500 7700 3200 +Wire Wire Line + 7700 3200 8200 3200 +Text Notes 4400 2750 0 60 ~ 0 +A +Text Notes 4400 3050 0 60 ~ 0 +B +Text Notes 4350 3500 0 60 ~ 0 +Cin +Text Notes 7950 2850 0 60 ~ 0 +Sum +Text Notes 7950 3150 0 60 ~ 0 +Cout +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub new file mode 100644 index 00000000..0ea4496d --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub @@ -0,0 +1,26 @@ +* Subcircuit Full-Adder +.subckt Full-Adder net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor +* u5 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor +* u4 net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and +* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5 +a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3 +a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends Full-Adder \ No newline at end of file diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml new file mode 100644 index 00000000..c7136641 --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_xord_xord_andd_andd_or \ No newline at end of file diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz \ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/3_and-cache.lib b/src/SubcircuitLibrary/74153/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/3_and.cir b/src/SubcircuitLibrary/74153/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/74153/3_and.cir.out b/src/SubcircuitLibrary/74153/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/3_and.pro b/src/SubcircuitLibrary/74153/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/74153/3_and.sch b/src/SubcircuitLibrary/74153/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/3_and.sub b/src/SubcircuitLibrary/74153/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml b/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_OR-cache.lib b/src/SubcircuitLibrary/74153/4_OR-cache.lib new file mode 100644 index 00000000..a3c1c972 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/4_OR.cir b/src/SubcircuitLibrary/74153/4_OR.cir new file mode 100644 index 00000000..7adbf177 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/74153/4_OR.cir.out b/src/SubcircuitLibrary/74153/4_OR.cir.out new file mode 100644 index 00000000..4388b975 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/4_OR.pro b/src/SubcircuitLibrary/74153/4_OR.pro new file mode 100644 index 00000000..1e19b3a7 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.pro @@ -0,0 +1,45 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/74153/4_OR.sch b/src/SubcircuitLibrary/74153/4_OR.sch new file mode 100644 index 00000000..2f28896c --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/4_OR.sub b/src/SubcircuitLibrary/74153/4_OR.sub new file mode 100644 index 00000000..53fc8b33 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_and-cache.lib b/src/SubcircuitLibrary/74153/4_and-cache.lib new file mode 100644 index 00000000..cb84d8f2 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/4_and-rescue.lib b/src/SubcircuitLibrary/74153/4_and-rescue.lib new file mode 100644 index 00000000..6b2c17f7 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/4_and.cir b/src/SubcircuitLibrary/74153/4_and.cir new file mode 100644 index 00000000..35e46097 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/74153/4_and.cir.out b/src/SubcircuitLibrary/74153/4_and.cir.out new file mode 100644 index 00000000..6e35b18a --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/4_and.pro b/src/SubcircuitLibrary/74153/4_and.pro new file mode 100644 index 00000000..814ad76a --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and.pro @@ -0,0 +1,58 @@ +update=06/01/19 15:08:42 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/74153/4_and.sch b/src/SubcircuitLibrary/74153/4_and.sch new file mode 100644 index 00000000..2d8296d4 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/4_and.sub b/src/SubcircuitLibrary/74153/4_and.sub new file mode 100644 index 00000000..bf20b628 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml b/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/74153-cache.lib b/src/SubcircuitLibrary/74153/74153-cache.lib new file mode 100644 index 00000000..4f81c933 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/74153.cir b/src/SubcircuitLibrary/74153/74153.cir new file mode 100644 index 00000000..955b30b1 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.cir @@ -0,0 +1,25 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/74153/74153.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 26 15:19:41 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad14_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U35 Net-_U1-Pad1_ Net-_U35-Pad2_ d_inverter +U34 Net-_U1-Pad15_ Net-_U34-Pad2_ d_inverter +X8 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and +X9 Net-_U1-Pad14_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and +X4 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and +X10 Net-_U1-Pad14_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and +X5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad10_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and +X6 Net-_U1-Pad14_ Net-_U3-Pad2_ Net-_U1-Pad11_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and +X3 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad12_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and +X7 Net-_U1-Pad14_ Net-_U1-Pad2_ Net-_U1-Pad13_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad9_ 4_OR +X2 Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad7_ 4_OR + +.end diff --git a/src/SubcircuitLibrary/74153/74153.cir.out b/src/SubcircuitLibrary/74153/74153.cir.out new file mode 100644 index 00000000..93b8fdd1 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.cir.out @@ -0,0 +1,40 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74153/74153.cir + +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad14_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u35 net-_u1-pad1_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad15_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad5_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad10_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad11_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad12_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad13_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad9_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad7_ 4_OR +a1 net-_u1-pad14_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 net-_u1-pad1_ net-_u35-pad2_ u35 +a4 net-_u1-pad15_ net-_u34-pad2_ u34 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-03 0e-00 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/74153.pro b/src/SubcircuitLibrary/74153/74153.pro new file mode 100644 index 00000000..78440d11 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.pro @@ -0,0 +1,43 @@ +update=Tue Jun 25 16:51:16 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/74153/74153.sch b/src/SubcircuitLibrary/74153/74153.sch new file mode 100644 index 00000000..fc9b4516 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.sch @@ -0,0 +1,576 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:74153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 5C9378F6 +P 2650 1350 +F 0 "U2" H 2650 1250 60 0000 C CNN +F 1 "d_inverter" H 2650 1500 60 0000 C CNN +F 2 "" H 2700 1300 60 0000 C CNN +F 3 "" H 2700 1300 60 0000 C CNN + 1 2650 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C93798D +P 2700 950 +F 0 "U3" H 2700 850 60 0000 C CNN +F 1 "d_inverter" H 2700 1100 60 0000 C CNN +F 2 "" H 2750 900 60 0000 C CNN +F 3 "" H 2750 900 60 0000 C CNN + 1 2700 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C93A0F9 +P 1350 2050 +F 0 "U1" H 1400 2150 30 0000 C CNN +F 1 "PORT" H 1350 2050 30 0000 C CNN +F 2 "" H 1350 2050 60 0000 C CNN +F 3 "" H 1350 2050 60 0000 C CNN + 6 1350 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C93A174 +P 1350 4700 +F 0 "U1" H 1400 4800 30 0000 C CNN +F 1 "PORT" H 1350 4700 30 0000 C CNN +F 2 "" H 1350 4700 60 0000 C CNN +F 3 "" H 1350 4700 60 0000 C CNN + 10 1350 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C93AA3C +P 1350 2600 +F 0 "U1" H 1400 2700 30 0000 C CNN +F 1 "PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 5 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 4 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 3 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C93AD97 +P 1350 5250 +F 0 "U1" H 1400 5350 30 0000 C CNN +F 1 "PORT" H 1350 5250 30 0000 C CNN +F 2 "" H 1350 5250 60 0000 C CNN +F 3 "" H 1350 5250 60 0000 C CNN + 11 1350 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C93ADFC +P 1350 5850 +F 0 "U1" H 1400 5950 30 0000 C CNN +F 1 "PORT" H 1350 5850 30 0000 C CNN +F 2 "" H 1350 5850 60 0000 C CNN +F 3 "" H 1350 5850 60 0000 C CNN + 12 1350 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C93AE63 +P 1350 6350 +F 0 "U1" H 1400 6450 30 0000 C CNN +F 1 "PORT" H 1350 6350 30 0000 C CNN +F 2 "" H 1350 6350 60 0000 C CNN +F 3 "" H 1350 6350 60 0000 C CNN + 13 1350 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C93AECA +P 1350 3950 +F 0 "U1" H 1400 4050 30 0000 C CNN +F 1 "PORT" H 1350 3950 30 0000 C CNN +F 2 "" H 1350 3950 60 0000 C CNN +F 3 "" H 1350 3950 60 0000 C CNN + 1 1350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 5C93AF79 +P 1350 6600 +F 0 "U1" H 1400 6700 30 0000 C CNN +F 1 "PORT" H 1350 6600 30 0000 C CNN +F 2 "" H 1350 6600 60 0000 C CNN +F 3 "" H 1350 6600 60 0000 C CNN + 15 1350 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C93B10A +P 1550 950 +F 0 "U1" H 1600 1050 30 0000 C CNN +F 1 "PORT" H 1550 950 30 0000 C CNN +F 2 "" H 1550 950 60 0000 C CNN +F 3 "" H 1550 950 60 0000 C CNN + 2 1550 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B179 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 14 1550 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 7 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 9 7900 5250 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 5C95CBCC +P 2700 3950 +F 0 "U35" H 2700 3850 60 0000 C CNN +F 1 "d_inverter" H 2700 4100 60 0000 C CNN +F 2 "" H 2750 3900 60 0000 C CNN +F 3 "" H 2750 3900 60 0000 C CNN + 1 2700 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 5C95CC99 +P 2650 6600 +F 0 "U34" H 2650 6500 60 0000 C CNN +F 1 "d_inverter" H 2650 6750 60 0000 C CNN +F 2 "" H 2700 6550 60 0000 C CNN +F 3 "" H 2700 6550 60 0000 C CNN + 1 2650 6600 + 1 0 0 -1 +$EndComp +Text Notes 1750 2050 0 60 ~ 12 +A0 +Text Notes 1800 2600 0 60 ~ 12 +A1 +Text Notes 1800 3200 0 60 ~ 12 +A2 +Text Notes 1750 3700 0 60 ~ 12 +A3\n +Text Notes 1750 3950 0 60 ~ 12 +EnA\n +Text Notes 1800 4700 0 60 ~ 12 +B0\n +Text Notes 1800 5250 0 60 ~ 12 +B1 +Text Notes 1800 5850 0 60 ~ 12 +B2 +Text Notes 1750 6350 0 60 ~ 12 +B3 +Text Notes 1800 6600 0 60 ~ 12 +EnB +Text Notes 2000 950 0 60 ~ 12 +S1\n +Text Notes 2000 1350 0 60 ~ 12 +S0 +Text Notes 7350 2600 0 60 ~ 12 +YA +Text Notes 7400 5250 0 60 ~ 12 +YB +$Comp +L 4_and X8 +U 1 1 5C9D0C22 +P 4200 1950 +F 0 "X8" H 4250 1950 60 0000 C CNN +F 1 "4_and" H 4300 2050 60 0000 C CNN +F 2 "" H 4200 1950 60 0000 C CNN +F 3 "" H 4200 1950 60 0000 C CNN + 1 4200 1950 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X9 +U 1 1 5C9D0CA2 +P 4200 2500 +F 0 "X9" H 4250 2500 60 0000 C CNN +F 1 "4_and" H 4300 2600 60 0000 C CNN +F 2 "" H 4200 2500 60 0000 C CNN +F 3 "" H 4200 2500 60 0000 C CNN + 1 4200 2500 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 5C9D0D16 +P 4150 3100 +F 0 "X4" H 4200 3100 60 0000 C CNN +F 1 "4_and" H 4250 3200 60 0000 C CNN +F 2 "" H 4150 3100 60 0000 C CNN +F 3 "" H 4150 3100 60 0000 C CNN + 1 4150 3100 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X10 +U 1 1 5C9D0D93 +P 4200 3600 +F 0 "X10" H 4250 3600 60 0000 C CNN +F 1 "4_and" H 4300 3700 60 0000 C CNN +F 2 "" H 4200 3600 60 0000 C CNN +F 3 "" H 4200 3600 60 0000 C CNN + 1 4200 3600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 5C9D182A +P 4150 4600 +F 0 "X5" H 4200 4600 60 0000 C CNN +F 1 "4_and" H 4250 4700 60 0000 C CNN +F 2 "" H 4150 4600 60 0000 C CNN +F 3 "" H 4150 4600 60 0000 C CNN + 1 4150 4600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 5C9D1830 +P 4150 5150 +F 0 "X6" H 4200 5150 60 0000 C CNN +F 1 "4_and" H 4250 5250 60 0000 C CNN +F 2 "" H 4150 5150 60 0000 C CNN +F 3 "" H 4150 5150 60 0000 C CNN + 1 4150 5150 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 5C9D1836 +P 4100 5750 +F 0 "X3" H 4150 5750 60 0000 C CNN +F 1 "4_and" H 4200 5850 60 0000 C CNN +F 2 "" H 4100 5750 60 0000 C CNN +F 3 "" H 4100 5750 60 0000 C CNN + 1 4100 5750 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 5C9D183C +P 4150 6250 +F 0 "X7" H 4200 6250 60 0000 C CNN +F 1 "4_and" H 4250 6350 60 0000 C CNN +F 2 "" H 4150 6250 60 0000 C CNN +F 3 "" H 4150 6250 60 0000 C CNN + 1 4150 6250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 1800 3800 1800 +Wire Wire Line + 3100 1350 3100 5600 +Wire Wire Line + 3200 1900 3800 1900 +Wire Wire Line + 3200 950 3200 5100 +Wire Wire Line + 2950 1350 3100 1350 +Connection ~ 3100 1800 +Wire Wire Line + 3000 950 3200 950 +Connection ~ 3200 1900 +Wire Wire Line + 1800 950 2400 950 +Wire Wire Line + 1800 1350 2350 1350 +Wire Wire Line + 2200 950 2200 6200 +Connection ~ 2200 950 +Wire Wire Line + 2300 1350 2300 6100 +Wire Wire Line + 3300 2100 3800 2100 +Wire Wire Line + 3300 2100 3300 3800 +Wire Wire Line + 3300 2700 3800 2700 +Wire Wire Line + 3300 3300 3750 3300 +Connection ~ 3300 2700 +Wire Wire Line + 3000 3800 3800 3800 +Connection ~ 3300 3300 +Wire Wire Line + 1600 3700 3800 3700 +Wire Wire Line + 1600 3200 3750 3200 +Wire Wire Line + 3400 2600 1600 2600 +Wire Wire Line + 1600 2050 3800 2050 +Wire Wire Line + 3000 3800 3000 3950 +Wire Wire Line + 1600 3950 2400 3950 +Connection ~ 3300 3800 +Wire Wire Line + 3100 4450 3750 4450 +Wire Wire Line + 3200 4550 3750 4550 +Wire Wire Line + 3300 4800 3750 4800 +Wire Wire Line + 3300 4800 3300 6450 +Wire Wire Line + 3300 5350 3750 5350 +Wire Wire Line + 3300 5950 3700 5950 +Connection ~ 3300 5350 +Wire Wire Line + 3200 6450 3750 6450 +Connection ~ 3300 5950 +Wire Wire Line + 3350 6350 1600 6350 +Wire Wire Line + 1600 5850 3700 5850 +Wire Wire Line + 1600 5250 3750 5250 +Wire Wire Line + 3350 4700 1600 4700 +Wire Wire Line + 3200 6600 3200 6450 +Wire Wire Line + 2950 6600 3200 6600 +Wire Wire Line + 1600 6600 2350 6600 +Connection ~ 3300 6450 +Connection ~ 2300 1350 +Connection ~ 3100 4450 +Connection ~ 3200 4550 +Wire Wire Line + 6550 2600 7600 2600 +Wire Wire Line + 6450 5250 7650 5250 +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3750 5100 +Wire Wire Line + 2300 5000 3750 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3700 5600 +Wire Wire Line + 2200 5700 3700 5700 +Wire Wire Line + 2200 6200 3750 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3750 6100 +Wire Wire Line + 3200 2450 3800 2450 +Connection ~ 3200 2450 +Wire Wire Line + 2300 2350 3800 2350 +Connection ~ 2300 2350 +Wire Wire Line + 2200 3050 3750 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3100 2950 3750 2950 +Connection ~ 3100 2950 +Wire Wire Line + 2300 3450 3800 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 2200 3550 3800 3550 +Connection ~ 2200 3550 +Wire Wire Line + 3800 2050 3800 2000 +Wire Wire Line + 3400 2600 3400 2550 +Wire Wire Line + 3400 2550 3800 2550 +Wire Wire Line + 3800 2700 3800 2650 +Wire Wire Line + 3750 3200 3750 3150 +Wire Wire Line + 3750 3300 3750 3250 +Wire Wire Line + 3800 3700 3800 3650 +Wire Wire Line + 3800 3800 3800 3750 +Wire Wire Line + 3350 4700 3350 4650 +Wire Wire Line + 3350 4650 3750 4650 +Wire Wire Line + 3750 4800 3750 4750 +Wire Wire Line + 3750 5250 3750 5200 +Wire Wire Line + 3750 5350 3750 5300 +Wire Wire Line + 3700 5850 3700 5800 +Wire Wire Line + 3700 5950 3700 5900 +Wire Wire Line + 3350 6350 3350 6300 +Wire Wire Line + 3350 6300 3750 6300 +Wire Wire Line + 3750 6450 3750 6400 +$Comp +L 4_OR X1 +U 1 1 5C9D22F7 +P 5900 5250 +F 0 "X1" H 6000 5250 60 0000 C CNN +F 1 "4_OR" H 6050 5350 60 0000 C CNN +F 2 "" H 5900 5250 60 0000 C CNN +F 3 "" H 5900 5250 60 0000 C CNN + 1 5900 5250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 5100 5550 4600 +Wire Wire Line + 5550 4600 4650 4600 +Wire Wire Line + 5550 5200 4650 5200 +Wire Wire Line + 4650 5200 4650 5150 +Wire Wire Line + 4600 5750 4600 5300 +Wire Wire Line + 4600 5300 5550 5300 +Wire Wire Line + 4650 6250 4650 5400 +Wire Wire Line + 4650 5400 5550 5400 +$Comp +L 4_OR X2 +U 1 1 5C9D28DE +P 6000 2600 +F 0 "X2" H 6100 2600 60 0000 C CNN +F 1 "4_OR" H 6150 2700 60 0000 C CNN +F 2 "" H 6000 2600 60 0000 C CNN +F 3 "" H 6000 2600 60 0000 C CNN + 1 6000 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 1950 5650 1950 +Wire Wire Line + 5650 1950 5650 2450 +Wire Wire Line + 5650 2550 4700 2550 +Wire Wire Line + 4700 2550 4700 2500 +Wire Wire Line + 4650 3100 4650 2650 +Wire Wire Line + 4650 2650 5650 2650 +Wire Wire Line + 4700 3600 4700 2750 +Wire Wire Line + 4700 2750 5650 2750 +$Comp +L PORT U1 +U 16 1 5D11F8AE +P 7450 1200 +F 0 "U1" H 7500 1300 30 0000 C CNN +F 1 "PORT" H 7450 1200 30 0000 C CNN +F 2 "" H 7450 1200 60 0000 C CNN +F 3 "" H 7450 1200 60 0000 C CNN + 16 7450 1200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5D11F97A +P 7400 1550 +F 0 "U1" H 7450 1650 30 0000 C CNN +F 1 "PORT" H 7400 1550 30 0000 C CNN +F 2 "" H 7400 1550 60 0000 C CNN +F 3 "" H 7400 1550 60 0000 C CNN + 8 7400 1550 + -1 0 0 1 +$EndComp +NoConn ~ 7200 1200 +NoConn ~ 7150 1550 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/74153.sub b/src/SubcircuitLibrary/74153/74153.sub new file mode 100644 index 00000000..0bbdea00 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.sub @@ -0,0 +1,34 @@ +* Subcircuit 74153 +.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74153/74153.cir +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad14_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u35 net-_u1-pad1_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad15_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad5_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad10_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad11_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad12_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad13_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad9_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad7_ 4_OR +a1 net-_u1-pad14_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 net-_u1-pad1_ net-_u35-pad2_ u35 +a4 net-_u1-pad15_ net-_u34-pad2_ u34 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74153 \ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/74153_Previous_Values.xml b/src/SubcircuitLibrary/74153/74153_Previous_Values.xml new file mode 100644 index 00000000..028f2d75 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_andd_andd_andd_andd_andd_andd_ord_ord_ord_inverterd_inverterd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_ord_ord_ord_andd_andd_andd_andd_inverterd_inverter/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_OR/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_OR/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesmsmsSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib b/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib new file mode 100644 index 00000000..32c8b38f --- /dev/null +++ b/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.cir b/src/SubcircuitLibrary/74153/Dual4to1MUX.cir new file mode 100644 index 00000000..5dddad23 --- /dev/null +++ b/src/SubcircuitLibrary/74153/Dual4to1MUX.cir @@ -0,0 +1,45 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U14 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U25 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and +U5 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and +U7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and +U18 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and +U24 Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and +U28 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or +U29 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or +U32 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or +U2 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U3 Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter +U15 Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U6 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and +U8 Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and +U4 Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and +U16 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and +U27 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and +U22 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and +U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and +U23 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and +U19 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and +U26 Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and +U30 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or +U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or +U33 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or +U17 Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and +U11 Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U13 Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and +U9 Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U34 Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter +U35 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter + +.end diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.sch b/src/SubcircuitLibrary/74153/Dual4to1MUX.sch new file mode 100644 index 00000000..bb19bb7d --- /dev/null +++ b/src/SubcircuitLibrary/74153/Dual4to1MUX.sch @@ -0,0 +1,814 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:74153-cache 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5C93AE63 +P 1350 6350 +F 0 "U1" H 1400 6450 30 0000 C CNN +F 1 "PORT" H 1350 6350 30 0000 C CNN +F 2 "" H 1350 6350 60 0000 C CNN +F 3 "" H 1350 6350 60 0000 C CNN + 9 1350 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C93AECA +P 1350 3950 +F 0 "U1" H 1400 4050 30 0000 C CNN +F 1 "PORT" H 1350 3950 30 0000 C CNN +F 2 "" H 1350 3950 60 0000 C CNN +F 3 "" H 1350 3950 60 0000 C CNN + 5 1350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C93AF79 +P 1350 6600 +F 0 "U1" H 1400 6700 30 0000 C CNN +F 1 "PORT" H 1350 6600 30 0000 C CNN +F 2 "" H 1350 6600 60 0000 C CNN +F 3 "" H 1350 6600 60 0000 C CNN + 10 1350 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C93B10A +P 1550 950 +F 0 "U1" H 1600 1050 30 0000 C CNN +F 1 "PORT" H 1550 950 30 0000 C CNN +F 2 "" H 1550 950 60 0000 C CNN +F 3 "" H 1550 950 60 0000 C CNN + 11 1550 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C93B179 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 2600 7600 2600 +Wire Wire Line + 7300 5250 7650 5250 +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3400 5100 +Wire Wire Line + 3400 5000 2300 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3350 5600 +Wire Wire Line + 2200 5700 3350 5700 +Wire Wire Line + 2200 6200 3350 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3350 6100 +Wire Wire Line + 3400 2450 3200 2450 +Connection ~ 3200 2450 +Wire Wire Line + 3400 2350 2300 2350 +Connection ~ 2300 2350 +Wire Wire Line + 3350 3050 2200 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3350 2950 3100 2950 +Connection ~ 3100 2950 +Wire Wire Line + 3350 3450 2300 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 3350 3550 2200 3550 +Connection ~ 2200 3550 +$Comp +L d_inverter U34 +U 1 1 5C95C9D0 +P 2650 3950 +F 0 "U34" H 2650 3850 60 0000 C CNN +F 1 "d_inverter" H 2650 4100 60 0000 C CNN +F 2 "" H 2700 3900 60 0000 C CNN +F 3 "" H 2700 3900 60 0000 C CNN + 1 2650 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 5C95CD17 +P 2700 6600 +F 0 "U35" H 2700 6500 60 0000 C CNN +F 1 "d_inverter" H 2700 6750 60 0000 C CNN +F 2 "" H 2750 6550 60 0000 C CNN +F 3 "" H 2750 6550 60 0000 C CNN + 1 2700 6600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/analysis b/src/SubcircuitLibrary/74153/analysis new file mode 100644 index 00000000..655d30ed --- /dev/null +++ b/src/SubcircuitLibrary/74153/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-00 0e-03 \ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/3_and-cache.lib b/src/SubcircuitLibrary/74157/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74157/3_and.cir b/src/SubcircuitLibrary/74157/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/74157/3_and.cir.out b/src/SubcircuitLibrary/74157/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74157/3_and.pro b/src/SubcircuitLibrary/74157/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/74157/3_and.sch b/src/SubcircuitLibrary/74157/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74157/3_and.sub b/src/SubcircuitLibrary/74157/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml b/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/74157-cache.lib b/src/SubcircuitLibrary/74157/74157-cache.lib new file mode 100644 index 00000000..d72d1628 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-74157 +# +DEF 3_and-RESCUE-74157 X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-74157" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74157/74157-rescue.lib b/src/SubcircuitLibrary/74157/74157-rescue.lib new file mode 100644 index 00000000..cac27fc1 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-74157 +# +DEF 3_and-RESCUE-74157 X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-74157" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74157/74157.cir b/src/SubcircuitLibrary/74157/74157.cir new file mode 100644 index 00000000..cfd1c0e9 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.cir @@ -0,0 +1,25 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/74157/74157.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 20:50:36 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad4_ d_or +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad7_ d_or +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad9_ d_or +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad12_ d_or +U3 Net-_U1-Pad1_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U2 Net-_U1-Pad15_ Net-_U2-Pad2_ d_inverter +X2 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad1_ 3_and +X3 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U21-Pad1_ 3_and +X4 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U22-Pad1_ 3_and +X5 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad14_ Net-_U23-Pad1_ 3_and +X6 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U20-Pad2_ 3_and +X7 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U21-Pad2_ 3_and +X1 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad10_ Net-_U22-Pad2_ 3_and +X8 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad13_ Net-_U23-Pad2_ 3_and + +.end diff --git a/src/SubcircuitLibrary/74157/74157.cir.out b/src/SubcircuitLibrary/74157/74157.cir.out new file mode 100644 index 00000000..b9a19223 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.cir.out @@ -0,0 +1,45 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74157/74157.cir + +.include 3_and.sub +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad4_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad7_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad9_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad12_ d_or +* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad11_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u23-pad1_ 3_and +x6 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad3_ net-_u20-pad2_ 3_and +x7 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad2_ 3_and +x1 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad10_ net-_u22-pad2_ 3_and +x8 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad13_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad4_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad7_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad9_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad12_ u23 +a5 net-_u1-pad1_ net-_u3-pad2_ u3 +a6 net-_u1-pad15_ net-_u2-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74157/74157.pro b/src/SubcircuitLibrary/74157/74157.pro new file mode 100644 index 00000000..4042e1e9 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.pro @@ -0,0 +1,44 @@ +update=Tue Jun 25 20:59:09 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=74157-rescue +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/74157/74157.sch b/src/SubcircuitLibrary/74157/74157.sch new file mode 100644 index 00000000..c7c64ece --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.sch @@ -0,0 +1,560 @@ +EESchema Schematic File Version 2 +LIBS:74157-rescue +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:74157-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U20 +U 1 1 5C95E06C +P 6650 3300 +F 0 "U20" H 6650 3300 60 0000 C CNN +F 1 "d_or" H 6650 3400 60 0000 C CNN +F 2 "" H 6650 3300 60 0000 C CNN +F 3 "" H 6650 3300 60 0000 C CNN + 1 6650 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U21 +U 1 1 5C95E114 +P 6650 3800 +F 0 "U21" H 6650 3800 60 0000 C CNN +F 1 "d_or" H 6650 3900 60 0000 C CNN +F 2 "" H 6650 3800 60 0000 C CNN +F 3 "" H 6650 3800 60 0000 C CNN + 1 6650 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U22 +U 1 1 5C95E16E +P 6650 4250 +F 0 "U22" H 6650 4250 60 0000 C CNN +F 1 "d_or" H 6650 4350 60 0000 C CNN +F 2 "" H 6650 4250 60 0000 C CNN +F 3 "" H 6650 4250 60 0000 C CNN + 1 6650 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U23 +U 1 1 5C95E1C9 +P 6650 4750 +F 0 "U23" H 6650 4750 60 0000 C CNN +F 1 "d_or" H 6650 4850 60 0000 C CNN +F 2 "" H 6650 4750 60 0000 C CNN +F 3 "" H 6650 4750 60 0000 C CNN + 1 6650 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C95E74D +P 2750 6250 +F 0 "U3" H 2750 6150 60 0000 C CNN +F 1 "d_inverter" H 2750 6400 60 0000 C CNN +F 2 "" H 2800 6200 60 0000 C CNN +F 3 "" H 2800 6200 60 0000 C CNN + 1 2750 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C95E920 +P 1400 1850 +F 0 "U1" H 1450 1950 30 0000 C CNN +F 1 "PORT" H 1400 1850 30 0000 C CNN +F 2 "" H 1400 1850 60 0000 C CNN +F 3 "" H 1400 1850 60 0000 C CNN + 2 1400 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C95E9CF +P 1400 2150 +F 0 "U1" H 1450 2250 30 0000 C CNN +F 1 "PORT" H 1400 2150 30 0000 C CNN +F 2 "" H 1400 2150 60 0000 C CNN +F 3 "" H 1400 2150 60 0000 C CNN + 3 1400 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C95EA28 +P 1400 3350 +F 0 "U1" H 1450 3450 30 0000 C CNN +F 1 "PORT" H 1400 3350 30 0000 C CNN +F 2 "" H 1400 3350 60 0000 C CNN +F 3 "" H 1400 3350 60 0000 C CNN + 11 1400 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C95EA9C +P 1400 3600 +F 0 "U1" H 1450 3700 30 0000 C CNN +F 1 "PORT" H 1400 3600 30 0000 C CNN +F 2 "" H 1400 3600 60 0000 C CNN +F 3 "" H 1400 3600 60 0000 C CNN + 10 1400 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C95EAFD +P 1400 2650 +F 0 "U1" H 1450 2750 30 0000 C CNN +F 1 "PORT" H 1400 2650 30 0000 C CNN +F 2 "" H 1400 2650 60 0000 C CNN +F 3 "" H 1400 2650 60 0000 C CNN + 5 1400 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C95EB63 +P 1400 2900 +F 0 "U1" H 1450 3000 30 0000 C CNN +F 1 "PORT" H 1400 2900 30 0000 C CNN +F 2 "" H 1400 2900 60 0000 C CNN +F 3 "" H 1400 2900 60 0000 C CNN + 6 1400 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C95EC38 +P 1400 4300 +F 0 "U1" H 1450 4400 30 0000 C CNN +F 1 "PORT" H 1400 4300 30 0000 C CNN +F 2 "" H 1400 4300 60 0000 C CNN +F 3 "" H 1400 4300 60 0000 C CNN + 13 1400 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C95ECA1 +P 1450 6250 +F 0 "U1" H 1500 6350 30 0000 C CNN +F 1 "PORT" H 1450 6250 30 0000 C CNN +F 2 "" H 1450 6250 60 0000 C CNN +F 3 "" H 1450 6250 60 0000 C CNN + 1 1450 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 5C95ED51 +P 1400 6650 +F 0 "U1" H 1450 6750 30 0000 C CNN +F 1 "PORT" H 1400 6650 30 0000 C CNN +F 2 "" H 1400 6650 60 0000 C CNN +F 3 "" H 1400 6650 60 0000 C CNN + 15 1400 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C95EDCC +P 8550 3250 +F 0 "U1" H 8600 3350 30 0000 C CNN +F 1 "PORT" H 8550 3250 30 0000 C CNN +F 2 "" H 8550 3250 60 0000 C CNN +F 3 "" H 8550 3250 60 0000 C CNN + 4 8550 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C95EEA6 +P 8550 3750 +F 0 "U1" H 8600 3850 30 0000 C CNN +F 1 "PORT" H 8550 3750 30 0000 C CNN +F 2 "" H 8550 3750 60 0000 C CNN +F 3 "" H 8550 3750 60 0000 C CNN + 7 8550 3750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C95EF2D +P 8550 4200 +F 0 "U1" H 8600 4300 30 0000 C CNN +F 1 "PORT" H 8550 4200 30 0000 C CNN +F 2 "" H 8550 4200 60 0000 C CNN +F 3 "" H 8550 4200 60 0000 C CNN + 9 8550 4200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C95EFB5 +P 8500 4700 +F 0 "U1" H 8550 4800 30 0000 C CNN +F 1 "PORT" H 8500 4700 30 0000 C CNN +F 2 "" H 8500 4700 60 0000 C CNN +F 3 "" H 8500 4700 60 0000 C CNN + 12 8500 4700 + -1 0 0 1 +$EndComp +Text Notes 1950 1800 0 60 ~ 12 +A0\n +Text Notes 1950 2100 0 60 ~ 12 +A1 +Text Notes 1900 2600 0 60 ~ 12 +B0 +Text Notes 1900 2900 0 60 ~ 12 +B1\n +Text Notes 1900 3350 0 60 ~ 12 +C0\n +Text Notes 1900 3600 0 60 ~ 12 +C1\n +Text Notes 1800 4050 0 60 ~ 12 +D0 +Text Notes 1800 4300 0 60 ~ 12 +D1 +Text Notes 1850 6250 0 60 ~ 12 +SEL\n +Text Notes 1800 6650 0 60 ~ 12 +~EN +$Comp +L d_inverter U2 +U 1 1 5C95FD56 +P 2650 6650 +F 0 "U2" H 2650 6550 60 0000 C CNN +F 1 "d_inverter" H 2650 6800 60 0000 C CNN +F 2 "" H 2700 6600 60 0000 C CNN +F 3 "" H 2700 6600 60 0000 C CNN + 1 2650 6650 + 1 0 0 -1 +$EndComp +Text Notes 7850 3200 0 60 ~ 12 +YA +Text Notes 7850 3700 0 60 ~ 12 +YB +Text Notes 7850 4200 2 60 ~ 12 +YC +Text Notes 7800 4700 0 60 ~ 12 +YD +$Comp +L 3_and-RESCUE-74157 X2 +U 1 1 5C9D0110 +P 3450 2400 +F 0 "X2" H 4350 2700 60 0000 C CNN +F 1 "3_and" H 4400 2900 60 0000 C CNN +F 2 "" H 3450 2400 60 0000 C CNN +F 3 "" H 3450 2400 60 0000 C CNN + 1 3450 2400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and-RESCUE-74157 X3 +U 1 1 5C9D01B8 +P 3450 2900 +F 0 "X3" H 4350 3200 60 0000 C CNN +F 1 "3_and" H 4400 3400 60 0000 C CNN +F 2 "" H 3450 2900 60 0000 C CNN +F 3 "" H 3450 2900 60 0000 C CNN + 1 3450 2900 + 1 0 0 -1 +$EndComp +$Comp +L 3_and-RESCUE-74157 X4 +U 1 1 5C9D0222 +P 3450 3350 +F 0 "X4" H 4350 3650 60 0000 C CNN +F 1 "3_and" H 4400 3850 60 0000 C CNN +F 2 "" H 3450 3350 60 0000 C CNN +F 3 "" H 3450 3350 60 0000 C CNN + 1 3450 3350 + 1 0 0 -1 +$EndComp +$Comp +L 3_and-RESCUE-74157 X5 +U 1 1 5C9D0289 +P 3450 3850 +F 0 "X5" H 4350 4150 60 0000 C CNN +F 1 "3_and" H 4400 4350 60 0000 C CNN +F 2 "" H 3450 3850 60 0000 C CNN +F 3 "" H 3450 3850 60 0000 C CNN + 1 3450 3850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and-RESCUE-74157 X6 +U 1 1 5C9D0361 +P 3450 4650 +F 0 "X6" H 4350 4950 60 0000 C CNN +F 1 "3_and" H 4400 5150 60 0000 C CNN +F 2 "" H 3450 4650 60 0000 C CNN +F 3 "" H 3450 4650 60 0000 C CNN + 1 3450 4650 + 1 0 0 -1 +$EndComp +$Comp +L 3_and-RESCUE-74157 X7 +U 1 1 5C9D0367 +P 3450 5150 +F 0 "X7" H 4350 5450 60 0000 C CNN +F 1 "3_and" H 4400 5650 60 0000 C CNN +F 2 "" H 3450 5150 60 0000 C CNN +F 3 "" H 3450 5150 60 0000 C CNN + 1 3450 5150 + 1 0 0 -1 +$EndComp +$Comp +L 3_and-RESCUE-74157 X1 +U 1 1 5C9D036D +P 3400 5600 +F 0 "X1" H 4300 5900 60 0000 C CNN +F 1 "3_and" H 4350 6100 60 0000 C CNN +F 2 "" H 3400 5600 60 0000 C CNN +F 3 "" H 3400 5600 60 0000 C CNN + 1 3400 5600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and-RESCUE-74157 X8 +U 1 1 5C9D0373 +P 3450 6100 +F 0 "X8" H 4350 6400 60 0000 C CNN +F 1 "3_and" H 4400 6600 60 0000 C CNN +F 2 "" H 3450 6100 60 0000 C CNN +F 3 "" H 3450 6100 60 0000 C CNN + 1 3450 6100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5D123D14 +P 8450 1500 +F 0 "U1" H 8500 1600 30 0000 C CNN +F 1 "PORT" H 8450 1500 30 0000 C CNN +F 2 "" H 8450 1500 60 0000 C CNN +F 3 "" H 8450 1500 60 0000 C CNN + 8 8450 1500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 5D123E38 +P 8450 1850 +F 0 "U1" H 8500 1950 30 0000 C CNN +F 1 "PORT" H 8450 1850 30 0000 C CNN +F 2 "" H 8450 1850 60 0000 C CNN +F 3 "" H 8450 1850 60 0000 C CNN + 16 8450 1850 + -1 0 0 1 +$EndComp +Wire Wire Line + 1650 1850 2750 1850 +Wire Wire Line + 2750 3350 1650 3350 +Wire Wire Line + 2750 3050 2750 3350 +Wire Wire Line + 2800 4050 1650 4050 +Wire Wire Line + 2800 3550 2800 4050 +Wire Wire Line + 2200 2150 2200 4350 +Wire Wire Line + 2200 2150 1650 2150 +Wire Wire Line + 2150 2900 2150 4850 +Wire Wire Line + 2150 2900 1650 2900 +Wire Wire Line + 2100 3600 2100 5300 +Wire Wire Line + 2100 3600 1650 3600 +Wire Wire Line + 2050 4300 2050 5800 +Wire Wire Line + 1650 4300 2050 4300 +Wire Wire Line + 2200 5500 2200 6250 +Wire Wire Line + 6200 3200 5950 3200 +Wire Wire Line + 5950 3200 5950 2000 +Wire Wire Line + 5950 2000 4750 2000 +Wire Wire Line + 6200 3700 5850 3700 +Wire Wire Line + 5850 3700 5850 2500 +Wire Wire Line + 5850 2500 4750 2500 +Wire Wire Line + 6200 4150 5750 4150 +Wire Wire Line + 5750 4150 5750 2950 +Wire Wire Line + 5750 2950 4750 2950 +Wire Wire Line + 6200 4650 5650 4650 +Wire Wire Line + 5650 4650 5650 3450 +Wire Wire Line + 5650 3450 4750 3450 +Wire Wire Line + 4750 4250 5450 4250 +Wire Wire Line + 5450 4250 5450 3300 +Wire Wire Line + 5450 3300 6200 3300 +Wire Wire Line + 4750 4750 5550 4750 +Wire Wire Line + 5550 4750 5550 3800 +Wire Wire Line + 5550 3800 6200 3800 +Wire Wire Line + 4700 5200 5600 5200 +Wire Wire Line + 5600 5200 5600 4250 +Wire Wire Line + 5600 4250 6200 4250 +Wire Wire Line + 4750 5700 5700 5700 +Wire Wire Line + 5700 5700 5700 4750 +Wire Wire Line + 5700 4750 6200 4750 +Wire Wire Line + 7100 3250 8300 3250 +Wire Wire Line + 7100 3750 8300 3750 +Wire Wire Line + 7100 4200 8300 4200 +Wire Wire Line + 7100 4700 8250 4700 +Wire Wire Line + 1700 6250 2450 6250 +Connection ~ 2200 6250 +Wire Wire Line + 3400 6650 2950 6650 +Wire Wire Line + 1650 6650 2350 6650 +Wire Wire Line + 3450 2000 3900 2000 +Wire Wire Line + 3450 2000 3450 5700 +Wire Wire Line + 3450 2500 3900 2500 +Wire Wire Line + 3450 2950 3900 2950 +Connection ~ 3450 2500 +Wire Wire Line + 3450 3450 3900 3450 +Connection ~ 3450 2950 +Wire Wire Line + 3450 4250 3900 4250 +Connection ~ 3450 3450 +Wire Wire Line + 3450 4750 3900 4750 +Connection ~ 3450 4250 +Wire Wire Line + 3450 5200 3850 5200 +Connection ~ 3450 4750 +Wire Wire Line + 3400 5700 3900 5700 +Connection ~ 3450 5200 +Wire Wire Line + 3300 5600 3900 5600 +Wire Wire Line + 3300 4150 3300 5600 +Wire Wire Line + 3300 5100 3850 5100 +Wire Wire Line + 3300 4650 3900 4650 +Connection ~ 3300 5100 +Wire Wire Line + 3300 4150 3900 4150 +Connection ~ 3300 4650 +Wire Wire Line + 3250 3350 3900 3350 +Wire Wire Line + 3250 1900 3250 3350 +Wire Wire Line + 3250 2850 3900 2850 +Wire Wire Line + 3250 2400 3900 2400 +Connection ~ 3250 2850 +Wire Wire Line + 3250 1900 3900 1900 +Connection ~ 3250 2400 +Wire Wire Line + 3250 3000 3100 3000 +Wire Wire Line + 3100 3000 3100 6250 +Wire Wire Line + 3100 6250 3050 6250 +Connection ~ 3250 3000 +Wire Wire Line + 3300 5500 2200 5500 +Connection ~ 3300 5500 +Wire Wire Line + 3400 6650 3400 5700 +Connection ~ 3450 5700 +Wire Wire Line + 3900 2100 2750 2100 +Wire Wire Line + 2750 2100 2750 1850 +Wire Wire Line + 3900 2600 1650 2600 +Wire Wire Line + 1650 2600 1650 2650 +Wire Wire Line + 3900 3050 2750 3050 +Wire Wire Line + 3900 3550 2800 3550 +Wire Wire Line + 2200 4350 3900 4350 +Wire Wire Line + 2150 4850 3900 4850 +Wire Wire Line + 2100 5300 3850 5300 +Wire Wire Line + 2050 5800 3900 5800 +$Comp +L PORT U1 +U 14 1 5C95EBC8 +P 1400 4050 +F 0 "U1" H 1450 4150 30 0000 C CNN +F 1 "PORT" H 1400 4050 30 0000 C CNN +F 2 "" H 1400 4050 60 0000 C CNN +F 3 "" H 1400 4050 60 0000 C CNN + 14 1400 4050 + 1 0 0 -1 +$EndComp +NoConn ~ 8200 1500 +NoConn ~ 8200 1850 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74157/74157.sub b/src/SubcircuitLibrary/74157/74157.sub new file mode 100644 index 00000000..54897c26 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.sub @@ -0,0 +1,39 @@ +* Subcircuit 74157 +.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74157/74157.cir +.include 3_and.sub +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad4_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad7_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad9_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad12_ d_or +* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad11_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u23-pad1_ 3_and +x6 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad3_ net-_u20-pad2_ 3_and +x7 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad2_ 3_and +x1 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad10_ net-_u22-pad2_ 3_and +x8 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad13_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad4_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad7_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad9_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad12_ u23 +a5 net-_u1-pad1_ net-_u3-pad2_ u3 +a6 net-_u1-pad15_ net-_u2-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74157 \ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml new file mode 100644 index 00000000..6fa26ea2 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_ord_ord_ord_ord_inverterd_inverter/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/analysis b/src/SubcircuitLibrary/74157/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/74157/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/3_and-cache.lib b/src/SubcircuitLibrary/7485/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/3_and.cir b/src/SubcircuitLibrary/7485/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/3_and.cir.out b/src/SubcircuitLibrary/7485/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/3_and.pro b/src/SubcircuitLibrary/7485/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/7485/3_and.sch b/src/SubcircuitLibrary/7485/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/3_and.sub b/src/SubcircuitLibrary/7485/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/4_and-cache.lib b/src/SubcircuitLibrary/7485/4_and-cache.lib new file mode 100644 index 00000000..cb84d8f2 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/4_and-rescue.lib b/src/SubcircuitLibrary/7485/4_and-rescue.lib new file mode 100644 index 00000000..6b2c17f7 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/4_and.cir b/src/SubcircuitLibrary/7485/4_and.cir new file mode 100644 index 00000000..35e46097 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/4_and.cir.out b/src/SubcircuitLibrary/7485/4_and.cir.out new file mode 100644 index 00000000..6e35b18a --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/4_and.pro b/src/SubcircuitLibrary/7485/4_and.pro new file mode 100644 index 00000000..814ad76a --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.pro @@ -0,0 +1,58 @@ +update=06/01/19 15:08:42 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/7485/4_and.sch b/src/SubcircuitLibrary/7485/4_and.sch new file mode 100644 index 00000000..2d8296d4 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/4_and.sub b/src/SubcircuitLibrary/7485/4_and.sub new file mode 100644 index 00000000..bf20b628 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_and-cache.lib b/src/SubcircuitLibrary/7485/5_and-cache.lib new file mode 100644 index 00000000..4cf915be --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/5_and.cir b/src/SubcircuitLibrary/7485/5_and.cir new file mode 100644 index 00000000..ca1199bd --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/5_and.cir.out b/src/SubcircuitLibrary/7485/5_and.cir.out new file mode 100644 index 00000000..20d3f8a5 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/5_and.pro b/src/SubcircuitLibrary/7485/5_and.pro new file mode 100644 index 00000000..a9d6304f --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/7485/5_and.sch b/src/SubcircuitLibrary/7485/5_and.sch new file mode 100644 index 00000000..0d86cdec --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/5_and.sub b/src/SubcircuitLibrary/7485/5_and.sub new file mode 100644 index 00000000..9d929fcb --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_nor-cache.lib b/src/SubcircuitLibrary/7485/5_nor-cache.lib new file mode 100644 index 00000000..7098010f --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/5_nor.cir b/src/SubcircuitLibrary/7485/5_nor.cir new file mode 100644 index 00000000..0e4db1ea --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor.cir @@ -0,0 +1,19 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor/5_nor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:34:56 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT +X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and + +.end diff --git a/src/SubcircuitLibrary/7485/5_nor.cir.out b/src/SubcircuitLibrary/7485/5_nor.cir.out new file mode 100644 index 00000000..bc90e004 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor.cir.out @@ -0,0 +1,42 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir + +.include 5_and.sub +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/5_nor.pro b/src/SubcircuitLibrary/7485/5_nor.pro new file mode 100644 index 00000000..4716d4ae --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor.pro @@ -0,0 +1,73 @@ +update=Tue Jun 25 23:32:34 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User +LibName37=eSim_Plot +LibName38=eSim_PSpice +LibName39=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/7485/5_nor.sch b/src/SubcircuitLibrary/7485/5_nor.sch new file mode 100644 index 00000000..6bb6fcb8 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor.sch @@ -0,0 +1,275 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:c_gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U8 +U 1 1 5D126275 +P 5600 3300 +F 0 "U8" H 5600 3300 60 0000 C CNN +F 1 "d_and" H 5650 3400 60 0000 C CNN +F 2 "" H 5600 3300 60 0000 C CNN +F 3 "" H 5600 3300 60 0000 C CNN + 1 5600 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3200 5150 2850 +Wire Wire Line + 4150 2650 4150 2350 +Wire Wire Line + 4150 2350 3600 2350 +Wire Wire Line + 4150 2750 4050 2750 +Wire Wire Line + 4050 2750 4050 2550 +Wire Wire Line + 4050 2550 3600 2550 +Wire Wire Line + 4150 2850 3700 2850 +Wire Wire Line + 3700 2850 3700 2750 +Wire Wire Line + 3700 2750 3600 2750 +Wire Wire Line + 4150 2950 3600 2950 +Wire Wire Line + 4150 3050 4150 3150 +Wire Wire Line + 4150 3150 3600 3150 +Wire Wire Line + 5150 3300 3600 3300 +$Comp +L d_inverter U2 +U 1 1 5D126276 +P 3300 2350 +F 0 "U2" H 3300 2250 60 0000 C CNN +F 1 "d_inverter" H 3300 2500 60 0000 C CNN +F 2 "" H 3350 2300 60 0000 C CNN +F 3 "" H 3350 2300 60 0000 C CNN + 1 3300 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5D126277 +P 3300 2550 +F 0 "U3" H 3300 2450 60 0000 C CNN +F 1 "d_inverter" H 3300 2700 60 0000 C CNN +F 2 "" H 3350 2500 60 0000 C CNN +F 3 "" H 3350 2500 60 0000 C CNN + 1 3300 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5D126278 +P 3300 2750 +F 0 "U4" H 3300 2650 60 0000 C CNN +F 1 "d_inverter" H 3300 2900 60 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3300 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5D126279 +P 3300 2950 +F 0 "U5" H 3300 2850 60 0000 C CNN +F 1 "d_inverter" H 3300 3100 60 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 1 3300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5D12627A +P 3300 3150 +F 0 "U6" H 3300 3050 60 0000 C CNN +F 1 "d_inverter" H 3300 3300 60 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 1 3300 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5D12627B +P 3300 3300 +F 0 "U7" H 3300 3200 60 0000 C CNN +F 1 "d_inverter" H 3300 3450 60 0000 C CNN +F 2 "" H 3350 3250 60 0000 C CNN +F 3 "" H 3350 3250 60 0000 C CNN + 1 3300 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2350 2000 2350 +Wire Wire Line + 3000 2550 2000 2550 +Wire Wire Line + 3000 2750 2050 2750 +Wire Wire Line + 3000 2950 2050 2950 +Wire Wire Line + 3000 3150 2050 3150 +Wire Wire Line + 3000 3300 2050 3300 +Wire Wire Line + 6050 3250 6950 3250 +$Comp +L PORT U1 +U 1 1 5D12627C +P 1750 2350 +F 0 "U1" H 1800 2450 30 0000 C CNN +F 1 "PORT" H 1750 2350 30 0000 C CNN +F 2 "" H 1750 2350 60 0000 C CNN +F 3 "" H 1750 2350 60 0000 C CNN + 1 1750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D12627D +P 1750 2550 +F 0 "U1" H 1800 2650 30 0000 C CNN +F 1 "PORT" H 1750 2550 30 0000 C CNN +F 2 "" H 1750 2550 60 0000 C CNN +F 3 "" H 1750 2550 60 0000 C CNN + 2 1750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5D12627E +P 1800 2750 +F 0 "U1" H 1850 2850 30 0000 C CNN +F 1 "PORT" H 1800 2750 30 0000 C CNN +F 2 "" H 1800 2750 60 0000 C CNN +F 3 "" H 1800 2750 60 0000 C CNN + 3 1800 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5D12627F +P 1800 2950 +F 0 "U1" H 1850 3050 30 0000 C CNN +F 1 "PORT" H 1800 2950 30 0000 C CNN +F 2 "" H 1800 2950 60 0000 C CNN +F 3 "" H 1800 2950 60 0000 C CNN + 4 1800 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5D126280 +P 1800 3150 +F 0 "U1" H 1850 3250 30 0000 C CNN +F 1 "PORT" H 1800 3150 30 0000 C CNN +F 2 "" H 1800 3150 60 0000 C CNN +F 3 "" H 1800 3150 60 0000 C CNN + 5 1800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5D126281 +P 1800 3300 +F 0 "U1" H 1850 3400 30 0000 C CNN +F 1 "PORT" H 1800 3300 30 0000 C CNN +F 2 "" H 1800 3300 60 0000 C CNN +F 3 "" H 1800 3300 60 0000 C CNN + 6 1800 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5D126282 +P 7200 3250 +F 0 "U1" H 7250 3350 30 0000 C CNN +F 1 "PORT" H 7200 3250 30 0000 C CNN +F 2 "" H 7200 3250 60 0000 C CNN +F 3 "" H 7200 3250 60 0000 C CNN + 7 7200 3250 + -1 0 0 1 +$EndComp +Text Notes 2400 2350 0 60 ~ 12 +in1 +Text Notes 2400 2550 0 60 ~ 12 +in2 +Text Notes 2400 2750 0 60 ~ 12 +in3 +Text Notes 2400 2950 0 60 ~ 12 +in4 +Text Notes 2400 3150 0 60 ~ 12 +in5 +Text Notes 2400 3300 0 60 ~ 12 +in6 +Text Notes 6350 3250 0 60 ~ 12 +out +$Comp +L 5_and X1 +U 1 1 5D1262D5 +P 4600 2850 +F 0 "X1" H 4650 2750 60 0000 C CNN +F 1 "5_and" H 4700 3000 60 0000 C CNN +F 2 "" H 4600 2850 60 0000 C CNN +F 3 "" H 4600 2850 60 0000 C CNN + 1 4600 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/5_nor.sub b/src/SubcircuitLibrary/7485/5_nor.sub new file mode 100644 index 00000000..dbcdb750 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor.sub @@ -0,0 +1,36 @@ +* Subcircuit 5_nor +.subckt 5_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir +.include 5_and.sub +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_nor \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml b/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml new file mode 100644 index 00000000..75f5258c --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_andd_inverterd_inverterd_inverterd_inverterd_inverterd_inverter/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485-cache.lib b/src/SubcircuitLibrary/7485/7485-cache.lib new file mode 100644 index 00000000..eb9a059e --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485-cache.lib @@ -0,0 +1,177 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_nor +# +DEF 5_nor X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_nor" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 400 60 0 0 0 name~is~c_gate Normal 0 C C +T 0 50 450 60 0 0 0 subcircuit~file Normal 0 C C +A 150 0 316 716 -716 0 1 0 N 250 300 250 -300 +P 2 0 1 0 -300 300 250 300 N +P 4 0 1 0 -300 300 -300 -300 200 -300 250 -300 N +X in1 1 -500 250 200 R 50 50 1 1 I I +X in2 2 -500 150 200 R 50 50 1 1 I I +X in3 3 -500 50 200 R 50 50 1 1 I I +X in4 4 -500 -50 200 R 50 50 1 1 I I +X in5 5 -500 -150 200 R 50 50 1 1 I I +X in6 6 -500 -250 200 R 50 50 1 1 I I +X out 7 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/7485.cir b/src/SubcircuitLibrary/7485/7485.cir new file mode 100644 index 00000000..87188910 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.cir @@ -0,0 +1,42 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/7485/7485.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:22:51 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U6 Net-_U1-Pad15_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and +U2 Net-_U1-Pad15_ Net-_U1-Pad1_ Net-_U18-Pad2_ d_nand +U7 Net-_U18-Pad2_ Net-_U1-Pad1_ Net-_U14-Pad2_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor +U19 Net-_U1-Pad1_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and +U18 Net-_U1-Pad15_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +U8 Net-_U1-Pad13_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and +U3 Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U3-Pad3_ d_nand +U9 Net-_U3-Pad3_ Net-_U1-Pad14_ Net-_U15-Pad2_ d_and +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor +U12 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U5 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U12-Pad2_ d_nand +U13 Net-_U12-Pad2_ Net-_U1-Pad9_ Net-_U13-Pad3_ d_and +U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nor +U10 Net-_U1-Pad12_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U4 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U10-Pad2_ d_nand +U11 Net-_U10-Pad2_ Net-_U1-Pad11_ Net-_U11-Pad3_ d_and +U16 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +X7 Net-_U1-Pad14_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad2_ 3_and +X8 Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X12-Pad3_ 4_and +X3 Net-_U15-Pad3_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U1-Pad12_ Net-_X1-Pad4_ 4_and +X2 Net-_U14-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad13_ Net-_X1-Pad5_ 3_and +X6 Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad10_ Net-_X1-Pad3_ 5_and +X5 Net-_U1-Pad4_ Net-_U17-Pad3_ Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad2_ 5_and +X4 Net-_U1-Pad3_ Net-_U17-Pad3_ Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad1_ 5_and +X11 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X11-Pad6_ 5_and +X10 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X10-Pad6_ 5_and +X9 Net-_U1-Pad9_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X12-Pad4_ 5_and +X13 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad6_ 5_and +X12 Net-_U19-Pad3_ Net-_X12-Pad2_ Net-_X12-Pad3_ Net-_X12-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad5_ 5_nor +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad7_ 5_nor + +.end diff --git a/src/SubcircuitLibrary/7485/7485.cir.out b/src/SubcircuitLibrary/7485/7485.cir.out new file mode 100644 index 00000000..76e4fe6d --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.cir.out @@ -0,0 +1,101 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/7485/7485.cir + +.include 5_nor.sub +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +* u6 net-_u1-pad15_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad15_ net-_u1-pad1_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad1_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u19 net-_u1-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u18 net-_u1-pad15_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u8 net-_u1-pad13_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad13_ net-_u1-pad14_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad14_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad9_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad9_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u10 net-_u1-pad12_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad12_ net-_u1-pad11_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad11_ net-_u11-pad3_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +x7 net-_u1-pad14_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad2_ 3_and +x8 net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x12-pad3_ 4_and +x3 net-_u15-pad3_ net-_u10-pad2_ net-_u14-pad3_ net-_u1-pad12_ net-_x1-pad4_ 4_and +x2 net-_u14-pad3_ net-_u3-pad3_ net-_u1-pad13_ net-_x1-pad5_ 3_and +x6 net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u12-pad2_ net-_u1-pad10_ net-_x1-pad3_ 5_and +x5 net-_u1-pad4_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad2_ 5_and +x4 net-_u1-pad3_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad1_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x11-pad6_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x10-pad6_ 5_and +x9 net-_u1-pad9_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x12-pad4_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad6_ 5_and +x12 net-_u19-pad3_ net-_x12-pad2_ net-_x12-pad3_ net-_x12-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad5_ 5_nor +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad7_ 5_nor +a1 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad15_ net-_u1-pad1_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad1_ ] net-_u14-pad2_ u7 +a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u1-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad13_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad14_ ] net-_u15-pad2_ u9 +a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad9_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 [net-_u1-pad12_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad11_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/7485.pro b/src/SubcircuitLibrary/7485/7485.pro new file mode 100644 index 00000000..fee23d1f --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.pro @@ -0,0 +1,43 @@ +update=Tue Jun 25 23:21:38 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User +LibName10=eSim_Subckt diff --git a/src/SubcircuitLibrary/7485/7485.sch b/src/SubcircuitLibrary/7485/7485.sch new file mode 100644 index 00000000..32175173 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.sch @@ -0,0 +1,1017 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:7485-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U6 +U 1 1 5C9A2432 +P 3150 1200 +F 0 "U6" H 3150 1200 60 0000 C CNN +F 1 "d_and" H 3200 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10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +$Comp +L 3_and X7 +U 1 1 5D1262A3 +P 6850 1300 +F 0 "X7" H 6950 1250 60 0000 C CNN +F 1 "3_and" H 7000 1450 60 0000 C CNN +F 2 "" H 6850 1300 60 0000 C CNN +F 3 "" H 6850 1300 60 0000 C CNN + 1 6850 1300 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X8 +U 1 1 5D126302 +P 6900 1650 +F 0 "X8" H 6950 1600 60 0000 C CNN +F 1 "4_and" H 7000 1750 60 0000 C CNN +F 2 "" H 6900 1650 60 0000 C CNN +F 3 "" H 6900 1650 60 0000 C CNN + 1 6900 1650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 5D12638A +P 6350 6250 +F 0 "X3" H 6400 6200 60 0000 C CNN +F 1 "4_and" H 6450 6350 60 0000 C CNN +F 2 "" H 6350 6250 60 0000 C CNN +F 3 "" H 6350 6250 60 0000 C CNN + 1 6350 6250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 5D126462 +P 6300 6700 +F 0 "X2" H 6400 6650 60 0000 C CNN +F 1 "3_and" H 6450 6850 60 0000 C CNN +F 2 "" H 6300 6700 60 0000 C CNN +F 3 "" H 6300 6700 60 0000 C CNN + 1 6300 6700 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X6 +U 1 1 5D126552 +P 6400 5750 +F 0 "X6" H 6450 5650 60 0000 C CNN +F 1 "5_and" H 6500 5900 60 0000 C CNN +F 2 "" H 6400 5750 60 0000 C CNN +F 3 "" H 6400 5750 60 0000 C CNN + 1 6400 5750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X5 +U 1 1 5D1265DF +P 6400 5200 +F 0 "X5" H 6450 5100 60 0000 C CNN +F 1 "5_and" H 6500 5350 60 0000 C CNN +F 2 "" H 6400 5200 60 0000 C CNN +F 3 "" H 6400 5200 60 0000 C CNN + 1 6400 5200 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X4 +U 1 1 5D12666C +P 6400 4650 +F 0 "X4" H 6450 4550 60 0000 C CNN +F 1 "5_and" H 6500 4800 60 0000 C CNN +F 2 "" H 6400 4650 60 0000 C CNN +F 3 "" H 6400 4650 60 0000 C CNN + 1 6400 4650 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X11 +U 1 1 5D126706 +P 6950 3250 +F 0 "X11" H 7000 3150 60 0000 C CNN +F 1 "5_and" H 7050 3400 60 0000 C CNN +F 2 "" H 6950 3250 60 0000 C CNN +F 3 "" H 6950 3250 60 0000 C CNN + 1 6950 3250 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X10 +U 1 1 5D1267CB +P 6950 2700 +F 0 "X10" H 7000 2600 60 0000 C CNN +F 1 "5_and" H 7050 2850 60 0000 C CNN +F 2 "" H 6950 2700 60 0000 C CNN +F 3 "" H 6950 2700 60 0000 C CNN + 1 6950 2700 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X9 +U 1 1 5D12686F +P 6950 2150 +F 0 "X9" H 7000 2050 60 0000 C CNN +F 1 "5_and" H 7050 2300 60 0000 C CNN +F 2 "" H 6950 2150 60 0000 C CNN +F 3 "" H 6950 2150 60 0000 C CNN + 1 6950 2150 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X13 +U 1 1 5D126AC3 +P 8850 3950 +F 0 "X13" H 8900 3850 60 0000 C CNN +F 1 "5_and" H 8950 4100 60 0000 C CNN +F 2 "" H 8850 3950 60 0000 C CNN +F 3 "" H 8850 3950 60 0000 C CNN + 1 8850 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5D127AEB +P 10550 650 +F 0 "U1" H 10600 750 30 0000 C CNN +F 1 "PORT" H 10550 650 30 0000 C CNN +F 2 "" H 10550 650 60 0000 C CNN +F 3 "" H 10550 650 60 0000 C CNN + 8 10550 650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 5D127BBA +P 10550 900 +F 0 "U1" H 10600 1000 30 0000 C CNN +F 1 "PORT" H 10550 900 30 0000 C CNN +F 2 "" H 10550 900 60 0000 C CNN +F 3 "" H 10550 900 60 0000 C CNN + 16 10550 900 + -1 0 0 1 +$EndComp +NoConn ~ 10300 650 +NoConn ~ 10300 900 +NoConn ~ 2950 10200 +$Comp +L 5_nor X12 +U 1 1 5D12919D +P 8900 2050 +F 0 "X12" H 8950 1950 60 0000 C CNN +F 1 "5_nor" H 9000 2200 60 0000 C CNN +F 2 "" H 8900 2050 60 0000 C CNN +F 3 "" H 8900 2050 60 0000 C CNN + 1 8900 2050 + 1 0 0 -1 +$EndComp +$Comp +L 5_nor X1 +U 1 1 5D12935A +P 8700 5450 +F 0 "X1" H 8750 5350 60 0000 C CNN +F 1 "5_nor" H 8800 5600 60 0000 C CNN +F 2 "" H 8700 5450 60 0000 C CNN +F 3 "" H 8700 5450 60 0000 C CNN + 1 8700 5450 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/7485.sub b/src/SubcircuitLibrary/7485/7485.sub new file mode 100644 index 00000000..63ea7f3b --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.sub @@ -0,0 +1,95 @@ +* Subcircuit 7485 +.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/7485/7485.cir +.include 5_nor.sub +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +* u6 net-_u1-pad15_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad15_ net-_u1-pad1_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad1_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u19 net-_u1-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u18 net-_u1-pad15_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u8 net-_u1-pad13_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad13_ net-_u1-pad14_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad14_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad9_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad9_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u10 net-_u1-pad12_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad12_ net-_u1-pad11_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad11_ net-_u11-pad3_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +x7 net-_u1-pad14_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad2_ 3_and +x8 net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x12-pad3_ 4_and +x3 net-_u15-pad3_ net-_u10-pad2_ net-_u14-pad3_ net-_u1-pad12_ net-_x1-pad4_ 4_and +x2 net-_u14-pad3_ net-_u3-pad3_ net-_u1-pad13_ net-_x1-pad5_ 3_and +x6 net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u12-pad2_ net-_u1-pad10_ net-_x1-pad3_ 5_and +x5 net-_u1-pad4_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad2_ 5_and +x4 net-_u1-pad3_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad1_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x11-pad6_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x10-pad6_ 5_and +x9 net-_u1-pad9_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x12-pad4_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad6_ 5_and +x12 net-_u19-pad3_ net-_x12-pad2_ net-_x12-pad3_ net-_x12-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad5_ 5_nor +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad7_ 5_nor +a1 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad15_ net-_u1-pad1_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad1_ ] net-_u14-pad2_ u7 +a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u1-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad13_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad14_ ] net-_u15-pad2_ u9 +a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad9_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 [net-_u1-pad12_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad11_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 7485 \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml new file mode 100644 index 00000000..124a0047 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_nandd_andd_nord_andd_andd_andd_nandd_andd_nord_andd_nandd_andd_nord_andd_nandd_andd_nord_inverterd_inverterd_inverterd_inverterd_inverterd_inverter/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485mod-cache.lib b/src/SubcircuitLibrary/7485/7485mod-cache.lib new file mode 100644 index 00000000..f1f7990e --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485mod-cache.lib @@ -0,0 +1,175 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# c_gate +# +DEF c_gate X 0 40 Y Y 1 F N +F0 "X" 5900 4450 60 H V C CNN +F1 "c_gate" 5950 4700 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250 +P 2 0 1 0 5550 4850 6100 4850 N +P 4 0 1 0 5550 4850 5550 4250 6050 4250 6100 4250 N +X in1 1 5350 4800 200 R 50 50 1 1 I I +X in2 2 5350 4700 200 R 50 50 1 1 I I +X in3 3 5350 4600 200 R 50 50 1 1 I I +X in4 4 5350 4500 200 R 50 50 1 1 I I +X in5 5 5350 4400 200 R 50 50 1 1 I I +X in6 6 5350 4300 200 R 50 50 1 1 I I +X out 7 6500 4550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/7485mod.sch b/src/SubcircuitLibrary/7485/7485mod.sch new file mode 100644 index 00000000..9114b802 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485mod.sch @@ -0,0 +1,1007 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:7485-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U6 +U 1 1 5C9A2432 +P 3150 1200 +F 0 "U6" H 3150 1200 60 0000 C CNN +F 1 "d_and" H 3200 1300 60 0000 C CNN +F 2 "" H 3150 1200 60 0000 C CNN +F 3 "" H 3150 1200 60 0000 C CNN + 1 3150 1200 + 1 0 0 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"" H 800 3600 60 0000 C CNN +F 3 "" H 800 3600 60 0000 C CNN + 3 800 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 3250 1050 3150 +Wire Wire Line + 1050 3550 1050 3600 +Wire Wire Line + 1350 4000 1350 4100 +Wire Wire Line + 1350 4100 1200 4100 +Wire Wire Line + 9550 2050 9850 2050 +Wire Wire Line + 9400 3950 9850 3950 +Wire Wire Line + 9350 5450 9900 5450 +$Comp +L PORT U1 +U 12 1 5C9A9B26 +P 10100 2050 +F 0 "U1" H 10150 2150 30 0000 C CNN +F 1 "PORT" H 10100 2050 30 0000 C CNN +F 2 "" H 10100 2050 60 0000 C CNN +F 3 "" H 10100 2050 60 0000 C CNN + 12 10100 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C9A9BCA +P 10100 3950 +F 0 "U1" H 10150 4050 30 0000 C CNN +F 1 "PORT" H 10100 3950 30 0000 C CNN +F 2 "" H 10100 3950 60 0000 C CNN +F 3 "" H 10100 3950 60 0000 C CNN + 13 10100 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C9A9CA0 +P 10150 5450 +F 0 "U1" H 10200 5550 30 0000 C CNN +F 1 "PORT" H 10150 5450 30 0000 C CNN +F 2 "" H 10150 5450 60 0000 C CNN +F 3 "" H 10150 5450 60 0000 C CNN + 14 10150 5450 + -1 0 0 1 +$EndComp +Text Notes 9650 2000 0 60 ~ 12 +A>B +Text Notes 9600 3900 0 60 ~ 12 +A=B\n +Text Notes 9600 5400 0 60 ~ 12 +AB +Text Notes 1350 2750 2 60 ~ 12 +A2 +Text Notes 1350 2950 2 60 ~ 12 +B2 +Text Notes 1300 1350 2 60 ~ 12 +A3 +Text Notes 1300 1550 2 60 ~ 12 +B3 +Wire Wire Line + 8200 5600 7450 5600 +Wire Wire Line + 7450 5600 7450 6050 +Wire Wire Line + 7450 6050 6900 6050 +Wire Wire Line + 6800 6650 6800 6300 +Wire Wire Line + 6800 6300 6900 6300 +Wire Wire Line + 6900 6300 6900 6050 +Wire Notes Line + 500 3000 1350 3000 +Wire Notes Line + 1350 3000 1350 3750 +Wire Notes Line + 1350 3750 500 3750 +Wire Notes Line + 500 3750 500 3000 +Text Notes 600 3000 3 60 ~ 12 +Cascading Inputs +Wire Notes Line + 9500 1550 9500 6050 +Wire Notes Line + 9500 6050 10550 6050 +Wire Notes Line + 10550 6050 10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/analysis b/src/SubcircuitLibrary/7485/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/7485/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/c_gate-cache.lib b/src/SubcircuitLibrary/7485/c_gate-cache.lib new file mode 100644 index 00000000..e83bf18b --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/c_gate.cir b/src/SubcircuitLibrary/7485/c_gate.cir new file mode 100644 index 00000000..865e4229 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and +U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/c_gate.cir.out b/src/SubcircuitLibrary/7485/c_gate.cir.out new file mode 100644 index 00000000..249e9b8f --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.cir.out @@ -0,0 +1,42 @@ +* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir + +.include 5_and.sub +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/c_gate.pro b/src/SubcircuitLibrary/7485/c_gate.pro new file mode 100644 index 00000000..0ac5f7d7 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.pro @@ -0,0 +1,57 @@ +update=03/26/19 19:06:59 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/src/SubcircuitLibrary/7485/c_gate.sch b/src/SubcircuitLibrary/7485/c_gate.sch new file mode 100644 index 00000000..8205ff7f --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.sch @@ -0,0 +1,246 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:c_gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5C9A2B0B +P 3300 3750 +F 0 "X1" H 4650 4550 60 0000 C CNN +F 1 "5_and" H 4700 4800 60 0000 C CNN +F 2 "" H 3300 3750 60 0000 C CNN +F 3 "" H 3300 3750 60 0000 C CNN + 1 3300 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C9A2B3E +P 5600 3300 +F 0 "U8" H 5600 3300 60 0000 C CNN +F 1 "d_and" H 5650 3400 60 0000 C CNN +F 2 "" H 5600 3300 60 0000 C CNN +F 3 "" H 5600 3300 60 0000 C CNN + 1 5600 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3200 5150 2850 +Wire Wire Line + 4150 2650 4150 2350 +Wire Wire Line + 4150 2350 3600 2350 +Wire Wire Line + 4150 2750 4050 2750 +Wire Wire Line + 4050 2750 4050 2550 +Wire Wire Line + 4050 2550 3600 2550 +Wire Wire Line + 4150 2850 3700 2850 +Wire Wire Line + 3700 2850 3700 2750 +Wire Wire Line + 3700 2750 3600 2750 +Wire Wire Line + 4150 2950 3600 2950 +Wire Wire Line + 4150 3050 4150 3150 +Wire Wire Line + 4150 3150 3600 3150 +Wire Wire Line + 5150 3300 3600 3300 +$Comp +L d_inverter U2 +U 1 1 5C9A2CDC +P 3300 2350 +F 0 "U2" H 3300 2250 60 0000 C CNN +F 1 "d_inverter" H 3300 2500 60 0000 C CNN +F 2 "" H 3350 2300 60 0000 C CNN +F 3 "" H 3350 2300 60 0000 C CNN + 1 3300 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C9A2D06 +P 3300 2550 +F 0 "U3" H 3300 2450 60 0000 C CNN +F 1 "d_inverter" H 3300 2700 60 0000 C CNN +F 2 "" H 3350 2500 60 0000 C CNN +F 3 "" H 3350 2500 60 0000 C CNN + 1 3300 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5C9A2D26 +P 3300 2750 +F 0 "U4" H 3300 2650 60 0000 C CNN +F 1 "d_inverter" H 3300 2900 60 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3300 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5C9A2D49 +P 3300 2950 +F 0 "U5" H 3300 2850 60 0000 C CNN +F 1 "d_inverter" H 3300 3100 60 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 1 3300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5C9A2D73 +P 3300 3150 +F 0 "U6" H 3300 3050 60 0000 C CNN +F 1 "d_inverter" H 3300 3300 60 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 1 3300 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5C9A2D9E +P 3300 3300 +F 0 "U7" H 3300 3200 60 0000 C CNN +F 1 "d_inverter" H 3300 3450 60 0000 C CNN +F 2 "" H 3350 3250 60 0000 C CNN +F 3 "" H 3350 3250 60 0000 C CNN + 1 3300 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2350 2000 2350 +Wire Wire Line + 3000 2550 2000 2550 +Wire Wire Line + 3000 2750 2050 2750 +Wire Wire Line + 3000 2950 2050 2950 +Wire Wire Line + 3000 3150 2050 3150 +Wire Wire Line + 3000 3300 2050 3300 +Wire Wire Line + 6050 3250 6950 3250 +$Comp +L PORT U1 +U 1 1 5C9A2F6F +P 1750 2350 +F 0 "U1" H 1800 2450 30 0000 C CNN +F 1 "PORT" H 1750 2350 30 0000 C CNN +F 2 "" H 1750 2350 60 0000 C CNN +F 3 "" H 1750 2350 60 0000 C CNN + 1 1750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A2FAB +P 1750 2550 +F 0 "U1" H 1800 2650 30 0000 C CNN +F 1 "PORT" H 1750 2550 30 0000 C CNN +F 2 "" H 1750 2550 60 0000 C CNN +F 3 "" H 1750 2550 60 0000 C CNN + 2 1750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2FDD +P 1800 2750 +F 0 "U1" H 1850 2850 30 0000 C CNN +F 1 "PORT" H 1800 2750 30 0000 C CNN +F 2 "" H 1800 2750 60 0000 C CNN +F 3 "" H 1800 2750 60 0000 C CNN + 3 1800 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A301A +P 1800 2950 +F 0 "U1" H 1850 3050 30 0000 C CNN +F 1 "PORT" H 1800 2950 30 0000 C CNN +F 2 "" H 1800 2950 60 0000 C CNN +F 3 "" H 1800 2950 60 0000 C CNN + 4 1800 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A3052 +P 1800 3150 +F 0 "U1" H 1850 3250 30 0000 C CNN +F 1 "PORT" H 1800 3150 30 0000 C CNN +F 2 "" H 1800 3150 60 0000 C CNN +F 3 "" H 1800 3150 60 0000 C CNN + 5 1800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A308D +P 1800 3300 +F 0 "U1" H 1850 3400 30 0000 C CNN +F 1 "PORT" H 1800 3300 30 0000 C CNN +F 2 "" H 1800 3300 60 0000 C CNN +F 3 "" H 1800 3300 60 0000 C CNN + 6 1800 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C9A30DD +P 7200 3250 +F 0 "U1" H 7250 3350 30 0000 C CNN +F 1 "PORT" H 7200 3250 30 0000 C CNN +F 2 "" H 7200 3250 60 0000 C CNN +F 3 "" H 7200 3250 60 0000 C CNN + 7 7200 3250 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/c_gate.sub b/src/SubcircuitLibrary/7485/c_gate.sub new file mode 100644 index 00000000..e7138794 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.sub @@ -0,0 +1,36 @@ +* Subcircuit c_gate +.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ +* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir +.include 5_and.sub +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends c_gate \ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml b/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml new file mode 100644 index 00000000..e51d62de --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterC:\Users\malli\eSim\src\SubcircuitLibrary\5_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib new file mode 100644 index 00000000..f5944a63 --- /dev/null +++ b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib @@ -0,0 +1,112 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir new file mode 100644 index 00000000..52ab8ff8 --- /dev/null +++ b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir @@ -0,0 +1,56 @@ +* C:\esim\eSim\src\SubcircuitLibrary\9bit-Right_shift_register\9bit-Right_shift_register.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/24/19 01:43:15 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U20-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U26-Pad2_ ? d_dff +U4 Net-_U25-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U30-Pad2_ ? d_dff +U6 Net-_U29-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U34-Pad2_ ? d_dff +U15 Net-_U15-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U15-Pad5_ ? d_dff +U2 Net-_U14-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U2-Pad5_ ? d_dff +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad5_ ? d_dff +U18 Net-_U18-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U18-Pad5_ ? d_dff +U11 Net-_U11-Pad1_ Net-_U10-Pad3_ Net-_U1-Pad1_ d_or +U14 Net-_U14-Pad1_ Net-_U13-Pad3_ Net-_U14-Pad3_ d_or +U20 Net-_U20-Pad1_ Net-_U19-Pad3_ Net-_U20-Pad3_ d_or +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U8 Net-_U7-Pad2_ Net-_U5-Pad1_ Net-_U11-Pad1_ d_and +U7 Net-_U10-Pad1_ Net-_U7-Pad2_ d_inverter +U13 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U16 Net-_U10-Pad1_ Net-_U1-Pad5_ Net-_U14-Pad1_ d_and +U12 Net-_U10-Pad1_ Net-_U12-Pad2_ d_inverter +U19 Net-_U17-Pad2_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_and +U21 Net-_U10-Pad1_ Net-_U2-Pad5_ Net-_U20-Pad1_ d_and +U17 Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter +U25 Net-_U23-Pad3_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_or +U23 Net-_U22-Pad2_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_and +U26 Net-_U10-Pad1_ Net-_U26-Pad2_ Net-_U25-Pad2_ d_and +U22 Net-_U10-Pad1_ Net-_U22-Pad2_ d_inverter +U29 Net-_U28-Pad3_ Net-_U29-Pad2_ Net-_U29-Pad3_ d_or +U28 Net-_U27-Pad2_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_and +U30 Net-_U10-Pad1_ Net-_U30-Pad2_ Net-_U29-Pad2_ d_and +U27 Net-_U10-Pad1_ Net-_U27-Pad2_ d_inverter +U33 Net-_U32-Pad3_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_or +U40 Net-_U38-Pad3_ Net-_U40-Pad2_ Net-_U15-Pad1_ d_or +U32 Net-_U31-Pad2_ Net-_U32-Pad2_ Net-_U32-Pad3_ d_and +U34 Net-_U10-Pad1_ Net-_U34-Pad2_ Net-_U33-Pad2_ d_and +U38 Net-_U37-Pad2_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_and +U42 Net-_U10-Pad1_ Net-_U42-Pad2_ Net-_U40-Pad2_ d_and +U31 Net-_U10-Pad1_ Net-_U31-Pad2_ d_inverter +U37 Net-_U10-Pad1_ Net-_U37-Pad2_ d_inverter +U39 Net-_U36-Pad3_ Net-_U39-Pad2_ Net-_U18-Pad1_ d_or +U36 Net-_U36-Pad1_ Net-_U35-Pad2_ Net-_U36-Pad3_ d_and +U41 Net-_U15-Pad5_ Net-_U10-Pad1_ Net-_U39-Pad2_ d_and +U9 Net-_U33-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U42-Pad2_ ? d_dff +U35 Net-_U10-Pad1_ Net-_U35-Pad2_ d_inverter +U24 Net-_U24-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U10-Pad2_ ? d_dff +U45 Net-_U45-Pad1_ Net-_U44-Pad3_ Net-_U24-Pad1_ d_or +U46 Net-_U18-Pad5_ Net-_U10-Pad1_ Net-_U45-Pad1_ d_and +U44 Net-_U44-Pad1_ Net-_U43-Pad2_ Net-_U44-Pad3_ d_and +U43 Net-_U10-Pad1_ Net-_U43-Pad2_ d_inverter +U5 Net-_U5-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U13-Pad2_ Net-_U44-Pad1_ Net-_U19-Pad2_ Net-_U23-Pad2_ Net-_U10-Pad2_ Net-_U2-Pad5_ Net-_U30-Pad2_ Net-_U42-Pad2_ Net-_U18-Pad5_ Net-_U28-Pad2_ Net-_U1-Pad5_ Net-_U26-Pad2_ Net-_U34-Pad2_ Net-_U15-Pad5_ Net-_U36-Pad1_ Net-_U32-Pad2_ Net-_U38-Pad2_ Net-_U10-Pad1_ PORT + +.end diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out new file mode 100644 index 00000000..cff41387 --- /dev/null +++ b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out @@ -0,0 +1,192 @@ +* c:\esim\esim\src\subcircuitlibrary\9bit-right_shift_register\9bit-right_shift_register.cir + +* u3 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? d_dff +* u4 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? d_dff +* u6 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? d_dff +* u15 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? d_dff +* u2 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? d_dff +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? d_dff +* u18 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? d_dff +* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u1-pad1_ d_or +* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or +* u20 net-_u20-pad1_ net-_u19-pad3_ net-_u20-pad3_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u8 net-_u7-pad2_ net-_u5-pad1_ net-_u11-pad1_ d_and +* u7 net-_u10-pad1_ net-_u7-pad2_ d_inverter +* u13 net-_u12-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u16 net-_u10-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and +* u12 net-_u10-pad1_ net-_u12-pad2_ d_inverter +* u19 net-_u17-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_and +* u21 net-_u10-pad1_ net-_u2-pad5_ net-_u20-pad1_ d_and +* u17 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u25 net-_u23-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_or +* u23 net-_u22-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and +* u26 net-_u10-pad1_ net-_u26-pad2_ net-_u25-pad2_ d_and +* u22 net-_u10-pad1_ net-_u22-pad2_ d_inverter +* u29 net-_u28-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_or +* u28 net-_u27-pad2_ net-_u28-pad2_ net-_u28-pad3_ d_and +* u30 net-_u10-pad1_ net-_u30-pad2_ net-_u29-pad2_ d_and +* u27 net-_u10-pad1_ net-_u27-pad2_ d_inverter +* u33 net-_u32-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or +* u40 net-_u38-pad3_ net-_u40-pad2_ net-_u15-pad1_ d_or +* u32 net-_u31-pad2_ net-_u32-pad2_ net-_u32-pad3_ d_and +* u34 net-_u10-pad1_ net-_u34-pad2_ net-_u33-pad2_ d_and +* u38 net-_u37-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_and +* u42 net-_u10-pad1_ net-_u42-pad2_ net-_u40-pad2_ d_and +* u31 net-_u10-pad1_ net-_u31-pad2_ d_inverter +* u37 net-_u10-pad1_ net-_u37-pad2_ d_inverter +* u39 net-_u36-pad3_ net-_u39-pad2_ net-_u18-pad1_ d_or +* u36 net-_u36-pad1_ net-_u35-pad2_ net-_u36-pad3_ d_and +* u41 net-_u15-pad5_ net-_u10-pad1_ net-_u39-pad2_ d_and +* u9 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? d_dff +* u35 net-_u10-pad1_ net-_u35-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? d_dff +* u45 net-_u45-pad1_ net-_u44-pad3_ net-_u24-pad1_ d_or +* u46 net-_u18-pad5_ net-_u10-pad1_ net-_u45-pad1_ d_and +* u44 net-_u44-pad1_ net-_u43-pad2_ net-_u44-pad3_ d_and +* u43 net-_u10-pad1_ net-_u43-pad2_ d_inverter +* u5 net-_u5-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u13-pad2_ net-_u44-pad1_ net-_u19-pad2_ net-_u23-pad2_ net-_u10-pad2_ net-_u2-pad5_ net-_u30-pad2_ net-_u42-pad2_ net-_u18-pad5_ net-_u28-pad2_ net-_u1-pad5_ net-_u26-pad2_ net-_u34-pad2_ net-_u15-pad5_ net-_u36-pad1_ net-_u32-pad2_ net-_u38-pad2_ net-_u10-pad1_ port +a1 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? u3 +a2 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? u4 +a3 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? u6 +a4 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? u15 +a5 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? u2 +a6 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? u1 +a7 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? u18 +a8 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u1-pad1_ u11 +a9 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a10 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u20-pad3_ u20 +a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a12 [net-_u7-pad2_ net-_u5-pad1_ ] net-_u11-pad1_ u8 +a13 net-_u10-pad1_ net-_u7-pad2_ u7 +a14 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a15 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u16 +a16 net-_u10-pad1_ net-_u12-pad2_ u12 +a17 [net-_u17-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a18 [net-_u10-pad1_ net-_u2-pad5_ ] net-_u20-pad1_ u21 +a19 net-_u10-pad1_ net-_u17-pad2_ u17 +a20 [net-_u23-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25 +a21 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a22 [net-_u10-pad1_ net-_u26-pad2_ ] net-_u25-pad2_ u26 +a23 net-_u10-pad1_ net-_u22-pad2_ u22 +a24 [net-_u28-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29 +a25 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a26 [net-_u10-pad1_ net-_u30-pad2_ ] net-_u29-pad2_ u30 +a27 net-_u10-pad1_ net-_u27-pad2_ u27 +a28 [net-_u32-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33 +a29 [net-_u38-pad3_ net-_u40-pad2_ ] net-_u15-pad1_ u40 +a30 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u32-pad3_ u32 +a31 [net-_u10-pad1_ net-_u34-pad2_ ] net-_u33-pad2_ u34 +a32 [net-_u37-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a33 [net-_u10-pad1_ net-_u42-pad2_ ] net-_u40-pad2_ u42 +a34 net-_u10-pad1_ net-_u31-pad2_ u31 +a35 net-_u10-pad1_ net-_u37-pad2_ u37 +a36 [net-_u36-pad3_ net-_u39-pad2_ ] net-_u18-pad1_ u39 +a37 [net-_u36-pad1_ net-_u35-pad2_ ] net-_u36-pad3_ u36 +a38 [net-_u15-pad5_ net-_u10-pad1_ ] net-_u39-pad2_ u41 +a39 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? u9 +a40 net-_u10-pad1_ net-_u35-pad2_ u35 +a41 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? u24 +a42 [net-_u45-pad1_ net-_u44-pad3_ ] net-_u24-pad1_ u45 +a43 [net-_u18-pad5_ net-_u10-pad1_ ] net-_u45-pad1_ u46 +a44 [net-_u44-pad1_ net-_u43-pad2_ ] net-_u44-pad3_ u44 +a45 net-_u10-pad1_ net-_u43-pad2_ u43 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u4 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u6 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u1 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u25 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u29 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u40 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u39 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u41 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u9 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u24 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u45 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u46 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u44 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro new file mode 100644 index 00000000..ec294cbd --- /dev/null +++ b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro @@ -0,0 +1,85 @@ +update=Sat Jun 22 13:15:27 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 +[eeschema] +version=1 +LibDir=../../Abhradip_9bit-ShiftRegister/9bit-ShiftRegister;../../../eSim-1.1.2/kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=half-adder +LibName31=9bit-Right_shift_register-cache +LibName32=/home/mallikarjuna/Downloads/Abhradip/Abhradip_9bit-ShiftRegister/9bit-ShiftRegister/9bit-ShiftRegister-cache +LibName33=eSim_Analog +LibName34=eSim_Devices +LibName35=eSim_Digital +LibName36=eSim_Hybrid +LibName37=eSim_Miscellaneous +LibName38=eSim_Plot +LibName39=eSim_Power +LibName40=eSim_Sources +LibName41=eSim_Subckt +LibName42=eSim_User diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sch b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sch new file mode 100644 index 00000000..b14a8f30 --- /dev/null +++ b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sch @@ -0,0 +1,1495 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:9bit-Right_shift_register-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U3 +U 1 1 5C9296A4 +P 5950 4850 +F 0 "U3" H 5950 4850 60 0000 C CNN +F 1 "d_dff" H 5950 5000 60 0000 C CNN +F 2 "" H 5950 4850 60 0000 C CNN +F 3 "" H 5950 4850 60 0000 C CNN + 1 5950 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U4 +U 1 1 5C9296E7 +P 7250 4850 +F 0 "U4" H 7250 4850 60 0000 C CNN +F 1 "d_dff" H 7250 5000 60 0000 C CNN +F 2 "" H 7250 4850 60 0000 C CNN +F 3 "" H 7250 4850 60 0000 C CNN + 1 7250 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U6 +U 1 1 5C92970E +P 8550 4850 +F 0 "U6" H 8550 4850 60 0000 C CNN +F 1 "d_dff" H 8550 5000 60 0000 C CNN +F 2 "" H 8550 4850 60 0000 C CNN +F 3 "" H 8550 4850 60 0000 C CNN + 1 8550 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U15 +U 1 1 5C92975C +P 11150 4850 +F 0 "U15" H 11150 4850 60 0000 C CNN +F 1 "d_dff" H 11150 5000 60 0000 C CNN +F 2 "" H 11150 4850 60 0000 C CNN +F 3 "" H 11150 4850 60 0000 C CNN + 1 11150 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U2 +U 1 1 5C929793 +P 4650 4850 +F 0 "U2" H 4650 4850 60 0000 C CNN +F 1 "d_dff" H 4650 5000 60 0000 C CNN +F 2 "" H 4650 4850 60 0000 C CNN +F 3 "" H 4650 4850 60 0000 C CNN + 1 4650 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U1 +U 1 1 5C9297E2 +P 3350 4850 +F 0 "U1" H 3350 4850 60 0000 C CNN +F 1 "d_dff" H 3350 5000 60 0000 C CNN +F 2 "" H 3350 4850 60 0000 C CNN +F 3 "" H 3350 4850 60 0000 C CNN + 1 3350 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U18 +U 1 1 5C92A1EB +P 12450 4850 +F 0 "U18" H 12450 4850 60 0000 C CNN +F 1 "d_dff" H 12450 5000 60 0000 C CNN +F 2 "" H 12450 4850 60 0000 C CNN +F 3 "" H 12450 4850 60 0000 C CNN + 1 12450 4850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7900 3800 7900 2450 +Wire Wire Line + 8000 3700 8000 2550 +Wire Wire Line + 8100 3600 8100 2650 +Wire Wire Line + 8200 2750 8200 3500 +Wire Wire Line + 8200 2750 8900 2750 +Wire Wire Line + 8100 2650 9300 2650 +Wire Wire Line + 8000 2550 8900 2550 +Wire Wire Line + 7900 2450 9300 2450 +Wire Wire Line + 7800 2350 8900 2350 +Wire Wire Line + 6500 2250 9300 2250 +Wire Wire Line + 3900 2050 9300 2050 +$Comp +L d_or U11 +U 1 1 5C942586 +P 3450 6100 +F 0 "U11" H 3450 6100 60 0000 C CNN +F 1 "d_or" H 3450 6200 60 0000 C CNN +F 2 "" H 3450 6100 60 0000 C CNN +F 3 "" H 3450 6100 60 0000 C CNN + 1 3450 6100 + -1 0 0 1 +$EndComp +$Comp +L d_or U14 +U 1 1 5C9425C0 +P 4550 6100 +F 0 "U14" H 4550 6100 60 0000 C CNN +F 1 "d_or" H 4550 6200 60 0000 C CNN +F 2 "" H 4550 6100 60 0000 C CNN +F 3 "" H 4550 6100 60 0000 C CNN + 1 4550 6100 + -1 0 0 1 +$EndComp +$Comp +L d_or U20 +U 1 1 5C942640 +P 6450 7450 +F 0 "U20" H 6450 7450 60 0000 C CNN +F 1 "d_or" H 6450 7550 60 0000 C CNN +F 2 "" H 6450 7450 60 0000 C CNN +F 3 "" H 6450 7450 60 0000 C CNN + 1 6450 7450 + -1 0 0 1 +$EndComp +$Comp +L d_and U10 +U 1 1 5C9427D3 +P 3300 6950 +F 0 "U10" H 3300 6950 60 0000 C CNN +F 1 "d_and" H 3350 7050 60 0000 C CNN +F 2 "" H 3300 6950 60 0000 C CNN +F 3 "" H 3300 6950 60 0000 C CNN + 1 3300 6950 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U8 +U 1 1 5C942854 +P 2950 6950 +F 0 "U8" H 2950 6950 60 0000 C CNN +F 1 "d_and" H 3000 7050 60 0000 C CNN +F 2 "" H 2950 6950 60 0000 C CNN +F 3 "" H 2950 6950 60 0000 C CNN + 1 2950 6950 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5C942F4F +P 2850 7850 +F 0 "U7" H 2850 7750 60 0000 C CNN +F 1 "d_inverter" H 2850 8000 60 0000 C CNN +F 2 "" H 2900 7800 60 0000 C CNN +F 3 "" H 2900 7800 60 0000 C CNN + 1 2850 7850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U13 +U 1 1 5C943518 +P 4350 6850 +F 0 "U13" H 4350 6850 60 0000 C CNN +F 1 "d_and" H 4400 6950 60 0000 C CNN +F 2 "" H 4350 6850 60 0000 C CNN +F 3 "" H 4350 6850 60 0000 C CNN + 1 4350 6850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U16 +U 1 1 5C94358F +P 4700 6850 +F 0 "U16" H 4700 6850 60 0000 C CNN +F 1 "d_and" H 4750 6950 60 0000 C CNN +F 2 "" H 4700 6850 60 0000 C CNN +F 3 "" H 4700 6850 60 0000 C CNN + 1 4700 6850 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U12 +U 1 1 5C944206 +P 4250 7850 +F 0 "U12" H 4250 7750 60 0000 C CNN +F 1 "d_inverter" H 4250 8000 60 0000 C CNN +F 2 "" H 4300 7800 60 0000 C CNN +F 3 "" H 4300 7800 60 0000 C CNN + 1 4250 7850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U19 +U 1 1 5C947143 +P 6350 8200 +F 0 "U19" H 6350 8200 60 0000 C CNN +F 1 "d_and" H 6400 8300 60 0000 C CNN +F 2 "" H 6350 8200 60 0000 C CNN +F 3 "" H 6350 8200 60 0000 C CNN + 1 6350 8200 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U21 +U 1 1 5C9471B3 +P 6700 8200 +F 0 "U21" H 6700 8200 60 0000 C CNN +F 1 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d_inverter U27 +U 1 1 5C94E385 +P 9650 7600 +F 0 "U27" H 9650 7500 60 0000 C CNN +F 1 "d_inverter" H 9650 7750 60 0000 C CNN +F 2 "" H 9700 7550 60 0000 C CNN +F 3 "" H 9700 7550 60 0000 C CNN + 1 9650 7600 + 0 -1 -1 0 +$EndComp +$Comp +L d_or U33 +U 1 1 5C94FC0A +P 11150 5850 +F 0 "U33" H 11150 5850 60 0000 C CNN +F 1 "d_or" H 11150 5950 60 0000 C CNN +F 2 "" H 11150 5850 60 0000 C CNN +F 3 "" H 11150 5850 60 0000 C CNN + 1 11150 5850 + -1 0 0 1 +$EndComp +$Comp +L d_or U40 +U 1 1 5C94FC89 +P 12450 5850 +F 0 "U40" H 12450 5850 60 0000 C CNN +F 1 "d_or" H 12450 5950 60 0000 C CNN +F 2 "" H 12450 5850 60 0000 C CNN +F 3 "" H 12450 5850 60 0000 C CNN + 1 12450 5850 + -1 0 0 1 +$EndComp +$Comp +L d_and U32 +U 1 1 5C94FD1B +P 11000 6650 +F 0 "U32" H 11000 6650 60 0000 C CNN +F 1 "d_and" H 11050 6750 60 0000 C CNN +F 2 "" H 11000 6650 60 0000 C CNN +F 3 "" H 11000 6650 60 0000 C CNN + 1 11000 6650 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U34 +U 1 1 5C94FDA6 +P 11350 6650 +F 0 "U34" H 11350 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-1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 15 1 5C9829D6 +P 9550 2250 +F 0 "U5" H 9600 2350 30 0000 C CNN +F 1 "PORT" H 9550 2250 30 0000 C CNN +F 2 "" H 9550 2250 60 0000 C CNN +F 3 "" H 9550 2250 60 0000 C CNN + 15 9550 2250 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 9 1 5C982A5D +P 9150 2150 +F 0 "U5" H 9200 2250 30 0000 C CNN +F 1 "PORT" H 9150 2150 30 0000 C CNN +F 2 "" H 9150 2150 60 0000 C CNN +F 3 "" H 9150 2150 60 0000 C CNN + 9 9150 2150 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 14 1 5C982AE0 +P 9550 2050 +F 0 "U5" H 9600 2150 30 0000 C CNN +F 1 "PORT" H 9550 2050 30 0000 C CNN +F 2 "" H 9550 2050 60 0000 C CNN +F 3 "" H 9550 2050 60 0000 C CNN + 14 9550 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 8 1 5C982B81 +P 9150 1950 +F 0 "U5" H 9200 2050 30 0000 C CNN +F 1 "PORT" H 9150 1950 30 0000 C CNN +F 2 "" H 9150 1950 60 0000 C CNN +F 3 "" H 9150 1950 60 0000 C CNN + 8 9150 1950 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 21 1 5C983602 +P 13250 8700 +F 0 "U5" H 13300 8800 30 0000 C CNN +F 1 "PORT" H 13250 8700 30 0000 C CNN +F 2 "" H 13250 8700 60 0000 C CNN +F 3 "" H 13250 8700 60 0000 C CNN + 21 13250 8700 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 18 1 5C983C2F +P 9950 2000 +F 0 "U5" H 10000 2100 30 0000 C CNN +F 1 "PORT" H 9950 2000 30 0000 C CNN +F 2 "" H 9950 2000 60 0000 C CNN +F 3 "" H 9950 2000 60 0000 C CNN + 18 9950 2000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 20 1 5C984048 +P 11800 9050 +F 0 "U5" H 11850 9150 30 0000 C CNN +F 1 "PORT" H 11800 9050 30 0000 C CNN +F 2 "" H 11800 9050 60 0000 C CNN +F 3 "" H 11800 9050 60 0000 C CNN + 20 11800 9050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 19 1 5C9840D3 +P 10400 9050 +F 0 "U5" H 10450 9150 30 0000 C CNN +F 1 "PORT" H 10400 9050 30 0000 C CNN +F 2 "" H 10400 9050 60 0000 C CNN +F 3 "" H 10400 9050 60 0000 C CNN + 19 10400 9050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 13 1 5C984164 +P 9150 9050 +F 0 "U5" H 9200 9150 30 0000 C CNN +F 1 "PORT" H 9150 9050 30 0000 C CNN +F 2 "" H 9150 9050 60 0000 C CNN +F 3 "" H 9150 9050 60 0000 C CNN + 13 9150 9050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 7 1 5C985678 +P 7200 9050 +F 0 "U5" H 7250 9150 30 0000 C CNN +F 1 "PORT" H 7200 9050 30 0000 C CNN +F 2 "" H 7200 9050 60 0000 C CNN +F 3 "" H 7200 9050 60 0000 C CNN + 7 7200 9050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 6 1 5C985709 +P 5600 9100 +F 0 "U5" H 5650 9200 30 0000 C CNN +F 1 "PORT" H 5600 9100 30 0000 C CNN +F 2 "" H 5600 9100 60 0000 C CNN +F 3 "" H 5600 9100 60 0000 C CNN + 6 5600 9100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 4 1 5C98579A +P 3700 9100 +F 0 "U5" H 3750 9200 30 0000 C CNN +F 1 "PORT" H 3700 9100 30 0000 C CNN +F 2 "" H 3700 9100 60 0000 C CNN +F 3 "" H 3700 9100 60 0000 C CNN + 4 3700 9100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 1 1 5C98582D +P 2700 8800 +F 0 "U5" H 2750 8900 30 0000 C CNN +F 1 "PORT" H 2700 8800 30 0000 C CNN +F 2 "" H 2700 8800 60 0000 C CNN +F 3 "" H 2700 8800 60 0000 C CNN + 1 2700 8800 + 0 1 1 0 +$EndComp +$Comp +L PORT U5 +U 5 1 5C98694B +P 5450 2750 +F 0 "U5" H 5500 2850 30 0000 C CNN +F 1 "PORT" H 5450 2750 30 0000 C CNN +F 2 "" H 5450 2750 60 0000 C CNN +F 3 "" H 5450 2750 60 0000 C CNN + 5 5450 2750 + 0 -1 -1 0 +$EndComp +Text Notes 5400 2450 1 60 ~ 0 +IN8 +Text Notes 2650 2000 0 60 ~ 0 +GND +$Comp +L PORT U5 +U 2 1 5C986B72 +P 3100 2050 +F 0 "U5" H 3150 2150 30 0000 C CNN +F 1 "PORT" H 3100 2050 30 0000 C CNN +F 2 "" H 3100 2050 60 0000 C CNN +F 3 "" H 3100 2050 60 0000 C CNN + 2 3100 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 3 1 5C986C25 +P 3150 3900 +F 0 "U5" H 3200 4000 30 0000 C CNN +F 1 "PORT" H 3150 3900 30 0000 C CNN +F 2 "" H 3150 3900 60 0000 C CNN +F 3 "" H 3150 3900 60 0000 C CNN + 3 3150 3900 + 0 -1 -1 0 +$EndComp +Text Notes 2850 3600 0 60 ~ 0 +CLK +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub new file mode 100644 index 00000000..e94cb0f4 --- /dev/null +++ b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub @@ -0,0 +1,186 @@ +* Subcircuit 9bit-Right_shift_register +.subckt 9bit-Right_shift_register net-_u5-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u13-pad2_ net-_u44-pad1_ net-_u19-pad2_ net-_u23-pad2_ net-_u10-pad2_ net-_u2-pad5_ net-_u30-pad2_ net-_u42-pad2_ net-_u18-pad5_ net-_u28-pad2_ net-_u1-pad5_ net-_u26-pad2_ net-_u34-pad2_ net-_u15-pad5_ net-_u36-pad1_ net-_u32-pad2_ net-_u38-pad2_ net-_u10-pad1_ +* c:\esim\esim\src\subcircuitlibrary\9bit-right_shift_register\9bit-right_shift_register.cir +* u3 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? d_dff +* u4 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? d_dff +* u6 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? d_dff +* u15 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? d_dff +* u2 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? d_dff +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? d_dff +* u18 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? d_dff +* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u1-pad1_ d_or +* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or +* u20 net-_u20-pad1_ net-_u19-pad3_ net-_u20-pad3_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u8 net-_u7-pad2_ net-_u5-pad1_ net-_u11-pad1_ d_and +* u7 net-_u10-pad1_ net-_u7-pad2_ d_inverter +* u13 net-_u12-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u16 net-_u10-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and +* u12 net-_u10-pad1_ net-_u12-pad2_ d_inverter +* u19 net-_u17-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_and +* u21 net-_u10-pad1_ net-_u2-pad5_ net-_u20-pad1_ d_and +* u17 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u25 net-_u23-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_or +* u23 net-_u22-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and +* u26 net-_u10-pad1_ net-_u26-pad2_ net-_u25-pad2_ d_and +* u22 net-_u10-pad1_ net-_u22-pad2_ d_inverter +* u29 net-_u28-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_or +* u28 net-_u27-pad2_ net-_u28-pad2_ net-_u28-pad3_ d_and +* u30 net-_u10-pad1_ net-_u30-pad2_ net-_u29-pad2_ d_and +* u27 net-_u10-pad1_ net-_u27-pad2_ d_inverter +* u33 net-_u32-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or +* u40 net-_u38-pad3_ net-_u40-pad2_ net-_u15-pad1_ d_or +* u32 net-_u31-pad2_ net-_u32-pad2_ net-_u32-pad3_ d_and +* u34 net-_u10-pad1_ net-_u34-pad2_ net-_u33-pad2_ d_and +* u38 net-_u37-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_and +* u42 net-_u10-pad1_ net-_u42-pad2_ net-_u40-pad2_ d_and +* u31 net-_u10-pad1_ net-_u31-pad2_ d_inverter +* u37 net-_u10-pad1_ net-_u37-pad2_ d_inverter +* u39 net-_u36-pad3_ net-_u39-pad2_ net-_u18-pad1_ d_or +* u36 net-_u36-pad1_ net-_u35-pad2_ net-_u36-pad3_ d_and +* u41 net-_u15-pad5_ net-_u10-pad1_ net-_u39-pad2_ d_and +* u9 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? d_dff +* u35 net-_u10-pad1_ net-_u35-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? d_dff +* u45 net-_u45-pad1_ net-_u44-pad3_ net-_u24-pad1_ d_or +* u46 net-_u18-pad5_ net-_u10-pad1_ net-_u45-pad1_ d_and +* u44 net-_u44-pad1_ net-_u43-pad2_ net-_u44-pad3_ d_and +* u43 net-_u10-pad1_ net-_u43-pad2_ d_inverter +a1 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? u3 +a2 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? u4 +a3 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? u6 +a4 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? u15 +a5 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? u2 +a6 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? u1 +a7 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? u18 +a8 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u1-pad1_ u11 +a9 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a10 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u20-pad3_ u20 +a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a12 [net-_u7-pad2_ net-_u5-pad1_ ] net-_u11-pad1_ u8 +a13 net-_u10-pad1_ net-_u7-pad2_ u7 +a14 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a15 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u16 +a16 net-_u10-pad1_ net-_u12-pad2_ u12 +a17 [net-_u17-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a18 [net-_u10-pad1_ net-_u2-pad5_ ] net-_u20-pad1_ u21 +a19 net-_u10-pad1_ net-_u17-pad2_ u17 +a20 [net-_u23-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25 +a21 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a22 [net-_u10-pad1_ net-_u26-pad2_ ] net-_u25-pad2_ u26 +a23 net-_u10-pad1_ net-_u22-pad2_ u22 +a24 [net-_u28-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29 +a25 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a26 [net-_u10-pad1_ net-_u30-pad2_ ] net-_u29-pad2_ u30 +a27 net-_u10-pad1_ net-_u27-pad2_ u27 +a28 [net-_u32-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33 +a29 [net-_u38-pad3_ net-_u40-pad2_ ] net-_u15-pad1_ u40 +a30 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u32-pad3_ u32 +a31 [net-_u10-pad1_ net-_u34-pad2_ ] net-_u33-pad2_ u34 +a32 [net-_u37-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a33 [net-_u10-pad1_ net-_u42-pad2_ ] net-_u40-pad2_ u42 +a34 net-_u10-pad1_ net-_u31-pad2_ u31 +a35 net-_u10-pad1_ net-_u37-pad2_ u37 +a36 [net-_u36-pad3_ net-_u39-pad2_ ] net-_u18-pad1_ u39 +a37 [net-_u36-pad1_ net-_u35-pad2_ ] net-_u36-pad3_ u36 +a38 [net-_u15-pad5_ net-_u10-pad1_ ] net-_u39-pad2_ u41 +a39 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? u9 +a40 net-_u10-pad1_ net-_u35-pad2_ u35 +a41 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? u24 +a42 [net-_u45-pad1_ net-_u44-pad3_ ] net-_u24-pad1_ u45 +a43 [net-_u18-pad5_ net-_u10-pad1_ ] net-_u45-pad1_ u46 +a44 [net-_u44-pad1_ net-_u43-pad2_ ] net-_u44-pad3_ u44 +a45 net-_u10-pad1_ net-_u43-pad2_ u43 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u4 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u6 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u1 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u25 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u29 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u40 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u39 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u41 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u9 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u24 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u45 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u46 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u44 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 9bit-Right_shift_register \ No newline at end of file diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml new file mode 100644 index 00000000..28c290d4 --- /dev/null +++ b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml @@ -0,0 +1 @@ +d_dffd_dffd_dffd_dffd_dffd_dffd_dffd_ord_ord_ord_andd_andd_inverterd_andd_andd_inverterd_andd_andd_inverterd_ord_andd_andd_inverterd_ord_andd_andd_inverterd_ord_ord_andd_andd_andd_andd_inverterd_inverterd_ord_andd_andd_dffd_inverterd_dffd_ord_andd_andd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/analysis b/src/SubcircuitLibrary/9bit-Right_shift_register/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/src/SubcircuitLibrary/9bit-Right_shift_register/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz \ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/AD620-cache.lib b/src/SubcircuitLibrary/AD620/AD620-cache.lib new file mode 100644 index 00000000..b2ef0045 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -350 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X in- 2 -550 150 200 R 50 38 1 1 I +X in+ 3 -550 -100 200 R 50 38 1 1 I +X V- 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X V+ 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/AD620/AD620.cir b/src/SubcircuitLibrary/AD620/AD620.cir new file mode 100644 index 00000000..c82fdfd6 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620.cir @@ -0,0 +1,26 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\AD620\AD620.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/19 16:16:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X2 Net-_R8-Pad1_ Net-_R1-Pad2_ Net-_U1-Pad2_ Net-_R10-Pad2_ Net-_R10-Pad1_ Net-_R1-Pad1_ Net-_U1-Pad7_ ? lm_741 +X1 Net-_R7-Pad2_ Net-_R2-Pad1_ Net-_U1-Pad3_ Net-_R10-Pad2_ Net-_R9-Pad2_ Net-_R2-Pad2_ Net-_U1-Pad7_ ? lm_741 +X3 Net-_R11-Pad2_ Net-_R4-Pad1_ Net-_R3-Pad1_ Net-_R10-Pad2_ Net-_R12-Pad2_ Net-_R6-Pad1_ Net-_U1-Pad7_ ? lm_741 +R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 24.7k +R2 Net-_R2-Pad1_ Net-_R2-Pad2_ 24.7k +R4 Net-_R4-Pad1_ Net-_R1-Pad1_ 10k +R3 Net-_R3-Pad1_ Net-_R2-Pad2_ 10k +R6 Net-_R6-Pad1_ Net-_R4-Pad1_ 10k +R5 Net-_R5-Pad1_ Net-_R3-Pad1_ 10k +U1 Net-_R1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_R10-Pad2_ Net-_R5-Pad1_ Net-_R6-Pad1_ Net-_U1-Pad7_ Net-_R2-Pad1_ PORT +R8 Net-_R8-Pad1_ Net-_R10-Pad2_ 0.297k +R10 Net-_R10-Pad1_ Net-_R10-Pad2_ 1k +R7 Net-_R10-Pad2_ Net-_R7-Pad2_ 0.297k +R9 Net-_R10-Pad2_ Net-_R9-Pad2_ 1k +R12 Net-_R10-Pad2_ Net-_R12-Pad2_ 1k +R11 Net-_R10-Pad2_ Net-_R11-Pad2_ 0.75732k + +.end diff --git a/src/SubcircuitLibrary/AD620/AD620.cir.out b/src/SubcircuitLibrary/AD620/AD620.cir.out new file mode 100644 index 00000000..082780e2 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620.cir.out @@ -0,0 +1,28 @@ +* c:\users\malli\esim\src\subcircuitlibrary\ad620\ad620.cir + +.include lm_741.sub +x2 net-_r8-pad1_ net-_r1-pad2_ net-_u1-pad2_ net-_r10-pad2_ net-_r10-pad1_ net-_r1-pad1_ net-_u1-pad7_ ? lm_741 +x1 net-_r7-pad2_ net-_r2-pad1_ net-_u1-pad3_ net-_r10-pad2_ net-_r9-pad2_ net-_r2-pad2_ net-_u1-pad7_ ? lm_741 +x3 net-_r11-pad2_ net-_r4-pad1_ net-_r3-pad1_ net-_r10-pad2_ net-_r12-pad2_ net-_r6-pad1_ net-_u1-pad7_ ? lm_741 +r1 net-_r1-pad1_ net-_r1-pad2_ 24.7k +r2 net-_r2-pad1_ net-_r2-pad2_ 24.7k +r4 net-_r4-pad1_ net-_r1-pad1_ 10k +r3 net-_r3-pad1_ net-_r2-pad2_ 10k +r6 net-_r6-pad1_ net-_r4-pad1_ 10k +r5 net-_r5-pad1_ net-_r3-pad1_ 10k +* u1 net-_r1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r10-pad2_ net-_r5-pad1_ net-_r6-pad1_ net-_u1-pad7_ net-_r2-pad1_ port +r8 net-_r8-pad1_ net-_r10-pad2_ 0.297k +r10 net-_r10-pad1_ net-_r10-pad2_ 1k +r7 net-_r10-pad2_ net-_r7-pad2_ 0.297k +r9 net-_r10-pad2_ net-_r9-pad2_ 1k +r12 net-_r10-pad2_ net-_r12-pad2_ 1k +r11 net-_r10-pad2_ net-_r11-pad2_ 0.75732k +.tran 0e-03 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/AD620/AD620.pro b/src/SubcircuitLibrary/AD620/AD620.pro new file mode 100644 index 00000000..21e55e98 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620.pro @@ -0,0 +1,44 @@ +update=Thu Jun 27 12:48:03 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_User +LibName11=eSim_Subckt diff --git a/src/SubcircuitLibrary/AD620/AD620.sch b/src/SubcircuitLibrary/AD620/AD620.sch new file mode 100644 index 00000000..8724fe19 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620.sch @@ -0,0 +1,424 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:AD620-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X2 +U 1 1 5CEE7415 +P 3800 2750 +F 0 "X2" H 3600 2750 60 0000 C CNN +F 1 "lm_741" H 3700 2500 60 0000 C CNN +F 2 "" H 3800 2750 60 0000 C CNN +F 3 "" H 3800 2750 60 0000 C CNN + 1 3800 2750 + 1 0 0 1 +$EndComp +$Comp +L lm_741 X1 +U 1 1 5CEE7416 +P 3750 5650 +F 0 "X1" H 3550 5650 60 0000 C CNN +F 1 "lm_741" H 3650 5400 60 0000 C CNN +F 2 "" H 3750 5650 60 0000 C CNN +F 3 "" H 3750 5650 60 0000 C CNN + 1 3750 5650 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X3 +U 1 1 5CEE7417 +P 6800 4050 +F 0 "X3" H 6600 4050 60 0000 C CNN +F 1 "lm_741" H 6700 3800 60 0000 C CNN +F 2 "" H 6800 4050 60 0000 C CNN +F 3 "" H 6800 4050 60 0000 C CNN + 1 6800 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 7150 1700 7150 +Wire Wire Line + 3600 6100 3600 7150 +Wire Wire Line + 6650 6700 3600 6700 +Wire Wire Line + 6650 4500 6650 6700 +Connection ~ 3600 6700 +$Comp +L eSim_R R1 +U 1 1 5CEE741A +P 4550 3350 +F 0 "R1" H 4600 3480 50 0000 C CNN +F 1 "24.7k" H 4600 3400 50 0000 C CNN +F 2 "" H 4600 3330 30 0000 C CNN +F 3 "" V 4600 3400 30 0000 C CNN + 1 4550 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CEE741C +P 4550 5000 +F 0 "R2" H 4600 5130 50 0000 C CNN +F 1 "24.7k" H 4600 5050 50 0000 C CNN +F 2 "" H 4600 4980 30 0000 C CNN +F 3 "" V 4600 5050 30 0000 C CNN + 1 4550 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 4600 5200 4600 5650 +Wire Wire Line + 4300 5650 4900 5650 +Wire Wire Line + 4600 4450 4600 4900 +Wire Wire Line + 4600 3550 4600 4150 +Wire Wire Line + 4600 3250 4600 2750 +Wire Wire Line + 4350 2750 5000 2750 +Wire Wire Line + 4600 3800 2900 3800 +Wire Wire Line + 2900 3800 2900 2900 +Wire Wire Line + 2900 2900 3250 2900 +Connection ~ 4600 3800 +Wire Wire Line + 4600 4700 2900 4700 +Wire Wire Line + 2900 4700 2900 5500 +Wire Wire Line + 2900 5500 3200 5500 +Connection ~ 4600 4700 +$Comp +L eSim_R R4 +U 1 1 5CEE741D +P 5200 2700 +F 0 "R4" H 5250 2830 50 0000 C CNN +F 1 "10k" H 5250 2750 50 0000 C CNN +F 2 "" H 5250 2680 30 0000 C CNN +F 3 "" V 5250 2750 30 0000 C CNN + 1 5200 2700 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CEE741E +P 5100 5600 +F 0 "R3" H 5150 5730 50 0000 C CNN +F 1 "10k" H 5150 5650 50 0000 C CNN +F 2 "" H 5150 5580 30 0000 C CNN +F 3 "" V 5150 5650 30 0000 C CNN + 1 5100 5600 + -1 0 0 1 +$EndComp +Connection ~ 4600 5650 +Wire Wire Line + 5200 5650 6200 5650 +Wire Wire Line + 5950 5650 5950 4150 +Wire Wire Line + 5950 4150 6250 4150 +Wire Wire Line + 6250 3900 5950 3900 +Wire Wire Line + 5950 3900 5950 2750 +Wire Wire Line + 5300 2750 6450 2750 +Connection ~ 4600 2750 +$Comp +L eSim_R R6 +U 1 1 5CEE741F +P 6650 2700 +F 0 "R6" H 6700 2830 50 0000 C CNN +F 1 "10k" H 6700 2750 50 0000 C CNN +F 2 "" H 6700 2680 30 0000 C CNN +F 3 "" V 6700 2750 30 0000 C CNN + 1 6650 2700 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CEE7420 +P 6400 5600 +F 0 "R5" H 6450 5730 50 0000 C CNN +F 1 "10k" H 6450 5650 50 0000 C CNN +F 2 "" H 6450 5580 30 0000 C CNN +F 3 "" V 6450 5650 30 0000 C CNN + 1 6400 5600 + -1 0 0 1 +$EndComp +Connection ~ 5950 5650 +Connection ~ 5950 2750 +Wire Wire Line + 6750 2750 7650 2750 +Wire Wire Line + 7350 4050 7850 4050 +Wire Wire Line + 2200 1150 6300 1150 +Wire Wire Line + 6300 1150 6300 3600 +Wire Wire Line + 6300 3600 6650 3600 +Wire Wire Line + 2700 1150 2700 3550 +Wire Wire Line + 2700 3550 3650 3550 +Wire Wire Line + 3650 3550 3650 3200 +Connection ~ 2700 1150 +Wire Wire Line + 3600 5200 3600 3550 +Connection ~ 3600 3550 +Wire Wire Line + 2000 1800 2000 7150 +Wire Wire Line + 2000 1800 3650 1800 +Wire Wire Line + 3650 1800 3650 2300 +Connection ~ 2000 7150 +Connection ~ 7650 4050 +Wire Wire Line + 6500 5650 7200 5650 +Wire Wire Line + 1850 2650 3250 2650 +$Comp +L PORT U1 +U 2 1 5CEE7CF8 +P 1600 2650 +F 0 "U1" H 1650 2750 30 0000 C CNN +F 1 "PORT" H 1600 2650 30 0000 C CNN +F 2 "" H 1600 2650 60 0000 C CNN +F 3 "" H 1600 2650 60 0000 C CNN + 2 1600 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE7E32 +P 1500 5800 +F 0 "U1" H 1550 5900 30 0000 C CNN +F 1 "PORT" H 1500 5800 30 0000 C CNN +F 2 "" H 1500 5800 60 0000 C CNN +F 3 "" H 1500 5800 60 0000 C CNN + 3 1500 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE7FF8 +P 1450 7150 +F 0 "U1" H 1500 7250 30 0000 C CNN +F 1 "PORT" H 1450 7150 30 0000 C CNN +F 2 "" H 1450 7150 60 0000 C CNN +F 3 "" H 1450 7150 60 0000 C CNN + 4 1450 7150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE80BC +P 1950 1150 +F 0 "U1" H 2000 1250 30 0000 C CNN +F 1 "PORT" H 1950 1150 30 0000 C CNN +F 2 "" H 1950 1150 60 0000 C CNN +F 3 "" H 1950 1150 60 0000 C CNN + 7 1950 1150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE8180 +P 4350 4150 +F 0 "U1" H 4400 4250 30 0000 C CNN +F 1 "PORT" H 4350 4150 30 0000 C CNN +F 2 "" H 4350 4150 60 0000 C CNN +F 3 "" H 4350 4150 60 0000 C CNN + 1 4350 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE8456 +P 4350 4450 +F 0 "U1" H 4400 4550 30 0000 C CNN +F 1 "PORT" H 4350 4450 30 0000 C CNN +F 2 "" H 4350 4450 60 0000 C CNN +F 3 "" H 4350 4450 60 0000 C CNN + 8 4350 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE84A1 +P 7450 5650 +F 0 "U1" H 7500 5750 30 0000 C CNN +F 1 "PORT" H 7450 5650 30 0000 C CNN +F 2 "" H 7450 5650 60 0000 C CNN +F 3 "" H 7450 5650 60 0000 C CNN + 5 7450 5650 + -1 0 0 1 +$EndComp +Wire Wire Line + 7650 2750 7650 4050 +$Comp +L PORT U1 +U 6 1 5CEE8938 +P 8100 4050 +F 0 "U1" H 8150 4150 30 0000 C CNN +F 1 "PORT" H 8100 4050 30 0000 C CNN +F 2 "" H 8100 4050 60 0000 C CNN +F 3 "" H 8100 4050 60 0000 C CNN + 6 8100 4050 + -1 0 0 1 +$EndComp +Wire Wire Line + 1750 5800 3200 5800 +Wire Wire Line + 3200 5800 3200 5750 +$Comp +L eSim_R R8 +U 1 1 5CEFB54F +P 3700 3350 +F 0 "R8" H 3750 3480 50 0000 C CNN +F 1 "0.297k" H 3750 3400 50 0000 C CNN +F 2 "" H 3750 3330 30 0000 C CNN +F 3 "" V 3750 3400 30 0000 C CNN + 1 3700 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CEFB5A3 +P 4000 3350 +F 0 "R10" H 4050 3480 50 0000 C CNN +F 1 "1k" H 4050 3400 50 0000 C CNN +F 2 "" H 4050 3330 30 0000 C CNN +F 3 "" V 4050 3400 30 0000 C CNN + 1 4000 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 4050 3250 4050 3100 +Wire Wire Line + 4050 3100 3850 3100 +Wire Wire Line + 3750 3150 3750 3250 +Wire Wire Line + 3750 3550 3750 3650 +Wire Wire Line + 3750 3650 4050 3650 +Wire Wire Line + 4050 3650 4050 3550 +Wire Wire Line + 3900 3650 3900 3950 +Wire Wire Line + 3900 3950 2000 3950 +Connection ~ 2000 3950 +Connection ~ 3900 3650 +$Comp +L eSim_R R7 +U 1 1 5CEFB900 +P 3650 4950 +F 0 "R7" H 3700 5080 50 0000 C CNN +F 1 "0.297k" H 3700 5000 50 0000 C CNN +F 2 "" H 3700 4930 30 0000 C CNN +F 3 "" V 3700 5000 30 0000 C CNN + 1 3650 4950 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CEFB962 +P 3950 4950 +F 0 "R9" H 4000 5080 50 0000 C CNN +F 1 "1k" H 4000 5000 50 0000 C CNN +F 2 "" H 4000 4930 30 0000 C CNN +F 3 "" V 4000 5000 30 0000 C CNN + 1 3950 4950 + 0 1 1 0 +$EndComp +Wire Wire Line + 4000 4800 4000 4850 +Wire Wire Line + 3700 4800 4000 4800 +Wire Wire Line + 3700 4800 3700 4850 +Wire Wire Line + 3700 5150 3700 5250 +Wire Wire Line + 3800 5300 3800 5150 +Wire Wire Line + 3800 5150 4000 5150 +Wire Wire Line + 3900 4800 3900 4500 +Wire Wire Line + 3900 4500 2000 4500 +Connection ~ 2000 4500 +Connection ~ 3900 4800 +$Comp +L eSim_R R12 +U 1 1 5CEFB846 +P 7050 3350 +F 0 "R12" H 7100 3480 50 0000 C CNN +F 1 "1k" H 7100 3400 50 0000 C CNN +F 2 "" H 7100 3330 30 0000 C CNN +F 3 "" V 7100 3400 30 0000 C CNN + 1 7050 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CEFB8CA +P 6700 3350 +F 0 "R11" H 6750 3480 50 0000 C CNN +F 1 "0.75732k" H 6750 3400 50 0000 C CNN +F 2 "" H 6750 3330 30 0000 C CNN +F 3 "" V 6750 3400 30 0000 C CNN + 1 6700 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 6750 3550 6750 3650 +Wire Wire Line + 6750 3250 6750 3100 +Wire Wire Line + 6750 3100 7500 3100 +Wire Wire Line + 7100 3100 7100 3250 +Wire Wire Line + 7100 3550 7100 3700 +Wire Wire Line + 7100 3700 6850 3700 +Wire Wire Line + 7500 3100 7500 4650 +Wire Wire Line + 7500 4650 6650 4650 +Connection ~ 6650 4650 +Connection ~ 7100 3100 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/AD620/AD620.sub b/src/SubcircuitLibrary/AD620/AD620.sub new file mode 100644 index 00000000..1be97dbd --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620.sub @@ -0,0 +1,22 @@ +* Subcircuit AD620 +.subckt AD620 net-_r1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r10-pad2_ net-_r5-pad1_ net-_r6-pad1_ net-_u1-pad7_ net-_r2-pad1_ +* c:\users\malli\esim\src\subcircuitlibrary\ad620\ad620.cir +.include lm_741.sub +x2 net-_r8-pad1_ net-_r1-pad2_ net-_u1-pad2_ net-_r10-pad2_ net-_r10-pad1_ net-_r1-pad1_ net-_u1-pad7_ ? lm_741 +x1 net-_r7-pad2_ net-_r2-pad1_ net-_u1-pad3_ net-_r10-pad2_ net-_r9-pad2_ net-_r2-pad2_ net-_u1-pad7_ ? lm_741 +x3 net-_r11-pad2_ net-_r4-pad1_ net-_r3-pad1_ net-_r10-pad2_ net-_r12-pad2_ net-_r6-pad1_ net-_u1-pad7_ ? lm_741 +r1 net-_r1-pad1_ net-_r1-pad2_ 24.7k +r2 net-_r2-pad1_ net-_r2-pad2_ 24.7k +r4 net-_r4-pad1_ net-_r1-pad1_ 10k +r3 net-_r3-pad1_ net-_r2-pad2_ 10k +r6 net-_r6-pad1_ net-_r4-pad1_ 10k +r5 net-_r5-pad1_ net-_r3-pad1_ 10k +r8 net-_r8-pad1_ net-_r10-pad2_ 0.297k +r10 net-_r10-pad1_ net-_r10-pad2_ 1k +r7 net-_r10-pad2_ net-_r7-pad2_ 0.297k +r9 net-_r10-pad2_ net-_r9-pad2_ 1k +r12 net-_r10-pad2_ net-_r12-pad2_ 1k +r11 net-_r10-pad2_ net-_r11-pad2_ 0.75732k +* Control Statements + +.ends AD620 \ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml b/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml new file mode 100644 index 00000000..3a4f8217 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml @@ -0,0 +1 @@ +C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/NPN.lib b/src/SubcircuitLibrary/AD620/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/AD620/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/AD620/PNP.lib b/src/SubcircuitLibrary/AD620/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/AD620/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/AD620/analysis b/src/SubcircuitLibrary/AD620/analysis new file mode 100644 index 00000000..cf94dd7f --- /dev/null +++ b/src/SubcircuitLibrary/AD620/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/lm_741-cache.lib b/src/SubcircuitLibrary/AD620/lm_741-cache.lib new file mode 100644 index 00000000..6e908886 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/AD620/lm_741.cir b/src/SubcircuitLibrary/AD620/lm_741.cir new file mode 100644 index 00000000..b7989199 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/src/SubcircuitLibrary/AD620/lm_741.cir.out b/src/SubcircuitLibrary/AD620/lm_741.cir.out new file mode 100644 index 00000000..0184209e --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/AD620/lm_741.pro b/src/SubcircuitLibrary/AD620/lm_741.pro new file mode 100644 index 00000000..d7d4217f --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741.pro @@ -0,0 +1,45 @@ +update=05/25/19 14:52:30 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/AD620/lm_741.sch b/src/SubcircuitLibrary/AD620/lm_741.sch new file mode 100644 index 00000000..6a74cf22 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 0000 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE90A88 +P 5400 4700 +F 0 "Q13" H 5300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CE90A89 +P 5250 5200 +F 0 "R4" H 5300 5330 50 0000 C CNN +F 1 "5k" H 5300 5250 50 0000 C CNN +F 2 "" H 5300 5180 30 0000 C CNN +F 3 "" V 5300 5250 30 0000 C CNN + 1 5250 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CE90A8A +P 6350 2750 +F 0 "R11" H 6400 2880 50 0000 C CNN +F 1 "39k" H 6400 2800 50 0000 C CNN +F 2 "" H 6400 2730 30 0000 C CNN +F 3 "" V 6400 2800 30 0000 C CNN + 1 6350 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 5CE90A8B +P 6500 1950 +F 0 "Q10" H 6400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN +F 2 "" H 6700 2050 29 0000 C CNN +F 3 "" H 6500 1950 60 0000 C CNN + 1 6500 1950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 5CE90A8C +P 7500 1950 +F 0 "Q11" H 7400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 7450 2100 50 0000 R CNN +F 2 "" H 7700 2050 29 0000 C CNN +F 3 "" H 7500 1950 60 0000 C CNN + 1 7500 1950 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 5CE90A8D +P 7500 3050 +F 0 "Q14" H 7400 3100 50 0000 R CNN +F 1 "eSim_NPN" H 7450 3200 50 0000 R CNN +F 2 "" H 7700 3150 29 0000 C CNN +F 3 "" H 7500 3050 60 0000 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CE90A8E +P 7300 2600 +F 0 "R8" H 7350 2730 50 0000 C CNN +F 1 "4.5k" H 7350 2650 50 0000 C CNN +F 2 "" H 7350 2580 30 0000 C CNN +F 3 "" V 7350 2650 30 0000 C CNN + 1 7300 2600 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CE90A8F +P 7300 3400 +F 0 "R7" H 7350 3530 50 0000 C CNN +F 1 "7.5k" H 7350 3450 50 0000 C CNN +F 2 "" H 7350 3380 30 0000 C CNN +F 3 "" V 7350 3450 30 0000 C CNN + 1 7300 3400 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE90A90 +P 6600 3200 +F 0 "C1" H 6625 3300 50 0000 L CNN +F 1 "30p" H 6625 3100 50 0000 L CNN +F 2 "" H 6638 3050 30 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 5CE90A91 +P 7050 3950 +F 0 "Q16" H 6950 4000 50 0000 R CNN +F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN +F 2 "" H 7250 4050 29 0000 C CNN +F 3 "" H 7050 3950 60 0000 C CNN + 1 7050 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 5CE90A92 +P 7500 4300 +F 0 "Q15" H 7400 4350 50 0000 R CNN +F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN +F 2 "" H 7700 4400 29 0000 C CNN +F 3 "" H 7500 4300 60 0000 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CE90A93 +P 7100 5050 +F 0 "R5" H 7150 5180 50 0000 C CNN +F 1 "50k" H 7150 5100 50 0000 C CNN +F 2 "" H 7150 5030 30 0000 C CNN +F 3 "" V 7150 5100 30 0000 C CNN + 1 7100 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CE90A94 +P 7550 5050 +F 0 "R6" H 7600 5180 50 0000 C CNN +F 1 "50" H 7600 5100 50 0000 C CNN +F 2 "" H 7600 5030 30 0000 C CNN +F 3 "" V 7600 5100 30 0000 C CNN + 1 7550 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE90A95 +P 6800 4700 +F 0 "Q17" H 6700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN +F 2 "" H 7000 4800 29 0000 C CNN +F 3 "" H 6800 4700 60 0000 C CNN + 1 6800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 5CE90A96 +P 8800 2300 +F 0 "Q18" H 8700 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN +F 2 "" H 9000 2400 29 0000 C CNN +F 3 "" H 8800 2300 60 0000 C CNN + 1 8800 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 5CE90A97 +P 8400 2750 +F 0 "Q20" H 8300 2800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN +F 2 "" H 8600 2850 29 0000 C CNN +F 3 "" H 8400 2750 60 0000 C CNN + 1 8400 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CE90A98 +P 8850 3000 +F 0 "R9" H 8900 3130 50 0000 C CNN +F 1 "25" H 8900 3050 50 0000 C CNN +F 2 "" H 8900 2980 30 0000 C CNN +F 3 "" V 8900 3050 30 0000 C CNN + 1 8850 3000 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CE90A99 +P 8850 3750 +F 0 "R10" H 8900 3880 50 0000 C CNN +F 1 "50" H 8900 3800 50 0000 C CNN +F 2 "" H 8900 3730 30 0000 C CNN +F 3 "" V 8900 3800 30 0000 C CNN + 1 8850 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 5CE90A9A +P 8800 4600 +F 0 "Q19" H 8700 4650 50 0000 R CNN +F 1 "eSim_PNP" H 8750 4750 50 0000 R CNN +F 2 "" H 9000 4700 29 0000 C CNN +F 3 "" H 8800 4600 60 0000 C CNN + 1 8800 4600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CE90A9B +P 1900 1200 +F 0 "U1" H 1950 1300 30 0000 C CNN +F 1 "PORT" H 1900 1200 30 0000 C CNN +F 2 "" H 1900 1200 60 0000 C CNN +F 3 "" H 1900 1200 60 0000 C CNN + 3 1900 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CE90A9C +P 4500 1050 +F 0 "U1" H 4550 1150 30 0000 C CNN +F 1 "PORT" H 4500 1050 30 0000 C CNN +F 2 "" H 4500 1050 60 0000 C CNN +F 3 "" H 4500 1050 60 0000 C CNN + 2 4500 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CE90A9D +P 9750 1650 +F 0 "U1" H 9800 1750 30 0000 C CNN +F 1 "PORT" H 9750 1650 30 0000 C CNN +F 2 "" H 9750 1650 60 0000 C CNN +F 3 "" H 9750 1650 60 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4250 +Wire Wire Line + 5900 4250 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5300 5100 5300 4900 +Wire Wire Line + 5300 5550 5300 5400 +Connection ~ 4050 5550 +Wire Wire Line + 6400 5550 6400 4900 +Connection ~ 5300 5550 +Connection ~ 5300 3500 +Wire Wire Line + 6400 1650 6400 1750 +Connection ~ 5300 1650 +Wire Wire Line + 6400 2150 6400 2650 +Connection ~ 6400 4250 +Wire Wire Line + 6700 1950 7300 1950 +Wire Wire Line + 7000 1950 7000 2250 +Wire Wire Line + 7000 2250 6400 2250 +Connection ~ 6400 2250 +Wire Wire Line + 7600 1650 7600 1750 +Connection ~ 6400 1650 +Connection ~ 7000 1950 +Wire Wire Line + 7600 3250 7600 4100 +Wire Wire Line + 7600 3450 7400 3450 +Wire Wire Line + 6900 3450 7100 3450 +Wire Wire Line + 6900 2650 6900 3450 +Wire Wire Line + 6900 3050 7300 3050 +Wire Wire Line + 7600 2150 7600 2850 +Wire Wire Line + 7600 2650 7400 2650 +Wire Wire Line + 7100 2650 6900 2650 +Connection ~ 6900 3050 +Connection ~ 7600 2650 +Wire Wire Line + 7300 4300 7150 4300 +Wire Wire Line + 7150 4150 7150 4950 +Connection ~ 7600 3450 +Wire Wire Line + 7600 3700 7150 3700 +Wire Wire Line + 7150 3700 7150 3750 +Connection ~ 7600 3700 +Wire Wire Line + 6600 3050 6600 2450 +Wire Wire Line + 6600 2450 7600 2450 +Connection ~ 7600 2450 +Wire Wire Line + 6600 3350 6600 3950 +Wire Wire Line + 4050 3950 6850 3950 +Wire Wire Line + 6700 3950 6700 4500 +Connection ~ 6700 3950 +Wire Wire Line + 6700 4900 6700 5550 +Connection ~ 6400 5550 +Connection ~ 7150 4300 +Wire Wire Line + 7600 4950 7600 4500 +Wire Wire Line + 7000 4700 7600 4700 +Connection ~ 7600 4700 +Wire Wire Line + 7600 5550 7600 5250 +Connection ~ 6700 5550 +Wire Wire Line + 7150 5250 7150 5550 +Connection ~ 7150 5550 +Wire Wire Line + 7600 2300 8600 2300 +Wire Wire Line + 8300 2300 8300 2550 +Connection ~ 8300 2300 +Connection ~ 7600 2300 +Wire Wire Line + 8900 2100 8900 1650 +Wire Wire Line + 7550 1650 9500 1650 +Connection ~ 7550 1650 +Connection ~ 8900 1650 +Wire Wire Line + 8900 2500 8900 2900 +Wire Wire Line + 8900 2750 8600 2750 +Connection ~ 8900 2750 +Wire Wire Line + 8300 2950 8300 3350 +Wire Wire Line + 8300 3350 8900 3350 +Wire Wire Line + 8900 3200 8900 3650 +Wire Wire Line + 8900 4400 8900 3950 +Connection ~ 8900 3350 +Wire Wire Line + 8900 3500 9500 3500 +Connection ~ 8900 3500 +Wire Wire Line + 8900 5550 8900 4800 +Connection ~ 7600 5550 +Connection ~ 8900 5550 +Wire Wire Line + 8600 4600 8100 4600 +Wire Wire Line + 8100 4600 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +Connection ~ 4050 3950 +Connection ~ 6600 3950 +Wire Wire Line + 4500 2700 4750 2700 +Wire Wire Line + 4750 2700 4750 1050 +Wire Wire Line + 2450 2700 2150 2700 +Wire Wire Line + 2150 2700 2150 1200 +$Comp +L PORT U1 +U 5 1 5CE90AA0 +P 1850 4850 +F 0 "U1" H 1900 4950 30 0000 C CNN +F 1 "PORT" H 1850 4850 30 0000 C CNN +F 2 "" H 1850 4850 60 0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/AD620/lm_741.sub b/src/SubcircuitLibrary/AD620/lm_741.sub new file mode 100644 index 00000000..3842c902 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741 \ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml b/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/npn_1.lib b/src/SubcircuitLibrary/AD620/npn_1.lib new file mode 100644 index 00000000..4a863e3e --- /dev/null +++ b/src/SubcircuitLibrary/AD620/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/pnp_1.lib b/src/SubcircuitLibrary/AD620/pnp_1.lib new file mode 100644 index 00000000..c486429f --- /dev/null +++ b/src/SubcircuitLibrary/AD620/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/src/SubcircuitLibrary/CA3096/CA3096-cache.lib b/src/SubcircuitLibrary/CA3096/CA3096-cache.lib new file mode 100644 index 00000000..16f09ee3 --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/CA3096-cache.lib @@ -0,0 +1,83 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/CA3096/CA3096.cir b/src/SubcircuitLibrary/CA3096/CA3096.cir new file mode 100644 index 00000000..5a3af0fb --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/CA3096.cir @@ -0,0 +1,16 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/CA3096/CA3096.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 22 12:00:17 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_PNP +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_PNP +U1 Net-_Q1-Pad2_ Net-_Q1-Pad3_ Net-_Q1-Pad1_ Net-_Q2-Pad3_ Net-_Q2-Pad2_ Net-_Q2-Pad1_ Net-_Q3-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad1_ Net-_Q4-Pad3_ Net-_Q5-Pad2_ Net-_Q5-Pad1_ Net-_Q5-Pad3_ Net-_Q4-Pad2_ Net-_Q4-Pad1_ ? PORT +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN + +.end diff --git a/src/SubcircuitLibrary/CA3096/CA3096.cir.out b/src/SubcircuitLibrary/CA3096/CA3096.cir.out new file mode 100644 index 00000000..89c57845 --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/CA3096.cir.out @@ -0,0 +1,19 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ca3096/ca3096.cir + +.include PNP.lib +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2907A +* u1 net-_q1-pad2_ net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ net-_q2-pad2_ net-_q2-pad1_ net-_q3-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q4-pad3_ net-_q5-pad2_ net-_q5-pad1_ net-_q5-pad3_ net-_q4-pad2_ net-_q4-pad1_ ? port +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/CA3096/CA3096.pro b/src/SubcircuitLibrary/CA3096/CA3096.pro new file mode 100644 index 00000000..d91a953f --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/CA3096.pro @@ -0,0 +1,82 @@ +update=Sat Jun 22 11:58:40 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Plot +LibName36=eSim_Power +LibName37=eSim_Sources +LibName38=eSim_Subckt +LibName39=eSim_User +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName41=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName42=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName43=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName44=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName45=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName46=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName47=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName48=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName49=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/CA3096/CA3096.sch b/src/SubcircuitLibrary/CA3096/CA3096.sch new file mode 100644 index 00000000..3c08258c --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/CA3096.sch @@ -0,0 +1,328 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:CA3096-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5C98EEF5 +P 4150 4250 +F 0 "Q1" H 4050 4300 50 0000 R CNN +F 1 "eSim_NPN" H 4100 4400 50 0000 R CNN +F 2 "" H 4350 4350 29 0000 C CNN +F 3 "" H 4150 4250 60 0000 C CNN + 1 4150 4250 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5C98EFC9 +P 4250 4950 +F 0 "Q2" H 4150 5000 50 0000 R CNN +F 1 "eSim_NPN" H 4200 5100 50 0000 R CNN +F 2 "" H 4450 5050 29 0000 C CNN +F 3 "" H 4250 4950 60 0000 C CNN + 1 4250 4950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5C98F076 +P 5300 5400 +F 0 "Q5" H 5200 5450 50 0000 R CNN +F 1 "eSim_PNP" H 5250 5550 50 0000 R CNN +F 2 "" H 5500 5500 29 0000 C CNN +F 3 "" H 5300 5400 60 0000 C CNN + 1 5300 5400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5C98F0A7 +P 5300 4650 +F 0 "Q4" H 5200 4700 50 0000 R CNN +F 1 "eSim_PNP" H 5250 4800 50 0000 R CNN +F 2 "" H 5500 4750 29 0000 C CNN +F 3 "" H 5300 4650 60 0000 C CNN + 1 5300 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4350 3800 4350 4250 +Wire Wire Line + 4350 5450 4350 5150 +Wire Wire Line + 5200 5600 5200 5700 +Wire Wire Line + 5200 4850 5200 4950 +Wire Wire Line + 5200 4200 5200 4450 +$Comp +L PORT U1 +U 1 1 5C98F1D4 +P 2950 3800 +F 0 "U1" H 3000 3900 30 0000 C CNN +F 1 "PORT" H 2950 3800 30 0000 C CNN +F 2 "" H 2950 3800 60 0000 C CNN +F 3 "" H 2950 3800 60 0000 C CNN + 1 2950 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C98F222 +P 2950 4450 +F 0 "U1" H 3000 4550 30 0000 C CNN +F 1 "PORT" H 2950 4450 30 0000 C CNN +F 2 "" H 2950 4450 60 0000 C CNN +F 3 "" H 2950 4450 60 0000 C CNN + 3 2950 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C98F272 +P 2950 4950 +F 0 "U1" H 3000 5050 30 0000 C CNN +F 1 "PORT" H 2950 4950 30 0000 C CNN +F 2 "" H 2950 4950 60 0000 C CNN +F 3 "" H 2950 4950 60 0000 C CNN + 5 2950 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C98F29F +P 2950 5450 +F 0 "U1" H 3000 5550 30 0000 C CNN +F 1 "PORT" H 2950 5450 30 0000 C CNN +F 2 "" H 2950 5450 60 0000 C CNN +F 3 "" H 2950 5450 60 0000 C CNN + 6 2950 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C98F38F +P 6150 6050 +F 0 "U1" H 6200 6150 30 0000 C CNN +F 1 "PORT" H 6150 6050 30 0000 C CNN +F 2 "" H 6150 6050 60 0000 C CNN +F 3 "" H 6150 6050 60 0000 C CNN + 9 6150 6050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C98F4ED +P 6150 5400 +F 0 "U1" H 6200 5500 30 0000 C CNN +F 1 "PORT" H 6150 5400 30 0000 C CNN +F 2 "" H 6150 5400 60 0000 C CNN +F 3 "" H 6150 5400 60 0000 C CNN + 11 6150 5400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C98F52C +P 6150 5200 +F 0 "U1" H 6200 5300 30 0000 C CNN +F 1 "PORT" H 6150 5200 30 0000 C CNN +F 2 "" H 6150 5200 60 0000 C CNN +F 3 "" H 6150 5200 60 0000 C CNN + 12 6150 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C98F5BA +P 6150 4650 +F 0 "U1" H 6200 4750 30 0000 C CNN +F 1 "PORT" H 6150 4650 30 0000 C CNN +F 2 "" H 6150 4650 60 0000 C CNN +F 3 "" H 6150 4650 60 0000 C CNN + 14 6150 4650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 5C98F5FF +P 6150 4200 +F 0 "U1" H 6200 4300 30 0000 C CNN +F 1 "PORT" H 6150 4200 30 0000 C CNN +F 2 "" H 6150 4200 60 0000 C CNN +F 3 "" H 6150 4200 60 0000 C CNN + 15 6150 4200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C9C8B88 +P 6150 4950 +F 0 "U1" H 6200 5050 30 0000 C CNN +F 1 "PORT" H 6150 4950 30 0000 C CNN +F 2 "" H 6150 4950 60 0000 C CNN +F 3 "" H 6150 4950 60 0000 C CNN + 10 6150 4950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C9C9E21 +P 6150 5700 +F 0 "U1" H 6200 5800 30 0000 C CNN +F 1 "PORT" H 6150 5700 30 0000 C CNN +F 2 "" H 6150 5700 60 0000 C CNN +F 3 "" H 6150 5700 60 0000 C CNN + 13 6150 5700 + -1 0 0 1 +$EndComp +Wire Wire Line + 3200 3800 4350 3800 +Wire Wire Line + 3200 4450 4050 4450 +Wire Wire Line + 3200 4750 4350 4750 +Wire Wire Line + 3200 4950 4050 4950 +Wire Wire Line + 3200 5450 4350 5450 +Wire Wire Line + 4050 5850 3200 5850 +Wire Wire Line + 3200 5650 4350 5650 +Wire Wire Line + 5900 6050 4350 6050 +Wire Wire Line + 5200 5700 5900 5700 +Wire Wire Line + 5900 5400 5500 5400 +Wire Wire Line + 5200 5200 5900 5200 +Wire Wire Line + 5200 4950 5900 4950 +Wire Wire Line + 5500 4650 5900 4650 +Wire Wire Line + 5200 4200 5900 4200 +Wire Wire Line + 4050 4050 3200 4050 +$Comp +L PORT U1 +U 7 1 5C9CB60F +P 2950 5650 +F 0 "U1" H 3000 5750 30 0000 C CNN +F 1 "PORT" H 2950 5650 30 0000 C CNN +F 2 "" H 2950 5650 60 0000 C CNN +F 3 "" H 2950 5650 60 0000 C CNN + 7 2950 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9CB58F +P 2950 4750 +F 0 "U1" H 3000 4850 30 0000 C CNN +F 1 "PORT" H 2950 4750 30 0000 C CNN +F 2 "" H 2950 4750 60 0000 C CNN +F 3 "" H 2950 4750 60 0000 C CNN + 4 2950 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9CB511 +P 2950 4050 +F 0 "U1" H 3000 4150 30 0000 C CNN +F 1 "PORT" H 2950 4050 30 0000 C CNN +F 2 "" H 2950 4050 60 0000 C CNN +F 3 "" H 2950 4050 60 0000 C CNN + 2 2950 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C9CBE1D +P 2950 5850 +F 0 "U1" H 3000 5950 30 0000 C CNN +F 1 "PORT" H 2950 5850 30 0000 C CNN +F 2 "" H 2950 5850 60 0000 C CNN +F 3 "" H 2950 5850 60 0000 C CNN + 8 2950 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 5D0DDF9F +P 6200 3950 +F 0 "U1" H 6250 4050 30 0000 C CNN +F 1 "PORT" H 6200 3950 30 0000 C CNN +F 2 "" H 6200 3950 60 0000 C CNN +F 3 "" H 6200 3950 60 0000 C CNN + 16 6200 3950 + -1 0 0 1 +$EndComp +NoConn ~ 5950 3950 +$Comp +L eSim_NPN Q3 +U 1 1 5C98F006 +P 4250 5850 +F 0 "Q3" H 4150 5900 50 0000 R CNN +F 1 "eSim_NPN" H 4200 6000 50 0000 R CNN +F 2 "" H 4450 5950 29 0000 C CNN +F 3 "" H 4250 5850 60 0000 C CNN + 1 4250 5850 + 1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/CA3096/CA3096.sub b/src/SubcircuitLibrary/CA3096/CA3096.sub new file mode 100644 index 00000000..f79667b7 --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/CA3096.sub @@ -0,0 +1,13 @@ +* Subcircuit CA3096 +.subckt CA3096 net-_q1-pad2_ net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ net-_q2-pad2_ net-_q2-pad1_ net-_q3-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q4-pad3_ net-_q5-pad2_ net-_q5-pad1_ net-_q5-pad3_ net-_q4-pad2_ net-_q4-pad1_ ? +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ca3096/ca3096.cir +.include PNP.lib +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2907A +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +* Control Statements + +.ends CA3096 \ No newline at end of file diff --git a/src/SubcircuitLibrary/CA3096/CA3096.xml b/src/SubcircuitLibrary/CA3096/CA3096.xml new file mode 100644 index 00000000..24f50baa --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/CA3096.xml @@ -0,0 +1,191 @@ + + + + C:/esim_1/eSim/src/SubcircuitLibrary/CA3096/CA3096.sch + 03/31/19 09:48:27 + Eeschema 4.0.2-stable + + + + <company/> + <rev/> + <date/> + <source>CA3096.sch</source> + <comment number="1" value=""/> + <comment number="2" value=""/> + <comment number="3" value=""/> + <comment number="4" value=""/> + </title_block> + </sheet> + </design> + <components> + <comp ref="Q1"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98EEF5</tstamp> + </comp> + <comp ref="Q2"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98EFC9</tstamp> + </comp> + <comp ref="Q3"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98F006</tstamp> + </comp> + <comp ref="Q5"> + <value>eSim_PNP</value> + <libsource lib="eSim_Devices" part="eSim_PNP"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98F076</tstamp> + </comp> + <comp ref="Q4"> + <value>eSim_PNP</value> + <libsource lib="eSim_Devices" part="eSim_PNP"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98F0A7</tstamp> + </comp> + <comp ref="U1"> + <value>PORT</value> + <libsource lib="eSim_Miscellaneous" part="PORT"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98F1D4</tstamp> + </comp> + </components> + <libparts> + <libpart lib="eSim_Miscellaneous" part="PORT"> + <fields> + <field name="Reference">U</field> + <field name="Value">PORT</field> + </fields> + <pins> + <pin num="1" name="~" type="input"/> + <pin num="2" name="~" type="input"/> + <pin num="3" name="~" type="input"/> + <pin num="4" name="~" type="input"/> + <pin num="5" name="~" type="input"/> + <pin num="6" name="~" type="input"/> + <pin num="7" name="~" type="input"/> + <pin num="8" name="~" type="input"/> + <pin num="9" name="~" type="input"/> + <pin num="10" name="~" type="input"/> + <pin num="11" name="~" type="input"/> + <pin num="12" name="~" type="input"/> + <pin num="13" name="~" type="input"/> + <pin num="14" name="~" type="input"/> + <pin num="15" name="~" type="input"/> + <pin num="16" name="~" type="input"/> + <pin num="17" name="~" type="input"/> + <pin num="18" name="~" type="input"/> + <pin num="19" name="~" type="input"/> + <pin num="20" name="~" type="input"/> + <pin num="21" name="~" type="input"/> + <pin num="22" name="~" type="input"/> + <pin num="23" name="~" type="input"/> + <pin num="24" name="~" type="input"/> + <pin num="25" name="~" type="input"/> + <pin num="26" name="~" type="input"/> + </pins> + </libpart> + <libpart lib="eSim_Devices" part="eSim_NPN"> + <aliases> + <alias>BC547</alias> + <alias>Q2N2222</alias> + </aliases> + <fields> + <field name="Reference">Q</field> + <field name="Value">eSim_NPN</field> + </fields> + <pins> + <pin num="1" name="C" type="openCol"/> + <pin num="2" name="B" type="input"/> + <pin num="3" name="E" type="openEm"/> + </pins> + </libpart> + <libpart lib="eSim_Devices" part="eSim_PNP"> + <fields> + <field name="Reference">Q</field> + <field name="Value">eSim_PNP</field> + </fields> + <pins> + <pin num="1" name="C" type="openCol"/> + <pin num="2" name="B" type="input"/> + <pin num="3" name="E" type="openEm"/> + </pins> + </libpart> + </libparts> + <libraries> + <library logical="eSim_Devices"> + <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Devices.lib</uri> + </library> + <library logical="eSim_Miscellaneous"> + <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Miscellaneous.lib</uri> + </library> + </libraries> + <nets> + <net code="1" name="Net-(Q5-Pad2)"> + <node ref="U1" pin="11"/> + <node ref="Q5" pin="2"/> + </net> + <net code="2" name="Net-(Q2-Pad2)"> + <node ref="U1" pin="5"/> + <node ref="Q2" pin="2"/> + </net> + <net code="3" name="Net-(Q3-Pad2)"> + <node ref="U1" pin="8"/> + <node ref="Q3" pin="2"/> + </net> + <net code="4" name="Net-(Q4-Pad2)"> + <node ref="U1" pin="14"/> + <node ref="Q4" pin="2"/> + </net> + <net code="5" name="Net-(Q1-Pad1)"> + <node ref="U1" pin="3"/> + <node ref="Q1" pin="1"/> + </net> + <net code="6" name="Net-(Q2-Pad3)"> + <node ref="Q2" pin="3"/> + <node ref="U1" pin="4"/> + </net> + <net code="7" name="Net-(Q3-Pad3)"> + <node ref="Q3" pin="3"/> + <node ref="U1" pin="7"/> + </net> + <net code="8" name="Net-(Q3-Pad1)"> + <node ref="U1" pin="9"/> + <node ref="Q3" pin="1"/> + </net> + <net code="9" name="Net-(Q5-Pad1)"> + <node ref="U1" pin="12"/> + <node ref="Q5" pin="1"/> + </net> + <net code="10" name="Net-(Q1-Pad2)"> + <node ref="U1" pin="1"/> + <node ref="Q1" pin="2"/> + </net> + <net code="11" name="Net-(Q1-Pad3)"> + <node ref="U1" pin="2"/> + <node ref="Q1" pin="3"/> + </net> + <net code="12" name="Net-(Q2-Pad1)"> + <node ref="Q2" pin="1"/> + <node ref="U1" pin="6"/> + </net> + <net code="13" name="Net-(Q5-Pad3)"> + <node ref="Q5" pin="3"/> + <node ref="U1" pin="13"/> + </net> + <net code="14" name="Net-(Q4-Pad1)"> + <node ref="U1" pin="15"/> + <node ref="Q4" pin="1"/> + </net> + <net code="15" name="Net-(Q4-Pad3)"> + <node ref="Q4" pin="3"/> + <node ref="U1" pin="10"/> + </net> + </nets> +</export> diff --git a/src/SubcircuitLibrary/CA3096/CA3096_Previous_Values.xml b/src/SubcircuitLibrary/CA3096/CA3096_Previous_Values.xml new file mode 100644 index 00000000..82a40fb6 --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/CA3096_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/CA3096/D.lib b/src/SubcircuitLibrary/CA3096/D.lib new file mode 100644 index 00000000..8a7fb4da --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/D.lib @@ -0,0 +1,2 @@ +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/src/SubcircuitLibrary/CA3096/NPN.lib b/src/SubcircuitLibrary/CA3096/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/CA3096/PNP.lib b/src/SubcircuitLibrary/CA3096/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/CA3096/analysis b/src/SubcircuitLibrary/CA3096/analysis new file mode 100644 index 00000000..d5e13546 --- /dev/null +++ b/src/SubcircuitLibrary/CA3096/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib new file mode 100644 index 00000000..f7d63760 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib @@ -0,0 +1,185 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Logic_adder +# +DEF Logic_adder X 0 40 Y Y 1 F N +F0 "X" 0 -250 60 H V C CNN +F1 "Logic_adder" 50 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -550 550 550 -600 0 1 0 N +X IN1 1 -750 350 200 R 50 50 1 1 I +X IN2 2 -750 -50 200 R 50 50 1 1 I +X CIN 3 -750 -450 200 R 50 50 1 1 I +X SUM 4 750 350 200 L 50 50 1 1 O +X COUT 5 750 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# MUX +# +DEF MUX X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "MUX" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 350 250 -150 0 1 0 N +X sel 1 0 550 200 D 50 50 1 1 I +X a0 2 -500 150 200 R 50 50 1 1 I +X a1 3 -500 -50 200 R 50 50 1 1 I +X y 4 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir new file mode 100644 index 00000000..fee511ed --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir @@ -0,0 +1,29 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 8 18:40:34 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U3-Pad3_ d_and +U5 Net-_U2-Pad2_ Net-_U2-Pad1_ Net-_U5-Pad3_ d_xor +U6 Net-_U2-Pad3_ Net-_U3-Pad1_ Net-_U6-Pad3_ d_xor +U7 Net-_U3-Pad3_ Net-_U7-Pad2_ Net-_U7-Pad3_ d_xor +U8 Net-_U3-Pad3_ Net-_U8-Pad2_ Net-_U8-Pad3_ d_xor +U4 Net-_U2-Pad2_ Net-_U4-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +X3 Net-_U1-Pad1_ Net-_U1-Pad5_ Net-_U9-Pad2_ Net-_U2-Pad2_ Net-_X1-Pad3_ Logic_adder +X1 Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_X1-Pad3_ Net-_U2-Pad1_ Net-_X1-Pad5_ Logic_adder +X2 Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_X1-Pad5_ Net-_U3-Pad1_ Net-_X2-Pad5_ Logic_adder +X4 Net-_U1-Pad4_ Net-_U1-Pad8_ Net-_X2-Pad5_ Net-_U7-Pad2_ Net-_U8-Pad2_ Logic_adder +X7 Net-_U1-Pad9_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad10_ MUX +X5 Net-_U1-Pad9_ Net-_U2-Pad1_ Net-_U5-Pad3_ Net-_U1-Pad11_ MUX +X8 Net-_U1-Pad9_ Net-_U3-Pad1_ Net-_U6-Pad3_ Net-_U1-Pad12_ MUX +X6 Net-_U1-Pad9_ Net-_U7-Pad2_ Net-_U7-Pad3_ Net-_U1-Pad13_ MUX +X9 Net-_U1-Pad9_ Net-_U8-Pad2_ Net-_U8-Pad3_ Net-_U1-Pad14_ MUX +v1 Net-_U9-Pad1_ GND 0 +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ adc_bridge_1 + +.end diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out new file mode 100644 index 00000000..9bfd2402 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out @@ -0,0 +1,56 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/csla_bec1_logic/csla_bec1_logic.cir + +.include LOGIC_ADDER.sub +.include MUX.sub +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_and +* u5 net-_u2-pad2_ net-_u2-pad1_ net-_u5-pad3_ d_xor +* u6 net-_u2-pad3_ net-_u3-pad1_ net-_u6-pad3_ d_xor +* u7 net-_u3-pad3_ net-_u7-pad2_ net-_u7-pad3_ d_xor +* u8 net-_u3-pad3_ net-_u8-pad2_ net-_u8-pad3_ d_xor +* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +x3 net-_u1-pad1_ net-_u1-pad5_ net-_u9-pad2_ net-_u2-pad2_ net-_x1-pad3_ LOGIC_ADDER +x1 net-_u1-pad2_ net-_u1-pad6_ net-_x1-pad3_ net-_u2-pad1_ net-_x1-pad5_ LOGIC_ADDER +x2 net-_u1-pad3_ net-_u1-pad7_ net-_x1-pad5_ net-_u3-pad1_ net-_x2-pad5_ LOGIC_ADDER +x4 net-_u1-pad4_ net-_u1-pad8_ net-_x2-pad5_ net-_u7-pad2_ net-_u8-pad2_ LOGIC_ADDER +x7 net-_u1-pad9_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad10_ MUX +x5 net-_u1-pad9_ net-_u2-pad1_ net-_u5-pad3_ net-_u1-pad11_ MUX +x8 net-_u1-pad9_ net-_u3-pad1_ net-_u6-pad3_ net-_u1-pad12_ MUX +x6 net-_u1-pad9_ net-_u7-pad2_ net-_u7-pad3_ net-_u1-pad13_ MUX +x9 net-_u1-pad9_ net-_u8-pad2_ net-_u8-pad3_ net-_u1-pad14_ MUX +v1 net-_u9-pad1_ gnd 0 +* u9 net-_u9-pad1_ net-_u9-pad2_ adc_bridge_1 +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad2_ net-_u2-pad1_ ] net-_u5-pad3_ u5 +a4 [net-_u2-pad3_ net-_u3-pad1_ ] net-_u6-pad3_ u6 +a5 [net-_u3-pad3_ net-_u7-pad2_ ] net-_u7-pad3_ u7 +a6 [net-_u3-pad3_ net-_u8-pad2_ ] net-_u8-pad3_ u8 +a7 net-_u2-pad2_ net-_u4-pad2_ u4 +a8 [net-_u9-pad1_ ] [net-_u9-pad2_ ] u9 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u8 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro new file mode 100644 index 00000000..a546f71d --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro @@ -0,0 +1,46 @@ +update=Sat Jun 8 13:24:24 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User +LibName11=eSim_Subckt +LibName12=power + diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch new file mode 100644 index 00000000..e7eac906 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch @@ -0,0 +1,654 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_PSpice +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:power +LIBS:CSLA_BEC1_logic-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5CFB5959 +P 4800 3500 +F 0 "U2" H 4800 3500 60 0000 C CNN +F 1 "d_and" H 4850 3600 60 0000 C CNN +F 2 "" H 4800 3500 60 0000 C CNN +F 3 "" H 4800 3500 60 0000 C CNN + 1 4800 3500 + 0 1 1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5CFB595A +P 4850 5350 +F 0 "U3" H 4850 5350 60 0000 C CNN +F 1 "d_and" H 4900 5450 60 0000 C CNN +F 2 "" H 4850 5350 60 0000 C CNN +F 3 "" H 4850 5350 60 0000 C CNN + 1 4850 5350 + 0 1 1 0 +$EndComp +$Comp +L d_xor U5 +U 1 1 5CFB595B +P 5750 2900 +F 0 "U5" H 5750 2900 60 0000 C CNN +F 1 "d_xor" H 5800 3000 47 0000 C CNN +F 2 "" H 5750 2900 60 0000 C CNN +F 3 "" H 5750 2900 60 0000 C CNN + 1 5750 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U6 +U 1 1 5CFB595C +P 5800 4450 +F 0 "U6" H 5800 4450 60 0000 C CNN +F 1 "d_xor" H 5850 4550 47 0000 C CNN +F 2 "" H 5800 4450 60 0000 C CNN +F 3 "" H 5800 4450 60 0000 C CNN + 1 5800 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U7 +U 1 1 5CFB595D +P 5900 5250 +F 0 "U7" H 5900 5250 60 0000 C CNN +F 1 "d_xor" H 5950 5350 47 0000 C CNN +F 2 "" H 5900 5250 60 0000 C CNN +F 3 "" H 5900 5250 60 0000 C CNN + 1 5900 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U8 +U 1 1 5CFB595E +P 5900 6700 +F 0 "U8" H 5900 6700 60 0000 C CNN +F 1 "d_xor" H 5950 6800 47 0000 C CNN +F 2 "" H 5900 6700 60 0000 C CNN +F 3 "" H 5900 6700 60 0000 C CNN + 1 5900 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CFB595F +P 5600 1300 +F 0 "U4" H 5600 1200 60 0000 C CNN +F 1 "d_inverter" H 5600 1450 60 0000 C CNN +F 2 "" H 5650 1250 60 0000 C CNN +F 3 "" H 5650 1250 60 0000 C CNN + 1 5600 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CFB6267 +P 1950 1300 +F 0 "U1" H 2000 1400 30 0000 C CNN +F 1 "PORT" H 1950 1300 30 0000 C CNN +F 2 "" H 1950 1300 60 0000 C CNN +F 3 "" H 1950 1300 60 0000 C CNN + 1 1950 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CFB62F5 +P 1950 1700 +F 0 "U1" H 2000 1800 30 0000 C CNN +F 1 "PORT" H 1950 1700 30 0000 C CNN +F 2 "" H 1950 1700 60 0000 C CNN +F 3 "" H 1950 1700 60 0000 C CNN + 5 1950 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CFB6357 +P 1950 2100 +F 0 "U1" H 2000 2200 30 0000 C CNN +F 1 "PORT" H 1950 2100 30 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Line + 2250 5900 3100 5900 +Wire Wire Line + 2550 6300 3100 6300 +Wire Wire Line + 2400 4850 3050 4850 +Wire Wire Line + 2150 4450 3050 4450 +Wire Wire Line + 5450 5900 5450 5250 +Wire Wire Line + 5400 5150 5450 5150 +Wire Wire Line + 5400 5800 5400 5150 +Wire Wire Line + 6350 6650 6650 6650 +Connection ~ 5350 5900 +Connection ~ 5400 6700 +Wire Wire Line + 4900 6600 5450 6600 +Wire Wire Line + 4900 5800 4900 6600 +Wire Wire Line + 4900 5800 5400 5800 +Connection ~ 4950 4450 +Wire Wire Line + 4950 4450 4950 4900 +Wire Wire Line + 4850 3950 4850 4900 +Wire Wire Line + 2800 6700 3100 6700 +Wire Wire Line + 2800 5600 2800 6700 +Wire Wire Line + 4600 5600 2800 5600 +Wire Wire Line + 4600 5250 4600 5600 +Wire Wire Line + 2750 5250 3050 5250 +Wire Wire Line + 2750 4100 2750 5250 +Wire Wire Line + 4550 4100 2750 4100 +Wire Wire Line + 4550 3700 4550 4100 +Connection ~ 4850 4350 +Wire Wire Line + 4850 4350 5350 4350 +Connection ~ 4900 2900 +Wire Wire Line + 4900 2900 4900 3050 +Connection ~ 4800 2750 +Wire Wire Line + 5300 2750 5300 2800 +Wire Wire Line + 4800 2750 5300 2750 +Connection ~ 4800 1300 +Wire Wire Line + 4800 1300 4800 3050 +Wire Wire Line + 2700 3700 3000 3700 +Wire Wire Line + 2700 2500 2700 3700 +Wire Wire Line + 4650 2500 2700 2500 +Wire Wire Line + 4650 2100 4650 2500 +Wire Wire Line + 6900 1050 5300 1050 +Wire Wire Line + 5300 1050 5300 1300 +Connection ~ 6600 4700 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub new file mode 100644 index 00000000..fd844be7 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub @@ -0,0 +1,50 @@ +* Subcircuit CSLA_BEC1_logic +.subckt CSLA_BEC1_logic net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/csla_bec1_logic/csla_bec1_logic.cir +.include LOGIC_ADDER.sub +.include MUX.sub +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_and +* u5 net-_u2-pad2_ net-_u2-pad1_ net-_u5-pad3_ d_xor +* u6 net-_u2-pad3_ net-_u3-pad1_ net-_u6-pad3_ d_xor +* u7 net-_u3-pad3_ net-_u7-pad2_ net-_u7-pad3_ d_xor +* u8 net-_u3-pad3_ net-_u8-pad2_ net-_u8-pad3_ d_xor +* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter +x3 net-_u1-pad1_ net-_u1-pad5_ net-_u9-pad2_ net-_u2-pad2_ net-_x1-pad3_ LOGIC_ADDER +x1 net-_u1-pad2_ net-_u1-pad6_ net-_x1-pad3_ net-_u2-pad1_ net-_x1-pad5_ LOGIC_ADDER +x2 net-_u1-pad3_ net-_u1-pad7_ net-_x1-pad5_ net-_u3-pad1_ net-_x2-pad5_ LOGIC_ADDER +x4 net-_u1-pad4_ net-_u1-pad8_ net-_x2-pad5_ net-_u7-pad2_ net-_u8-pad2_ LOGIC_ADDER +x7 net-_u1-pad9_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad10_ MUX +x5 net-_u1-pad9_ net-_u2-pad1_ net-_u5-pad3_ net-_u1-pad11_ MUX +x8 net-_u1-pad9_ net-_u3-pad1_ net-_u6-pad3_ net-_u1-pad12_ MUX +x6 net-_u1-pad9_ net-_u7-pad2_ net-_u7-pad3_ net-_u1-pad13_ MUX +x9 net-_u1-pad9_ net-_u8-pad2_ net-_u8-pad3_ net-_u1-pad14_ MUX +v1 net-_u9-pad1_ gnd 0 +* u9 net-_u9-pad1_ net-_u9-pad2_ adc_bridge_1 +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad2_ net-_u2-pad1_ ] net-_u5-pad3_ u5 +a4 [net-_u2-pad3_ net-_u3-pad1_ ] net-_u6-pad3_ u6 +a5 [net-_u3-pad3_ net-_u7-pad2_ ] net-_u7-pad3_ u7 +a6 [net-_u3-pad3_ net-_u8-pad2_ ] net-_u8-pad3_ u8 +a7 net-_u2-pad2_ net-_u4-pad2_ u4 +a8 [net-_u9-pad1_ ] [net-_u9-pad2_ ] u9 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u8 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Control Statements + +.ends CSLA_BEC1_logic \ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml new file mode 100644 index 00000000..55dd75da --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">0</v1></source><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_xor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_xor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u4><u9 name="type">adc_bridge<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter value for in_high (default=2.0)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /><field25 name="Enter value for in_low (default=1.0)" /></u9></model><devicemodel /><subcircuit><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x9><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x3><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib new file mode 100644 index 00000000..34588988 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir new file mode 100644 index 00000000..ec177d39 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir @@ -0,0 +1,16 @@ +* C:\eSim\eSim\src\SubcircuitLibrary\LOGIC_ADDER\LOGIC_ADDER.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:23:20 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 A B Net-_U2-Pad3_ d_and +U4 Net-_U3-Pad3_ CIN Net-_U4-Pad3_ d_and +U3 A B Net-_U3-Pad3_ d_xor +U5 Net-_U3-Pad3_ CIN SUM d_xor +U6 Net-_U2-Pad3_ Net-_U4-Pad3_ CARRY d_or +U1 A B CIN SUM CARRY PORT + +.end diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out new file mode 100644 index 00000000..df9bcde6 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out @@ -0,0 +1,32 @@ +* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir + +* u2 a b net-_u2-pad3_ d_and +* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and +* u3 a b net-_u3-pad3_ d_xor +* u5 net-_u3-pad3_ cin sum d_xor +* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or +* u1 a b cin sum carry port +a1 [a b ] net-_u2-pad3_ u2 +a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4 +a3 [a b ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ cin ] sum u5 +a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro new file mode 100644 index 00000000..a2b9fa1f --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro @@ -0,0 +1,44 @@ +update=Sat Jun 8 13:01:54 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch new file mode 100644 index 00000000..d39a1b78 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch @@ -0,0 +1,245 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:LOGIC_ADDER-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5AB647D1 +P 4100 2200 +F 0 "U2" H 4100 2200 60 0000 C CNN +F 1 "d_and" H 4150 2300 60 0000 C CNN +F 2 "" H 4100 2200 60 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5AB648AD +P 5250 2300 +F 0 "U4" H 5250 2300 60 0000 C CNN +F 1 "d_and" H 5300 2400 60 0000 C CNN +F 2 "" H 5250 2300 60 0000 C CNN +F 3 "" H 5250 2300 60 0000 C CNN + 1 5250 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U3 +U 1 1 5AB648E7 +P 4100 2750 +F 0 "U3" H 4100 2750 60 0000 C CNN +F 1 "d_xor" H 4150 2850 47 0000 C CNN +F 2 "" H 4100 2750 60 0000 C CNN +F 3 "" H 4100 2750 60 0000 C CNN + 1 4100 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U5 +U 1 1 5AB6498F +P 5250 2600 +F 0 "U5" H 5250 2600 60 0000 C CNN +F 1 "d_xor" H 5300 2700 47 0000 C CNN +F 2 "" H 5250 2600 60 0000 C CNN +F 3 "" H 5250 2600 60 0000 C CNN + 1 5250 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 5AB64A11 +P 6250 2250 +F 0 "U6" H 6250 2250 60 0000 C CNN +F 1 "d_or" H 6250 2350 60 0000 C CNN +F 2 "" H 6250 2250 60 0000 C CNN +F 3 "" H 6250 2250 60 0000 C CNN + 1 6250 2250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5AB64A78 +P 2650 2100 +F 0 "U1" H 2700 2200 30 0000 C CNN +F 1 "PORT" H 2650 2100 30 0000 C CNN +F 2 "" H 2650 2100 60 0000 C CNN +F 3 "" H 2650 2100 60 0000 C CNN + 1 2650 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5AB64BE9 +P 2650 2300 +F 0 "U1" H 2700 2400 30 0000 C CNN +F 1 "PORT" H 2650 2300 30 0000 C CNN +F 2 "" H 2650 2300 60 0000 C CNN +F 3 "" H 2650 2300 60 0000 C CNN + 2 2650 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5AB64C18 +P 6300 2550 +F 0 "U1" H 6350 2650 30 0000 C CNN +F 1 "PORT" H 6300 2550 30 0000 C CNN +F 2 "" H 6300 2550 60 0000 C CNN +F 3 "" H 6300 2550 60 0000 C CNN + 4 6300 2550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5AB64C59 +P 2650 2900 +F 0 "U1" H 2700 3000 30 0000 C CNN +F 1 "PORT" H 2650 2900 30 0000 C CNN +F 2 "" H 2650 2900 60 0000 C CNN +F 3 "" H 2650 2900 60 0000 C CNN + 3 2650 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5AB64C94 +P 7150 2200 +F 0 "U1" H 7200 2300 30 0000 C CNN +F 1 "PORT" H 7150 2200 30 0000 C CNN +F 2 "" H 7150 2200 60 0000 C CNN +F 3 "" H 7150 2200 60 0000 C CNN + 5 7150 2200 + -1 0 0 1 +$EndComp +Wire Wire Line + 2900 2100 3650 2100 +Wire Wire Line + 2900 2250 3650 2250 +Wire Wire Line + 3650 2250 3650 2200 +Wire Wire Line + 3400 2100 3400 2650 +Wire Wire Line + 3400 2650 3650 2650 +Connection ~ 3400 2100 +Wire Wire Line + 3150 2250 3150 2750 +Wire Wire Line + 3150 2750 3650 2750 +Connection ~ 3150 2250 +Wire Wire Line + 4550 2700 4550 2500 +Wire Wire Line + 4550 2500 4800 2500 +Wire Wire Line + 2900 2900 4800 2900 +Wire Wire Line + 4800 2900 4800 2600 +Wire Wire Line + 4700 2500 4700 2200 +Wire Wire Line + 4700 2200 4800 2200 +Connection ~ 4700 2500 +Wire Wire Line + 4800 2300 4600 2300 +Wire Wire Line + 4600 2300 4600 2900 +Connection ~ 4600 2900 +Wire Wire Line + 5700 2250 5800 2250 +Wire Wire Line + 4550 2150 4550 2000 +Wire Wire Line + 4550 2000 5800 2000 +Wire Wire Line + 5800 2000 5800 2150 +Wire Wire Line + 5700 2550 6050 2550 +Wire Wire Line + 6700 2200 6900 2200 +Wire Wire Line + 2900 2250 2900 2300 +Text GLabel 3000 1850 0 60 Input ~ 0 +A +Text GLabel 3000 2500 0 60 Input ~ 0 +B +Text GLabel 3000 3250 0 60 Input ~ 0 +CIN +Wire Wire Line + 3000 3250 3050 3250 +Wire Wire Line + 3050 3250 3050 2900 +Connection ~ 3050 2900 +Wire Wire Line + 3000 1850 3100 1850 +Wire Wire Line + 3100 1850 3100 2100 +Connection ~ 3100 2100 +Wire Wire Line + 3000 2500 3000 2250 +Connection ~ 3000 2250 +Text GLabel 6750 1700 0 60 Output ~ 0 +CARRY +Text GLabel 5950 2800 0 60 Output ~ 0 +SUM +Wire Wire Line + 6750 1700 6800 1700 +Wire Wire Line + 6800 1700 6800 2200 +Connection ~ 6800 2200 +Wire Wire Line + 5950 2550 5950 2800 +Connection ~ 5950 2550 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub new file mode 100644 index 00000000..a1e1cfac --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub @@ -0,0 +1,26 @@ +* Subcircuit LOGIC_ADDER +.subckt LOGIC_ADDER a b cin sum carry +* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir +* u2 a b net-_u2-pad3_ d_and +* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and +* u3 a b net-_u3-pad3_ d_xor +* u5 net-_u3-pad3_ cin sum d_xor +* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or +a1 [a b ] net-_u2-pad3_ u2 +a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4 +a3 [a b ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ cin ] sum u5 +a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends LOGIC_ADDER \ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml new file mode 100644 index 00000000..ab59f216 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib new file mode 100644 index 00000000..9fa4b3f9 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir new file mode 100644 index 00000000..8d97f9a1 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir @@ -0,0 +1,15 @@ +* C:\eSim\eSim\src\SubcircuitLibrary\MUX\MUX.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:29:10 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_and +U4 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and +U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad4_ d_or +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out new file mode 100644 index 00000000..342293e7 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out @@ -0,0 +1,28 @@ +* c:\esim\esim\src\subcircuitlibrary\mux\mux.cir + +* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and +* u4 net-_u1-pad1_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5 +a4 net-_u1-pad1_ net-_u2-pad2_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro new file mode 100644 index 00000000..07f53b67 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro @@ -0,0 +1,43 @@ +update=Sat Jun 8 12:53:13 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch new file mode 100644 index 00000000..eb095e0e --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch @@ -0,0 +1,172 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U3 +U 1 1 5AB62CE3 +P 5050 2550 +F 0 "U3" H 5050 2550 60 0000 C CNN +F 1 "d_and" H 5100 2650 60 0000 C CNN +F 2 "" H 5050 2550 60 0000 C CNN +F 3 "" H 5050 2550 60 0000 C CNN + 1 5050 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5AB62D59 +P 5050 3400 +F 0 "U4" H 5050 3400 60 0000 C CNN +F 1 "d_and" H 5100 3500 60 0000 C CNN +F 2 "" H 5050 3400 60 0000 C CNN +F 3 "" H 5050 3400 60 0000 C CNN + 1 5050 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U5 +U 1 1 5AB62DBD +P 6300 2950 +F 0 "U5" H 6300 2950 60 0000 C CNN +F 1 "d_or" H 6300 3050 60 0000 C CNN +F 2 "" H 6300 2950 60 0000 C CNN +F 3 "" H 6300 2950 60 0000 C CNN + 1 6300 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 2500 5550 2500 +Wire Wire Line + 5550 2500 5550 2850 +Wire Wire Line + 5550 2850 5850 2850 +Wire Wire Line + 5500 3350 5550 3350 +Wire Wire Line + 5550 3350 5550 2950 +Wire Wire Line + 5550 2950 5850 2950 +$Comp +L d_inverter U2 +U 1 1 5AB62FFA +P 4200 2550 +F 0 "U2" H 4200 2450 60 0000 C CNN +F 1 "d_inverter" H 4200 2700 60 0000 C CNN +F 2 "" H 4250 2500 60 0000 C CNN +F 3 "" H 4250 2500 60 0000 C CNN + 1 4200 2550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4500 2550 4600 2550 +$Comp +L PORT U1 +U 1 1 5AB6307B +P 3450 3300 +F 0 "U1" H 3500 3400 30 0000 C CNN +F 1 "PORT" H 3450 3300 30 0000 C CNN +F 2 "" H 3450 3300 60 0000 C CNN +F 3 "" H 3450 3300 60 0000 C CNN + 1 3450 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 2550 3900 3300 +Wire Wire Line + 3700 3300 4600 3300 +Connection ~ 3900 3300 +$Comp +L PORT U1 +U 2 1 5AB631BF +P 4100 2050 +F 0 "U1" H 4150 2150 30 0000 C CNN +F 1 "PORT" H 4100 2050 30 0000 C CNN +F 2 "" H 4100 2050 60 0000 C CNN +F 3 "" H 4100 2050 60 0000 C CNN + 2 4100 2050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 2050 4600 2050 +Wire Wire Line + 4600 2050 4600 2450 +$Comp +L PORT U1 +U 3 1 5AB6340B +P 4200 3850 +F 0 "U1" H 4250 3950 30 0000 C CNN +F 1 "PORT" H 4200 3850 30 0000 C CNN +F 2 "" H 4200 3850 60 0000 C CNN +F 3 "" H 4200 3850 60 0000 C CNN + 3 4200 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4600 3400 4600 3850 +Wire Wire Line + 4600 3850 4450 3850 +$Comp +L PORT U1 +U 4 1 5AB63737 +P 7100 2900 +F 0 "U1" H 7150 3000 30 0000 C CNN +F 1 "PORT" H 7100 2900 30 0000 C CNN +F 2 "" H 7100 2900 60 0000 C CNN +F 3 "" H 7100 2900 60 0000 C CNN + 4 7100 2900 + -1 0 0 1 +$EndComp +Wire Wire Line + 6750 2900 6850 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub new file mode 100644 index 00000000..473dc907 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub @@ -0,0 +1,22 @@ +* Subcircuit MUX +.subckt MUX net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\esim\esim\src\subcircuitlibrary\mux\mux.cir +* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and +* u4 net-_u1-pad1_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5 +a4 net-_u1-pad1_ net-_u2-pad2_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends MUX \ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml new file mode 100644 index 00000000..6f43d20b --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u2 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis b/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/IB3858/IB3858-cache.lib b/src/SubcircuitLibrary/IB3858/IB3858-cache.lib new file mode 100644 index 00000000..df4966f4 --- /dev/null +++ b/src/SubcircuitLibrary/IB3858/IB3858-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_L +# +DEF eSim_L L 0 40 N N 1 F N +F0 "L" 1950 500 50 H V C CNN +F1 "eSim_L" 1950 650 50 H V C CNN +F2 "" 1950 550 60 V V C CNN +F3 "" 1950 550 60 V V C CNN +DRAW +A 1802 550 48 11 1789 0 1 0 N 1849 551 1754 551 +A 1899 550 51 11 1789 0 1 0 N 1949 551 1848 551 +A 1999 550 51 11 1789 0 1 0 N 2049 551 1948 551 +A 2100 550 50 11 1789 0 1 0 N 2149 551 2050 551 +X 1 1 1650 550 100 R 70 70 1 1 P +X 2 2 2250 550 100 L 70 70 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/IB3858/IB3858.cir b/src/SubcircuitLibrary/IB3858/IB3858.cir new file mode 100644 index 00000000..e89f69e1 --- /dev/null +++ b/src/SubcircuitLibrary/IB3858/IB3858.cir @@ -0,0 +1,16 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/IB3858/IB3858.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 24 16:30:15 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_R1-Pad1_ Net-_L1-Pad1_ 5.2 +L1 Net-_L1-Pad1_ Net-_C1-Pad1_ 3.08m +L2 Net-_C1-Pad1_ Net-_C1-Pad2_ 61.100458m +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 896.8481u +R2 Net-_C1-Pad1_ Net-_C1-Pad2_ 73.6254 +U1 Net-_R1-Pad1_ Net-_C1-Pad2_ PORT + +.end diff --git a/src/SubcircuitLibrary/IB3858/IB3858.cir.out b/src/SubcircuitLibrary/IB3858/IB3858.cir.out new file mode 100644 index 00000000..3b84dfd6 --- /dev/null +++ b/src/SubcircuitLibrary/IB3858/IB3858.cir.out @@ -0,0 +1,17 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ib3858/ib3858.cir + +r1 net-_r1-pad1_ net-_l1-pad1_ 5.2 +l1 net-_l1-pad1_ net-_c1-pad1_ 3.08m +l2 net-_c1-pad1_ net-_c1-pad2_ 61.100458m +c1 net-_c1-pad1_ net-_c1-pad2_ 896.8481u +r2 net-_c1-pad1_ net-_c1-pad2_ 73.6254 +* u1 net-_r1-pad1_ net-_c1-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/IB3858/IB3858.pro b/src/SubcircuitLibrary/IB3858/IB3858.pro new file mode 100644 index 00000000..148e9ed5 --- /dev/null +++ b/src/SubcircuitLibrary/IB3858/IB3858.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice + diff --git a/src/SubcircuitLibrary/IB3858/IB3858.sch b/src/SubcircuitLibrary/IB3858/IB3858.sch new file mode 100644 index 00000000..bbc79e75 --- /dev/null +++ b/src/SubcircuitLibrary/IB3858/IB3858.sch @@ -0,0 +1,157 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:speaker-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R1 +U 1 1 5D10AD49 +P 6050 3150 +F 0 "R1" H 6100 3280 50 0000 C CNN +F 1 "5.2" H 6100 3200 50 0000 C CNN +F 2 "" H 6100 3130 30 0000 C CNN +F 3 "" V 6100 3200 30 0000 C CNN + 1 6050 3150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_L L1 +U 1 1 5D10AD4A +P 4800 3650 +F 0 "L1" H 6750 4150 50 0000 C CNN +F 1 "3.08m" H 6750 4300 50 0000 C CNN +F 2 "" V 6750 4200 60 0000 C CNN +F 3 "" V 6750 4200 60 0000 C CNN + 1 4800 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_L L2 +U 1 1 5D10AD4B +P 7300 1750 +F 0 "L2" H 9250 2250 50 0000 C CNN +F 1 "61.100458m" H 9250 2400 50 0000 C CNN +F 2 "" V 9250 2300 60 0000 C CNN +F 3 "" V 9250 2300 60 0000 C CNN + 1 7300 1750 + 0 1 1 0 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D10AD4C +P 7350 3700 +F 0 "C1" H 7375 3800 50 0000 L CNN +F 1 "896.8481u" H 7375 3600 50 0000 L CNN +F 2 "" H 7388 3550 30 0000 C CNN +F 3 "" H 7350 3700 60 0000 C CNN + 1 7350 3700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5D10AD4D +P 8450 3700 +F 0 "R2" H 8500 3830 50 0000 C CNN +F 1 "73.6254" H 8500 3750 50 0000 C CNN +F 2 "" H 8500 3680 30 0000 C CNN +F 3 "" V 8500 3750 30 0000 C CNN + 1 8450 3700 + 0 1 1 0 +$EndComp +Wire Wire Line + 7350 3850 7350 4350 +Connection ~ 7850 4350 +Wire Wire Line + 7850 4000 7850 4350 +Wire Wire Line + 8500 4350 8500 3900 +Connection ~ 7850 3100 +Wire Wire Line + 8500 3100 8500 3600 +Connection ~ 7350 3100 +Wire Wire Line + 7850 3100 7850 3400 +Wire Wire Line + 7350 3100 7350 3550 +Wire Wire Line + 7050 3100 8500 3100 +Wire Wire Line + 6250 3100 6450 3100 +Wire Wire Line + 7050 4350 8500 4350 +$Comp +L PORT U1 +U 1 1 5D10B0D2 +P 5250 3100 +F 0 "U1" H 5300 3200 30 0000 C CNN +F 1 "PORT" H 5250 3100 30 0000 C CNN +F 2 "" H 5250 3100 60 0000 C CNN +F 3 "" H 5250 3100 60 0000 C CNN + 1 5250 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D10B10F +P 6800 4350 +F 0 "U1" H 6850 4450 30 0000 C CNN +F 1 "PORT" H 6800 4350 30 0000 C CNN +F 2 "" H 6800 4350 60 0000 C CNN +F 3 "" H 6800 4350 60 0000 C CNN + 2 6800 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5950 3100 5500 3100 +Connection ~ 7350 4350 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/IB3858/IB3858.sub b/src/SubcircuitLibrary/IB3858/IB3858.sub new file mode 100644 index 00000000..cc9a9809 --- /dev/null +++ b/src/SubcircuitLibrary/IB3858/IB3858.sub @@ -0,0 +1,11 @@ +* Subcircuit IB3858 +.subckt IB3858 net-_r1-pad1_ net-_c1-pad2_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ib3858/ib3858.cir +r1 net-_r1-pad1_ net-_l1-pad1_ 5.2 +l1 net-_l1-pad1_ net-_c1-pad1_ 3.08m +l2 net-_c1-pad1_ net-_c1-pad2_ 61.100458m +c1 net-_c1-pad1_ net-_c1-pad2_ 896.8481u +r2 net-_c1-pad1_ net-_c1-pad2_ 73.6254 +* Control Statements + +.ends IB3858 \ No newline at end of file diff --git a/src/SubcircuitLibrary/IB3858/IB3858_Previous_Values.xml b/src/SubcircuitLibrary/IB3858/IB3858_Previous_Values.xml new file mode 100644 index 00000000..56ce5d3f --- /dev/null +++ b/src/SubcircuitLibrary/IB3858/IB3858_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/IB3858/analysis b/src/SubcircuitLibrary/IB3858/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/IB3858/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/LM108/LM108-cache.lib b/src/SubcircuitLibrary/LM108/LM108-cache.lib new file mode 100644 index 00000000..1d0c038e --- /dev/null +++ b/src/SubcircuitLibrary/LM108/LM108-cache.lib @@ -0,0 +1,120 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 I +X ~ 2 250 0 100 L 30 30 2 1 I +X ~ 3 250 0 100 L 30 30 3 1 I +X ~ 4 250 0 100 L 30 30 4 1 I +X ~ 5 250 0 100 L 30 30 5 1 I +X ~ 6 250 0 100 L 30 30 6 1 I +X ~ 7 250 0 100 L 30 30 7 1 I +X ~ 8 250 0 100 L 30 30 8 1 I +X ~ 9 250 0 100 L 30 30 9 1 I +X ~ 10 250 0 100 L 30 30 10 1 I +X ~ 11 250 0 100 L 30 30 11 1 I +X ~ 12 250 0 100 L 30 30 12 1 I +X ~ 13 250 0 100 L 30 30 13 1 I +X ~ 14 250 0 100 L 30 30 14 1 I +X ~ 15 250 0 100 L 30 30 15 1 I +X ~ 16 250 0 100 L 30 30 16 1 I +X ~ 17 250 0 100 L 30 30 17 1 I +X ~ 18 250 0 100 L 30 30 18 1 I +X ~ 19 250 0 100 L 30 30 19 1 I +X ~ 20 250 0 100 L 30 30 20 1 I +X ~ 21 250 0 100 L 30 30 21 1 I +X ~ 22 250 0 100 L 30 30 22 1 I +X ~ 23 250 0 100 L 30 30 23 1 I +X ~ 24 250 0 100 L 30 30 24 1 I +X ~ 25 250 0 100 L 30 30 25 1 I +X ~ 26 250 0 100 L 30 30 26 1 I +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 C +X G 2 -200 0 210 R 50 50 1 1 I +X S 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/LM108/LM108.cir b/src/SubcircuitLibrary/LM108/LM108.cir new file mode 100644 index 00000000..f8d793b5 --- /dev/null +++ b/src/SubcircuitLibrary/LM108/LM108.cir @@ -0,0 +1,59 @@ +* C:\esim_1\eSim\src\SubcircuitLibrary\LM108\LM108.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/31/19 16:57:39 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R2 v+ Net-_Q2-Pad3_ 20k +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q5 Net-_Q13-Pad1_ Net-_Q2-Pad1_ Net-_Q11-Pad3_ eSim_PNP +Q3 Net-_Q2-Pad1_ Net-_Q14-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q7 CompensationA Net-_Q14-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q9 CompensationA CompensationA Net-_Q9-Pad3_ eSim_PNP +Q11 Net-_Q11-Pad1_ CompensationA Net-_Q11-Pad3_ eSim_PNP +R3 v+ Net-_Q9-Pad3_ 20K +R7 v+ Net-_Q11-Pad3_ 10K +Q1 Net-_Q1-Pad1_ Input- Net-_Q1-Pad3_ eSim_NPN +Q4 Net-_Q4-Pad1_ Input+ Input- eSim_NPN +Q6 Net-_Q4-Pad1_ Input- Input+ eSim_NPN +R1 Net-_Q1-Pad3_ Net-_Q10-Pad1_ 2K +R5 Net-_Q4-Pad1_ Net-_Q12-Pad3_ 50K +Q8 Net-_Q7-Pad3_ Input+ Net-_Q8-Pad3_ eSim_NPN +R8 v+ Net-_Q15-Pad3_ 10K +Q15 Net-_Q14-Pad1_ Net-_J1-Pad3_ Net-_Q15-Pad3_ eSim_PNP +R12 CompensationB Net-_Q11-Pad1_ 5.6k +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_Q13-Pad3_ eSim_NPN +Q17 Net-_Q11-Pad1_ Net-_Q13-Pad1_ Net-_Q13-Pad3_ eSim_NPN +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad1_ Net-_Q12-Pad3_ eSim_NPN +R4 Net-_Q8-Pad3_ Net-_Q10-Pad1_ 2k +Q12 V- Net-_Q10-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q18 Net-_J1-Pad3_ Net-_J1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +J1 Net-_J1-Pad1_ V- Net-_J1-Pad3_ eSim_NJF +R13 Net-_J1-Pad1_ Net-_Q16-Pad2_ 940 +R14 Net-_Q18-Pad3_ Net-_Q24-Pad2_ 20k +Q24 Net-_Q13-Pad3_ Net-_Q24-Pad2_ Net-_Q24-Pad3_ eSim_NPN +R6 Net-_Q10-Pad3_ Net-_R10-Pad1_ 6.4K +R9 Net-_Q10-Pad2_ Net-_R10-Pad1_ 60K +R11 Net-_Q18-Pad3_ Net-_Q19-Pad3_ 20K +R10 Net-_R10-Pad1_ Net-_Q19-Pad3_ 500 +R15 Net-_Q19-Pad3_ V- 1K +Q19 Net-_Q16-Pad2_ Net-_Q18-Pad3_ Net-_Q19-Pad3_ eSim_NPN +R17 Net-_Q24-Pad3_ V- 820 +Q21 v+ Net-_J1-Pad3_ Net-_Q20-Pad1_ eSim_NPN +Q20 Net-_Q20-Pad1_ Net-_Q11-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R16 Net-_J1-Pad3_ Net-_Q23-Pad1_ 2K +Q23 Net-_Q23-Pad1_ Net-_J1-Pad3_ Net-_Q22-Pad3_ eSim_NPN +Q26 v+ Net-_Q23-Pad1_ Net-_Q25-Pad2_ eSim_NPN +Q25 Net-_Q23-Pad1_ Net-_Q25-Pad2_ Output eSim_NPN +Q22 V- Net-_Q13-Pad3_ Net-_Q22-Pad3_ eSim_PNP +Q27 V- Net-_Q13-Pad3_ Net-_Q27-Pad3_ eSim_PNP +R18 Net-_Q25-Pad2_ Net-_Q27-Pad3_ 240 +R19 Net-_Q25-Pad2_ Output 90 +U1 CompensationA Input+ Input- V- Output v+ CompensationB PORT +Q29 Net-_J1-Pad3_ Net-_J1-Pad3_ v+ eSim_PNP +Q16 Net-_J1-Pad3_ Net-_Q16-Pad2_ Net-_Q10-Pad2_ eSim_NPN + +.end diff --git a/src/SubcircuitLibrary/LM108/LM108.cir.out b/src/SubcircuitLibrary/LM108/LM108.cir.out new file mode 100644 index 00000000..6e2ff4a1 --- /dev/null +++ b/src/SubcircuitLibrary/LM108/LM108.cir.out @@ -0,0 +1,63 @@ +* c:\esim_1\esim\src\subcircuitlibrary\lm108\lm108.cir + +.include PNP.lib +.include NJF.lib +.include NPN.lib +r2 v+ net-_q2-pad3_ 20k +q2 net-_q2-pad1_ net-_q2-pad1_ net-_q2-pad3_ Q2N2907A +q5 net-_q13-pad1_ net-_q2-pad1_ net-_q11-pad3_ Q2N2907A +q3 net-_q2-pad1_ net-_q14-pad1_ net-_q1-pad1_ Q2N2222 +q7 compensationa net-_q14-pad1_ net-_q7-pad3_ Q2N2222 +q9 compensationa compensationa net-_q9-pad3_ Q2N2907A +q11 net-_q11-pad1_ compensationa net-_q11-pad3_ Q2N2907A +r3 v+ net-_q9-pad3_ 20k +r7 v+ net-_q11-pad3_ 10k +q1 net-_q1-pad1_ input- net-_q1-pad3_ Q2N2222 +q4 net-_q4-pad1_ input+ input- Q2N2222 +q6 net-_q4-pad1_ input- input+ Q2N2222 +r1 net-_q1-pad3_ net-_q10-pad1_ 2k +r5 net-_q4-pad1_ net-_q12-pad3_ 50k +q8 net-_q7-pad3_ input+ net-_q8-pad3_ Q2N2222 +r8 v+ net-_q15-pad3_ 10k +q15 net-_q14-pad1_ net-_j1-pad3_ net-_q15-pad3_ Q2N2907A +r12 compensationb net-_q11-pad1_ 5.6k +q13 net-_q13-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222 +q17 net-_q11-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_q14-pad1_ net-_q14-pad1_ net-_q12-pad3_ Q2N2222 +r4 net-_q8-pad3_ net-_q10-pad1_ 2k +q12 v- net-_q10-pad1_ net-_q12-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q18 net-_j1-pad3_ net-_j1-pad1_ net-_q18-pad3_ Q2N2222 +j1 net-_j1-pad1_ v- net-_j1-pad3_ J2N3819 +r13 net-_j1-pad1_ net-_q16-pad2_ 940 +r14 net-_q18-pad3_ net-_q24-pad2_ 20k +q24 net-_q13-pad3_ net-_q24-pad2_ net-_q24-pad3_ Q2N2222 +r6 net-_q10-pad3_ net-_r10-pad1_ 6.4k +r9 net-_q10-pad2_ net-_r10-pad1_ 60k +r11 net-_q18-pad3_ net-_q19-pad3_ 20k +r10 net-_r10-pad1_ net-_q19-pad3_ 500 +r15 net-_q19-pad3_ v- 1k +q19 net-_q16-pad2_ net-_q18-pad3_ net-_q19-pad3_ Q2N2222 +r17 net-_q24-pad3_ v- 820 +q21 v+ net-_j1-pad3_ net-_q20-pad1_ Q2N2222 +q20 net-_q20-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222 +r16 net-_j1-pad3_ net-_q23-pad1_ 2k +q23 net-_q23-pad1_ net-_j1-pad3_ net-_q22-pad3_ Q2N2222 +q26 v+ net-_q23-pad1_ net-_q25-pad2_ Q2N2222 +q25 net-_q23-pad1_ net-_q25-pad2_ output Q2N2222 +q22 v- net-_q13-pad3_ net-_q22-pad3_ Q2N2907A +q27 v- net-_q13-pad3_ net-_q27-pad3_ Q2N2907A +r18 net-_q25-pad2_ net-_q27-pad3_ 240 +r19 net-_q25-pad2_ output 90 +* u1 compensationa input+ input- v- output v+ compensationb port +q29 net-_j1-pad3_ net-_j1-pad3_ v+ Q2N2907A +q16 net-_j1-pad3_ net-_q16-pad2_ net-_q10-pad2_ Q2N2222 +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/LM108/LM108.pro b/src/SubcircuitLibrary/LM108/LM108.pro new file mode 100644 index 00000000..c76222d6 --- /dev/null +++ b/src/SubcircuitLibrary/LM108/LM108.pro @@ -0,0 +1,83 @@ +update=03/31/19 17:48:06 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../../../Program Files (x86)/KiCad/share/library +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Plot +LibName36=eSim_Power +LibName37=eSim_PSpice +LibName38=eSim_Sources +LibName39=eSim_User +LibName40=eSim_Subckt +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Spice +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/src/SubcircuitLibrary/LM108/LM108.sch b/src/SubcircuitLibrary/LM108/LM108.sch new file mode 100644 index 00000000..a9735ce5 --- /dev/null +++ b/src/SubcircuitLibrary/LM108/LM108.sch @@ -0,0 +1,1013 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:LM108-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R2 +U 1 1 5C9DB838 +P 2750 1400 +F 0 "R2" H 2800 1530 50 0000 C CNN +F 1 "20k" H 2800 1450 50 0000 C CNN +F 2 "" H 2800 1380 30 0000 C CNN +F 3 "" V 2800 1450 30 0000 C CNN + 1 2750 1400 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 5C9DB867 +P 2900 1975 +F 0 "Q2" H 2800 2025 50 0000 R CNN +F 1 "eSim_PNP" H 2850 2125 50 0000 R CNN +F 2 "" H 3100 2075 29 0000 C CNN +F 3 "" H 2900 1975 60 0000 C CNN + 1 2900 1975 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5C9DB8A6 +P 3350 1975 +F 0 "Q5" H 3250 2025 50 0000 R CNN +F 1 "eSim_PNP" H 3300 2125 50 0000 R CNN +F 2 "" H 3550 2075 29 0000 C CNN +F 3 "" H 3350 1975 60 0000 C CNN + 1 3350 1975 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5C9DB912 +P 2900 2625 +F 0 "Q3" H 2800 2675 50 0000 R CNN +F 1 "eSim_NPN" H 2850 2775 50 0000 R CNN +F 2 "" H 3100 2725 29 0000 C CNN +F 3 "" H 2900 2625 60 0000 C CNN + 1 2900 2625 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5C9DB94B +P 3600 2625 +F 0 "Q7" H 3500 2675 50 0000 R CNN +F 1 "eSim_NPN" H 3550 2775 50 0000 R CNN +F 2 "" H 3800 2725 29 0000 C CNN +F 3 "" H 3600 2625 60 0000 C CNN + 1 3600 2625 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5C9DB994 +P 3800 2075 +F 0 "Q9" H 3700 2125 50 0000 R CNN +F 1 "eSim_PNP" H 3750 2225 50 0000 R CNN +F 2 "" H 4000 2175 29 0000 C CNN +F 3 "" H 3800 2075 60 0000 C CNN + 1 3800 2075 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 5C9DB9EF +P 4275 2075 +F 0 "Q11" H 4175 2125 50 0000 R CNN +F 1 "eSim_PNP" H 4225 2225 50 0000 R CNN +F 2 "" H 4475 2175 29 0000 C CNN +F 3 "" H 4275 2075 60 0000 C CNN + 1 4275 2075 + 1 0 0 1 +$EndComp +Wire Wire Line + 2800 1600 2800 1775 +Wire Wire Line + 3100 1975 3150 1975 +Wire Wire Line + 3125 1975 3125 2225 +Wire Wire Line + 3125 2225 2800 2225 +Wire Wire Line + 2800 2175 2800 2425 +Connection ~ 3125 1975 +Wire Wire Line + 4000 2075 4075 2075 +Wire Wire Line + 3700 2275 3700 2425 +Wire Wire Line + 4050 1100 4050 2325 +Wire Wire Line + 4050 2325 3700 2325 +Connection ~ 3700 2325 +Connection ~ 4050 2075 +Connection ~ 2800 2225 +Wire Wire Line + 3100 2625 3400 2625 +$Comp +L eSim_R R3 +U 1 1 5C9DBD46 +P 3650 1400 +F 0 "R3" H 3700 1530 50 0000 C CNN +F 1 "20K" H 3700 1450 50 0000 C CNN +F 2 "" H 3700 1380 30 0000 C CNN +F 3 "" V 3700 1450 30 0000 C CNN + 1 3650 1400 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5C9DBD83 +P 4325 1400 +F 0 "R7" H 4375 1530 50 0000 C CNN +F 1 "10K" H 4375 1450 50 0000 C CNN +F 2 "" H 4375 1380 30 0000 C CNN +F 3 "" V 4375 1450 30 0000 C CNN + 1 4325 1400 + 0 1 1 0 +$EndComp +Wire Wire Line + 3700 1600 3700 1875 +Wire Wire Line + 4375 1600 4375 1875 +Wire Wire Line + 3450 1775 3450 1700 +Wire Wire Line + 3450 1700 4375 1700 +Connection ~ 4375 1700 +Wire Wire Line + 2800 1300 2800 1225 +Wire Wire Line + 2800 1225 7575 1225 +Wire Wire Line + 3700 1225 3700 1300 +Wire Wire Line + 4375 1225 4375 1300 +Connection ~ 3700 1225 +$Comp +L eSim_NPN Q1 +U 1 1 5C9DBEE9 +P 2650 3375 +F 0 "Q1" H 2550 3425 50 0000 R CNN +F 1 "eSim_NPN" H 2600 3525 50 0000 R CNN +F 2 "" H 2850 3475 29 0000 C CNN +F 3 "" H 2650 3375 60 0000 C CNN + 1 2650 3375 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3175 2750 2825 +Wire Wire Line + 2750 2825 2800 2825 +Wire Wire Line + 2450 3375 2375 3375 +$Comp +L eSim_NPN Q4 +U 1 1 5C9DBF74 +P 2950 3975 +F 0 "Q4" H 2850 4025 50 0000 R CNN +F 1 "eSim_NPN" H 2900 4125 50 0000 R CNN +F 2 "" H 3150 4075 29 0000 C CNN +F 3 "" H 2950 3975 60 0000 C CNN + 1 2950 3975 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 5C9DBFBB +P 3500 3975 +F 0 "Q6" H 3400 4025 50 0000 R CNN +F 1 "eSim_NPN" H 3450 4125 50 0000 R CNN +F 2 "" H 3700 4075 29 0000 C CNN +F 3 "" H 3500 3975 60 0000 C CNN + 1 3500 3975 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 3775 3600 3650 +Wire Wire Line + 2850 3650 4050 3650 +Wire Wire Line + 2850 3650 2850 3775 +Wire Wire Line + 3150 3975 3150 4175 +Wire Wire Line + 3150 4175 3600 4175 +Wire Wire Line + 3300 4250 3300 3975 +Wire Wire Line + 2450 4250 3300 4250 +Wire Wire Line + 2850 4250 2850 4175 +Wire Wire Line + 2450 4250 2450 3375 +Connection ~ 2850 4250 +$Comp +L eSim_R R1 +U 1 1 5C9DC222 +P 2700 5000 +F 0 "R1" H 2750 5130 50 0000 C CNN +F 1 "2K" H 2750 5050 50 0000 C CNN +F 2 "" H 2750 4980 30 0000 C CNN +F 3 "" V 2750 5050 30 0000 C CNN + 1 2700 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 2750 3575 2750 4900 +$Comp +L eSim_R R5 +U 1 1 5C9DC2A7 +P 4150 3700 +F 0 "R5" H 4200 3830 50 0000 C CNN +F 1 "50K" H 4200 3750 50 0000 C CNN +F 2 "" H 4200 3680 30 0000 C CNN +F 3 "" V 4200 3750 30 0000 C CNN + 1 4150 3700 + 1 0 0 -1 +$EndComp +Connection ~ 3600 3650 +$Comp +L eSim_NPN Q8 +U 1 1 5C9DC459 +P 3625 4425 +F 0 "Q8" H 3525 4475 50 0000 R CNN +F 1 "eSim_NPN" H 3575 4575 50 0000 R CNN +F 2 "" H 3825 4525 29 0000 C CNN +F 3 "" H 3625 4425 60 0000 C CNN + 1 3625 4425 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 4425 3400 4175 +Wire Wire Line + 2400 4425 3425 4425 +Connection ~ 3400 4175 +Wire Wire Line + 3725 4225 3725 2825 +Wire Wire Line + 3725 2825 3700 2825 +$Comp +L eSim_R R8 +U 1 1 5C9DCB0B +P 4575 1400 +F 0 "R8" H 4625 1530 50 0000 C CNN +F 1 "10K" H 4625 1450 50 0000 C CNN +F 2 "" H 4625 1380 30 0000 C CNN +F 3 "" V 4625 1450 30 0000 C CNN + 1 4575 1400 + 0 1 1 0 +$EndComp +Wire Wire Line + 4625 1225 4625 1300 +Connection ~ 4375 1225 +$Comp +L eSim_PNP Q15 +U 1 1 5C9DCBA9 +P 4775 1850 +F 0 "Q15" H 4675 1900 50 0000 R CNN +F 1 "eSim_PNP" H 4725 2000 50 0000 R CNN +F 2 "" H 4975 1950 29 0000 C CNN +F 3 "" H 4775 1850 60 0000 C CNN + 1 4775 1850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4675 1650 4625 1650 +Wire Wire Line + 4625 1650 4625 1600 +Connection ~ 4625 1225 +$Comp +L eSim_R R12 +U 1 1 5C9DC058 +P 5550 1925 +F 0 "R12" H 5600 2055 50 0000 C CNN +F 1 "5.6k" H 5600 1975 50 0000 C CNN +F 2 "" H 5600 1905 30 0000 C CNN +F 3 "" V 5600 1975 30 0000 C CNN + 1 5550 1925 + 0 1 1 0 +$EndComp +Wire Wire Line + 5600 2125 5600 2550 +Wire Wire Line + 4375 2275 5725 2275 +$Comp +L eSim_NPN Q13 +U 1 1 5C9DC257 +P 4525 2750 +F 0 "Q13" H 4425 2800 50 0000 R CNN +F 1 "eSim_NPN" H 4475 2900 50 0000 R CNN +F 2 "" H 4725 2850 29 0000 C CNN +F 3 "" H 4525 2750 60 0000 C CNN + 1 4525 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5C9DC2B6 +P 5500 2750 +F 0 "Q17" H 5400 2800 50 0000 R CNN +F 1 "eSim_NPN" H 5450 2900 50 0000 R CNN +F 2 "" H 5700 2850 29 0000 C CNN +F 3 "" H 5500 2750 60 0000 C CNN + 1 5500 2750 + 1 0 0 -1 +$EndComp +Connection ~ 5600 2275 +Wire Wire Line + 4725 2750 5300 2750 +Wire Wire Line + 3450 2175 3450 2400 +Wire Wire Line + 3450 2400 5050 2400 +Wire Wire Line + 4425 2400 4425 2550 +Wire Wire Line + 5050 2400 5050 2750 +Connection ~ 5050 2750 +Connection ~ 4425 2400 +Wire Wire Line + 4425 2950 4425 3075 +Wire Wire Line + 4425 3075 7275 3075 +Wire Wire Line + 5600 3075 5600 2950 +$Comp +L eSim_NPN Q14 +U 1 1 5C9DC732 +P 4525 3400 +F 0 "Q14" H 4425 3450 50 0000 R CNN +F 1 "eSim_NPN" H 4475 3550 50 0000 R CNN +F 2 "" H 4725 3500 29 0000 C CNN +F 3 "" H 4525 3400 60 0000 C CNN + 1 4525 3400 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3200 3200 4725 3200 +Wire Wire Line + 4725 2225 4725 3400 +Wire Wire Line + 4725 2225 4675 2225 +Wire Wire Line + 4675 2225 4675 2050 +Connection ~ 4725 3200 +Wire Wire Line + 3200 3200 3200 2625 +Connection ~ 3200 2625 +Connection ~ 4425 3200 +Wire Wire Line + 4425 3600 4425 5125 +Wire Wire Line + 4425 3650 4350 3650 +$Comp +L eSim_R R4 +U 1 1 5C9DCD74 +P 3675 5000 +F 0 "R4" H 3725 5130 50 0000 C CNN +F 1 "2k" H 3725 5050 50 0000 C CNN +F 2 "" H 3725 4980 30 0000 C CNN +F 3 "" V 3725 5050 30 0000 C CNN + 1 3675 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 3725 4625 3725 4900 +Wire Wire Line + 3725 5200 3725 5600 +Wire Wire Line + 2750 5325 4125 5325 +Wire Wire Line + 2750 5325 2750 5200 +$Comp +L eSim_PNP Q12 +U 1 1 5C9DD197 +P 4325 5325 +F 0 "Q12" H 4225 5375 50 0000 R CNN +F 1 "eSim_PNP" H 4275 5475 50 0000 R CNN +F 2 "" H 4525 5425 29 0000 C CNN +F 3 "" H 4325 5325 60 0000 C CNN + 1 4325 5325 + 1 0 0 1 +$EndComp +Connection ~ 3725 5325 +Connection ~ 4425 3650 +$Comp +L eSim_NPN Q10 +U 1 1 5C9DD5DD +P 3825 5800 +F 0 "Q10" H 3725 5850 50 0000 R CNN +F 1 "eSim_NPN" H 3775 5950 50 0000 R CNN +F 2 "" H 4025 5900 29 0000 C CNN +F 3 "" H 3825 5800 60 0000 C CNN + 1 3825 5800 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4825 5225 4825 5875 +Wire Wire Line + 4825 5800 4025 5800 +$Comp +L eSim_NPN Q18 +U 1 1 5C9DDBBA +P 5650 4175 +F 0 "Q18" H 5550 4225 50 0000 R CNN +F 1 "eSim_NPN" H 5600 4325 50 0000 R CNN +F 2 "" H 5850 4275 29 0000 C CNN +F 3 "" H 5650 4175 60 0000 C CNN + 1 5650 4175 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NJF J1 +U 1 1 5C9DDDE9 +P 6400 4100 +F 0 "J1" H 6300 4150 50 0000 R CNN +F 1 "eSim_NJF" H 6350 4250 50 0000 R CNN +F 2 "" H 6600 4200 29 0000 C CNN +F 3 "" H 6400 4100 60 0000 C CNN + 1 6400 4100 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R13 +U 1 1 5C9DFBCC +P 6250 4625 +F 0 "R13" H 6300 4755 50 0000 C CNN +F 1 "940" H 6300 4675 50 0000 C CNN +F 2 "" H 6300 4605 30 0000 C CNN +F 3 "" V 6300 4675 30 0000 C CNN + 1 6250 4625 + 0 1 1 0 +$EndComp +Wire Wire Line + 6300 4300 6300 4525 +Wire Wire Line + 5125 5025 6300 5025 +Wire Wire Line + 6300 4825 6300 5475 +$Comp +L eSim_R R14 +U 1 1 5C9DFE3D +P 6500 4550 +F 0 "R14" H 6550 4680 50 0000 C CNN +F 1 "20k" H 6550 4600 50 0000 C CNN +F 2 "" H 6550 4530 30 0000 C CNN +F 3 "" V 6550 4600 30 0000 C CNN + 1 6500 4550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6400 4500 5550 4500 +Wire Wire Line + 5550 4375 5550 5875 +Wire Wire Line + 4425 5525 6850 5525 +Wire Wire Line + 6850 4100 6850 6250 +Wire Wire Line + 6850 4100 6600 4100 +$Comp +L eSim_NPN Q24 +U 1 1 5C9E055D +P 7225 4500 +F 0 "Q24" H 7125 4550 50 0000 R CNN +F 1 "eSim_NPN" H 7175 4650 50 0000 R CNN +F 2 "" H 7425 4600 29 0000 C CNN +F 3 "" H 7225 4500 60 0000 C CNN + 1 7225 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7025 4500 6700 4500 +$Comp +L eSim_R R6 +U 1 1 5C9E0948 +P 4225 6300 +F 0 "R6" H 4275 6430 50 0000 C CNN +F 1 "6.4K" H 4275 6350 50 0000 C CNN +F 2 "" H 4275 6280 30 0000 C CNN +F 3 "" V 4275 6350 30 0000 C CNN + 1 4225 6300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5C9E09B9 +P 4775 5975 +F 0 "R9" H 4825 6105 50 0000 C CNN +F 1 "60K" H 4825 6025 50 0000 C CNN +F 2 "" H 4825 5955 30 0000 C CNN +F 3 "" V 4825 6025 30 0000 C CNN + 1 4775 5975 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5C9E0B22 +P 5500 5975 +F 0 "R11" H 5550 6105 50 0000 C CNN +F 1 "20K" H 5550 6025 50 0000 C CNN +F 2 "" H 5550 5955 30 0000 C CNN +F 3 "" V 5550 6025 30 0000 C CNN + 1 5500 5975 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5C9E0B8F +P 5125 6300 +F 0 "R10" H 5175 6430 50 0000 C CNN +F 1 "500" H 5175 6350 50 0000 C CNN +F 2 "" H 5175 6280 30 0000 C CNN +F 3 "" V 5175 6350 30 0000 C CNN + 1 5125 6300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R15 +U 1 1 5C9E0BFA +P 6500 6300 +F 0 "R15" H 6550 6430 50 0000 C CNN +F 1 "1K" H 6550 6350 50 0000 C CNN +F 2 "" H 6550 6280 30 0000 C CNN +F 3 "" V 6550 6350 30 0000 C CNN + 1 6500 6300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 5C9E0C83 +P 5750 5675 +F 0 "Q19" H 5650 5725 50 0000 R CNN +F 1 "eSim_NPN" H 5700 5825 50 0000 R CNN +F 2 "" H 5950 5775 29 0000 C CNN +F 3 "" H 5750 5675 60 0000 C CNN + 1 5750 5675 + 1 0 0 -1 +$EndComp +Connection ~ 5550 4500 +Connection ~ 5550 5675 +Wire Wire Line + 5550 6175 5550 6250 +Wire Wire Line + 5325 6250 6400 6250 +Wire Wire Line + 4425 6250 5025 6250 +Wire Wire Line + 4825 6250 4825 6175 +Connection ~ 4825 6250 +Connection ~ 4825 5800 +Wire Wire Line + 4125 6250 3725 6250 +Wire Wire Line + 3725 6250 3725 6000 +Connection ~ 5550 6250 +Wire Wire Line + 5850 5875 6225 5875 +Wire Wire Line + 6225 5875 6225 6250 +Connection ~ 6225 6250 +Wire Wire Line + 6700 6250 8600 6250 +Connection ~ 6850 5525 +Wire Wire Line + 6300 5475 5850 5475 +Connection ~ 6300 5025 +$Comp +L eSim_R R17 +U 1 1 5C9E17A1 +P 7275 5325 +F 0 "R17" H 7325 5455 50 0000 C CNN +F 1 "820" H 7325 5375 50 0000 C CNN +F 2 "" H 7325 5305 30 0000 C CNN +F 3 "" V 7325 5375 30 0000 C CNN + 1 7275 5325 + 0 1 1 0 +$EndComp +Wire Wire Line + 7325 4700 7325 5225 +Wire Wire Line + 7325 6250 7325 5525 +Connection ~ 6850 6250 +$Comp +L eSim_NPN Q21 +U 1 1 5C9E2938 +P 6125 1525 +F 0 "Q21" H 6025 1575 50 0000 R CNN +F 1 "eSim_NPN" H 6075 1675 50 0000 R CNN +F 2 "" H 6325 1625 29 0000 C CNN +F 3 "" H 6125 1525 60 0000 C CNN + 1 6125 1525 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 5C9E29AB +P 5925 2275 +F 0 "Q20" H 5825 2325 50 0000 R CNN +F 1 "eSim_NPN" H 5875 2425 50 0000 R CNN +F 2 "" H 6125 2375 29 0000 C CNN +F 3 "" H 5925 2275 60 0000 C CNN + 1 5925 2275 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6025 1725 6025 2075 +Wire Wire Line + 5700 1300 5700 1675 +Wire Wire Line + 7575 1300 8450 1300 +Wire Wire Line + 6375 1300 6375 1800 +Wire Wire Line + 6325 1525 6675 1525 +$Comp +L eSim_R R16 +U 1 1 5C9E2CC0 +P 6775 1575 +F 0 "R16" H 6825 1705 50 0000 C CNN +F 1 "2K" H 6825 1625 50 0000 C CNN +F 2 "" H 6825 1555 30 0000 C CNN +F 3 "" V 6825 1625 30 0000 C CNN + 1 6775 1575 + 1 0 0 -1 +$EndComp +Connection ~ 6375 1525 +$Comp +L eSim_NPN Q23 +U 1 1 5C9E2F0C +P 6875 1800 +F 0 "Q23" H 6775 1850 50 0000 R CNN +F 1 "eSim_NPN" H 6825 1950 50 0000 R CNN +F 2 "" H 7075 1900 29 0000 C CNN +F 3 "" H 6875 1800 60 0000 C CNN + 1 6875 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6975 1525 6975 1600 +Wire Wire Line + 6375 1800 6675 1800 +$Comp +L eSim_NPN Q26 +U 1 1 5C9E318C +P 7475 1525 +F 0 "Q26" H 7375 1575 50 0000 R CNN +F 1 "eSim_NPN" H 7425 1675 50 0000 R CNN +F 2 "" H 7675 1625 29 0000 C CNN +F 3 "" H 7475 1525 60 0000 C CNN + 1 7475 1525 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6975 1525 7275 1525 +$Comp +L eSim_NPN Q25 +U 1 1 5C9E32C5 +P 7300 1800 +F 0 "Q25" H 7200 1850 50 0000 R CNN +F 1 "eSim_NPN" H 7250 1950 50 0000 R CNN +F 2 "" H 7500 1900 29 0000 C CNN +F 3 "" H 7300 1800 60 0000 C CNN + 1 7300 1800 + -1 0 0 -1 +$EndComp +Wire Wire Line + 7200 1600 7200 1525 +Connection ~ 7200 1525 +Wire Wire Line + 7575 1725 7575 2275 +Wire Wire Line + 7500 1800 7825 1800 +Wire Wire Line + 7575 1225 7575 1325 +$Comp +L eSim_PNP Q22 +U 1 1 5C9E36C9 +P 6850 2775 +F 0 "Q22" H 6750 2825 50 0000 R CNN +F 1 "eSim_PNP" H 6800 2925 50 0000 R CNN +F 2 "" H 7050 2875 29 0000 C CNN +F 3 "" H 6850 2775 60 0000 C CNN + 1 6850 2775 + 1 0 0 1 +$EndComp +Wire Wire Line + 6975 2000 6975 2575 +Wire Wire Line + 6975 2575 6950 2575 +Connection ~ 5600 3075 +Wire Wire Line + 6025 3075 6025 2475 +Wire Wire Line + 6650 2775 6650 3325 +Connection ~ 6025 3075 +$Comp +L eSim_PNP Q27 +U 1 1 5C9E3F8C +P 7475 3075 +F 0 "Q27" H 7375 3125 50 0000 R CNN +F 1 "eSim_PNP" H 7425 3225 50 0000 R CNN +F 2 "" H 7675 3175 29 0000 C CNN +F 3 "" H 7475 3075 60 0000 C CNN + 1 7475 3075 + 1 0 0 1 +$EndComp +Connection ~ 6650 3075 +$Comp +L eSim_R R18 +U 1 1 5C9E431A +P 7525 2375 +F 0 "R18" H 7575 2505 50 0000 C CNN +F 1 "240" H 7575 2425 50 0000 C CNN +F 2 "" H 7575 2355 30 0000 C CNN +F 3 "" V 7575 2425 30 0000 C CNN + 1 7525 2375 + 0 1 1 0 +$EndComp +Connection ~ 7575 1800 +Wire Wire Line + 7575 2575 7575 2875 +$Comp +L eSim_R R19 +U 1 1 5C9E45DF +P 7925 1850 +F 0 "R19" H 7975 1980 50 0000 C CNN +F 1 "90" H 7975 1900 50 0000 C CNN +F 2 "" H 7975 1830 30 0000 C CNN +F 3 "" V 7975 1900 30 0000 C CNN + 1 7925 1850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7200 2000 8250 2000 +Wire Wire Line + 8250 2000 8250 1800 +Wire Wire Line + 8125 1800 8475 1800 +Wire Wire Line + 7325 4300 7325 3325 +Wire Wire Line + 7325 3325 6650 3325 +Wire Wire Line + 6950 2975 7300 2975 +Wire Wire Line + 7300 2975 7300 2750 +Wire Wire Line + 7300 2750 7875 2750 +Wire Wire Line + 7875 2750 7875 6250 +Connection ~ 7325 6250 +Wire Wire Line + 7575 3275 7575 6250 +Connection ~ 7575 6250 +Connection ~ 7875 6250 +Connection ~ 8250 1800 +Connection ~ 7575 1300 +$Comp +L PORT U1 +U 7 1 5C9EBDC2 +P 8700 1300 +F 0 "U1" H 8750 1400 30 0000 C CNN +F 1 "PORT" H 8700 1300 30 0000 C CNN +F 2 "" H 8700 1300 60 0000 C CNN +F 3 "" H 8700 1300 60 0000 C CNN + 7 8700 1300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9EBE57 +P 8725 1800 +F 0 "U1" H 8775 1900 30 0000 C CNN +F 1 "PORT" H 8725 1800 30 0000 C CNN +F 2 "" H 8725 1800 60 0000 C CNN +F 3 "" H 8725 1800 60 0000 C CNN + 6 8725 1800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9EC714 +P 8850 6250 +F 0 "U1" H 8900 6350 30 0000 C CNN +F 1 "PORT" H 8850 6250 30 0000 C CNN +F 2 "" H 8850 6250 60 0000 C CNN +F 3 "" H 8850 6250 60 0000 C CNN + 4 8850 6250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9ED09C +P 2125 3375 +F 0 "U1" H 2175 3475 30 0000 C CNN +F 1 "PORT" H 2125 3375 30 0000 C CNN +F 2 "" H 2125 3375 60 0000 C CNN +F 3 "" H 2125 3375 60 0000 C CNN + 2 2125 3375 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9ED12F +P 2150 4425 +F 0 "U1" H 2200 4525 30 0000 C CNN +F 1 "PORT" H 2150 4425 30 0000 C CNN +F 2 "" H 2150 4425 60 0000 C CNN +F 3 "" H 2150 4425 60 0000 C CNN + 3 2150 4425 + 1 0 0 -1 +$EndComp +Connection ~ 3400 4425 +Text GLabel 8425 1075 0 60 Input ~ 0 +v+ +Wire Wire Line + 8425 1075 8450 1075 +Wire Wire Line + 8450 1075 8450 1300 +Text GLabel 8475 1675 0 60 Input ~ 0 +Output +Wire Wire Line + 8475 1800 8475 1675 +Text GLabel 8600 6150 0 60 Input ~ 0 +V- +Wire Wire Line + 8600 6250 8600 6150 +Text GLabel 2375 4600 0 60 Input ~ 0 +Input+ +Wire Wire Line + 2375 4600 2450 4600 +Wire Wire Line + 2450 4600 2450 4425 +Connection ~ 2450 4425 +Text GLabel 2350 3525 0 60 Input ~ 0 +Input- +Wire Wire Line + 2350 3525 2375 3525 +Wire Wire Line + 2375 3525 2375 3375 +Wire Wire Line + 6025 1225 6025 1325 +Connection ~ 6025 1225 +Wire Wire Line + 5700 1300 6375 1300 +Wire Wire Line + 5600 1825 5600 1125 +$Comp +L PORT U1 +U 1 1 5C9FE719 +P 4050 850 +F 0 "U1" H 4100 950 30 0000 C CNN +F 1 "PORT" H 4050 850 30 0000 C CNN +F 2 "" H 4050 850 60 0000 C CNN +F 3 "" H 4050 850 60 0000 C CNN + 1 4050 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C9FF058 +P 5600 875 +F 0 "U1" H 5650 975 30 0000 C CNN +F 1 "PORT" H 5600 875 30 0000 C CNN +F 2 "" H 5600 875 60 0000 C CNN +F 3 "" H 5600 875 60 0000 C CNN + 8 5600 875 + 0 1 1 0 +$EndComp +Text GLabel 5500 1125 0 60 Input ~ 0 +CompensationB +Wire Wire Line + 5600 1125 5500 1125 +Text GLabel 3875 1075 0 60 Input ~ 0 +CompensationA +Wire Wire Line + 3875 1075 3975 1075 +Wire Wire Line + 3975 1075 3975 1150 +Wire Wire Line + 3975 1150 4050 1150 +Connection ~ 4050 1150 +Wire Wire Line + 5850 4175 5850 4375 +Wire Wire Line + 5850 4375 6300 4375 +Connection ~ 6300 4375 +$Comp +L eSim_PNP Q28 +U 1 1 5CA09126 +P 5075 1475 +F 0 "Q28" H 4975 1525 50 0000 R CNN +F 1 "eSim_PNP" H 5025 1625 50 0000 R CNN +F 2 "" H 5275 1575 29 0000 C CNN +F 3 "" H 5075 1475 60 0000 C CNN + 1 5075 1475 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q29 +U 1 1 5CA091C3 +P 5400 1475 +F 0 "Q29" H 5300 1525 50 0000 R CNN +F 1 "eSim_PNP" H 5350 1625 50 0000 R CNN +F 2 "" H 5600 1575 29 0000 C CNN +F 3 "" H 5400 1475 60 0000 C CNN + 1 5400 1475 + 1 0 0 1 +$EndComp +Wire Wire Line + 5500 1275 5500 1225 +Connection ~ 5500 1225 +Wire Wire Line + 4875 1475 4875 1675 +Wire Wire Line + 4875 1675 4975 1675 +Wire Wire Line + 5175 1675 5175 1850 +Wire Wire Line + 5700 1675 5500 1675 +$Comp +L eSim_NPN Q16 +U 1 1 5CA0B93F +P 4925 5025 +F 0 "Q16" H 4825 5075 50 0000 R CNN +F 1 "eSim_NPN" H 4875 5175 50 0000 R CNN +F 2 "" H 5125 5125 29 0000 C CNN +F 3 "" H 4925 5025 60 0000 C CNN + 1 4925 5025 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5200 1475 5200 1275 +Wire Wire Line + 5200 1275 5175 1275 +Wire Wire Line + 5175 1850 4975 1850 +Wire Wire Line + 4975 1675 4975 3975 +Wire Wire Line + 4825 3975 6100 3975 +Connection ~ 4975 1850 +Wire Wire Line + 6100 3975 6100 3900 +Wire Wire Line + 6100 3900 6300 3900 +Connection ~ 5550 3975 +Wire Wire Line + 4825 3975 4825 4825 +Connection ~ 4975 3975 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/LM108/LM108.sub b/src/SubcircuitLibrary/LM108/LM108.sub new file mode 100644 index 00000000..b04676f7 --- /dev/null +++ b/src/SubcircuitLibrary/LM108/LM108.sub @@ -0,0 +1,57 @@ +* Subcircuit LM108 +.subckt LM108 compensationa input+ input- v- output v+ compensationb +* c:\esim_1\esim\src\subcircuitlibrary\lm108\lm108.cir +.include PNP.lib +.include NJF.lib +.include NPN.lib +r2 v+ net-_q2-pad3_ 20k +q2 net-_q2-pad1_ net-_q2-pad1_ net-_q2-pad3_ Q2N2907A +q5 net-_q13-pad1_ net-_q2-pad1_ net-_q11-pad3_ Q2N2907A +q3 net-_q2-pad1_ net-_q14-pad1_ net-_q1-pad1_ Q2N2222 +q7 compensationa net-_q14-pad1_ net-_q7-pad3_ Q2N2222 +q9 compensationa compensationa net-_q9-pad3_ Q2N2907A +q11 net-_q11-pad1_ compensationa net-_q11-pad3_ Q2N2907A +r3 v+ net-_q9-pad3_ 20k +r7 v+ net-_q11-pad3_ 10k +q1 net-_q1-pad1_ input- net-_q1-pad3_ Q2N2222 +q4 net-_q4-pad1_ input+ input- Q2N2222 +q6 net-_q4-pad1_ input- input+ Q2N2222 +r1 net-_q1-pad3_ net-_q10-pad1_ 2k +r5 net-_q4-pad1_ net-_q12-pad3_ 50k +q8 net-_q7-pad3_ input+ net-_q8-pad3_ Q2N2222 +r8 v+ net-_q15-pad3_ 10k +q15 net-_q14-pad1_ net-_j1-pad3_ net-_q15-pad3_ Q2N2907A +r12 compensationb net-_q11-pad1_ 5.6k +q13 net-_q13-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222 +q17 net-_q11-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_q14-pad1_ net-_q14-pad1_ net-_q12-pad3_ Q2N2222 +r4 net-_q8-pad3_ net-_q10-pad1_ 2k +q12 v- net-_q10-pad1_ net-_q12-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q18 net-_j1-pad3_ net-_j1-pad1_ net-_q18-pad3_ Q2N2222 +j1 net-_j1-pad1_ v- net-_j1-pad3_ J2N3819 +r13 net-_j1-pad1_ net-_q16-pad2_ 940 +r14 net-_q18-pad3_ net-_q24-pad2_ 20k +q24 net-_q13-pad3_ net-_q24-pad2_ net-_q24-pad3_ Q2N2222 +r6 net-_q10-pad3_ net-_r10-pad1_ 6.4k +r9 net-_q10-pad2_ net-_r10-pad1_ 60k +r11 net-_q18-pad3_ net-_q19-pad3_ 20k +r10 net-_r10-pad1_ net-_q19-pad3_ 500 +r15 net-_q19-pad3_ v- 1k +q19 net-_q16-pad2_ net-_q18-pad3_ net-_q19-pad3_ Q2N2222 +r17 net-_q24-pad3_ v- 820 +q21 v+ net-_j1-pad3_ net-_q20-pad1_ Q2N2222 +q20 net-_q20-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222 +r16 net-_j1-pad3_ net-_q23-pad1_ 2k +q23 net-_q23-pad1_ net-_j1-pad3_ net-_q22-pad3_ Q2N2222 +q26 v+ net-_q23-pad1_ net-_q25-pad2_ Q2N2222 +q25 net-_q23-pad1_ net-_q25-pad2_ output Q2N2222 +q22 v- net-_q13-pad3_ net-_q22-pad3_ Q2N2907A +q27 v- net-_q13-pad3_ net-_q27-pad3_ Q2N2907A +r18 net-_q25-pad2_ net-_q27-pad3_ 240 +r19 net-_q25-pad2_ output 90 +q29 net-_j1-pad3_ net-_j1-pad3_ v+ Q2N2907A +q16 net-_j1-pad3_ net-_q16-pad2_ net-_q10-pad2_ Q2N2222 +* Control Statements + +.ends LM108 \ No newline at end of file diff --git a/src/SubcircuitLibrary/LM108/LM108_Previous_Values.xml b/src/SubcircuitLibrary/LM108/LM108_Previous_Values.xml new file mode 100644 index 00000000..c3161654 --- /dev/null +++ b/src/SubcircuitLibrary/LM108/LM108_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><j1><field>C:/esim_1/eSim/src/deviceModelLibrary/JFET/NJF.lib</field></j1><q20><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q20><q21><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q21><q22><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q22><q23><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q23><q24><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q24><q25><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q25><q26><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q26><q27><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q27><q29><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q29><q1><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q2><q5><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q15><q14><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q14><q17><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q11><q10><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q12><q19><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q19><q18><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/LM108/NJF.lib b/src/SubcircuitLibrary/LM108/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/src/SubcircuitLibrary/LM108/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/src/SubcircuitLibrary/LM108/NPN.lib b/src/SubcircuitLibrary/LM108/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/LM108/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/LM108/PNP.lib b/src/SubcircuitLibrary/LM108/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/LM108/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/LM3046/LM3046-cache.lib b/src/SubcircuitLibrary/LM3046/LM3046-cache.lib new file mode 100644 index 00000000..27505ab7 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046-cache.lib @@ -0,0 +1,77 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/LM3046/LM3046.cir b/src/SubcircuitLibrary/LM3046/LM3046.cir new file mode 100644 index 00000000..f9716c63 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.cir @@ -0,0 +1,16 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM3046/LM3046.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 22 11:57:18 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_NPN +Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q1-Pad3_ eSim_NPN +U1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ Net-_Q5-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ Net-_Q4-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ Net-_Q2-Pad1_ PORT + +.end diff --git a/src/SubcircuitLibrary/LM3046/LM3046.cir.out b/src/SubcircuitLibrary/LM3046/LM3046.cir.out new file mode 100644 index 00000000..801e68d2 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.cir.out @@ -0,0 +1,18 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm3046/lm3046.cir + +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222 +* u1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q5-pad2_ net-_q5-pad3_ net-_q5-pad1_ net-_q4-pad2_ net-_q4-pad3_ net-_q4-pad1_ net-_q2-pad2_ net-_q2-pad3_ net-_q2-pad1_ port +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/LM3046/LM3046.pro b/src/SubcircuitLibrary/LM3046/LM3046.pro new file mode 100644 index 00000000..38ae7a8e --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.pro @@ -0,0 +1,73 @@ +update=Fri Jun 21 16:28:59 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../eSim-1.1.2/kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Plot +LibName35=eSim_Power +LibName36=eSim_PSpice +LibName37=eSim_Sources +LibName38=eSim_Subckt +LibName39=eSim_User +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous diff --git a/src/SubcircuitLibrary/LM3046/LM3046.sch b/src/SubcircuitLibrary/LM3046/LM3046.sch new file mode 100644 index 00000000..3ba1a18a --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.sch @@ -0,0 +1,326 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Miscellaneous +LIBS:LM3046-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5C98EC0E +P 4150 3500 +F 0 "Q1" H 4050 3550 50 0000 R CNN +F 1 "eSim_NPN" H 4100 3650 50 0000 R CNN +F 2 "" H 4350 3600 29 0000 C CNN +F 3 "" H 4150 3500 60 0000 C CNN + 1 4150 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5C98EC83 +P 4200 2400 +F 0 "Q2" H 4100 2450 50 0000 R CNN +F 1 "eSim_NPN" H 4150 2550 50 0000 R CNN +F 2 "" H 4400 2500 29 0000 C CNN +F 3 "" H 4200 2400 60 0000 C CNN + 1 4200 2400 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 5C98ECC0 +P 5400 2400 +F 0 "Q4" H 5300 2450 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2550 50 0000 R CNN +F 2 "" H 5600 2500 29 0000 C CNN +F 3 "" H 5400 2400 60 0000 C CNN + 1 5400 2400 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 5C98ED6B +P 6350 3450 +F 0 "Q5" H 6250 3500 50 0000 R CNN +F 1 "eSim_NPN" H 6300 3600 50 0000 R CNN +F 2 "" H 6550 3550 29 0000 C CNN +F 3 "" H 6350 3450 60 0000 C CNN + 1 6350 3450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5C98EDA0 +P 5150 3500 +F 0 "Q3" H 5050 3550 50 0000 R CNN +F 1 "eSim_NPN" H 5100 3650 50 0000 R CNN +F 2 "" H 5350 3600 29 0000 C CNN +F 3 "" H 5150 3500 60 0000 C CNN + 1 5150 3500 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4250 3700 5050 3700 +Wire Wire Line + 4650 3700 4650 4250 +Connection ~ 4650 3700 +Wire Wire Line + 5350 3500 5350 4250 +Wire Wire Line + 5050 3300 5700 3300 +Wire Wire Line + 5700 3300 5700 4250 +Wire Wire Line + 6150 3450 6000 3450 +Wire Wire Line + 6000 3450 6000 4250 +Wire Wire Line + 6450 3250 6450 1700 +Wire Wire Line + 6450 3650 6450 4250 +Wire Wire Line + 3950 3500 3950 4250 +Wire Wire Line + 4250 3300 4250 3200 +Wire Wire Line + 4250 3200 3500 3200 +Wire Wire Line + 3500 3200 3500 4250 +Wire Wire Line + 4100 2200 4100 1700 +Wire Wire Line + 4100 2600 3500 2600 +Wire Wire Line + 3500 2600 3500 1700 +Wire Wire Line + 4400 2400 4400 1700 +Wire Wire Line + 5300 2200 5300 1700 +Wire Wire Line + 5300 2600 4800 2600 +Wire Wire Line + 4800 2600 4800 1700 +Wire Wire Line + 5600 2400 5900 2400 +Wire Wire Line + 5900 2400 5900 1700 +$Comp +L PORT U1 +U 1 1 5C98EEE0 +P 3500 4500 +F 0 "U1" H 3550 4600 30 0000 C CNN +F 1 "PORT" H 3500 4500 30 0000 C CNN +F 2 "" H 3500 4500 60 0000 C CNN +F 3 "" H 3500 4500 60 0000 C CNN + 1 3500 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5C98EF2D +P 3950 4500 +F 0 "U1" H 4000 4600 30 0000 C CNN +F 1 "PORT" H 3950 4500 30 0000 C CNN +F 2 "" H 3950 4500 60 0000 C CNN +F 3 "" H 3950 4500 60 0000 C CNN + 2 3950 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5C98EF86 +P 4650 4500 +F 0 "U1" H 4700 4600 30 0000 C CNN +F 1 "PORT" H 4650 4500 30 0000 C CNN +F 2 "" H 4650 4500 60 0000 C CNN +F 3 "" H 4650 4500 60 0000 C CNN + 3 4650 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 5C98EFBD +P 5350 4500 +F 0 "U1" H 5400 4600 30 0000 C CNN +F 1 "PORT" H 5350 4500 30 0000 C CNN +F 2 "" H 5350 4500 60 0000 C CNN +F 3 "" H 5350 4500 60 0000 C CNN + 4 5350 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 5C98EFF0 +P 5700 4500 +F 0 "U1" H 5750 4600 30 0000 C CNN +F 1 "PORT" H 5700 4500 30 0000 C CNN +F 2 "" H 5700 4500 60 0000 C CNN +F 3 "" H 5700 4500 60 0000 C CNN + 5 5700 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 5C98F02D +P 6000 4500 +F 0 "U1" H 6050 4600 30 0000 C CNN +F 1 "PORT" H 6000 4500 30 0000 C CNN +F 2 "" H 6000 4500 60 0000 C CNN +F 3 "" H 6000 4500 60 0000 C CNN + 6 6000 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C98F05E +P 6450 4500 +F 0 "U1" H 6500 4600 30 0000 C CNN +F 1 "PORT" H 6450 4500 30 0000 C CNN +F 2 "" H 6450 4500 60 0000 C CNN +F 3 "" H 6450 4500 60 0000 C CNN + 7 6450 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C98F0C3 +P 6450 1450 +F 0 "U1" H 6500 1550 30 0000 C CNN +F 1 "PORT" H 6450 1450 30 0000 C CNN +F 2 "" H 6450 1450 60 0000 C CNN +F 3 "" H 6450 1450 60 0000 C CNN + 8 6450 1450 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5C9CD7BF +P 6050 4250 +F 0 "#FLG01" H 6050 4345 50 0001 C CNN +F 1 "PWR_FLAG" H 6050 4430 50 0000 C CNN +F 2 "" H 6050 4250 50 0000 C CNN +F 3 "" H 6050 4250 50 0000 C CNN + 1 6050 4250 + 0 1 1 0 +$EndComp +Wire Wire Line + 6000 4250 6050 4250 +Wire Wire Line + 5600 2450 5600 2400 +$Comp +L PORT U1 +U 9 1 5D0CBFBB +P 5900 1450 +F 0 "U1" H 5950 1550 30 0000 C CNN +F 1 "PORT" H 5900 1450 30 0000 C CNN +F 2 "" H 5900 1450 60 0000 C CNN +F 3 "" H 5900 1450 60 0000 C CNN + 9 5900 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5D0CC62F +P 5300 1450 +F 0 "U1" H 5350 1550 30 0000 C CNN +F 1 "PORT" H 5300 1450 30 0000 C CNN +F 2 "" H 5300 1450 60 0000 C CNN +F 3 "" H 5300 1450 60 0000 C CNN + 10 5300 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 5D0CC70E +P 4800 1450 +F 0 "U1" H 4850 1550 30 0000 C CNN +F 1 "PORT" H 4800 1450 30 0000 C CNN +F 2 "" H 4800 1450 60 0000 C CNN +F 3 "" H 4800 1450 60 0000 C CNN + 11 4800 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 5D0CC84E +P 4400 1450 +F 0 "U1" H 4450 1550 30 0000 C CNN +F 1 "PORT" H 4400 1450 30 0000 C CNN +F 2 "" H 4400 1450 60 0000 C CNN +F 3 "" H 4400 1450 60 0000 C CNN + 12 4400 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 5D0CC96F +P 3500 1450 +F 0 "U1" H 3550 1550 30 0000 C CNN +F 1 "PORT" H 3500 1450 30 0000 C CNN +F 2 "" H 3500 1450 60 0000 C CNN +F 3 "" H 3500 1450 60 0000 C CNN + 14 3500 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 5D0CC9BD +P 4100 1450 +F 0 "U1" H 4150 1550 30 0000 C CNN +F 1 "PORT" H 4100 1450 30 0000 C CNN +F 2 "" H 4100 1450 60 0000 C CNN +F 3 "" H 4100 1450 60 0000 C CNN + 13 4100 1450 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/LM3046/LM3046.sub b/src/SubcircuitLibrary/LM3046/LM3046.sub new file mode 100644 index 00000000..251364bb --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.sub @@ -0,0 +1,12 @@ +* Subcircuit LM3046 +.subckt LM3046 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q5-pad2_ net-_q5-pad3_ net-_q5-pad1_ net-_q4-pad2_ net-_q4-pad3_ net-_q4-pad1_ net-_q2-pad2_ net-_q2-pad3_ net-_q2-pad1_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm3046/lm3046.cir +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222 +* Control Statements + +.ends LM3046 \ No newline at end of file diff --git a/src/SubcircuitLibrary/LM3046/LM3046.xml b/src/SubcircuitLibrary/LM3046/LM3046.xml new file mode 100644 index 00000000..94884e43 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.xml @@ -0,0 +1,177 @@ +<?xml version="1.0" encoding="UTF-8"?> +<export version="D"> + <design> + <source>C:/esim_1/eSim/src/SubcircuitLibrary/LM3046/LM3046.sch</source> + <date>03/27/19 23:15:04</date> + <tool>Eeschema 4.0.2-stable</tool> + <sheet number="1" name="/" tstamps="/"> + <title_block> + <title/> + <company/> + <rev/> + <date/> + <source>LM3046.sch</source> + <comment number="1" value=""/> + <comment number="2" value=""/> + <comment number="3" value=""/> + <comment number="4" value=""/> + </title_block> + </sheet> + </design> + <components> + <comp ref="Q1"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98EC0E</tstamp> + </comp> + <comp ref="Q2"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98EC83</tstamp> + </comp> + <comp ref="Q4"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98ECC0</tstamp> + </comp> + <comp ref="Q5"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98ED6B</tstamp> + </comp> + <comp ref="Q3"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98EDA0</tstamp> + </comp> + <comp ref="U1"> + <value>PORT</value> + <libsource lib="eSim_Miscellaneous" part="PORT"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98EEE0</tstamp> + </comp> + </components> + <libparts> + <libpart lib="eSim_Miscellaneous" part="PORT"> + <fields> + <field name="Reference">U</field> + <field name="Value">PORT</field> + </fields> + <pins> + <pin num="1" name="~" type="BiDi"/> + <pin num="2" name="~" type="BiDi"/> + <pin num="3" name="~" type="BiDi"/> + <pin num="4" name="~" type="BiDi"/> + <pin num="5" name="~" type="BiDi"/> + <pin num="6" name="~" type="BiDi"/> + <pin num="7" name="~" type="BiDi"/> + <pin num="8" name="~" type="BiDi"/> + <pin num="9" name="~" type="BiDi"/> + <pin num="10" name="~" type="BiDi"/> + <pin num="11" name="~" type="BiDi"/> + <pin num="12" name="~" type="BiDi"/> + <pin num="13" name="~" type="BiDi"/> + <pin num="14" name="~" type="BiDi"/> + <pin num="15" name="~" type="BiDi"/> + <pin num="16" name="~" type="BiDi"/> + <pin num="17" name="~" type="BiDi"/> + <pin num="18" name="~" type="BiDi"/> + <pin num="19" name="~" type="BiDi"/> + <pin num="20" name="~" type="BiDi"/> + <pin num="21" name="~" type="BiDi"/> + <pin num="22" name="~" type="BiDi"/> + <pin num="23" name="~" type="BiDi"/> + <pin num="24" name="~" type="BiDi"/> + <pin num="25" name="~" type="BiDi"/> + <pin num="26" name="~" type="BiDi"/> + </pins> + </libpart> + <libpart lib="eSim_Devices" part="eSim_NPN"> + <aliases> + <alias>BC547</alias> + <alias>Q2N2222</alias> + </aliases> + <fields> + <field name="Reference">Q</field> + <field name="Value">eSim_NPN</field> + </fields> + <pins> + <pin num="1" name="C" type="openCol"/> + <pin num="2" name="B" type="input"/> + <pin num="3" name="E" type="openEm"/> + </pins> + </libpart> + </libparts> + <libraries> + <library logical="eSim_Miscellaneous"> + <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Miscellaneous.lib</uri> + </library> + <library logical="eSim_Devices"> + <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Devices.lib</uri> + </library> + </libraries> + <nets> + <net code="1" name="Net-(Q1-Pad1)"> + <node ref="Q1" pin="1"/> + <node ref="U1" pin="1"/> + </net> + <net code="2" name="Net-(Q2-Pad3)"> + <node ref="Q2" pin="3"/> + <node ref="U1" pin="13"/> + </net> + <net code="3" name="Net-(Q2-Pad1)"> + <node ref="Q2" pin="1"/> + <node ref="U1" pin="14"/> + </net> + <net code="4" name="Net-(Q2-Pad2)"> + <node ref="Q2" pin="2"/> + <node ref="U1" pin="12"/> + </net> + <net code="5" name="Net-(Q4-Pad3)"> + <node ref="Q4" pin="3"/> + <node ref="U1" pin="10"/> + </net> + <net code="6" name="Net-(Q4-Pad1)"> + <node ref="Q4" pin="1"/> + <node ref="U1" pin="11"/> + </net> + <net code="7" name="Net-(Q4-Pad2)"> + <node ref="Q4" pin="2"/> + <node ref="U1" pin="9"/> + </net> + <net code="8" name="Net-(Q1-Pad3)"> + <node ref="Q3" pin="3"/> + <node ref="Q1" pin="3"/> + <node ref="U1" pin="3"/> + </net> + <net code="9" name="Net-(Q3-Pad2)"> + <node ref="Q3" pin="2"/> + <node ref="U1" pin="4"/> + </net> + <net code="10" name="Net-(Q1-Pad2)"> + <node ref="Q1" pin="2"/> + <node ref="U1" pin="2"/> + </net> + <net code="11" name="Net-(Q5-Pad1)"> + <node ref="Q5" pin="1"/> + <node ref="U1" pin="8"/> + </net> + <net code="12" name="Net-(Q5-Pad2)"> + <node ref="U1" pin="6"/> + <node ref="Q5" pin="2"/> + </net> + <net code="13" name="Net-(Q5-Pad3)"> + <node ref="U1" pin="7"/> + <node ref="Q5" pin="3"/> + </net> + <net code="14" name="Net-(Q3-Pad1)"> + <node ref="U1" pin="5"/> + <node ref="Q3" pin="1"/> + </net> + </nets> +</export> diff --git a/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml b/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml new file mode 100644 index 00000000..0b34a8e5 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/LM3046/NPN.lib b/src/SubcircuitLibrary/LM3046/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/LM3046/analysis b/src/SubcircuitLibrary/LM3046/analysis new file mode 100644 index 00000000..d5e13546 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/LM565/LM565-cache.lib b/src/SubcircuitLibrary/LM565/LM565-cache.lib new file mode 100644 index 00000000..dd2449b9 --- /dev/null +++ b/src/SubcircuitLibrary/LM565/LM565-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 I +X ~ 2 250 0 100 L 30 30 2 1 I +X ~ 3 250 0 100 L 30 30 3 1 I +X ~ 4 250 0 100 L 30 30 4 1 I +X ~ 5 250 0 100 L 30 30 5 1 I +X ~ 6 250 0 100 L 30 30 6 1 I +X ~ 7 250 0 100 L 30 30 7 1 I +X ~ 8 250 0 100 L 30 30 8 1 I +X ~ 9 250 0 100 L 30 30 9 1 I +X ~ 10 250 0 100 L 30 30 10 1 I +X ~ 11 250 0 100 L 30 30 11 1 I +X ~ 12 250 0 100 L 30 30 12 1 I +X ~ 13 250 0 100 L 30 30 13 1 I +X ~ 14 250 0 100 L 30 30 14 1 I +X ~ 15 250 0 100 L 30 30 15 1 I +X ~ 16 250 0 100 L 30 30 16 1 I +X ~ 17 250 0 100 L 30 30 17 1 I +X ~ 18 250 0 100 L 30 30 18 1 I +X ~ 19 250 0 100 L 30 30 19 1 I +X ~ 20 250 0 100 L 30 30 20 1 I +X ~ 21 250 0 100 L 30 30 21 1 I +X ~ 22 250 0 100 L 30 30 22 1 I +X ~ 23 250 0 100 L 30 30 23 1 I +X ~ 24 250 0 100 L 30 30 24 1 I +X ~ 25 250 0 100 L 30 30 25 1 I +X ~ 26 250 0 100 L 30 30 26 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/LM565/LM565.cir b/src/SubcircuitLibrary/LM565/LM565.cir new file mode 100644 index 00000000..c1f63f94 --- /dev/null +++ b/src/SubcircuitLibrary/LM565/LM565.cir @@ -0,0 +1,78 @@ +* C:\esim_1\eSim\src\SubcircuitLibrary\LM565\LM565.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/31/19 18:47:10 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 +Vcc Net-_Q1-Pad1_ 7.2k +R3 +Vcc Net-_Q14-Pad2_ 7.2k +Q4 Net-_Q14-Pad2_ Net-_Q14-Pad2_ Net-_Q1-Pad1_ eSim_NPN +Q5 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q14-Pad2_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ +Vcc eSim_NPN +R4 +Vcc Net-_Q3-Pad2_ 5.7k +R6 +Vcc Reference_output 1.75k +R7 Reference_output Net-_Q1-Pad2_ 3.8k +Q12 +Vcc Net-_Q1-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q14 Vco_control_voltage Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R12 +Vcc Vco_control_voltage 3.6K +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q3 Net-_Q14-Pad2_ Net-_Q3-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q7 Net-_Q1-Pad1_ Net-_Q3-Pad2_ Net-_Q7-Pad3_ eSim_NPN +Q9 Net-_Q14-Pad2_ Net-_Q1-Pad2_ Net-_Q7-Pad3_ eSim_NPN +R5 Net-_Q3-Pad2_ -Vcc 13k +Q2 Net-_Q1-Pad3_ Input Net-_Q2-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Input Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q2-Pad3_ Net-_Q11-Pad1_ Net-_Q6-Pad3_ eSim_NPN +R2 Net-_Q6-Pad3_ -Vcc 200 +R8 Net-_Q1-Pad2_ Net-_Q11-Pad1_ 8.1K +R10 Net-_Q12-Pad3_ Net-_Q13-Pad1_ 1K +R13 Net-_Q14-Pad3_ Net-_Q13-Pad1_ 1K +Q13 Net-_Q13-Pad1_ Net-_Q11-Pad1_ Net-_Q13-Pad3_ eSim_NPN +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad1_ Net-_Q11-Pad3_ eSim_NPN +R9 Net-_Q11-Pad3_ -Vcc 200 +R11 Net-_Q13-Pad3_ -Vcc 205 +Q16 Timming_resistor Vco_control_voltage Net-_Q15-Pad2_ eSim_NPN +Q18 Net-_Q15-Pad2_ Net-_Q18-Pad2_ Net-_Q17-Pad1_ eSim_NPN +Q20 Net-_Q18-Pad2_ Net-_Q18-Pad2_ Net-_Q17-Pad1_ eSim_NPN +Q17 Net-_Q17-Pad1_ Net-_Q17-Pad1_ Net-_Q17-Pad3_ eSim_NPN +Q21 Timing_capacitor Timing_capacitor Net-_Q17-Pad1_ eSim_PNP +Q22 Timing_capacitor Net-_Q17-Pad3_ Net-_Q19-Pad2_ eSim_NPN +Q19 Net-_Q17-Pad3_ Net-_Q19-Pad2_ Net-_Q19-Pad3_ eSim_NPN +Q23 Net-_Q19-Pad2_ Net-_Q19-Pad2_ Net-_Q23-Pad3_ eSim_NPN +R14 Net-_Q19-Pad3_ Net-_Q24-Pad1_ 530 +R15 Net-_Q23-Pad3_ Net-_Q24-Pad1_ 530 +Q25 +Vcc Timing_capacitor Net-_Q25-Pad3_ eSim_NPN +R17 +Vcc Net-_Q28-Pad1_ 6.5K +Q28 Net-_Q28-Pad1_ Net-_Q28-Pad1_ Net-_Q25-Pad3_ eSim_PNP +Q27 ? Net-_Q25-Pad3_ Net-_Q27-Pad3_ eSim_NPN +Q30 Net-_Q28-Pad1_ Net-_Q27-Pad3_ Net-_Q30-Pad3_ eSim_NPN +Q31 ? Net-_Q28-Pad1_ Net-_Q31-Pad3_ eSim_NPN +Q32 Net-_Q32-Pad1_ Net-_Q32-Pad1_ Net-_Q28-Pad1_ eSim_PNP +R19 +Vcc Net-_Q32-Pad1_ 4.7k +Q33 Net-_Q32-Pad1_ Net-_Q31-Pad3_ Net-_Q30-Pad3_ eSim_NPN +R18 Net-_Q31-Pad3_ Net-_Q30-Pad3_ 8.4K +Q35 +Vcc Net-_Q32-Pad1_ Vco_output eSim_NPN +R20 Net-_Q30-Pad3_ -Vcc 2.6K +R22 Vco_output -Vcc 4.8K +Q24 Net-_Q24-Pad1_ Net-_Q24-Pad2_ -Vcc eSim_NPN +Q26 Net-_Q24-Pad1_ Net-_Q24-Pad1_ Net-_Q26-Pad3_ eSim_PNP +R16 Net-_Q24-Pad2_ -Vcc 7K +Q29 Net-_Q26-Pad3_ Net-_Q26-Pad3_ Net-_Q24-Pad2_ eSim_NPN +Q34 Net-_Q25-Pad3_ Net-_Q11-Pad1_ Net-_Q34-Pad3_ eSim_NPN +R21 Net-_Q34-Pad3_ -Vcc 2.4K +Q36 -Vcc Vco_output Net-_Q36-Pad3_ eSim_PNP +Q38 Net-_Q37-Pad2_ Net-_Q38-Pad2_ Net-_Q36-Pad3_ eSim_PNP +R23 +Vcc Net-_Q36-Pad3_ 16K +R24 Net-_Q37-Pad2_ Net-_Q26-Pad3_ 5.8k +Q37 Net-_Q36-Pad3_ Net-_Q37-Pad2_ Net-_Q26-Pad3_ eSim_NPN +Q40 Net-_Q38-Pad2_ Net-_Q11-Pad1_ Net-_Q40-Pad3_ eSim_NPN +R26 Net-_Q40-Pad3_ -Vcc 200 +R25 +Vcc Net-_Q38-Pad2_ 4.3k +Q39 ? Net-_Q38-Pad2_ +Vcc eSim_NPN +U1 -Vcc Input Input Vco_output +Vcc Reference_output Vco_control_voltage Timming_resistor Timing_capacitor +Vcc PORT +Q15 ? Net-_Q15-Pad2_ Vco_control_voltage eSim_NPN +Q41 Net-_Q18-Pad2_ Net-_Q15-Pad2_ Timming_resistor eSim_PNP + +.end diff --git a/src/SubcircuitLibrary/LM565/LM565.cir.out b/src/SubcircuitLibrary/LM565/LM565.cir.out new file mode 100644 index 00000000..e39ed5f4 --- /dev/null +++ b/src/SubcircuitLibrary/LM565/LM565.cir.out @@ -0,0 +1,81 @@ +* c:\esim_1\esim\src\subcircuitlibrary\lm565\lm565.cir + +.include PNP.lib +.include NPN.lib +r1 +vcc net-_q1-pad1_ 7.2k +r3 +vcc net-_q14-pad2_ 7.2k +q4 net-_q14-pad2_ net-_q14-pad2_ net-_q1-pad1_ Q2N2222 +q5 net-_q1-pad1_ net-_q1-pad1_ net-_q14-pad2_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad1_ +vcc Q2N2222 +r4 +vcc net-_q3-pad2_ 5.7k +r6 +vcc reference_output 1.75k +r7 reference_output net-_q1-pad2_ 3.8k +q12 +vcc net-_q1-pad1_ net-_q12-pad3_ Q2N2222 +q14 vco_control_voltage net-_q14-pad2_ net-_q14-pad3_ Q2N2222 +r12 +vcc vco_control_voltage 3.6k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q3 net-_q14-pad2_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222 +q7 net-_q1-pad1_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222 +q9 net-_q14-pad2_ net-_q1-pad2_ net-_q7-pad3_ Q2N2222 +r5 net-_q3-pad2_ -vcc 13k +q2 net-_q1-pad3_ input net-_q2-pad3_ Q2N2222 +q8 net-_q7-pad3_ input net-_q2-pad3_ Q2N2222 +q6 net-_q2-pad3_ net-_q11-pad1_ net-_q6-pad3_ Q2N2222 +r2 net-_q6-pad3_ -vcc 200 +r8 net-_q1-pad2_ net-_q11-pad1_ 8.1k +r10 net-_q12-pad3_ net-_q13-pad1_ 1k +r13 net-_q14-pad3_ net-_q13-pad1_ 1k +q13 net-_q13-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222 +q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2222 +r9 net-_q11-pad3_ -vcc 200 +r11 net-_q13-pad3_ -vcc 205 +q16 timming_resistor vco_control_voltage net-_q15-pad2_ Q2N2222 +q18 net-_q15-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222 +q20 net-_q18-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222 +q17 net-_q17-pad1_ net-_q17-pad1_ net-_q17-pad3_ Q2N2222 +q21 timing_capacitor timing_capacitor net-_q17-pad1_ Q2N2907A +q22 timing_capacitor net-_q17-pad3_ net-_q19-pad2_ Q2N2222 +q19 net-_q17-pad3_ net-_q19-pad2_ net-_q19-pad3_ Q2N2222 +q23 net-_q19-pad2_ net-_q19-pad2_ net-_q23-pad3_ Q2N2222 +r14 net-_q19-pad3_ net-_q24-pad1_ 530 +r15 net-_q23-pad3_ net-_q24-pad1_ 530 +q25 +vcc timing_capacitor net-_q25-pad3_ Q2N2222 +r17 +vcc net-_q28-pad1_ 6.5k +q28 net-_q28-pad1_ net-_q28-pad1_ net-_q25-pad3_ Q2N2907A +q27 ? net-_q25-pad3_ net-_q27-pad3_ Q2N2222 +q30 net-_q28-pad1_ net-_q27-pad3_ net-_q30-pad3_ Q2N2222 +q31 ? net-_q28-pad1_ net-_q31-pad3_ Q2N2222 +q32 net-_q32-pad1_ net-_q32-pad1_ net-_q28-pad1_ Q2N2907A +r19 +vcc net-_q32-pad1_ 4.7k +q33 net-_q32-pad1_ net-_q31-pad3_ net-_q30-pad3_ Q2N2222 +r18 net-_q31-pad3_ net-_q30-pad3_ 8.4k +q35 +vcc net-_q32-pad1_ vco_output Q2N2222 +r20 net-_q30-pad3_ -vcc 2.6k +r22 vco_output -vcc 4.8k +q24 net-_q24-pad1_ net-_q24-pad2_ -vcc Q2N2222 +q26 net-_q24-pad1_ net-_q24-pad1_ net-_q26-pad3_ Q2N2907A +r16 net-_q24-pad2_ -vcc 7k +q29 net-_q26-pad3_ net-_q26-pad3_ net-_q24-pad2_ Q2N2222 +q34 net-_q25-pad3_ net-_q11-pad1_ net-_q34-pad3_ Q2N2222 +r21 net-_q34-pad3_ -vcc 2.4k +q36 -vcc vco_output net-_q36-pad3_ Q2N2907A +q38 net-_q37-pad2_ net-_q38-pad2_ net-_q36-pad3_ Q2N2907A +r23 +vcc net-_q36-pad3_ 16k +r24 net-_q37-pad2_ net-_q26-pad3_ 5.8k +q37 net-_q36-pad3_ net-_q37-pad2_ net-_q26-pad3_ Q2N2222 +q40 net-_q38-pad2_ net-_q11-pad1_ net-_q40-pad3_ Q2N2222 +r26 net-_q40-pad3_ -vcc 200 +r25 +vcc net-_q38-pad2_ 4.3k +q39 ? net-_q38-pad2_ +vcc Q2N2222 +* u1 -vcc input input vco_output +vcc reference_output vco_control_voltage timming_resistor timing_capacitor +vcc port +q15 ? net-_q15-pad2_ vco_control_voltage Q2N2222 +q41 net-_q18-pad2_ net-_q15-pad2_ timming_resistor Q2N2907A +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/LM565/LM565.pro b/src/SubcircuitLibrary/LM565/LM565.pro new file mode 100644 index 00000000..94072b3e --- /dev/null +++ b/src/SubcircuitLibrary/LM565/LM565.pro @@ -0,0 +1,83 @@ +update=03/31/19 19:39:59 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../../../Program Files (x86)/KiCad/share/library +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Plot +LibName36=eSim_Power +LibName37=eSim_PSpice +LibName38=eSim_Sources +LibName39=eSim_Subckt +LibName40=eSim_User +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/src/SubcircuitLibrary/LM565/LM565.sch b/src/SubcircuitLibrary/LM565/LM565.sch new file mode 100644 index 00000000..9f5ad21c --- /dev/null +++ b/src/SubcircuitLibrary/LM565/LM565.sch @@ -0,0 +1,1365 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:LM565-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R1 +U 1 1 5C9D9F95 +P 850 975 +F 0 "R1" H 900 1105 50 0000 C CNN +F 1 "7.2k" H 900 1025 50 0000 C CNN +F 2 "" H 900 955 30 0000 C CNN +F 3 "" V 900 1025 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+F 3 "" H 5150 4825 60 0000 C CNN + 1 5150 4825 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4950 4825 4925 4825 +Wire Wire Line + 5250 3925 5250 4625 +Wire Wire Line + 5250 4275 4925 4275 +Wire Wire Line + 4925 4275 4925 4825 +Connection ~ 5250 4275 +$Comp +L eSim_R R14 +U 1 1 5C9E1F6D +P 4575 5350 +F 0 "R14" H 4625 5480 50 0000 C CNN +F 1 "530" H 4625 5400 50 0000 C CNN +F 2 "" H 4625 5330 30 0000 C CNN +F 3 "" V 4625 5400 30 0000 C CNN + 1 4575 5350 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R15 +U 1 1 5C9E219A +P 5200 5350 +F 0 "R15" H 5250 5480 50 0000 C CNN +F 1 "530" H 5250 5400 50 0000 C CNN +F 2 "" H 5250 5330 30 0000 C CNN +F 3 "" V 5250 5400 30 0000 C CNN + 1 5200 5350 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q25 +U 1 1 5C9E2EDE +P 6050 1400 +F 0 "Q25" H 5950 1450 50 0000 R CNN +F 1 "eSim_NPN" H 6000 1550 50 0000 R CNN +F 2 "" H 6250 1500 29 0000 C CNN +F 3 "" H 6050 1400 60 0000 C CNN + 1 6050 1400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1400 5575 1400 +Connection ~ 5575 1400 +$Comp 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"Q30" H 6650 2800 50 0000 R CNN +F 1 "eSim_NPN" H 6700 2900 50 0000 R CNN +F 2 "" H 6950 2850 29 0000 C CNN +F 3 "" H 6750 2750 60 0000 C CNN + 1 6750 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6550 2750 6450 2750 +Wire Wire Line + 6450 2750 6450 2700 +Connection ~ 6150 1775 +$Comp +L eSim_NPN Q31 +U 1 1 5C9E49F3 +P 7075 2350 +F 0 "Q31" H 6975 2400 50 0000 R CNN +F 1 "eSim_NPN" H 7025 2500 50 0000 R CNN +F 2 "" H 7275 2450 29 0000 C CNN +F 3 "" H 7075 2350 60 0000 C CNN + 1 7075 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q32 +U 1 1 5C9E4B46 +P 7125 1875 +F 0 "Q32" H 7025 1925 50 0000 R CNN +F 1 "eSim_PNP" H 7075 2025 50 0000 R CNN +F 2 "" H 7325 1975 29 0000 C CNN +F 3 "" H 7125 1875 60 0000 C CNN + 1 7125 1875 + 0 1 -1 0 +$EndComp +Wire Wire Line + 6850 1550 6850 2550 +Wire Wire Line + 6725 1775 6925 1775 +Connection ~ 6850 1775 +$Comp +L eSim_R R19 +U 1 1 5C9E5284 +P 7400 1225 +F 0 "R19" H 7450 1355 50 0000 C CNN +F 1 "4.7k" H 7450 1275 50 0000 C CNN +F 2 "" H 7450 1205 30 0000 C CNN +F 3 "" V 7450 1275 30 0000 C CNN + 1 7400 1225 + 0 1 1 0 +$EndComp +Wire Wire Line + 7450 1425 7450 2350 +Wire Wire Line + 7325 1775 7625 1775 +Wire Wire Line + 7450 2075 7125 2075 +Connection ~ 7450 1775 +$Comp +L eSim_NPN Q33 +U 1 1 5C9E59CA +P 7375 2725 +F 0 "Q33" H 7275 2775 50 0000 R CNN +F 1 "eSim_NPN" H 7325 2875 50 0000 R CNN +F 2 "" H 7575 2825 29 0000 C CNN +F 3 "" H 7375 2725 60 0000 C CNN + 1 7375 2725 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7450 2350 7475 2350 +Wire Wire Line + 7475 2350 7475 2525 +Connection ~ 7450 2075 +Wire Wire Line + 7175 2550 7175 3000 +$Comp +L eSim_R R18 +U 1 1 5C9E62BC +P 7125 3100 +F 0 "R18" H 7175 3230 50 0000 C CNN +F 1 "8.4K" H 7175 3150 50 0000 C CNN +F 2 "" H 7175 3080 30 0000 C CNN +F 3 "" V 7175 3150 30 0000 C CNN + 1 7125 3100 + 0 1 1 0 +$EndComp +Connection ~ 7175 2725 +Wire Wire Line + 6850 2950 6850 3300 +Wire Wire Line + 6850 3300 7475 3300 +Wire Wire Line + 7475 2925 7475 3600 +Connection ~ 7175 3300 +Wire Wire Line + 7450 875 7450 1125 +$Comp +L eSim_NPN Q35 +U 1 1 5C9E6F03 +P 7825 1775 +F 0 "Q35" H 7725 1825 50 0000 R CNN +F 1 "eSim_NPN" H 7775 1925 50 0000 R CNN +F 2 "" H 8025 1875 29 0000 C CNN +F 3 "" H 7825 1775 60 0000 C CNN + 1 7825 1775 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7925 875 7925 1575 +Connection ~ 7450 875 +$Comp +L eSim_R R20 +U 1 1 5C9E7FB4 +P 7425 3700 +F 0 "R20" H 7475 3830 50 0000 C CNN +F 1 "2.6K" H 7475 3750 50 0000 C CNN +F 2 "" H 7475 3680 30 0000 C CNN +F 3 "" V 7475 3750 30 0000 C CNN + 1 7425 3700 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R22 +U 1 1 5C9E803D +P 7875 3675 +F 0 "R22" H 7925 3805 50 0000 C CNN +F 1 "4.8K" H 7925 3725 50 0000 C CNN +F 2 "" H 7925 3655 30 0000 C CNN +F 3 "" V 7925 3725 30 0000 C CNN + 1 7875 3675 + 0 1 1 0 +$EndComp +Wire Wire Line + 7925 1975 7925 3575 +Connection ~ 7475 3300 +$Comp +L eSim_NPN Q24 +U 1 1 5C9E8FD5 +P 5650 5800 +F 0 "Q24" H 5550 5850 50 0000 R CNN +F 1 "eSim_NPN" H 5600 5950 50 0000 R CNN +F 2 "" H 5850 5900 29 0000 C CNN +F 3 "" H 5650 5800 60 0000 C CNN + 1 5650 5800 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5250 5025 5250 5250 +Wire Wire Line + 4625 5025 4625 5250 +Wire Wire Line + 5250 5550 5250 5650 +Wire Wire Line + 5250 5650 4625 5650 +Wire Wire Line + 4625 5650 4625 5550 +Connection ~ 3550 6000 +Wire Wire Line + 5550 5600 5250 5600 +Connection ~ 5250 5600 +$Comp +L eSim_PNP Q26 +U 1 1 5C9EA5DE +P 6150 4925 +F 0 "Q26" H 6050 4975 50 0000 R CNN +F 1 "eSim_PNP" H 6100 5075 50 0000 R CNN +F 2 "" H 6350 5025 29 0000 C CNN +F 3 "" H 6150 4925 60 0000 C CNN + 1 6150 4925 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5950 4825 5550 4825 +Wire Wire Line + 5550 4825 5550 5600 +Wire Wire Line + 6150 5125 6150 5250 +Wire Wire Line + 6150 5250 5550 5250 +Connection ~ 5550 5250 +$Comp +L eSim_R R16 +U 1 1 5C9EA881 +P 6100 5800 +F 0 "R16" H 6150 5930 50 0000 C CNN +F 1 "7K" H 6150 5850 50 0000 C CNN +F 2 "" H 6150 5780 30 0000 C CNN +F 3 "" V 6150 5850 30 0000 C CNN + 1 6100 5800 + 0 1 1 0 +$EndComp +Connection ~ 5550 6000 +Wire Wire Line + 5850 5800 5850 5575 +Wire Wire Line + 5850 5575 6150 5575 +Wire Wire Line + 6150 5575 6150 5700 +$Comp +L eSim_NPN Q29 +U 1 1 5C9EAB2D +P 6725 5400 +F 0 "Q29" H 6625 5450 50 0000 R CNN +F 1 "eSim_NPN" H 6675 5550 50 0000 R CNN +F 2 "" H 6925 5500 29 0000 C CNN +F 3 "" H 6725 5400 60 0000 C CNN + 1 6725 5400 + -1 0 0 -1 +$EndComp +Wire Wire Line + 6625 5600 6150 5600 +Connection ~ 6150 5600 +Wire Wire Line + 6625 5200 6625 4825 +Wire Wire Line + 6350 4825 9075 4825 +Wire Wire Line + 6925 5400 7000 5400 +Wire Wire Line + 7000 5400 7000 4825 +Connection ~ 6625 4825 +$Comp +L eSim_NPN Q34 +U 1 1 5C9EB3F8 +P 7625 5075 +F 0 "Q34" H 7525 5125 50 0000 R CNN +F 1 "eSim_NPN" H 7575 5225 50 0000 R CNN +F 2 "" H 7825 5175 29 0000 C CNN +F 3 "" H 7625 5075 60 0000 C CNN + 1 7625 5075 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R21 +U 1 1 5C9EB4C7 +P 7475 5750 +F 0 "R21" H 7525 5880 50 0000 C CNN +F 1 "2.4K" H 7525 5800 50 0000 C CNN +F 2 "" H 7525 5730 30 0000 C CNN +F 3 "" V 7525 5800 30 0000 C CNN + 1 7475 5750 + 0 1 1 0 +$EndComp +Wire Wire Line + 7525 5275 7525 5650 +Wire Wire Line + 7525 6000 7525 5950 +Connection ~ 6150 6000 +Wire Wire Line + 7525 4875 7525 4625 +Wire Wire Line + 7525 4625 6150 4625 +Connection ~ 6150 2500 +NoConn ~ 6450 2300 +NoConn ~ 7175 2150 +Wire Wire Line + 7475 3900 7475 4425 +Wire Wire Line + 7475 4425 7875 4425 +Wire Wire Line + 7875 4425 7875 6000 +Connection ~ 7525 6000 +Wire Wire Line + 7925 6000 7925 3875 +Connection ~ 7875 6000 +$Comp +L eSim_PNP Q36 +U 1 1 5C9EEDA4 +P 8475 2300 +F 0 "Q36" H 8375 2350 50 0000 R CNN +F 1 "eSim_PNP" H 8425 2450 50 0000 R CNN +F 2 "" H 8675 2400 29 0000 C CNN +F 3 "" H 8475 2300 60 0000 C CNN + 1 8475 2300 + 1 0 0 1 +$EndComp +Wire Wire Line + 7925 2300 8275 2300 +Connection ~ 7925 2300 +Wire Wire Line + 8575 2500 8575 6275 +Connection ~ 7925 6000 +$Comp +L eSim_PNP Q38 +U 1 1 5C9F04CE +P 9175 2300 +F 0 "Q38" H 9075 2350 50 0000 R CNN +F 1 "eSim_PNP" H 9125 2450 50 0000 R CNN +F 2 "" H 9375 2400 29 0000 C CNN +F 3 "" H 9175 2300 60 0000 C CNN + 1 9175 2300 + -1 0 0 1 +$EndComp +Wire Wire Line + 8575 2100 9075 2100 +$Comp +L eSim_R R23 +U 1 1 5C9F0909 +P 8800 1275 +F 0 "R23" H 8850 1405 50 0000 C CNN +F 1 "16K" H 8850 1325 50 0000 C CNN +F 2 "" H 8850 1255 30 0000 C CNN +F 3 "" V 8850 1325 30 0000 C CNN + 1 8800 1275 + 0 1 1 0 +$EndComp +Wire Wire Line + 8850 1475 8850 2625 +Connection ~ 8850 2100 +Wire Wire Line + 8850 875 8850 1175 +Connection ~ 7925 875 +Wire Wire Line + 8175 2300 8175 800 +Connection ~ 8175 2300 +$Comp +L eSim_R R24 +U 1 1 5C9F1F80 +P 9025 3775 +F 0 "R24" H 9075 3905 50 0000 C CNN +F 1 "5.8k" H 9075 3825 50 0000 C CNN +F 2 "" H 9075 3755 30 0000 C CNN +F 3 "" V 9075 3825 30 0000 C CNN + 1 9025 3775 + 0 1 1 0 +$EndComp +Wire Wire Line + 9075 2500 9075 3675 +Connection ~ 8575 6000 +$Comp +L eSim_NPN Q37 +U 1 1 5C9F3715 +P 8850 3025 +F 0 "Q37" H 8750 3075 50 0000 R CNN +F 1 "eSim_NPN" H 8800 3175 50 0000 R CNN +F 2 "" H 9050 3125 29 0000 C CNN +F 3 "" H 8850 3025 60 0000 C CNN + 1 8850 3025 + -1 0 0 -1 +$EndComp +Wire Wire Line + 8750 2825 8750 2625 +Wire Wire Line + 8750 2625 8850 2625 +Wire Wire Line + 9075 3025 9050 3025 +Connection ~ 9075 3025 +Wire Wire Line + 9075 4825 9075 3975 +Connection ~ 7000 4825 +Wire Wire Line + 8750 3225 8750 4825 +Connection ~ 8750 4825 +$Comp +L eSim_NPN Q40 +U 1 1 5C9F5A03 +P 9475 5100 +F 0 "Q40" H 9375 5150 50 0000 R CNN +F 1 "eSim_NPN" H 9425 5250 50 0000 R CNN +F 2 "" H 9675 5200 29 0000 C CNN +F 3 "" H 9475 5100 60 0000 C CNN + 1 9475 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7825 5100 9275 5100 +Wire Wire Line + 7825 5100 7825 5075 +$Comp +L eSim_R R26 +U 1 1 5C9F5D68 +P 9525 5600 +F 0 "R26" H 9575 5730 50 0000 C CNN +F 1 "200" H 9575 5650 50 0000 C CNN +F 2 "" H 9575 5580 30 0000 C CNN +F 3 "" V 9575 5650 30 0000 C CNN + 1 9525 5600 + 0 1 1 0 +$EndComp +Wire Wire Line + 9575 5300 9575 5500 +Wire Wire Line + 9575 6000 9575 5800 +Wire Wire Line + 9575 1300 9575 4900 +Wire Wire Line + 9575 2300 9375 2300 +$Comp +L eSim_R R25 +U 1 1 5C9F78A7 +P 9525 1100 +F 0 "R25" H 9575 1230 50 0000 C CNN +F 1 "4.3k" H 9575 1150 50 0000 C CNN +F 2 "" H 9575 1080 30 0000 C CNN +F 3 "" V 9575 1150 30 0000 C CNN + 1 9525 1100 + 0 1 1 0 +$EndComp +Wire Wire Line + 9575 875 9575 1000 +Connection ~ 8850 875 +Connection ~ 9575 2300 +$Comp +L eSim_NPN Q39 +U 1 1 5C9F7E6C +P 9300 1325 +F 0 "Q39" H 9200 1375 50 0000 R CNN +F 1 "eSim_NPN" H 9250 1475 50 0000 R CNN +F 2 "" H 9500 1425 29 0000 C CNN +F 3 "" H 9300 1325 60 0000 C CNN + 1 9300 1325 + -1 0 0 1 +$EndComp +Wire Wire Line + 9200 1125 9200 875 +Connection ~ 9200 875 +Wire Wire Line + 9500 1325 9575 1325 +Connection ~ 9575 1325 +NoConn ~ 9200 1525 +Wire Wire Line + 8375 5100 8375 6275 +Wire Wire Line + 8375 6275 1975 6275 +Wire Wire Line + 1975 6275 1975 4850 +Connection ~ 1975 4850 +Connection ~ 8375 5100 +$Comp +L PORT U1 +U 1 1 5C9FA174 +P 8575 6525 +F 0 "U1" H 8625 6625 30 0000 C CNN +F 1 "PORT" H 8575 6525 30 0000 C CNN +F 2 "" H 8575 6525 60 0000 C CNN +F 3 "" H 8575 6525 60 0000 C CNN + 1 8575 6525 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9FBFA4 +P 475 3950 +F 0 "U1" H 525 4050 30 0000 C CNN +F 1 "PORT" H 475 3950 30 0000 C CNN +F 2 "" H 475 3950 60 0000 C CNN +F 3 "" H 475 3950 60 0000 C CNN + 3 475 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9FC1B0 +P 600 4425 +F 0 "U1" H 650 4525 30 0000 C CNN +F 1 "PORT" H 600 4425 30 0000 C CNN +F 2 "" H 600 4425 60 0000 C CNN +F 3 "" H 600 4425 60 0000 C CNN + 2 600 4425 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2150 4425 850 4425 +$Comp +L PORT U1 +U 5 1 5C9FD8AC +P 2225 525 +F 0 "U1" H 2275 625 30 0000 C CNN +F 1 "PORT" H 2225 525 30 0000 C CNN +F 2 "" H 2225 525 60 0000 C CNN +F 3 "" H 2225 525 60 0000 C CNN + 5 2225 525 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9FD96B +P 2725 525 +F 0 "U1" H 2775 625 30 0000 C CNN +F 1 "PORT" H 2725 525 30 0000 C CNN +F 2 "" H 2725 525 60 0000 C CNN +F 3 "" H 2725 525 60 0000 C CNN + 6 2725 525 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C9FDA44 +P 3950 550 +F 0 "U1" H 4000 650 30 0000 C CNN +F 1 "PORT" H 3950 550 30 0000 C CNN +F 2 "" H 3950 550 60 0000 C CNN +F 3 "" H 3950 550 60 0000 C CNN + 7 3950 550 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C9FDAFF +P 4900 550 +F 0 "U1" H 4950 650 30 0000 C CNN +F 1 "PORT" H 4900 550 30 0000 C CNN +F 2 "" H 4900 550 60 0000 C CNN +F 3 "" H 4900 550 60 0000 C CNN + 8 4900 550 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 5C9FDBB4 +P 5575 550 +F 0 "U1" H 5625 650 30 0000 C CNN +F 1 "PORT" H 5575 550 30 0000 C CNN +F 2 "" H 5575 550 60 0000 C CNN +F 3 "" H 5575 550 60 0000 C CNN + 9 5575 550 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5C9FDC77 +P 6850 550 +F 0 "U1" H 6900 650 30 0000 C CNN +F 1 "PORT" H 6850 550 30 0000 C CNN +F 2 "" H 6850 550 60 0000 C CNN +F 3 "" H 6850 550 60 0000 C CNN + 10 6850 550 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9FE0D8 +P 8175 550 +F 0 "U1" H 8225 650 30 0000 C CNN +F 1 "PORT" H 8175 550 30 0000 C CNN +F 2 "" H 8175 550 60 0000 C CNN +F 3 "" H 8175 550 60 0000 C CNN + 4 8175 550 + 0 1 1 0 +$EndComp +Text GLabel 2125 775 0 60 Input ~ 0 +Phase_comparator_vco_input +Wire Wire Line + 2225 775 2125 775 +Text GLabel 2775 775 2 60 Input ~ 0 +Reference_output +Wire Wire Line + 2725 775 2775 775 +Text GLabel 3975 800 2 55 Input ~ 0 +Vco_control_voltage +Wire Wire Line + 3975 800 3950 800 +Text GLabel 4900 800 2 39 Input ~ 0 +Timming_resistor +Text GLabel 5575 800 2 39 Input ~ 0 +Timing_capacitor +Text GLabel 6850 800 0 39 Input ~ 0 ++Vcc +Text GLabel 8175 800 0 39 Input ~ 0 +Vco_output +Text GLabel 8575 6275 2 39 Input ~ 0 +-Vcc +Text GLabel 675 4075 0 39 Input ~ 0 +Input +Wire Wire Line + 675 4075 725 4075 +Wire Wire Line + 725 4075 725 3950 +Text GLabel 850 4250 0 39 Input ~ 0 +Input +Wire Wire Line + 850 4250 875 4250 +Wire Wire Line + 875 4250 875 4425 +Connection ~ 875 4425 +Wire Wire Line + 6525 2350 6525 2075 +Wire Wire Line + 6525 2350 6875 2350 +Connection ~ 6850 2350 +$Comp +L eSim_NPN Q15 +U 1 1 5CA0DF1A +P 4300 1350 +F 0 "Q15" H 4200 1400 50 0000 R CNN +F 1 "eSim_NPN" H 4250 1500 50 0000 R CNN +F 2 "" H 4500 1450 29 0000 C CNN +F 3 "" H 4300 1350 60 0000 C CNN + 1 4300 1350 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q41 +U 1 1 5CA0E6BE +P 5150 1350 +F 0 "Q41" H 5050 1400 50 0000 R CNN +F 1 "eSim_PNP" H 5100 1500 50 0000 R CNN +F 2 "" H 5350 1450 29 0000 C CNN +F 3 "" H 5150 1350 60 0000 C CNN + 1 5150 1350 + 1 0 0 1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5CA131E0 +P 2300 3950 +F 0 "#FLG01" H 2300 4045 50 0001 C CNN +F 1 "PWR_FLAG" H 2300 4130 50 0000 C CNN +F 2 "" H 2300 3950 50 0000 C CNN +F 3 "" H 2300 3950 50 0000 C CNN + 1 2300 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2150 3950 2300 3950 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/LM565/LM565.sub b/src/SubcircuitLibrary/LM565/LM565.sub new file mode 100644 index 00000000..31747d1e --- /dev/null +++ b/src/SubcircuitLibrary/LM565/LM565.sub @@ -0,0 +1,75 @@ +* Subcircuit LM565 +.subckt LM565 -vcc input input vco_output +vcc reference_output vco_control_voltage timming_resistor timing_capacitor +vcc +* c:\esim_1\esim\src\subcircuitlibrary\lm565\lm565.cir +.include PNP.lib +.include NPN.lib +r1 +vcc net-_q1-pad1_ 7.2k +r3 +vcc net-_q14-pad2_ 7.2k +q4 net-_q14-pad2_ net-_q14-pad2_ net-_q1-pad1_ Q2N2222 +q5 net-_q1-pad1_ net-_q1-pad1_ net-_q14-pad2_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad1_ +vcc Q2N2222 +r4 +vcc net-_q3-pad2_ 5.7k +r6 +vcc reference_output 1.75k +r7 reference_output net-_q1-pad2_ 3.8k +q12 +vcc net-_q1-pad1_ net-_q12-pad3_ Q2N2222 +q14 vco_control_voltage net-_q14-pad2_ net-_q14-pad3_ Q2N2222 +r12 +vcc vco_control_voltage 3.6k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q3 net-_q14-pad2_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222 +q7 net-_q1-pad1_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222 +q9 net-_q14-pad2_ net-_q1-pad2_ net-_q7-pad3_ Q2N2222 +r5 net-_q3-pad2_ -vcc 13k +q2 net-_q1-pad3_ input net-_q2-pad3_ Q2N2222 +q8 net-_q7-pad3_ input net-_q2-pad3_ Q2N2222 +q6 net-_q2-pad3_ net-_q11-pad1_ net-_q6-pad3_ Q2N2222 +r2 net-_q6-pad3_ -vcc 200 +r8 net-_q1-pad2_ net-_q11-pad1_ 8.1k +r10 net-_q12-pad3_ net-_q13-pad1_ 1k +r13 net-_q14-pad3_ net-_q13-pad1_ 1k +q13 net-_q13-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222 +q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2222 +r9 net-_q11-pad3_ -vcc 200 +r11 net-_q13-pad3_ -vcc 205 +q16 timming_resistor vco_control_voltage net-_q15-pad2_ Q2N2222 +q18 net-_q15-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222 +q20 net-_q18-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222 +q17 net-_q17-pad1_ net-_q17-pad1_ net-_q17-pad3_ Q2N2222 +q21 timing_capacitor timing_capacitor net-_q17-pad1_ Q2N2907A +q22 timing_capacitor net-_q17-pad3_ net-_q19-pad2_ Q2N2222 +q19 net-_q17-pad3_ net-_q19-pad2_ net-_q19-pad3_ Q2N2222 +q23 net-_q19-pad2_ net-_q19-pad2_ net-_q23-pad3_ Q2N2222 +r14 net-_q19-pad3_ net-_q24-pad1_ 530 +r15 net-_q23-pad3_ net-_q24-pad1_ 530 +q25 +vcc timing_capacitor net-_q25-pad3_ Q2N2222 +r17 +vcc net-_q28-pad1_ 6.5k +q28 net-_q28-pad1_ net-_q28-pad1_ net-_q25-pad3_ Q2N2907A +q27 ? net-_q25-pad3_ net-_q27-pad3_ Q2N2222 +q30 net-_q28-pad1_ net-_q27-pad3_ net-_q30-pad3_ Q2N2222 +q31 ? net-_q28-pad1_ net-_q31-pad3_ Q2N2222 +q32 net-_q32-pad1_ net-_q32-pad1_ net-_q28-pad1_ Q2N2907A +r19 +vcc net-_q32-pad1_ 4.7k +q33 net-_q32-pad1_ net-_q31-pad3_ net-_q30-pad3_ Q2N2222 +r18 net-_q31-pad3_ net-_q30-pad3_ 8.4k +q35 +vcc net-_q32-pad1_ vco_output Q2N2222 +r20 net-_q30-pad3_ -vcc 2.6k +r22 vco_output -vcc 4.8k +q24 net-_q24-pad1_ net-_q24-pad2_ -vcc Q2N2222 +q26 net-_q24-pad1_ net-_q24-pad1_ net-_q26-pad3_ Q2N2907A +r16 net-_q24-pad2_ -vcc 7k +q29 net-_q26-pad3_ net-_q26-pad3_ net-_q24-pad2_ Q2N2222 +q34 net-_q25-pad3_ net-_q11-pad1_ net-_q34-pad3_ Q2N2222 +r21 net-_q34-pad3_ -vcc 2.4k +q36 -vcc vco_output net-_q36-pad3_ Q2N2907A +q38 net-_q37-pad2_ net-_q38-pad2_ net-_q36-pad3_ Q2N2907A +r23 +vcc net-_q36-pad3_ 16k +r24 net-_q37-pad2_ net-_q26-pad3_ 5.8k +q37 net-_q36-pad3_ net-_q37-pad2_ net-_q26-pad3_ Q2N2222 +q40 net-_q38-pad2_ net-_q11-pad1_ net-_q40-pad3_ Q2N2222 +r26 net-_q40-pad3_ -vcc 200 +r25 +vcc net-_q38-pad2_ 4.3k +q39 ? net-_q38-pad2_ +vcc Q2N2222 +q15 ? net-_q15-pad2_ vco_control_voltage Q2N2222 +q41 net-_q18-pad2_ net-_q15-pad2_ timming_resistor Q2N2907A +* Control Statements + +.ends LM565 \ No newline at end of file diff --git a/src/SubcircuitLibrary/LM565/LM565_Previous_Values.xml b/src/SubcircuitLibrary/LM565/LM565_Previous_Values.xml new file mode 100644 index 00000000..c60f46f5 --- /dev/null +++ b/src/SubcircuitLibrary/LM565/LM565_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q35><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q35><q40><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q40><q41><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q41><q34><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q34><q20><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q20><q21><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q21><q22><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q22><q23><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q23><q24><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q24><q25><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q25><q26><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q26><q27><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q27><q28><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q28><q29><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q29><q1><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q5><q4><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q9><q8><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q33><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q33><q14><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q14><q17><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12><q39><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q39><q38><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q38><q19><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q19><q18><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q18><q15><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q32><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q32><q31><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q31><q30><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q30><q37><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q37><q36><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q36></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/LM565/NPN.lib b/src/SubcircuitLibrary/LM565/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/LM565/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/LM565/PNP.lib b/src/SubcircuitLibrary/LM565/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/LM565/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib new file mode 100644 index 00000000..34588988 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir new file mode 100644 index 00000000..ec177d39 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir @@ -0,0 +1,16 @@ +* C:\eSim\eSim\src\SubcircuitLibrary\LOGIC_ADDER\LOGIC_ADDER.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:23:20 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 A B Net-_U2-Pad3_ d_and +U4 Net-_U3-Pad3_ CIN Net-_U4-Pad3_ d_and +U3 A B Net-_U3-Pad3_ d_xor +U5 Net-_U3-Pad3_ CIN SUM d_xor +U6 Net-_U2-Pad3_ Net-_U4-Pad3_ CARRY d_or +U1 A B CIN SUM CARRY PORT + +.end diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out new file mode 100644 index 00000000..df9bcde6 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out @@ -0,0 +1,32 @@ +* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir + +* u2 a b net-_u2-pad3_ d_and +* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and +* u3 a b net-_u3-pad3_ d_xor +* u5 net-_u3-pad3_ cin sum d_xor +* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or +* u1 a b cin sum carry port +a1 [a b ] net-_u2-pad3_ u2 +a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4 +a3 [a b ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ cin ] sum u5 +a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro new file mode 100644 index 00000000..a2b9fa1f --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro @@ -0,0 +1,44 @@ +update=Sat Jun 8 13:01:54 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch new file mode 100644 index 00000000..d39a1b78 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch @@ -0,0 +1,245 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:LOGIC_ADDER-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5AB647D1 +P 4100 2200 +F 0 "U2" H 4100 2200 60 0000 C CNN +F 1 "d_and" H 4150 2300 60 0000 C CNN +F 2 "" H 4100 2200 60 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5AB648AD +P 5250 2300 +F 0 "U4" H 5250 2300 60 0000 C CNN +F 1 "d_and" H 5300 2400 60 0000 C CNN +F 2 "" H 5250 2300 60 0000 C CNN +F 3 "" H 5250 2300 60 0000 C CNN + 1 5250 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U3 +U 1 1 5AB648E7 +P 4100 2750 +F 0 "U3" H 4100 2750 60 0000 C CNN +F 1 "d_xor" H 4150 2850 47 0000 C CNN +F 2 "" H 4100 2750 60 0000 C CNN +F 3 "" H 4100 2750 60 0000 C CNN + 1 4100 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U5 +U 1 1 5AB6498F +P 5250 2600 +F 0 "U5" H 5250 2600 60 0000 C CNN +F 1 "d_xor" H 5300 2700 47 0000 C CNN +F 2 "" H 5250 2600 60 0000 C CNN +F 3 "" H 5250 2600 60 0000 C CNN + 1 5250 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 5AB64A11 +P 6250 2250 +F 0 "U6" H 6250 2250 60 0000 C CNN +F 1 "d_or" H 6250 2350 60 0000 C CNN +F 2 "" H 6250 2250 60 0000 C CNN +F 3 "" H 6250 2250 60 0000 C CNN + 1 6250 2250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5AB64A78 +P 2650 2100 +F 0 "U1" H 2700 2200 30 0000 C CNN +F 1 "PORT" H 2650 2100 30 0000 C CNN +F 2 "" H 2650 2100 60 0000 C CNN +F 3 "" H 2650 2100 60 0000 C CNN + 1 2650 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5AB64BE9 +P 2650 2300 +F 0 "U1" H 2700 2400 30 0000 C CNN +F 1 "PORT" H 2650 2300 30 0000 C CNN +F 2 "" H 2650 2300 60 0000 C CNN +F 3 "" H 2650 2300 60 0000 C CNN + 2 2650 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5AB64C18 +P 6300 2550 +F 0 "U1" H 6350 2650 30 0000 C CNN +F 1 "PORT" H 6300 2550 30 0000 C CNN +F 2 "" H 6300 2550 60 0000 C CNN +F 3 "" H 6300 2550 60 0000 C CNN + 4 6300 2550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5AB64C59 +P 2650 2900 +F 0 "U1" H 2700 3000 30 0000 C CNN +F 1 "PORT" H 2650 2900 30 0000 C CNN +F 2 "" H 2650 2900 60 0000 C CNN +F 3 "" H 2650 2900 60 0000 C CNN + 3 2650 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5AB64C94 +P 7150 2200 +F 0 "U1" H 7200 2300 30 0000 C CNN +F 1 "PORT" H 7150 2200 30 0000 C CNN +F 2 "" H 7150 2200 60 0000 C CNN +F 3 "" H 7150 2200 60 0000 C CNN + 5 7150 2200 + -1 0 0 1 +$EndComp +Wire Wire Line + 2900 2100 3650 2100 +Wire Wire Line + 2900 2250 3650 2250 +Wire Wire Line + 3650 2250 3650 2200 +Wire Wire Line + 3400 2100 3400 2650 +Wire Wire Line + 3400 2650 3650 2650 +Connection ~ 3400 2100 +Wire Wire Line + 3150 2250 3150 2750 +Wire Wire Line + 3150 2750 3650 2750 +Connection ~ 3150 2250 +Wire Wire Line + 4550 2700 4550 2500 +Wire Wire Line + 4550 2500 4800 2500 +Wire Wire Line + 2900 2900 4800 2900 +Wire Wire Line + 4800 2900 4800 2600 +Wire Wire Line + 4700 2500 4700 2200 +Wire Wire Line + 4700 2200 4800 2200 +Connection ~ 4700 2500 +Wire Wire Line + 4800 2300 4600 2300 +Wire Wire Line + 4600 2300 4600 2900 +Connection ~ 4600 2900 +Wire Wire Line + 5700 2250 5800 2250 +Wire Wire Line + 4550 2150 4550 2000 +Wire Wire Line + 4550 2000 5800 2000 +Wire Wire Line + 5800 2000 5800 2150 +Wire Wire Line + 5700 2550 6050 2550 +Wire Wire Line + 6700 2200 6900 2200 +Wire Wire Line + 2900 2250 2900 2300 +Text GLabel 3000 1850 0 60 Input ~ 0 +A +Text GLabel 3000 2500 0 60 Input ~ 0 +B +Text GLabel 3000 3250 0 60 Input ~ 0 +CIN +Wire Wire Line + 3000 3250 3050 3250 +Wire Wire Line + 3050 3250 3050 2900 +Connection ~ 3050 2900 +Wire Wire Line + 3000 1850 3100 1850 +Wire Wire Line + 3100 1850 3100 2100 +Connection ~ 3100 2100 +Wire Wire Line + 3000 2500 3000 2250 +Connection ~ 3000 2250 +Text GLabel 6750 1700 0 60 Output ~ 0 +CARRY +Text GLabel 5950 2800 0 60 Output ~ 0 +SUM +Wire Wire Line + 6750 1700 6800 1700 +Wire Wire Line + 6800 1700 6800 2200 +Connection ~ 6800 2200 +Wire Wire Line + 5950 2550 5950 2800 +Connection ~ 5950 2550 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub new file mode 100644 index 00000000..a1e1cfac --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub @@ -0,0 +1,26 @@ +* Subcircuit LOGIC_ADDER +.subckt LOGIC_ADDER a b cin sum carry +* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir +* u2 a b net-_u2-pad3_ d_and +* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and +* u3 a b net-_u3-pad3_ d_xor +* u5 net-_u3-pad3_ cin sum d_xor +* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or +a1 [a b ] net-_u2-pad3_ u2 +a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4 +a3 [a b ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ cin ] sum u5 +a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends LOGIC_ADDER \ No newline at end of file diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml new file mode 100644 index 00000000..ab59f216 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/analysis b/src/SubcircuitLibrary/LOGIC_ADDER/analysis new file mode 100644 index 00000000..d5e13546 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/NE566/NE566-cache.lib b/src/SubcircuitLibrary/NE566/NE566-cache.lib new file mode 100644 index 00000000..db4e06a4 --- /dev/null +++ b/src/SubcircuitLibrary/NE566/NE566-cache.lib @@ -0,0 +1,125 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 I +X ~ 2 250 0 100 L 30 30 2 1 I +X ~ 3 250 0 100 L 30 30 3 1 I +X ~ 4 250 0 100 L 30 30 4 1 I +X ~ 5 250 0 100 L 30 30 5 1 I +X ~ 6 250 0 100 L 30 30 6 1 I +X ~ 7 250 0 100 L 30 30 7 1 I +X ~ 8 250 0 100 L 30 30 8 1 I +X ~ 9 250 0 100 L 30 30 9 1 I +X ~ 10 250 0 100 L 30 30 10 1 I +X ~ 11 250 0 100 L 30 30 11 1 I +X ~ 12 250 0 100 L 30 30 12 1 I +X ~ 13 250 0 100 L 30 30 13 1 I +X ~ 14 250 0 100 L 30 30 14 1 I +X ~ 15 250 0 100 L 30 30 15 1 I +X ~ 16 250 0 100 L 30 30 16 1 I +X ~ 17 250 0 100 L 30 30 17 1 I +X ~ 18 250 0 100 L 30 30 18 1 I +X ~ 19 250 0 100 L 30 30 19 1 I +X ~ 20 250 0 100 L 30 30 20 1 I +X ~ 21 250 0 100 L 30 30 21 1 I +X ~ 22 250 0 100 L 30 30 22 1 I +X ~ 23 250 0 100 L 30 30 23 1 I +X ~ 24 250 0 100 L 30 30 24 1 I +X ~ 25 250 0 100 L 30 30 25 1 I +X ~ 26 250 0 100 L 30 30 26 1 I +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/NE566/NE566.cir b/src/SubcircuitLibrary/NE566/NE566.cir new file mode 100644 index 00000000..4d52179b --- /dev/null +++ b/src/SubcircuitLibrary/NE566/NE566.cir @@ -0,0 +1,57 @@ +* C:\esim_1\eSim\src\SubcircuitLibrary\NE566\NE566.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/31/19 13:55:47 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D10-Pad2_ Net-_D10-Pad1_ eSim_NPN +Q2 Net-_D10-Pad1_ Net-_Q2-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q5 Net-_Q2-Pad2_ Net-_Q2-Pad2_ Net-_D1-Pad1_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q6 Net-_D3-Pad2_ Net-_D1-Pad2_ Net-_Q3-Pad2_ eSim_NPN +Q8 Net-_D9-Pad2_ Net-_D3-Pad2_ Net-_D5-Pad1_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad2_ Net-_Q7-Pad3_ eSim_NPN +Q3 Net-_D1-Pad2_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +R1 Net-_Q3-Pad3_ Net-_D4-Pad2_ 5k +R3 Net-_Q7-Pad3_ Net-_D4-Pad2_ 5k +D4 Net-_D2-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q4 Net-_D4-Pad2_ Net-_D2-Pad2_ Net-_Q15-Pad1_ eSim_NPN +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +R2 Net-_D2-Pad2_ Net-_Q15-Pad1_ 5k +R4 Net-_Q9-Pad3_ Net-_Q15-Pad1_ 5k +Q10 Net-_D9-Pad2_ Net-_D5-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q9 Net-_D5-Pad1_ Net-_Q11-Pad2_ Net-_Q9-Pad3_ eSim_NPN +Q11 Net-_Q10-Pad3_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +D6 Net-_D5-Pad1_ Net-_D6-Pad2_ eSim_Diode +Q12 Net-_D5-Pad2_ Net-_D6-Pad2_ Net-_Q12-Pad3_ eSim_NPN +D8 Net-_D5-Pad2_ Net-_D8-Pad2_ eSim_Diode +D7 Net-_D5-Pad2_ Net-_D7-Pad2_ eSim_Diode +R6 Net-_D9-Pad2_ Net-_D5-Pad2_ 5k +R8 Net-_D9-Pad2_ Net-_D8-Pad2_ 5k +Q14 Net-_D9-Pad2_ Net-_D8-Pad2_ Net-_Q14-Pad3_ eSim_NPN +Q13 Net-_D8-Pad2_ Net-_D7-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R7 Net-_D7-Pad2_ Net-_Q12-Pad3_ 5k +Q15 Net-_Q15-Pad1_ Net-_Q14-Pad3_ Net-_Q15-Pad3_ eSim_PNP +Q16 Net-_Q15-Pad3_ Net-_Q16-Pad2_ Net-_D2-Pad1_ eSim_PNP +Q17 Net-_Q16-Pad2_ Net-_D9-Pad1_ Net-_Q15-Pad3_ eSim_PNP +R13 Net-_D9-Pad2_ Net-_D9-Pad1_ 5k +D9 Net-_D9-Pad1_ Net-_D9-Pad2_ eSim_Diode +R15 Net-_D9-Pad2_ Net-_Q11-Pad2_ 5k +R12 Net-_Q16-Pad2_ Net-_D2-Pad1_ 5k +R5 Net-_Q11-Pad3_ Net-_Q15-Pad1_ 5k +R9 Net-_Q12-Pad3_ Net-_Q15-Pad1_ 5k +R10 Net-_Q14-Pad3_ Net-_Q15-Pad1_ 5k +Q18 Net-_D9-Pad1_ Net-_Q11-Pad2_ Net-_Q18-Pad3_ eSim_NPN +Q19 Net-_Q11-Pad2_ Net-_Q11-Pad2_ Net-_Q19-Pad3_ eSim_NPN +R14 Net-_Q18-Pad3_ Net-_Q15-Pad1_ 5k +R16 Net-_Q19-Pad3_ Net-_Q15-Pad1_ 5k +U1 Net-_Q15-Pad1_ Net-_Q14-Pad3_ Net-_Q10-Pad3_ Net-_D10-Pad2_ Net-_Q1-Pad1_ Net-_D3-Pad2_ Net-_D9-Pad2_ PORT +R11 Net-_D9-Pad2_ Net-_Q15-Pad3_ 5k +D10 Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_Diode +Q20 Net-_Q2-Pad2_ Net-_D10-Pad1_ Net-_Q1-Pad1_ eSim_PNP + +.end diff --git a/src/SubcircuitLibrary/NE566/NE566.cir.out b/src/SubcircuitLibrary/NE566/NE566.cir.out new file mode 100644 index 00000000..c83f8b00 --- /dev/null +++ b/src/SubcircuitLibrary/NE566/NE566.cir.out @@ -0,0 +1,61 @@ +* c:\esim_1\esim\src\subcircuitlibrary\ne566\ne566.cir + +.include PNP.lib +.include D.lib +.include NPN.lib +q1 net-_q1-pad1_ net-_d10-pad2_ net-_d10-pad1_ Q2N2222 +q2 net-_d10-pad1_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222 +q5 net-_q2-pad2_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +q6 net-_d3-pad2_ net-_d1-pad2_ net-_q3-pad2_ Q2N2222 +q8 net-_d9-pad2_ net-_d3-pad2_ net-_d5-pad1_ Q2N2222 +q7 net-_q3-pad2_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222 +q3 net-_d1-pad2_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +r1 net-_q3-pad3_ net-_d4-pad2_ 5k +r3 net-_q7-pad3_ net-_d4-pad2_ 5k +d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148 +q4 net-_d4-pad2_ net-_d2-pad2_ net-_q15-pad1_ Q2N2222 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r2 net-_d2-pad2_ net-_q15-pad1_ 5k +r4 net-_q9-pad3_ net-_q15-pad1_ 5k +q10 net-_d9-pad2_ net-_d5-pad1_ net-_q10-pad3_ Q2N2222 +q9 net-_d5-pad1_ net-_q11-pad2_ net-_q9-pad3_ Q2N2222 +q11 net-_q10-pad3_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d5-pad1_ net-_d6-pad2_ 1N4148 +q12 net-_d5-pad2_ net-_d6-pad2_ net-_q12-pad3_ Q2N2222 +d8 net-_d5-pad2_ net-_d8-pad2_ 1N4148 +d7 net-_d5-pad2_ net-_d7-pad2_ 1N4148 +r6 net-_d9-pad2_ net-_d5-pad2_ 5k +r8 net-_d9-pad2_ net-_d8-pad2_ 5k +q14 net-_d9-pad2_ net-_d8-pad2_ net-_q14-pad3_ Q2N2222 +q13 net-_d8-pad2_ net-_d7-pad2_ net-_q12-pad3_ Q2N2222 +r7 net-_d7-pad2_ net-_q12-pad3_ 5k +q15 net-_q15-pad1_ net-_q14-pad3_ net-_q15-pad3_ Q2N2907A +q16 net-_q15-pad3_ net-_q16-pad2_ net-_d2-pad1_ Q2N2222 +q17 net-_q16-pad2_ net-_d9-pad1_ net-_q15-pad3_ Q2N2222 +r13 net-_d9-pad2_ net-_d9-pad1_ 5k +d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148 +r15 net-_d9-pad2_ net-_q11-pad2_ 5k +r12 net-_q16-pad2_ net-_d2-pad1_ 5k +r5 net-_q11-pad3_ net-_q15-pad1_ 5k +r9 net-_q12-pad3_ net-_q15-pad1_ 5k +r10 net-_q14-pad3_ net-_q15-pad1_ 5k +q18 net-_d9-pad1_ net-_q11-pad2_ net-_q18-pad3_ Q2N2222 +q19 net-_q11-pad2_ net-_q11-pad2_ net-_q19-pad3_ Q2N2222 +r14 net-_q18-pad3_ net-_q15-pad1_ 5k +r16 net-_q19-pad3_ net-_q15-pad1_ 5k +* u1 net-_q15-pad1_ net-_q14-pad3_ net-_q10-pad3_ net-_d10-pad2_ net-_q1-pad1_ net-_d3-pad2_ net-_d9-pad2_ port +r11 net-_d9-pad2_ net-_q15-pad3_ 5k +d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148 +q20 net-_q2-pad2_ net-_d10-pad1_ net-_q1-pad1_ Q2N2222 +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/NE566/NE566.pro b/src/SubcircuitLibrary/NE566/NE566.pro new file mode 100644 index 00000000..4b1e556f --- /dev/null +++ b/src/SubcircuitLibrary/NE566/NE566.pro @@ -0,0 +1,83 @@ +update=03/31/19 14:14:07 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../../../Users/hp/AppData/Roaming/SPB_Data/eSim-Workspace/Function_generator_using_NE566 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Plot +LibName36=eSim_Power +LibName37=eSim_PSpice +LibName38=eSim_Sources +LibName39=eSim_Subckt +LibName40=eSim_User +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/src/SubcircuitLibrary/NE566/NE566.sch b/src/SubcircuitLibrary/NE566/NE566.sch new file mode 100644 index 00000000..f4c9144d --- /dev/null +++ b/src/SubcircuitLibrary/NE566/NE566.sch @@ -0,0 +1,920 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:NE566-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5C9D1243 +P 1650 1650 +F 0 "Q1" H 1550 1700 50 0000 R CNN +F 1 "eSim_NPN" H 1600 1800 50 0000 R CNN +F 2 "" H 1850 1750 29 0000 C CNN +F 3 "" H 1650 1650 60 0000 C CNN + 1 1650 1650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5C9D1262 +P 1850 2450 +F 0 "Q2" H 1750 2500 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2600 50 0000 R CNN +F 2 "" H 2050 2550 29 0000 C CNN +F 3 "" H 1850 2450 60 0000 C CNN + 1 1850 2450 + -1 0 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5900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R14 +U 1 1 5C9D25BD +P 9500 6750 +F 0 "R14" H 9550 6880 50 0000 C CNN +F 1 "5k" H 9550 6800 50 0000 C CNN +F 2 "" H 9550 6730 30 0000 C CNN +F 3 "" V 9550 6800 30 0000 C CNN + 1 9500 6750 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R16 +U 1 1 5C9D2650 +P 10450 6750 +F 0 "R16" H 10500 6880 50 0000 C CNN +F 1 "5k" H 10500 6800 50 0000 C CNN +F 2 "" H 10500 6730 30 0000 C CNN +F 3 "" V 10500 6800 30 0000 C CNN + 1 10450 6750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D2BB3 +P 650 1650 +F 0 "U1" H 700 1750 30 0000 C CNN +F 1 "PORT" H 650 1650 30 0000 C CNN +F 2 "" H 650 1650 60 0000 C CNN +F 3 "" H 650 1650 60 0000 C CNN + 5 650 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9D68D0 +P 2100 800 +F 0 "U1" H 2150 900 30 0000 C CNN +F 1 "PORT" H 2100 800 30 0000 C CNN +F 2 "" H 2100 800 60 0000 C CNN +F 3 "" H 2100 800 60 0000 C CNN + 6 2100 800 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5C9D8B9B +P 7150 1350 +F 0 "R11" H 7200 1480 50 0000 C CNN +F 1 "5k" H 7200 1400 50 0000 C CNN +F 2 "" H 7200 1330 30 0000 C CNN +F 3 "" V 7200 1400 30 0000 C CNN + 1 7150 1350 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C9D98CB +P 3650 550 +F 0 "U1" H 3700 650 30 0000 C CNN +F 1 "PORT" H 3650 550 30 0000 C CNN +F 2 "" H 3650 550 60 0000 C CNN +F 3 "" H 3650 550 60 0000 C CNN + 8 3650 550 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C9E5DF3 +P 3150 3950 +F 0 "U1" H 3200 4050 30 0000 C CNN +F 1 "PORT" H 3150 3950 30 0000 C CNN +F 2 "" H 3150 3950 60 0000 C CNN +F 3 "" H 3150 3950 60 0000 C CNN + 7 3150 3950 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9E625B +P 4950 5150 +F 0 "U1" H 5000 5250 30 0000 C CNN +F 1 "PORT" H 4950 5150 30 0000 C CNN +F 2 "" H 4950 5150 60 0000 C CNN +F 3 "" H 4950 5150 60 0000 C CNN + 4 4950 5150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9E6ECC +P 6800 5100 +F 0 "U1" H 6850 5200 30 0000 C CNN +F 1 "PORT" H 6800 5100 30 0000 C CNN +F 2 "" H 6800 5100 60 0000 C CNN +F 3 "" H 6800 5100 60 0000 C CNN + 3 6800 5100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9E7FDD +P 11100 7250 +F 0 "U1" H 11150 7350 30 0000 C CNN +F 1 "PORT" H 11100 7250 30 0000 C CNN +F 2 "" H 11100 7250 60 0000 C CNN +F 3 "" H 11100 7250 60 0000 C CNN + 1 11100 7250 + 0 -1 -1 0 +$EndComp +Text Notes 500 1450 0 79 ~ 0 +Modulation Input\n +Text Notes 2200 800 0 79 ~ 0 +R1(External) +Text Notes 3300 5750 1 79 ~ 0 +C1(External)\n +Text Notes 4500 5050 0 79 ~ 0 +Triangle Wave Output +Text Notes 6500 5000 0 79 ~ 0 +Square Wave Output\n +Text Notes 10950 7000 0 79 ~ 0 +GND\n +Text Notes 3425 625 0 79 ~ 0 +V+\n +$Comp +L eSim_Diode D10 +U 1 1 5C9F4364 +P 1300 1850 +F 0 "D10" H 1300 1950 50 0000 C CNN +F 1 "eSim_Diode" H 1300 1750 50 0000 C CNN +F 2 "" H 1300 1850 60 0000 C CNN +F 3 "" H 1300 1850 60 0000 C CNN + 1 1300 1850 + 0 -1 -1 0 +$EndComp +Text Notes 950 1650 0 79 ~ 0 +Vc\n +Wire Wire Line + 1750 1850 1750 2250 +Wire Wire Line + 900 1650 1450 1650 +Wire Wire Line + 2750 2000 2750 2250 +Wire Wire Line + 2050 2450 2450 2450 +Wire Wire Line + 2750 2200 2250 2200 +Wire Wire Line + 2250 2200 2250 2450 +Connection ~ 2250 2450 +Connection ~ 2750 2200 +Wire Wire Line + 2100 1800 2450 1800 +Wire Wire Line + 2100 2000 2100 1800 +Wire Wire Line + 1300 2000 2100 2000 +Connection ~ 1750 2000 +Wire Wire Line + 2750 1450 1750 1450 +Wire Wire Line + 2750 2650 2750 3000 +Wire Wire Line + 1750 2650 1750 3000 +Wire Wire Line + 2750 2850 1750 2850 +Connection ~ 1750 2850 +Connection ~ 2750 2850 +Wire Wire Line + 2750 3300 2750 3900 +Wire Wire Line + 2450 4100 1750 4100 +Wire Wire Line + 1750 3300 1750 4700 +Connection ~ 1750 4100 +Wire Wire Line + 2750 4300 2750 4700 +Wire Wire Line + 2050 4900 2450 4900 +Wire Wire Line + 2750 3550 3350 3550 +Connection ~ 2750 3550 +Wire Wire Line + 2750 4500 2250 4500 +Wire Wire Line + 2250 4500 2250 4900 +Connection ~ 2250 4900 +Connection ~ 2750 4500 +Wire Wire Line + 2750 5100 2750 5400 +Wire Wire Line + 2750 5700 2750 5950 +Wire Wire Line + 1750 5100 1750 5450 +Wire Wire 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10500 5700 10450 5700 +Wire Wire Line + 9850 5900 10150 5900 +Wire Wire Line + 10500 5550 10000 5550 +Wire Wire Line + 10000 5550 10000 5900 +Connection ~ 10000 5900 +Connection ~ 10500 5550 +Wire Wire Line + 10450 6100 10450 6650 +Wire Wire Line + 10450 6650 10500 6650 +Wire Wire Line + 9550 6100 9550 6650 +Wire Wire Line + 9550 1600 9550 5700 +Wire Wire Line + 8500 1600 9550 1600 +Wire Wire Line + 9050 800 9050 1300 +Connection ~ 9050 800 +Connection ~ 9050 1600 +Wire Wire Line + 8500 1300 8500 800 +Connection ~ 8500 800 +Wire Wire Line + 9550 2650 8850 2650 +Connection ~ 9550 2650 +Wire Wire Line + 7200 2450 8550 2450 +Wire Wire Line + 7900 2450 7900 2550 +Wire Wire Line + 7200 1550 7200 2550 +Connection ~ 7900 2450 +Wire Wire Line + 7200 800 7200 1250 +Connection ~ 7200 800 +Connection ~ 7200 2450 +Wire Wire Line + 3650 3350 3650 800 +Connection ~ 3650 800 +Wire Wire Line + 3950 4400 3950 800 +Connection ~ 3950 800 +Wire Wire Line + 4950 1150 4950 800 +Connection ~ 4950 800 +Wire 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+Connection ~ 7900 6500 +Wire Wire Line + 7200 2950 7200 7000 +Wire Wire Line + 6500 1650 6500 800 +Connection ~ 6500 800 +Connection ~ 7200 7000 +Connection ~ 6000 7000 +Wire Wire Line + 6500 6950 6500 7000 +Connection ~ 6500 7000 +Wire Wire Line + 5350 3300 5650 3300 +Wire Wire Line + 5500 3300 5500 3450 +Connection ~ 5500 3300 +Wire Wire Line + 4950 4150 6000 4150 +Wire Wire Line + 5950 4150 5950 3500 +Wire Wire Line + 5500 3750 5500 4150 +Connection ~ 5500 4150 +Wire Wire Line + 6000 4150 6000 6650 +Connection ~ 5950 4150 +Connection ~ 5950 2350 +Wire Wire Line + 3150 3550 3150 3700 +Connection ~ 3150 3550 +Wire Wire Line + 4700 5150 4500 5150 +Connection ~ 4500 5150 +Wire Notes Line + 2200 800 2900 800 +Wire Notes Line + 3150 4050 3150 7000 +Wire Wire Line + 1300 1700 1300 1650 +Connection ~ 1300 1650 +Wire Wire Line + 5050 3300 4950 3300 +Connection ~ 4950 3300 +$Comp +L eSim_PNP Q20 +U 1 1 5CA087B6 +P 2650 1800 +F 0 "Q20" H 2550 1850 50 0000 R CNN +F 1 "eSim_PNP" H 2600 1950 50 0000 R CNN +F 2 "" H 2850 1900 29 0000 C CNN +F 3 "" H 2650 1800 60 0000 C CNN + 1 2650 1800 + 1 0 0 1 +$EndComp +Wire Wire Line + 2750 1450 2750 1600 +Wire Notes Line + 2925 800 3600 800 +Wire Wire Line + 10500 800 10500 1650 +Wire Wire Line + 6500 2050 6500 6650 +Wire Wire Line + 6500 5100 6550 5100 +Connection ~ 6500 5100 +Wire Wire Line + 6900 2750 6500 2750 +Connection ~ 6500 2750 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/NE566/NE566.sub b/src/SubcircuitLibrary/NE566/NE566.sub new file mode 100644 index 00000000..5b2fc943 --- /dev/null +++ b/src/SubcircuitLibrary/NE566/NE566.sub @@ -0,0 +1,55 @@ +* Subcircuit NE566 +.subckt NE566 net-_q15-pad1_ net-_q14-pad3_ net-_q10-pad3_ net-_d10-pad2_ net-_q1-pad1_ net-_d3-pad2_ net-_d9-pad2_ +* c:\esim_1\esim\src\subcircuitlibrary\ne566\ne566.cir +.include PNP.lib +.include D.lib +.include NPN.lib +q1 net-_q1-pad1_ net-_d10-pad2_ net-_d10-pad1_ Q2N2222 +q2 net-_d10-pad1_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222 +q5 net-_q2-pad2_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +q6 net-_d3-pad2_ net-_d1-pad2_ net-_q3-pad2_ Q2N2222 +q8 net-_d9-pad2_ net-_d3-pad2_ net-_d5-pad1_ Q2N2222 +q7 net-_q3-pad2_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222 +q3 net-_d1-pad2_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +r1 net-_q3-pad3_ net-_d4-pad2_ 5k +r3 net-_q7-pad3_ net-_d4-pad2_ 5k +d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148 +q4 net-_d4-pad2_ net-_d2-pad2_ net-_q15-pad1_ Q2N2222 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r2 net-_d2-pad2_ net-_q15-pad1_ 5k +r4 net-_q9-pad3_ net-_q15-pad1_ 5k +q10 net-_d9-pad2_ net-_d5-pad1_ net-_q10-pad3_ Q2N2222 +q9 net-_d5-pad1_ net-_q11-pad2_ net-_q9-pad3_ Q2N2222 +q11 net-_q10-pad3_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d5-pad1_ net-_d6-pad2_ 1N4148 +q12 net-_d5-pad2_ net-_d6-pad2_ net-_q12-pad3_ Q2N2222 +d8 net-_d5-pad2_ net-_d8-pad2_ 1N4148 +d7 net-_d5-pad2_ net-_d7-pad2_ 1N4148 +r6 net-_d9-pad2_ net-_d5-pad2_ 5k +r8 net-_d9-pad2_ net-_d8-pad2_ 5k +q14 net-_d9-pad2_ net-_d8-pad2_ net-_q14-pad3_ Q2N2222 +q13 net-_d8-pad2_ net-_d7-pad2_ net-_q12-pad3_ Q2N2222 +r7 net-_d7-pad2_ net-_q12-pad3_ 5k +q15 net-_q15-pad1_ net-_q14-pad3_ net-_q15-pad3_ Q2N2907A +q16 net-_q15-pad3_ net-_q16-pad2_ net-_d2-pad1_ Q2N2222 +q17 net-_q16-pad2_ net-_d9-pad1_ net-_q15-pad3_ Q2N2222 +r13 net-_d9-pad2_ net-_d9-pad1_ 5k +d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148 +r15 net-_d9-pad2_ net-_q11-pad2_ 5k +r12 net-_q16-pad2_ net-_d2-pad1_ 5k +r5 net-_q11-pad3_ net-_q15-pad1_ 5k +r9 net-_q12-pad3_ net-_q15-pad1_ 5k +r10 net-_q14-pad3_ net-_q15-pad1_ 5k +q18 net-_d9-pad1_ net-_q11-pad2_ net-_q18-pad3_ Q2N2222 +q19 net-_q11-pad2_ net-_q11-pad2_ net-_q19-pad3_ Q2N2222 +r14 net-_q18-pad3_ net-_q15-pad1_ 5k +r16 net-_q19-pad3_ net-_q15-pad1_ 5k +r11 net-_d9-pad2_ net-_q15-pad3_ 5k +d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148 +q20 net-_q2-pad2_ net-_d10-pad1_ net-_q1-pad1_ Q2N2222 +* Control Statements + +.ends NE566 \ No newline at end of file diff --git a/src/SubcircuitLibrary/NE566/NE566_Previous_Values.xml b/src/SubcircuitLibrary/NE566/NE566_Previous_Values.xml new file mode 100644 index 00000000..cd7c0b08 --- /dev/null +++ b/src/SubcircuitLibrary/NE566/NE566_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q20><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q20><d8><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d8><d9><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d9><d6><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d6><d7><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d7><d4><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d4><d5><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d5><d2><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d1><q1><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q5><q4><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q9><q8><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q15><q14><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q14><q17><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q17><q16><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q16><q11><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12><d10><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d10><q19><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q19><q18><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/analysis b/src/SubcircuitLibrary/full_sub/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 \ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib new file mode 100644 index 00000000..f874f5e2 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib new file mode 100644 index 00000000..416747ef --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib @@ -0,0 +1,20 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# half_sub-RESCUE-full_sub +# +DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1450 850 1550 -1050 0 1 0 N +X A 1 -1100 850 200 R 50 50 1 1 I +X B 2 -350 850 200 R 50 50 1 1 I +X D 3 -800 -1050 200 L 50 50 1 1 O +X BORROW 4 0 -1050 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir b/src/SubcircuitLibrary/full_sub/full_sub.cir new file mode 100644 index 00000000..7d6f198f --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.cir @@ -0,0 +1,14 @@ +* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or +U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT +X1 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub +X2 Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub + +.end diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir.out b/src/SubcircuitLibrary/full_sub/full_sub.cir.out new file mode 100644 index 00000000..e310dcd0 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.cir.out @@ -0,0 +1,19 @@ +* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir + +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/full_sub/full_sub.pro b/src/SubcircuitLibrary/full_sub/full_sub.pro new file mode 100644 index 00000000..3336e88e --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.pro @@ -0,0 +1,74 @@ +update=03/07/19 10:55:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=full_sub-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=device +LibName24=transistors +LibName25=conn +LibName26=linear +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_User +LibName39=eSim_Plot +LibName40=eSim_PSpice + diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sch b/src/SubcircuitLibrary/full_sub/full_sub.sch new file mode 100644 index 00000000..ed8ac50d --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.sch @@ -0,0 +1,211 @@ +EESchema Schematic File Version 2 +LIBS:full_sub-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:full_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U3 +U 1 1 5C80734A +P 9350 4050 +F 0 "U3" H 9350 4050 60 0000 C CNN +F 1 "d_or" H 9350 4150 60 0000 C CNN +F 2 "" H 9350 4050 60 0000 C CNN +F 3 "" H 9350 4050 60 0000 C CNN + 1 9350 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 3600 5800 3600 +Wire Wire Line + 4650 2800 8600 2800 +Wire Wire Line + 8600 2800 8600 3950 +Wire Wire Line + 8600 3950 8900 3950 +Wire Wire Line + 8100 4450 8650 4450 +Wire Wire Line + 8650 4450 8650 4050 +Wire Wire Line + 8650 4050 8900 4050 +Wire Wire Line + 2800 3450 2800 3250 +Wire Wire Line + 2800 3250 3300 3250 +Wire Wire Line + 1450 3550 3300 3550 +Wire Wire Line + 4050 5100 5200 5100 +Wire Wire Line + 5800 3600 5800 5250 +Wire Wire Line + 8250 5250 9350 5250 +Wire Wire Line + 9350 5250 9350 4900 +Wire Wire Line + 9350 4900 10750 4900 +Wire Wire Line + 9800 4000 9800 4600 +Wire Wire Line + 9800 4600 9550 4600 +Wire Wire Line + 9550 4600 9550 4800 +Wire Wire Line + 9550 4800 10750 4800 +$Comp +L PORT U5 +U 1 1 5C80A4E8 +P 1200 3450 +F 0 "U5" H 1250 3550 30 0000 C CNN +F 1 "PORT" H 1200 3450 30 0000 C CNN +F 2 "" H 1200 3450 60 0000 C CNN +F 3 "" H 1200 3450 60 0000 C CNN + 1 1200 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 2 1 5C80A51E +P 1200 3650 +F 0 "U5" H 1250 3750 30 0000 C CNN +F 1 "PORT" H 1200 3650 30 0000 C CNN +F 2 "" H 1200 3650 60 0000 C CNN +F 3 "" H 1200 3650 60 0000 C CNN + 2 1200 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 3 1 5C80A54E +P 3800 5100 +F 0 "U5" H 3850 5200 30 0000 C CNN +F 1 "PORT" H 3800 5100 30 0000 C CNN +F 2 "" H 3800 5100 60 0000 C CNN +F 3 "" H 3800 5100 60 0000 C CNN + 3 3800 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 5 1 5C80A828 +P 11000 4800 +F 0 "U5" H 11050 4900 30 0000 C CNN +F 1 "PORT" H 11000 4800 30 0000 C CNN +F 2 "" H 11000 4800 60 0000 C CNN +F 3 "" H 11000 4800 60 0000 C CNN + 5 11000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 4 1 5C80AB2A +P 11000 4950 +F 0 "U5" H 11050 5050 30 0000 C CNN +F 1 "PORT" H 11000 4950 30 0000 C CNN +F 2 "" H 11000 4950 60 0000 C CNN +F 3 "" H 11000 4950 60 0000 C CNN + 4 11000 4950 + -1 0 0 1 +$EndComp +Wire Wire Line + 1450 3450 2800 3450 +Wire Wire Line + 1450 3650 1450 3550 +Wire Wire Line + 10750 4900 10750 4950 +$Comp +L half_sub X1 +U 1 1 5C80AC4D +P 3800 3450 +F 0 "X1" H 3800 3450 60 0000 C CNN +F 1 "half_sub" H 3800 3450 60 0000 C CNN +F 2 "" H 3800 3450 60 0001 C CNN +F 3 "" H 3800 3450 60 0001 C CNN + 1 3800 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 3550 4650 3550 +Wire Wire Line + 4650 3550 4650 2800 +Wire Wire Line + 4300 3300 4850 3300 +Wire Wire Line + 4850 3300 4850 3600 +$Comp +L half_sub X2 +U 1 1 5C80AD72 +P 7300 5150 +F 0 "X2" H 7300 5150 60 0000 C CNN +F 1 "half_sub" H 7300 5150 60 0000 C CNN +F 2 "" H 7300 5150 60 0001 C CNN +F 3 "" H 7300 5150 60 0001 C CNN + 1 7300 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5800 5250 6800 5250 +Wire Wire Line + 5200 5100 5200 4950 +Wire Wire Line + 5200 4950 6800 4950 +Wire Wire Line + 7800 5000 8250 5000 +Wire Wire Line + 8250 5000 8250 5250 +Wire Wire Line + 7800 5250 8100 5250 +Wire Wire Line + 8100 5250 8100 4450 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sub b/src/SubcircuitLibrary/full_sub/full_sub.sub new file mode 100644 index 00000000..ec5698b5 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.sub @@ -0,0 +1,13 @@ +* Subcircuit full_sub +.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ +* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_sub \ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml b/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml new file mode 100644 index 00000000..fcdb63e0 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x1></subcircuit></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/half_sub-cache.lib b/src/SubcircuitLibrary/full_sub/half_sub-cache.lib new file mode 100644 index 00000000..bd15e664 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir b/src/SubcircuitLibrary/full_sub/half_sub.cir new file mode 100644 index 00000000..f20f0368 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub.cir @@ -0,0 +1,14 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir.out b/src/SubcircuitLibrary/full_sub/half_sub.cir.out new file mode 100644 index 00000000..95e6e2bd --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub.cir.out @@ -0,0 +1,24 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/full_sub/half_sub.pro b/src/SubcircuitLibrary/full_sub/half_sub.pro new file mode 100644 index 00000000..90e3ded9 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub.pro @@ -0,0 +1,74 @@ +update=Wed 06 Mar 2019 11:10:38 PM IST +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sch b/src/SubcircuitLibrary/full_sub/half_sub.sch new file mode 100644 index 00000000..e70b1675 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U3 +U 1 1 5C7FDDA3 +P 4400 3150 +F 0 "U3" H 4400 3150 60 0000 C CNN +F 1 "d_xor" H 4450 3250 47 0000 C CNN +F 2 "" H 4400 3150 60 0000 C CNN +F 3 "" H 4400 3150 60 0000 C CNN + 1 4400 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5C7FDDD8 +P 3400 3750 +F 0 "U2" H 3400 3650 60 0000 C CNN +F 1 "d_inverter" H 3400 3900 60 0000 C CNN +F 2 "" H 3450 3700 60 0000 C CNN +F 3 "" H 3450 3700 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FDE57 +P 4450 3750 +F 0 "U4" H 4450 3750 60 0000 C CNN +F 1 "d_and" H 4500 3850 60 0000 C CNN +F 2 "" H 4450 3750 60 0000 C CNN +F 3 "" H 4450 3750 60 0000 C CNN + 1 4450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 3150 3950 3650 +Wire Wire Line + 3950 3650 4000 3650 +Wire Wire Line + 3700 3750 4000 3750 +Wire Wire Line + 3100 3750 3100 3050 +Wire Wire Line + 2950 3050 3950 3050 +$Comp +L PORT U1 +U 1 1 5C7FDF5A +P 2700 3050 +F 0 "U1" H 2750 3150 30 0000 C CNN +F 1 "PORT" H 2700 3050 30 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FDF97 +P 3500 3350 +F 0 "U1" H 3550 3450 30 0000 C CNN +F 1 "PORT" H 3500 3350 30 0000 C CNN +F 2 "" H 3500 3350 60 0000 C CNN +F 3 "" H 3500 3350 60 0000 C CNN + 2 3500 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FE00A +P 5300 3100 +F 0 "U1" H 5350 3200 30 0000 C CNN +F 1 "PORT" H 5300 3100 30 0000 C CNN +F 2 "" H 5300 3100 60 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 3 5300 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7FE064 +P 5350 3700 +F 0 "U1" H 5400 3800 30 0000 C CNN +F 1 "PORT" H 5350 3700 30 0000 C CNN +F 2 "" H 5350 3700 60 0000 C CNN +F 3 "" H 5350 3700 60 0000 C CNN + 4 5350 3700 + -1 0 0 1 +$EndComp +Connection ~ 3100 3050 +Wire Wire Line + 3750 3350 3950 3350 +Connection ~ 3950 3350 +Wire Wire Line + 4850 3100 5050 3100 +Wire Wire Line + 4900 3700 5100 3700 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sub b/src/SubcircuitLibrary/full_sub/half_sub.sub new file mode 100644 index 00000000..1931f76e --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub.sub @@ -0,0 +1,18 @@ +* Subcircuit half_sub +.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_sub \ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml b/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml new file mode 100644 index 00000000..115ba703 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/half_sub/analysis b/src/SubcircuitLibrary/half_sub/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 \ No newline at end of file diff --git a/src/SubcircuitLibrary/half_sub/half_sub-cache.lib b/src/SubcircuitLibrary/half_sub/half_sub-cache.lib new file mode 100644 index 00000000..bd15e664 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/half_sub/half_sub.cir b/src/SubcircuitLibrary/half_sub/half_sub.cir new file mode 100644 index 00000000..f20f0368 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub.cir @@ -0,0 +1,14 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/half_sub/half_sub.cir.out b/src/SubcircuitLibrary/half_sub/half_sub.cir.out new file mode 100644 index 00000000..95e6e2bd --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub.cir.out @@ -0,0 +1,24 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/half_sub/half_sub.pro b/src/SubcircuitLibrary/half_sub/half_sub.pro new file mode 100644 index 00000000..90e3ded9 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub.pro @@ -0,0 +1,74 @@ +update=Wed 06 Mar 2019 11:10:38 PM IST +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/half_sub/half_sub.sch b/src/SubcircuitLibrary/half_sub/half_sub.sch new file mode 100644 index 00000000..e70b1675 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U3 +U 1 1 5C7FDDA3 +P 4400 3150 +F 0 "U3" H 4400 3150 60 0000 C CNN +F 1 "d_xor" H 4450 3250 47 0000 C CNN +F 2 "" H 4400 3150 60 0000 C CNN +F 3 "" H 4400 3150 60 0000 C CNN + 1 4400 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5C7FDDD8 +P 3400 3750 +F 0 "U2" H 3400 3650 60 0000 C CNN +F 1 "d_inverter" H 3400 3900 60 0000 C CNN +F 2 "" H 3450 3700 60 0000 C CNN +F 3 "" H 3450 3700 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FDE57 +P 4450 3750 +F 0 "U4" H 4450 3750 60 0000 C CNN +F 1 "d_and" H 4500 3850 60 0000 C CNN +F 2 "" H 4450 3750 60 0000 C CNN +F 3 "" H 4450 3750 60 0000 C CNN + 1 4450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 3150 3950 3650 +Wire Wire Line + 3950 3650 4000 3650 +Wire Wire Line + 3700 3750 4000 3750 +Wire Wire Line + 3100 3750 3100 3050 +Wire Wire Line + 2950 3050 3950 3050 +$Comp +L PORT U1 +U 1 1 5C7FDF5A +P 2700 3050 +F 0 "U1" H 2750 3150 30 0000 C CNN +F 1 "PORT" H 2700 3050 30 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FDF97 +P 3500 3350 +F 0 "U1" H 3550 3450 30 0000 C CNN +F 1 "PORT" H 3500 3350 30 0000 C CNN +F 2 "" H 3500 3350 60 0000 C CNN +F 3 "" H 3500 3350 60 0000 C CNN + 2 3500 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FE00A +P 5300 3100 +F 0 "U1" H 5350 3200 30 0000 C CNN +F 1 "PORT" H 5300 3100 30 0000 C CNN +F 2 "" H 5300 3100 60 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 3 5300 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7FE064 +P 5350 3700 +F 0 "U1" H 5400 3800 30 0000 C CNN +F 1 "PORT" H 5350 3700 30 0000 C CNN +F 2 "" H 5350 3700 60 0000 C CNN +F 3 "" H 5350 3700 60 0000 C CNN + 4 5350 3700 + -1 0 0 1 +$EndComp +Connection ~ 3100 3050 +Wire Wire Line + 3750 3350 3950 3350 +Connection ~ 3950 3350 +Wire Wire Line + 4850 3100 5050 3100 +Wire Wire Line + 4900 3700 5100 3700 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/half_sub/half_sub.sub b/src/SubcircuitLibrary/half_sub/half_sub.sub new file mode 100644 index 00000000..1931f76e --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub.sub @@ -0,0 +1,18 @@ +* Subcircuit half_sub +.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_sub \ No newline at end of file diff --git a/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml b/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml new file mode 100644 index 00000000..115ba703 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/opto_isolator_switch/analysis b/src/SubcircuitLibrary/opto_isolator_switch/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/opto_isolator_switch/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch-cache.lib b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch-cache.lib new file mode 100644 index 00000000..88d58478 --- /dev/null +++ b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch-cache.lib @@ -0,0 +1,99 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# CCCS +# +DEF CCCS F 0 40 Y Y 1 F N +F0 "F" 0 150 50 H V C CNN +F1 "CCCS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir new file mode 100644 index 00000000..5fc9dd50 --- /dev/null +++ b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir @@ -0,0 +1,15 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jun 20 15:52:58 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_R1-Pad1_ Net-_F1-Pad3_ 1000 +F1 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_F1-Pad3_ Net-_F1-Pad4_ 3 +R2 Net-_C1-Pad2_ Net-_F1-Pad4_ 1000 +U1 Net-_R1-Pad1_ Net-_F1-Pad4_ Net-_C1-Pad1_ Net-_C1-Pad2_ PORT +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 14n + +.end diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir.out b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir.out new file mode 100644 index 00000000..afeeaa02 --- /dev/null +++ b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir.out @@ -0,0 +1,18 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/opto_isolator_switch/opto_isolator_switch.cir + +r1 net-_r1-pad1_ net-_f1-pad3_ 1000 +* f1 +r2 net-_c1-pad2_ net-_f1-pad4_ 1000 +* u1 net-_r1-pad1_ net-_f1-pad4_ net-_c1-pad1_ net-_c1-pad2_ port +c1 net-_c1-pad1_ net-_c1-pad2_ 14n +Vf1 net-_f1-pad3_ net-_f1-pad4_ 0 +f1 net-_c1-pad1_ net-_c1-pad2_ Vf1 3 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.pro b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.pro new file mode 100644 index 00000000..47ae9917 --- /dev/null +++ b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.pro @@ -0,0 +1,83 @@ +update=Thu Jun 20 15:32:48 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName41=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName42=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName43=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName44=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName45=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName46=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName47=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName48=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName49=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User + diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sch b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sch new file mode 100644 index 00000000..3f1c7298 --- /dev/null +++ b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sch @@ -0,0 +1,178 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:opto_isolator_switch-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R1 +U 1 1 5D0B5974 +P 4350 3450 +F 0 "R1" H 4400 3580 50 0000 C CNN +F 1 "1000" H 4400 3500 50 0000 C CNN +F 2 "" H 4400 3430 30 0000 C CNN +F 3 "" V 4400 3500 30 0000 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F1 +U 1 1 5D0B59A2 +P 5200 3450 +F 0 "F1" H 5200 3600 50 0000 C CNN +F 1 "3" H 5000 3400 50 0000 C CNN +F 2 "" H 5200 3450 60 0000 C CNN +F 3 "" H 5200 3450 60 0000 C CNN + 1 5200 3450 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5D0B59D5 +P 5200 4050 +F 0 "R2" H 5250 4180 50 0000 C CNN +F 1 "1000" H 5250 4100 50 0000 C CNN +F 2 "" H 5250 4030 30 0000 C CNN +F 3 "" V 5250 4100 30 0000 C CNN + 1 5200 4050 + 0 1 1 0 +$EndComp +Wire Wire Line + 4550 3400 5000 3400 +Wire Wire Line + 5000 3500 4750 3500 +Wire Wire Line + 4750 3500 4750 3700 +Wire Wire Line + 5250 3950 5250 3750 +Wire Wire Line + 5250 3150 5250 3000 +Wire Wire Line + 5250 3000 5650 3000 +Wire Wire Line + 5650 3000 5650 3350 +Wire Wire Line + 5650 3350 5700 3350 +Wire Wire Line + 5250 4250 5250 4350 +Wire Wire Line + 4250 3400 4000 3400 +$Comp +L PORT U1 +U 1 1 5D0B5AC7 +P 3750 3400 +F 0 "U1" H 3800 3500 30 0000 C CNN +F 1 "PORT" H 3750 3400 30 0000 C CNN +F 2 "" H 3750 3400 60 0000 C CNN +F 3 "" H 3750 3400 60 0000 C CNN + 1 3750 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D0B5B16 +P 4750 3950 +F 0 "U1" H 4800 4050 30 0000 C CNN +F 1 "PORT" H 4750 3950 30 0000 C CNN +F 2 "" H 4750 3950 60 0000 C CNN +F 3 "" H 4750 3950 60 0000 C CNN + 2 4750 3950 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 5D0B5B84 +P 6050 3800 +F 0 "U1" H 6100 3900 30 0000 C CNN +F 1 "PORT" H 6050 3800 30 0000 C CNN +F 2 "" H 6050 3800 60 0000 C CNN +F 3 "" H 6050 3800 60 0000 C CNN + 4 6050 3800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5D0B5BF0 +P 5950 3350 +F 0 "U1" H 6000 3450 30 0000 C CNN +F 1 "PORT" H 5950 3350 30 0000 C CNN +F 2 "" H 5950 3350 60 0000 C CNN +F 3 "" H 5950 3350 60 0000 C CNN + 3 5950 3350 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D0B5EB6 +P 5500 3350 +F 0 "C1" H 5525 3450 50 0000 L CNN +F 1 "14n" H 5525 3250 50 0000 L CNN +F 2 "" H 5538 3200 30 0000 C CNN +F 3 "" H 5500 3350 60 0000 C CNN + 1 5500 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 3200 5500 3000 +Connection ~ 5500 3000 +Wire Wire Line + 5500 3500 5500 3800 +Wire Wire Line + 5250 3800 5800 3800 +Connection ~ 5250 3800 +Connection ~ 5500 3800 +Wire Wire Line + 5250 4350 4900 4350 +Wire Wire Line + 4900 4350 4900 3500 +Connection ~ 4900 3500 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sub b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sub new file mode 100644 index 00000000..4f386a6f --- /dev/null +++ b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sub @@ -0,0 +1,12 @@ +* Subcircuit opto_isolator_switch +.subckt opto_isolator_switch net-_r1-pad1_ net-_f1-pad4_ net-_c1-pad1_ net-_c1-pad2_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/opto_isolator_switch/opto_isolator_switch.cir +r1 net-_r1-pad1_ net-_f1-pad3_ 1000 +* f1 +r2 net-_c1-pad2_ net-_f1-pad4_ 1000 +c1 net-_c1-pad1_ net-_c1-pad2_ 14n +Vf1 net-_f1-pad3_ net-_f1-pad4_ 0 +f1 net-_c1-pad1_ net-_c1-pad2_ Vf1 3 +* Control Statements + +.ends opto_isolator_switch \ No newline at end of file diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch_Previous_Values.xml b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch_Previous_Values.xml new file mode 100644 index 00000000..2c2d65c1 --- /dev/null +++ b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/opto_isolator_switch/plot_data_i.txt b/src/SubcircuitLibrary/opto_isolator_switch/plot_data_i.txt new file mode 100644 index 00000000..e69de29b diff --git a/src/SubcircuitLibrary/opto_isolator_switch/plot_data_v.txt b/src/SubcircuitLibrary/opto_isolator_switch/plot_data_v.txt new file mode 100644 index 00000000..e69de29b diff --git a/src/SubcircuitLibrary/ujt/D.lib b/src/SubcircuitLibrary/ujt/D.lib new file mode 100644 index 00000000..8a7fb4da --- /dev/null +++ b/src/SubcircuitLibrary/ujt/D.lib @@ -0,0 +1,2 @@ +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/src/SubcircuitLibrary/ujt/analysis b/src/SubcircuitLibrary/ujt/analysis new file mode 100644 index 00000000..21dc4b94 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/analysis @@ -0,0 +1 @@ +.tran 5e-06 100e-03 0e-03 \ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/emitter.lib b/src/SubcircuitLibrary/ujt/emitter.lib new file mode 100644 index 00000000..3af759f4 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/emitter.lib @@ -0,0 +1,4 @@ +.MODEL emitter D( ++ Is=21.3P ++ N=1.8 +) \ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/plot_data_i.txt b/src/SubcircuitLibrary/ujt/plot_data_i.txt new file mode 100644 index 00000000..bb08d2c2 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/plot_data_i.txt @@ -0,0 +1,67 @@ + * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir + Transient Analysis Sat Jun 15 16:01:36 2019 +-------------------------------------------------------------------------------- +Index time h1#branch vh1#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 1.936296e-124 -1.93630e-121 +1 1.000000e-05 1.522607e-65 -1.52261e-62 +2 2.000000e-05 1.522589e-65 -1.52259e-62 +3 4.000000e-05 1.522545e-65 -1.52255e-62 +4 8.000000e-05 0.000000e+00 0.000000e+00 +5 1.600000e-04 0.000000e+00 0.000000e+00 +6 3.200000e-04 0.000000e+00 0.000000e+00 +7 6.400000e-04 0.000000e+00 0.000000e+00 +8 1.280000e-03 3.035283e-65 -3.03528e-62 +9 2.560000e-03 1.511759e-65 -1.51176e-62 +10 4.560000e-03 0.000000e+00 0.000000e+00 +11 6.560000e-03 0.000000e+00 0.000000e+00 +12 8.560000e-03 0.000000e+00 0.000000e+00 +13 1.056000e-02 0.000000e+00 0.000000e+00 +14 1.256000e-02 0.000000e+00 0.000000e+00 +15 1.456000e-02 0.000000e+00 0.000000e+00 +16 1.656000e-02 0.000000e+00 0.000000e+00 +17 1.856000e-02 0.000000e+00 0.000000e+00 +18 2.056000e-02 0.000000e+00 0.000000e+00 +19 2.256000e-02 0.000000e+00 0.000000e+00 +20 2.456000e-02 0.000000e+00 0.000000e+00 +21 2.656000e-02 0.000000e+00 0.000000e+00 +22 2.856000e-02 0.000000e+00 0.000000e+00 +23 3.056000e-02 0.000000e+00 0.000000e+00 +24 3.256000e-02 0.000000e+00 0.000000e+00 +25 3.456000e-02 0.000000e+00 0.000000e+00 +26 3.656000e-02 0.000000e+00 0.000000e+00 +27 3.856000e-02 0.000000e+00 0.000000e+00 +28 4.056000e-02 0.000000e+00 0.000000e+00 +29 4.256000e-02 0.000000e+00 0.000000e+00 +30 4.456000e-02 0.000000e+00 0.000000e+00 +31 4.656000e-02 0.000000e+00 0.000000e+00 +32 4.856000e-02 0.000000e+00 0.000000e+00 +33 5.056000e-02 0.000000e+00 0.000000e+00 +34 5.256000e-02 0.000000e+00 0.000000e+00 +35 5.456000e-02 0.000000e+00 0.000000e+00 +36 5.656000e-02 0.000000e+00 0.000000e+00 +37 5.856000e-02 0.000000e+00 0.000000e+00 +38 6.056000e-02 0.000000e+00 0.000000e+00 +39 6.256000e-02 0.000000e+00 0.000000e+00 +40 6.456000e-02 0.000000e+00 0.000000e+00 +41 6.656000e-02 0.000000e+00 0.000000e+00 +42 6.856000e-02 0.000000e+00 0.000000e+00 +43 7.056000e-02 0.000000e+00 0.000000e+00 +44 7.256000e-02 0.000000e+00 0.000000e+00 +45 7.456000e-02 0.000000e+00 0.000000e+00 +46 7.656000e-02 0.000000e+00 0.000000e+00 +47 7.856000e-02 0.000000e+00 0.000000e+00 +48 8.056000e-02 0.000000e+00 0.000000e+00 +49 8.256000e-02 0.000000e+00 0.000000e+00 +50 8.456000e-02 0.000000e+00 0.000000e+00 +51 8.656000e-02 0.000000e+00 0.000000e+00 +52 8.856000e-02 0.000000e+00 0.000000e+00 +53 9.056000e-02 0.000000e+00 0.000000e+00 +54 9.256000e-02 0.000000e+00 0.000000e+00 + +Index time h1#branch vh1#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 0.000000e+00 +56 9.656000e-02 0.000000e+00 0.000000e+00 +57 9.856000e-02 0.000000e+00 0.000000e+00 +58 1.000000e-01 3.640960e-66 -3.64096e-63 diff --git a/src/SubcircuitLibrary/ujt/plot_data_v.txt b/src/SubcircuitLibrary/ujt/plot_data_v.txt new file mode 100644 index 00000000..207ce5b7 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/plot_data_v.txt @@ -0,0 +1,203 @@ + * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir + Transient Analysis Sat Jun 15 16:01:36 2019 +-------------------------------------------------------------------------------- +Index time V(1) V(2) V(3) +-------------------------------------------------------------------------------- +0 0.000000e+00 6.088894e-52 -2.80622e-43 -2.80622e-43 +1 1.000000e-05 -2.51069e-46 -2.80871e-43 -2.80871e-43 +2 2.000000e-05 -2.51068e-46 -2.80868e-43 -2.80868e-43 +3 4.000000e-05 -2.51147e-46 -2.80860e-43 -2.80860e-43 +4 8.000000e-05 1.691803e-50 -2.80589e-43 -2.80589e-43 +5 1.600000e-04 -1.19543e-50 -2.80543e-43 -2.80543e-43 +6 3.200000e-04 -2.36974e-50 -2.80438e-43 -2.80438e-43 +7 6.400000e-04 4.520590e-52 -2.80203e-43 -2.80203e-43 +8 1.280000e-03 -2.71395e-46 -2.79955e-43 -2.79955e-43 +9 2.560000e-03 -3.13629e-46 -2.78870e-43 -2.78870e-43 +10 4.560000e-03 -5.10465e-52 -2.76667e-43 -2.76667e-43 +11 6.560000e-03 -2.20180e-52 -2.74650e-43 -2.74650e-43 +12 8.560000e-03 2.805351e-52 -2.72507e-43 -2.72507e-43 +13 1.056000e-02 -6.11918e-52 -2.70239e-43 -2.70239e-43 +14 1.256000e-02 -1.35091e-52 -2.67846e-43 -2.67846e-43 +15 1.456000e-02 6.127039e-53 -2.65331e-43 -2.65331e-43 +16 1.656000e-02 -6.60318e-52 -2.62693e-43 -2.62693e-43 +17 1.856000e-02 -2.70241e-52 -2.59936e-43 -2.59936e-43 +18 2.056000e-02 6.713684e-53 -2.57059e-43 -2.57059e-43 +19 2.256000e-02 -1.55773e-52 -2.54064e-43 -2.54064e-43 +20 2.456000e-02 3.929090e-53 -2.50953e-43 -2.50953e-43 +21 2.656000e-02 -5.71836e-52 -2.47727e-43 -2.47727e-43 +22 2.856000e-02 -1.42047e-52 -2.44388e-43 -2.44388e-43 +23 3.056000e-02 -4.85310e-52 -2.40937e-43 -2.40937e-43 +24 3.256000e-02 3.962144e-52 -2.37377e-43 -2.37377e-43 +25 3.456000e-02 -7.13895e-52 -2.33707e-43 -2.33707e-43 +26 3.656000e-02 -3.25981e-52 -2.29932e-43 -2.29932e-43 +27 3.856000e-02 -3.11521e-52 -2.26051e-43 -2.26051e-43 +28 4.056000e-02 2.279041e-52 -2.22068e-43 -2.22068e-43 +29 4.256000e-02 -4.09991e-52 -2.17983e-43 -2.17983e-43 +30 4.456000e-02 6.197036e-53 -2.13800e-43 -2.13800e-43 +31 4.656000e-02 -4.88067e-52 -2.09519e-43 -2.09519e-43 +32 4.856000e-02 -5.64247e-52 -2.05144e-43 -2.05144e-43 +33 5.056000e-02 -4.96151e-52 -2.00675e-43 -2.00675e-43 +34 5.256000e-02 -4.23061e-52 -1.96115e-43 -1.96115e-43 +35 5.456000e-02 2.057927e-52 -1.91467e-43 -1.91467e-43 +36 5.656000e-02 -6.33244e-52 -1.86732e-43 -1.86732e-43 +37 5.856000e-02 -3.34770e-52 -1.81913e-43 -1.81913e-43 +38 6.056000e-02 -2.07109e-52 -1.77011e-43 -1.77011e-43 +39 6.256000e-02 1.985474e-52 -1.72030e-43 -1.72030e-43 +40 6.456000e-02 -2.45836e-52 -1.66972e-43 -1.66972e-43 +41 6.656000e-02 -1.04902e-52 -1.61839e-43 -1.61839e-43 +42 6.856000e-02 -2.43454e-52 -1.56633e-43 -1.56633e-43 +43 7.056000e-02 -9.13597e-53 -1.51357e-43 -1.51357e-43 +44 7.256000e-02 -2.89902e-52 -1.46013e-43 -1.46013e-43 +45 7.456000e-02 -1.08625e-52 -1.40604e-43 -1.40604e-43 +46 7.656000e-02 -1.19143e-52 -1.35132e-43 -1.35132e-43 +47 7.856000e-02 -3.87284e-52 -1.29600e-43 -1.29600e-43 +48 8.056000e-02 -1.76399e-52 -1.24011e-43 -1.24011e-43 +49 8.256000e-02 9.167300e-53 -1.18367e-43 -1.18367e-43 +50 8.456000e-02 -1.40774e-52 -1.12671e-43 -1.12671e-43 +51 8.656000e-02 1.945441e-52 -1.06925e-43 -1.06925e-43 +52 8.856000e-02 -7.42845e-53 -1.01132e-43 -1.01132e-43 +53 9.056000e-02 -3.70259e-52 -9.52954e-44 -9.52954e-44 +54 9.256000e-02 -5.23530e-54 -8.94171e-44 -8.94171e-44 + +Index time V(1) V(2) V(3) +-------------------------------------------------------------------------------- +55 9.456000e-02 1.749423e-52 -8.35001e-44 -8.35001e-44 +56 9.656000e-02 -1.18682e-52 -7.75471e-44 -7.75471e-44 +57 9.856000e-02 -3.13438e-53 -7.15610e-44 -7.15610e-44 +58 1.000000e-01 6.326077e-47 -6.71639e-44 -6.71639e-44 + + * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir + Transient Analysis Sat Jun 15 16:01:36 2019 +-------------------------------------------------------------------------------- +Index time V(4) V(5) V(6) +-------------------------------------------------------------------------------- +0 0.000000e+00 -2.80622e-43 -2.80622e-43 -1.93630e-118 +1 1.000000e-05 -2.80871e-43 -2.80871e-43 -1.52261e-59 +2 2.000000e-05 -2.80868e-43 -2.80868e-43 -1.52259e-59 +3 4.000000e-05 -2.80860e-43 -2.80860e-43 -1.52255e-59 +4 8.000000e-05 -2.80589e-43 -2.80589e-43 0.000000e+00 +5 1.600000e-04 -2.80543e-43 -2.80543e-43 0.000000e+00 +6 3.200000e-04 -2.80438e-43 -2.80438e-43 0.000000e+00 +7 6.400000e-04 -2.80203e-43 -2.80203e-43 0.000000e+00 +8 1.280000e-03 -2.79955e-43 -2.79955e-43 -3.03528e-59 +9 2.560000e-03 -2.78870e-43 -2.78870e-43 -1.51176e-59 +10 4.560000e-03 -2.76667e-43 -2.76667e-43 0.000000e+00 +11 6.560000e-03 -2.74650e-43 -2.74650e-43 0.000000e+00 +12 8.560000e-03 -2.72507e-43 -2.72507e-43 0.000000e+00 +13 1.056000e-02 -2.70239e-43 -2.70239e-43 0.000000e+00 +14 1.256000e-02 -2.67846e-43 -2.67846e-43 0.000000e+00 +15 1.456000e-02 -2.65331e-43 -2.65331e-43 0.000000e+00 +16 1.656000e-02 -2.62693e-43 -2.62693e-43 0.000000e+00 +17 1.856000e-02 -2.59936e-43 -2.59936e-43 0.000000e+00 +18 2.056000e-02 -2.57059e-43 -2.57059e-43 0.000000e+00 +19 2.256000e-02 -2.54064e-43 -2.54064e-43 0.000000e+00 +20 2.456000e-02 -2.50953e-43 -2.50953e-43 0.000000e+00 +21 2.656000e-02 -2.47727e-43 -2.47727e-43 0.000000e+00 +22 2.856000e-02 -2.44388e-43 -2.44388e-43 0.000000e+00 +23 3.056000e-02 -2.40937e-43 -2.40937e-43 0.000000e+00 +24 3.256000e-02 -2.37377e-43 -2.37377e-43 0.000000e+00 +25 3.456000e-02 -2.33707e-43 -2.33707e-43 0.000000e+00 +26 3.656000e-02 -2.29932e-43 -2.29932e-43 0.000000e+00 +27 3.856000e-02 -2.26051e-43 -2.26051e-43 0.000000e+00 +28 4.056000e-02 -2.22068e-43 -2.22068e-43 0.000000e+00 +29 4.256000e-02 -2.17983e-43 -2.17983e-43 0.000000e+00 +30 4.456000e-02 -2.13800e-43 -2.13800e-43 0.000000e+00 +31 4.656000e-02 -2.09519e-43 -2.09519e-43 0.000000e+00 +32 4.856000e-02 -2.05144e-43 -2.05144e-43 0.000000e+00 +33 5.056000e-02 -2.00675e-43 -2.00675e-43 0.000000e+00 +34 5.256000e-02 -1.96115e-43 -1.96115e-43 0.000000e+00 +35 5.456000e-02 -1.91467e-43 -1.91467e-43 0.000000e+00 +36 5.656000e-02 -1.86732e-43 -1.86732e-43 0.000000e+00 +37 5.856000e-02 -1.81913e-43 -1.81913e-43 0.000000e+00 +38 6.056000e-02 -1.77011e-43 -1.77011e-43 0.000000e+00 +39 6.256000e-02 -1.72030e-43 -1.72030e-43 0.000000e+00 +40 6.456000e-02 -1.66972e-43 -1.66972e-43 0.000000e+00 +41 6.656000e-02 -1.61839e-43 -1.61839e-43 0.000000e+00 +42 6.856000e-02 -1.56633e-43 -1.56633e-43 0.000000e+00 +43 7.056000e-02 -1.51357e-43 -1.51357e-43 0.000000e+00 +44 7.256000e-02 -1.46013e-43 -1.46013e-43 0.000000e+00 +45 7.456000e-02 -1.40604e-43 -1.40604e-43 0.000000e+00 +46 7.656000e-02 -1.35132e-43 -1.35132e-43 0.000000e+00 +47 7.856000e-02 -1.29600e-43 -1.29600e-43 0.000000e+00 +48 8.056000e-02 -1.24011e-43 -1.24011e-43 0.000000e+00 +49 8.256000e-02 -1.18367e-43 -1.18367e-43 0.000000e+00 +50 8.456000e-02 -1.12671e-43 -1.12671e-43 0.000000e+00 +51 8.656000e-02 -1.06925e-43 -1.06925e-43 0.000000e+00 +52 8.856000e-02 -1.01132e-43 -1.01132e-43 0.000000e+00 +53 9.056000e-02 -9.52954e-44 -9.52954e-44 0.000000e+00 +54 9.256000e-02 -8.94171e-44 -8.94171e-44 0.000000e+00 + +Index time V(4) V(5) V(6) +-------------------------------------------------------------------------------- +55 9.456000e-02 -8.35001e-44 -8.35001e-44 0.000000e+00 +56 9.656000e-02 -7.75471e-44 -7.75471e-44 0.000000e+00 +57 9.856000e-02 -7.15610e-44 -7.15610e-44 0.000000e+00 +58 1.000000e-01 -6.71639e-44 -6.71639e-44 -3.64096e-60 + + * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir + Transient Analysis Sat Jun 15 16:01:36 2019 +-------------------------------------------------------------------------------- +Index time V(7) +-------------------------------------------------------------------------------- +0 0.000000e+00 -2.80622e-43 +1 1.000000e-05 -2.80871e-43 +2 2.000000e-05 -2.80868e-43 +3 4.000000e-05 -2.80860e-43 +4 8.000000e-05 -2.80589e-43 +5 1.600000e-04 -2.80543e-43 +6 3.200000e-04 -2.80438e-43 +7 6.400000e-04 -2.80203e-43 +8 1.280000e-03 -2.79955e-43 +9 2.560000e-03 -2.78870e-43 +10 4.560000e-03 -2.76667e-43 +11 6.560000e-03 -2.74650e-43 +12 8.560000e-03 -2.72507e-43 +13 1.056000e-02 -2.70239e-43 +14 1.256000e-02 -2.67846e-43 +15 1.456000e-02 -2.65331e-43 +16 1.656000e-02 -2.62693e-43 +17 1.856000e-02 -2.59936e-43 +18 2.056000e-02 -2.57059e-43 +19 2.256000e-02 -2.54064e-43 +20 2.456000e-02 -2.50953e-43 +21 2.656000e-02 -2.47727e-43 +22 2.856000e-02 -2.44388e-43 +23 3.056000e-02 -2.40937e-43 +24 3.256000e-02 -2.37377e-43 +25 3.456000e-02 -2.33707e-43 +26 3.656000e-02 -2.29932e-43 +27 3.856000e-02 -2.26051e-43 +28 4.056000e-02 -2.22068e-43 +29 4.256000e-02 -2.17983e-43 +30 4.456000e-02 -2.13800e-43 +31 4.656000e-02 -2.09519e-43 +32 4.856000e-02 -2.05144e-43 +33 5.056000e-02 -2.00675e-43 +34 5.256000e-02 -1.96115e-43 +35 5.456000e-02 -1.91467e-43 +36 5.656000e-02 -1.86732e-43 +37 5.856000e-02 -1.81913e-43 +38 6.056000e-02 -1.77011e-43 +39 6.256000e-02 -1.72030e-43 +40 6.456000e-02 -1.66972e-43 +41 6.656000e-02 -1.61839e-43 +42 6.856000e-02 -1.56633e-43 +43 7.056000e-02 -1.51357e-43 +44 7.256000e-02 -1.46013e-43 +45 7.456000e-02 -1.40604e-43 +46 7.656000e-02 -1.35132e-43 +47 7.856000e-02 -1.29600e-43 +48 8.056000e-02 -1.24011e-43 +49 8.256000e-02 -1.18367e-43 +50 8.456000e-02 -1.12671e-43 +51 8.656000e-02 -1.06925e-43 +52 8.856000e-02 -1.01132e-43 +53 9.056000e-02 -9.52954e-44 +54 9.256000e-02 -8.94171e-44 + +Index time V(7) +-------------------------------------------------------------------------------- +55 9.456000e-02 -8.35001e-44 +56 9.656000e-02 -7.75471e-44 +57 9.856000e-02 -7.15610e-44 +58 1.000000e-01 -6.71639e-44 diff --git a/src/SubcircuitLibrary/ujt/ujt-cache.lib b/src/SubcircuitLibrary/ujt/ujt-cache.lib new file mode 100644 index 00000000..e6fcb32b --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt-cache.lib @@ -0,0 +1,150 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# CCVS +# +DEF CCVS H 0 40 Y Y 1 F N +F0 "H" 0 150 50 H V C CNN +F1 "CCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# NLDS +# +DEF NLDS B 0 40 Y Y 1 F N +F0 "B" 0 0 60 H V C CNN +F1 "NLDS" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 0 141 0 1 0 N +X 1 1 0 350 200 D 50 50 1 1 B +X 2 2 0 -350 200 U 50 50 1 1 B +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/ujt/ujt.cir b/src/SubcircuitLibrary/ujt/ujt.cir new file mode 100644 index 00000000..017c4845 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.cir @@ -0,0 +1,18 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/ujt/ujt.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Jun 16 10:51:40 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R3 GND 6 1000k +C1 5 7 35p +R1 7 2 38.15 +R2 3 5 2.518k +U1 1 2 3 PORT +B1 5 7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6) +D1 1 4 eSim_Diode +H1 6 GND 4 5 1k + +.end diff --git a/src/SubcircuitLibrary/ujt/ujt.cir.out b/src/SubcircuitLibrary/ujt/ujt.cir.out new file mode 100644 index 00000000..c3186f1c --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.cir.out @@ -0,0 +1,22 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir + +.include emitter.lib +r3 gnd 6 1000k +c1 5 7 35p +r1 7 2 38.15 +r2 3 5 2.518k +* u1 1 2 3 port +b1 5 7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) +d1 1 4 emitter +* h1 +Vh1 4 5 0 +h1 6 gnd Vh1 1k +.tran 5e-06 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/ujt/ujt.pro b/src/SubcircuitLibrary/ujt/ujt.pro new file mode 100644 index 00000000..24c5e186 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.pro @@ -0,0 +1,44 @@ +update=Tue Jun 11 16:36:40 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User +LibName3=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName4=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName5=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName6=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName7=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName8=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName9=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName10=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName11=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog diff --git a/src/SubcircuitLibrary/ujt/ujt.sch b/src/SubcircuitLibrary/ujt/ujt.sch new file mode 100644 index 00000000..c1eb98f1 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.sch @@ -0,0 +1,205 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:ujt-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R3 +U 1 1 5CF5F733 +P 7400 2850 +F 0 "R3" H 7450 2980 50 0000 C CNN +F 1 "1000k" H 7450 2900 50 0000 C CNN +F 2 "" H 7450 2830 30 0000 C CNN +F 3 "" V 7450 2900 30 0000 C CNN + 1 7400 2850 + 0 1 -1 0 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CF61B3A +P 5150 4700 +F 0 "C1" H 5175 4800 50 0000 L CNN +F 1 "35p" H 5175 4600 50 0000 L CNN +F 2 "" H 5188 4550 30 0000 C CNN +F 3 "" H 5150 4700 60 0000 C CNN + 1 5150 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CF6211F +P 4300 4850 +F 0 "R1" H 4350 4980 50 0000 C CNN +F 1 "38.15" H 4350 4900 50 0000 C CNN +F 2 "" H 4350 4830 30 0000 C CNN +F 3 "" V 4350 4900 30 0000 C CNN + 1 4300 4850 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CF6218A +P 4550 3650 +F 0 "R2" H 4600 3780 50 0000 C CNN +F 1 "2.518k" H 4600 3700 50 0000 C CNN +F 2 "" H 4600 3630 30 0000 C CNN +F 3 "" V 4600 3700 30 0000 C CNN + 1 4550 3650 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF6830A +P 4250 4150 +F 0 "U1" H 4300 4250 30 0000 C CNN +F 1 "PORT" H 4250 4150 30 0000 C CNN +F 2 "" H 4250 4150 60 0000 C CNN +F 3 "" H 4250 4150 60 0000 C CNN + 2 4250 4150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF689AD +P 5950 1200 +F 0 "U1" H 6000 1300 30 0000 C CNN +F 1 "PORT" H 5950 1200 30 0000 C CNN +F 2 "" H 5950 1200 60 0000 C CNN +F 3 "" H 5950 1200 60 0000 C CNN + 1 5950 1200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF69586 +P 4600 3000 +F 0 "U1" H 4650 3100 30 0000 C CNN +F 1 "PORT" H 4600 3000 30 0000 C CNN +F 2 "" H 4600 3000 60 0000 C CNN +F 3 "" H 4600 3000 60 0000 C CNN + 3 4600 3000 + 0 1 1 0 +$EndComp +$Comp +L NLDS B1 +U 1 1 5CFD2C88 +P 5950 4800 +F 0 "B1" H 5950 4800 60 0000 C CNN +F 1 "I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)" H 7050 4900 60 0000 C CNN +F 2 "" H 5950 4800 60 0000 C CNN +F 3 "" H 5950 4800 60 0000 C CNN + 1 5950 4800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 5CFF8BB7 +P 5950 1850 +F 0 "D1" H 5950 1950 50 0000 C CNN +F 1 "eSim_Diode" H 5950 1750 50 0000 C CNN +F 2 "" H 5950 1850 60 0000 C CNN +F 3 "" H 5950 1850 60 0000 C CNN + 1 5950 1850 + 0 1 1 0 +$EndComp +Wire Wire Line + 6950 2500 7450 2500 +Wire Wire Line + 7450 2500 7450 2650 +Wire Wire Line + 6950 3100 7450 3100 +Wire Wire Line + 5950 1450 5950 1700 +Wire Wire Line + 5950 2000 5950 2750 +Wire Wire Line + 5950 2850 5950 4450 +Wire Wire Line + 5150 4100 5150 4550 +Wire Wire Line + 4600 4100 5950 4100 +Wire Wire Line + 5150 4850 5150 5250 +Wire Wire Line + 4250 5250 5950 5250 +Wire Wire Line + 4250 5250 4250 4950 +Wire Wire Line + 4600 4100 4600 3850 +Connection ~ 5150 4100 +Wire Wire Line + 4250 4650 4250 4400 +Wire Wire Line + 4600 3550 4600 3250 +Wire Wire Line + 5950 5250 5950 5150 +Connection ~ 5150 5250 +Wire Wire Line + 7450 3100 7450 2950 +Connection ~ 5950 4100 +$Comp +L CCVS H1 +U 1 1 5D04A7ED +P 6900 2800 +F 0 "H1" H 6900 2950 50 0000 C CNN +F 1 "1k" H 6700 2750 50 0000 C CNN +F 2 "" H 6900 2800 60 0000 C CNN +F 3 "" H 6900 2800 60 0000 C CNN + 1 6900 2800 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5D04C560 +P 7150 3150 +F 0 "#PWR01" H 7150 2900 50 0001 C CNN +F 1 "GND" H 7150 3000 50 0000 C CNN +F 2 "" H 7150 3150 50 0001 C CNN +F 3 "" H 7150 3150 50 0001 C CNN + 1 7150 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7150 3150 7150 3100 +Connection ~ 7150 3100 +Wire Wire Line + 5950 2750 6700 2750 +Wire Wire Line + 6700 2850 5950 2850 +Text GLabel 5950 1550 0 60 Input ~ 0 +1 +Text GLabel 5950 2200 0 60 Input ~ 0 +4 +Text GLabel 5950 3500 0 60 Input ~ 0 +5 +Text GLabel 5700 5250 3 60 Input ~ 0 +7 +Text GLabel 4250 4550 0 60 Input ~ 0 +2 +Text GLabel 4600 3350 0 60 Input ~ 0 +3 +Text GLabel 7200 2500 1 60 Input ~ 0 +6 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/ujt/ujt.sub b/src/SubcircuitLibrary/ujt/ujt.sub new file mode 100644 index 00000000..e86745b5 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.sub @@ -0,0 +1,16 @@ +* Subcircuit ujt +.subckt ujt 1 2 3 +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir +.include emitter.lib +r3 gnd 6 1000k +c1 5 7 35p +r1 7 2 38.15 +r2 3 5 2.518k +b1 5 7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) +d1 1 4 emitter +* h1 +Vh1 4 5 0 +h1 6 gnd Vh1 1k +* Control Statements + +.ends ujt \ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml b/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml new file mode 100644 index 00000000..993933d5 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">0</v1><ve1 name="Source type">0</ve1><i1 name="Source type">dc<field1 name="Value">0.000001m</field1></i1><v2 name="Source type">0</v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1></source><model /><devicemodel><d1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Diode/emitter.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file -- cgit