From acbec625b01f49d77386ed4196f7319ed94ab587 Mon Sep 17 00:00:00 2001 From: AmanShukla111 Date: Sun, 1 Jun 2025 19:51:16 +0530 Subject: Adding 74HC595-8-Bit Shift Registers With 3-State Output Registers --- .../SubcircuitLibrary/74HC595/74HC595-cache.lib | 91 ++++ library/SubcircuitLibrary/74HC595/74HC595.cir | 25 ++ library/SubcircuitLibrary/74HC595/74HC595.cir.out | 68 +++ library/SubcircuitLibrary/74HC595/74HC595.pro | 73 ++++ library/SubcircuitLibrary/74HC595/74HC595.sch | 479 +++++++++++++++++++++ library/SubcircuitLibrary/74HC595/74HC595.sub | 62 +++ .../74HC595/74HC595_Previous_Values.xml | 1 + library/SubcircuitLibrary/74HC595/analysis | 1 + 8 files changed, 800 insertions(+) create mode 100644 library/SubcircuitLibrary/74HC595/74HC595-cache.lib create mode 100644 library/SubcircuitLibrary/74HC595/74HC595.cir create mode 100644 library/SubcircuitLibrary/74HC595/74HC595.cir.out create mode 100644 library/SubcircuitLibrary/74HC595/74HC595.pro create mode 100644 library/SubcircuitLibrary/74HC595/74HC595.sch create mode 100644 library/SubcircuitLibrary/74HC595/74HC595.sub create mode 100644 library/SubcircuitLibrary/74HC595/74HC595_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/74HC595/analysis diff --git a/library/SubcircuitLibrary/74HC595/74HC595-cache.lib b/library/SubcircuitLibrary/74HC595/74HC595-cache.lib new file mode 100644 index 00000000..487b3c10 --- /dev/null +++ b/library/SubcircuitLibrary/74HC595/74HC595-cache.lib @@ -0,0 +1,91 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74HC595/74HC595.cir b/library/SubcircuitLibrary/74HC595/74HC595.cir new file mode 100644 index 00000000..c47a6ea2 --- /dev/null +++ b/library/SubcircuitLibrary/74HC595/74HC595.cir @@ -0,0 +1,25 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\serial_d_4\serial_d_4.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 3/30/2025 6:50:47 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad11_ Net-_U2-Pad2_ Net-_U3-Pad5_ ? d_dff +U5 Net-_U4-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad11_ Net-_U2-Pad2_ Net-_U5-Pad5_ ? d_dff +U6 Net-_U5-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad11_ Net-_U2-Pad2_ Net-_U1-Pad4_ ? d_dff +U7 Net-_U3-Pad5_ Net-_U1-Pad9_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U13-Pad1_ ? d_dff +U8 Net-_U4-Pad5_ Net-_U1-Pad9_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U14-Pad1_ ? d_dff +U9 Net-_U5-Pad5_ Net-_U1-Pad9_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad1_ ? d_dff +U10 Net-_U1-Pad4_ Net-_U1-Pad9_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U10-Pad5_ ? d_dff +U13 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U1-Pad7_ d_tristate +U14 Net-_U14-Pad1_ Net-_U11-Pad2_ Net-_U1-Pad8_ d_tristate +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U1-Pad5_ d_tristate +U12 Net-_U10-Pad5_ Net-_U11-Pad2_ Net-_U1-Pad6_ d_tristate +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT +U15 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter +U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter +U4 Net-_U3-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad11_ Net-_U2-Pad2_ Net-_U4-Pad5_ ? d_dff + +.end diff --git a/library/SubcircuitLibrary/74HC595/74HC595.cir.out b/library/SubcircuitLibrary/74HC595/74HC595.cir.out new file mode 100644 index 00000000..d4be2429 --- /dev/null +++ b/library/SubcircuitLibrary/74HC595/74HC595.cir.out @@ -0,0 +1,68 @@ +* c:\fossee\esim\library\subcircuitlibrary\serial_d_4\serial_d_4.cir + +* u3 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u3-pad5_ ? d_dff +* u5 net-_u4-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u5-pad5_ ? d_dff +* u6 net-_u5-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u1-pad4_ ? d_dff +* u7 net-_u3-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad1_ ? d_dff +* u8 net-_u4-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u14-pad1_ ? d_dff +* u9 net-_u5-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ ? d_dff +* u10 net-_u1-pad4_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad5_ ? d_dff +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u1-pad7_ d_tristate +* u14 net-_u14-pad1_ net-_u11-pad2_ net-_u1-pad8_ d_tristate +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad5_ d_tristate +* u12 net-_u10-pad5_ net-_u11-pad2_ net-_u1-pad6_ d_tristate +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port +* u15 net-_u1-pad10_ net-_u11-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u4 net-_u3-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u4-pad5_ ? d_dff +a1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u3-pad5_ ? u3 +a2 net-_u4-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u5-pad5_ ? u5 +a3 net-_u5-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u1-pad4_ ? u6 +a4 net-_u3-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad1_ ? u7 +a5 net-_u4-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u14-pad1_ ? u8 +a6 net-_u5-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ ? u9 +a7 net-_u1-pad4_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad5_ ? u10 +a8 net-_u13-pad1_ net-_u11-pad2_ net-_u1-pad7_ u13 +a9 net-_u14-pad1_ net-_u11-pad2_ net-_u1-pad8_ u14 +a10 net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad5_ u11 +a11 net-_u10-pad5_ net-_u11-pad2_ net-_u1-pad6_ u12 +a12 net-_u1-pad10_ net-_u11-pad2_ u15 +a13 net-_u1-pad2_ net-_u2-pad2_ u2 +a14 net-_u3-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u4-pad5_ ? u4 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74HC595/74HC595.pro b/library/SubcircuitLibrary/74HC595/74HC595.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/74HC595/74HC595.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74HC595/74HC595.sch b/library/SubcircuitLibrary/74HC595/74HC595.sch new file mode 100644 index 00000000..136a1953 --- /dev/null +++ b/library/SubcircuitLibrary/74HC595/74HC595.sch @@ -0,0 +1,479 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:serial_d_4-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U3 +U 1 1 67E7DBBC +P 2550 1350 +F 0 "U3" H 2550 1350 60 0000 C CNN +F 1 "d_dff" H 2550 1500 60 0000 C CNN +F 2 "" H 2550 1350 60 0000 C CNN +F 3 "" H 2550 1350 60 0000 C CNN + 1 2550 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U5 +U 1 1 67E7DC6C +P 2550 4900 +F 0 "U5" H 2550 4900 60 0000 C CNN +F 1 "d_dff" H 2550 5050 60 0000 C CNN +F 2 "" H 2550 4900 60 0000 C CNN +F 3 "" H 2550 4900 60 0000 C CNN + 1 2550 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U6 +U 1 1 67E7DCDE +P 2550 6700 +F 0 "U6" H 2550 6700 60 0000 C CNN +F 1 "d_dff" H 2550 6850 60 0000 C CNN +F 2 "" H 2550 6700 60 0000 C CNN +F 3 "" H 2550 6700 60 0000 C CNN + 1 2550 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U7 +U 1 1 67E7DDEF +P 4950 1350 +F 0 "U7" H 4950 1350 60 0000 C CNN +F 1 "d_dff" H 4950 1500 60 0000 C CNN +F 2 "" H 4950 1350 60 0000 C CNN +F 3 "" H 4950 1350 60 0000 C CNN + 1 4950 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U8 +U 1 1 67E7DE36 +P 4950 3150 +F 0 "U8" H 4950 3150 60 0000 C CNN +F 1 "d_dff" H 4950 3300 60 0000 C CNN +F 2 "" H 4950 3150 60 0000 C CNN +F 3 "" H 4950 3150 60 0000 C CNN + 1 4950 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U9 +U 1 1 67E7DE63 +P 4950 4900 +F 0 "U9" H 4950 4900 60 0000 C CNN +F 1 "d_dff" H 4950 5050 60 0000 C CNN +F 2 "" H 4950 4900 60 0000 C CNN +F 3 "" H 4950 4900 60 0000 C CNN + 1 4950 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U10 +U 1 1 67E7DE96 +P 4950 6700 +F 0 "U10" H 4950 6700 60 0000 C CNN +F 1 "d_dff" H 4950 6850 60 0000 C CNN +F 2 "" H 4950 6700 60 0000 C CNN +F 3 "" H 4950 6700 60 0000 C CNN + 1 4950 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U13 +U 1 1 67E7E539 +P 6850 1350 +F 0 "U13" H 6600 1600 60 0000 C CNN +F 1 "d_tristate" H 6650 1800 60 0000 C CNN +F 2 "" H 6750 1700 60 0000 C CNN +F 3 "" H 6750 1700 60 0000 C CNN + 1 6850 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U14 +U 1 1 67E7E5E0 +P 6850 3150 +F 0 "U14" H 6600 3400 60 0000 C CNN +F 1 "d_tristate" H 6650 3600 60 0000 C CNN +F 2 "" H 6750 3500 60 0000 C CNN +F 3 "" H 6750 3500 60 0000 C CNN + 1 6850 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U11 +U 1 1 67E7E617 +P 6800 4900 +F 0 "U11" H 6550 5150 60 0000 C CNN +F 1 "d_tristate" H 6600 5350 60 0000 C CNN +F 2 "" H 6700 5250 60 0000 C CNN +F 3 "" H 6700 5250 60 0000 C CNN + 1 6800 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U12 +U 1 1 67E7E9CB +P 6800 6700 +F 0 "U12" H 6550 6950 60 0000 C CNN +F 1 "d_tristate" H 6600 7150 60 0000 C CNN +F 2 "" H 6700 7050 60 0000 C CNN +F 3 "" H 6700 7050 60 0000 C CNN + 1 6800 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 67E7F8D1 +P 750 1650 +F 0 "U1" H 800 1750 30 0000 C CNN +F 1 "PORT" H 750 1650 30 0000 C CNN +F 2 "" H 750 1650 60 0000 C CNN +F 3 "" H 750 1650 60 0000 C CNN + 1 750 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67E80DFA +P 9350 2100 +F 0 "U1" H 9400 2200 30 0000 C CNN +F 1 "PORT" H 9350 2100 30 0000 C CNN +F 2 "" H 9350 2100 60 0000 C CNN +F 3 "" H 9350 2100 60 0000 C CNN + 9 9350 2100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 67E81E1B +P 10100 1600 +F 0 "U1" H 10150 1700 30 0000 C CNN +F 1 "PORT" H 10100 1600 30 0000 C CNN +F 2 "" H 10100 1600 60 0000 C CNN +F 3 "" H 10100 1600 60 0000 C CNN + 10 10100 1600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 67E83BEE +P 800 3050 +F 0 "U1" H 850 3150 30 0000 C CNN +F 1 "PORT" H 800 3050 30 0000 C CNN +F 2 "" H 800 3050 60 0000 C CNN +F 3 "" H 800 3050 60 0000 C CNN + 2 800 3050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 67E83DAD +P 1650 1000 +F 0 "U1" H 1700 1100 30 0000 C CNN +F 1 "PORT" H 1650 1000 30 0000 C CNN +F 2 "" H 1650 1000 60 0000 C CNN +F 3 "" H 1650 1000 60 0000 C CNN + 3 1650 1000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67E83EBA +P 3450 6800 +F 0 "U1" H 3500 6900 30 0000 C CNN +F 1 "PORT" H 3450 6800 30 0000 C CNN +F 2 "" H 3450 6800 60 0000 C CNN +F 3 "" H 3450 6800 60 0000 C CNN + 4 3450 6800 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 67E83F95 +P 7850 1000 +F 0 "U1" H 7900 1100 30 0000 C CNN +F 1 "PORT" H 7850 1000 30 0000 C CNN +F 2 "" H 7850 1000 60 0000 C CNN +F 3 "" H 7850 1000 60 0000 C CNN + 7 7850 1000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 67E84036 +P 7850 2800 +F 0 "U1" H 7900 2900 30 0000 C CNN +F 1 "PORT" H 7850 2800 30 0000 C CNN +F 2 "" H 7850 2800 60 0000 C CNN +F 3 "" H 7850 2800 60 0000 C CNN + 8 7850 2800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 67E8413E +P 7800 4550 +F 0 "U1" H 7850 4650 30 0000 C CNN +F 1 "PORT" H 7800 4550 30 0000 C CNN +F 2 "" H 7800 4550 60 0000 C CNN +F 3 "" H 7800 4550 60 0000 C CNN + 5 7800 4550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 67E841D1 +P 7800 6350 +F 0 "U1" H 7850 6450 30 0000 C CNN +F 1 "PORT" H 7800 6350 30 0000 C CNN +F 2 "" H 7800 6350 60 0000 C CNN +F 3 "" H 7800 6350 60 0000 C CNN + 6 7800 6350 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 67E84422 +P 9400 1600 +F 0 "U15" H 9400 1500 60 0000 C CNN +F 1 "d_inverter" H 9400 1750 60 0000 C CNN +F 2 "" H 9450 1550 60 0000 C CNN +F 3 "" H 9450 1550 60 0000 C CNN + 1 9400 1600 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 67E845AC +P 800 2350 +F 0 "U2" H 800 2250 60 0000 C CNN +F 1 "d_inverter" H 800 2500 60 0000 C CNN +F 2 "" H 850 2300 60 0000 C CNN +F 3 "" H 850 2300 60 0000 C CNN + 1 800 2350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3100 1000 4400 1000 +Wire Wire Line + 3100 2800 4400 2800 +Wire Wire Line + 3100 4550 4400 4550 +Wire Wire Line + 3100 6350 4400 6350 +Wire Wire Line + 2000 2800 2000 2300 +Wire Wire Line + 2000 2300 3650 2300 +Wire Wire Line + 3650 2300 3650 1000 +Connection ~ 3650 1000 +Wire Wire Line + 2000 4550 2000 3950 +Wire Wire Line + 2000 3950 3650 3950 +Wire Wire Line + 3650 3950 3650 2800 +Connection ~ 3650 2800 +Wire Wire Line + 2000 6350 2000 5750 +Wire Wire Line + 2000 5750 3650 5750 +Wire Wire Line + 3650 5750 3650 4550 +Connection ~ 3650 4550 +Wire Wire Line + 5500 6350 6200 6350 +Wire Wire Line + 5500 4550 6200 4550 +Wire Wire Line + 5500 1000 6250 1000 +Wire Wire Line + 5500 2800 6250 2800 +Wire Wire Line + 1000 1650 2000 1650 +Connection ~ 1350 1650 +Wire Wire Line + 1350 1650 1350 7000 +Wire Wire Line + 1350 7000 2000 7000 +Wire Wire Line + 2000 3450 1350 3450 +Connection ~ 1350 3450 +Wire Wire Line + 2000 5200 1350 5200 +Connection ~ 1350 5200 +Wire Wire Line + 9100 2100 4150 2100 +Wire Wire Line + 4150 1650 4150 7000 +Wire Wire Line + 4150 1650 4400 1650 +Connection ~ 4150 2100 +Wire Wire Line + 4150 7000 4400 7000 +Wire Wire Line + 4400 3450 4150 3450 +Connection ~ 4150 3450 +Wire Wire Line + 4400 5200 4150 5200 +Connection ~ 4150 5200 +Wire Wire Line + 9100 1600 9100 6650 +Wire Wire Line + 9100 6650 6750 6650 +Wire Wire Line + 6800 1300 6800 1750 +Wire Wire Line + 6800 1750 9100 1750 +Connection ~ 9100 1750 +Wire Wire Line + 6800 3100 9100 3100 +Connection ~ 9100 3100 +Wire Wire Line + 6750 4850 9100 4850 +Connection ~ 9100 4850 +Wire Wire Line + 1000 2050 1000 7300 +Wire Wire Line + 1000 7300 2550 7300 +Wire Wire Line + 2550 5500 1000 5500 +Connection ~ 1000 5500 +Wire Wire Line + 2550 3750 1000 3750 +Connection ~ 1000 3750 +Wire Wire Line + 2550 1950 2550 2200 +Wire Wire Line + 2550 2200 1000 2200 +Connection ~ 1000 2200 +Wire Wire Line + 1900 1000 2000 1000 +Wire Wire Line + 3450 6350 3450 6550 +Connection ~ 3450 6350 +Wire Wire Line + 7350 6350 7550 6350 +Wire Wire Line + 7350 4550 7550 4550 +Wire Wire Line + 7400 2800 7600 2800 +Wire Wire Line + 7400 1000 7600 1000 +Wire Wire Line + 9700 1600 9850 1600 +Wire Wire Line + 800 2050 1000 2050 +Wire Wire Line + 800 2650 800 2800 +$Comp +L d_dff U4 +U 1 1 67E7DC05 +P 2550 3150 +F 0 "U4" H 2550 3150 60 0000 C CNN +F 1 "d_dff" H 2550 3300 60 0000 C CNN +F 2 "" H 2550 3150 60 0000 C CNN +F 3 "" H 2550 3150 60 0000 C CNN + 1 2550 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 67E94DA5 +P 6050 7550 +F 0 "U1" H 6100 7650 30 0000 C CNN +F 1 "PORT" H 6050 7550 30 0000 C CNN +F 2 "" H 6050 7550 60 0000 C CNN +F 3 "" H 6050 7550 60 0000 C CNN + 11 6050 7550 + -1 0 0 1 +$EndComp +Wire Wire Line + 5800 7550 3900 7550 +Wire Wire Line + 3900 7550 3900 700 +Wire Wire Line + 2550 700 4950 700 +Connection ~ 3900 700 +Wire Wire Line + 4950 1950 3900 1950 +Connection ~ 3900 1950 +Wire Wire Line + 2550 2500 4950 2500 +Connection ~ 3900 2500 +Wire Wire Line + 4950 3750 3900 3750 +Connection ~ 3900 3750 +Wire Wire Line + 4950 4200 4950 4250 +Wire Wire Line + 4950 4200 3900 4200 +Connection ~ 3900 4200 +Wire Wire Line + 4950 5500 3900 5500 +Connection ~ 3900 5500 +Wire Wire Line + 2550 6050 4950 6050 +Connection ~ 3900 6050 +Wire Wire Line + 4950 7300 3900 7300 +Connection ~ 3900 7300 +Wire Wire Line + 2550 4250 3900 4250 +Connection ~ 3900 4250 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74HC595/74HC595.sub b/library/SubcircuitLibrary/74HC595/74HC595.sub new file mode 100644 index 00000000..d3065a50 --- /dev/null +++ b/library/SubcircuitLibrary/74HC595/74HC595.sub @@ -0,0 +1,62 @@ +* Subcircuit serial_d_4 +.subckt serial_d_4 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ +* c:\fossee\esim\library\subcircuitlibrary\serial_d_4\serial_d_4.cir +* u3 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u3-pad5_ ? d_dff +* u5 net-_u4-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u5-pad5_ ? d_dff +* u6 net-_u5-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u1-pad4_ ? d_dff +* u7 net-_u3-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad1_ ? d_dff +* u8 net-_u4-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u14-pad1_ ? d_dff +* u9 net-_u5-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ ? d_dff +* u10 net-_u1-pad4_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad5_ ? d_dff +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u1-pad7_ d_tristate +* u14 net-_u14-pad1_ net-_u11-pad2_ net-_u1-pad8_ d_tristate +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad5_ d_tristate +* u12 net-_u10-pad5_ net-_u11-pad2_ net-_u1-pad6_ d_tristate +* u15 net-_u1-pad10_ net-_u11-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u4 net-_u3-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u4-pad5_ ? d_dff +a1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u3-pad5_ ? u3 +a2 net-_u4-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u5-pad5_ ? u5 +a3 net-_u5-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u1-pad4_ ? u6 +a4 net-_u3-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad1_ ? u7 +a5 net-_u4-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u14-pad1_ ? u8 +a6 net-_u5-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ ? u9 +a7 net-_u1-pad4_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad5_ ? u10 +a8 net-_u13-pad1_ net-_u11-pad2_ net-_u1-pad7_ u13 +a9 net-_u14-pad1_ net-_u11-pad2_ net-_u1-pad8_ u14 +a10 net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad5_ u11 +a11 net-_u10-pad5_ net-_u11-pad2_ net-_u1-pad6_ u12 +a12 net-_u1-pad10_ net-_u11-pad2_ u15 +a13 net-_u1-pad2_ net-_u2-pad2_ u2 +a14 net-_u3-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u4-pad5_ ? u4 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends serial_d_4 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC595/74HC595_Previous_Values.xml b/library/SubcircuitLibrary/74HC595/74HC595_Previous_Values.xml new file mode 100644 index 00000000..c7725b32 --- /dev/null +++ b/library/SubcircuitLibrary/74HC595/74HC595_Previous_Values.xml @@ -0,0 +1 @@ +d_dffd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_tristated_tristated_tristated_tristated_inverterd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC595/analysis b/library/SubcircuitLibrary/74HC595/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74HC595/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit