From 7af669695786b5df3c1359dffc12ad9a41356f7d Mon Sep 17 00:00:00 2001
From: KARTHIKEYAN S
Date: Mon, 30 Jun 2025 15:28:20 +0530
Subject: Quadruple 2-Line to 1-Line Data Selectors/Multiplexers

---
 .../SN54LVC157A/SN54LVC157A-cache.lib              |  94 ++++
 .../SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir  |  28 ++
 .../SN54LVC157A/SN54LVC157A.cir.out                |  80 ++++
 .../SubcircuitLibrary/SN54LVC157A/SN54LVC157A.pro  |  73 +++
 .../SubcircuitLibrary/SN54LVC157A/SN54LVC157A.sch  | 512 +++++++++++++++++++++
 .../SubcircuitLibrary/SN54LVC157A/SN54LVC157A.sub  |  74 +++
 .../SN54LVC157A/SN54LVC157A_Previous_Values.xml    |   1 +
 library/SubcircuitLibrary/SN54LVC157A/analysis     |   1 +
 8 files changed, 863 insertions(+)
 create mode 100644 library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A-cache.lib
 create mode 100644 library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir
 create mode 100644 library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir.out
 create mode 100644 library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.pro
 create mode 100644 library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.sch
 create mode 100644 library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.sub
 create mode 100644 library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A_Previous_Values.xml
 create mode 100644 library/SubcircuitLibrary/SN54LVC157A/analysis

diff --git a/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A-cache.lib b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A-cache.lib
new file mode 100644
index 00000000..889b4267
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir
new file mode 100644
index 00000000..700f7f84
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir
@@ -0,0 +1,28 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN54LVC157A\SN54LVC157A.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/23/25 15:20:18
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U9  Net-_U1-Pad4_ Net-_U11-Pad2_ Net-_U16-Pad1_ d_and		
+U10  Net-_U1-Pad5_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and		
+U16  Net-_U16-Pad1_ Net-_U10-Pad3_ Net-_U1-Pad6_ d_or		
+U11  Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and		
+U12  Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U12-Pad3_ d_and		
+U17  Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad9_ d_or		
+U13  Net-_U1-Pad10_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and		
+U14  Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_and		
+U18  Net-_U13-Pad3_ Net-_U14-Pad3_ Net-_U1-Pad12_ d_or		
+U7  Net-_U1-Pad1_ Net-_U11-Pad2_ Net-_U15-Pad1_ d_and		
+U8  Net-_U1-Pad2_ Net-_U10-Pad2_ Net-_U15-Pad2_ d_and		
+U15  Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U1-Pad3_ d_or		
+U5  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U11-Pad2_ d_and		
+U6  Net-_U4-Pad2_ Net-_U1-Pad14_ Net-_U10-Pad2_ d_and		
+U2  Net-_U1-Pad13_ Net-_U2-Pad2_ d_inverter		
+U3  Net-_U1-Pad14_ Net-_U3-Pad2_ d_inverter		
+U4  Net-_U1-Pad13_ Net-_U4-Pad2_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir.out b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir.out
new file mode 100644
index 00000000..554080b1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.cir.out
@@ -0,0 +1,80 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn54lvc157a\sn54lvc157a.cir
+
+* u9  net-_u1-pad4_ net-_u11-pad2_ net-_u16-pad1_ d_and
+* u10  net-_u1-pad5_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u16  net-_u16-pad1_ net-_u10-pad3_ net-_u1-pad6_ d_or
+* u11  net-_u1-pad7_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u12  net-_u1-pad8_ net-_u10-pad2_ net-_u12-pad3_ d_and
+* u17  net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad9_ d_or
+* u13  net-_u1-pad10_ net-_u11-pad2_ net-_u13-pad3_ d_and
+* u14  net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ d_and
+* u18  net-_u13-pad3_ net-_u14-pad3_ net-_u1-pad12_ d_or
+* u7  net-_u1-pad1_ net-_u11-pad2_ net-_u15-pad1_ d_and
+* u8  net-_u1-pad2_ net-_u10-pad2_ net-_u15-pad2_ d_and
+* u15  net-_u15-pad1_ net-_u15-pad2_ net-_u1-pad3_ d_or
+* u5  net-_u2-pad2_ net-_u3-pad2_ net-_u11-pad2_ d_and
+* u6  net-_u4-pad2_ net-_u1-pad14_ net-_u10-pad2_ d_and
+* u2  net-_u1-pad13_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad14_ net-_u3-pad2_ d_inverter
+* u4  net-_u1-pad13_ net-_u4-pad2_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 [net-_u1-pad4_ net-_u11-pad2_ ] net-_u16-pad1_ u9
+a2 [net-_u1-pad5_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a3 [net-_u16-pad1_ net-_u10-pad3_ ] net-_u1-pad6_ u16
+a4 [net-_u1-pad7_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a5 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u12-pad3_ u12
+a6 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad9_ u17
+a7 [net-_u1-pad10_ net-_u11-pad2_ ] net-_u13-pad3_ u13
+a8 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u14-pad3_ u14
+a9 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u1-pad12_ u18
+a10 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u15-pad1_ u7
+a11 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u15-pad2_ u8
+a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u1-pad3_ u15
+a13 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u11-pad2_ u5
+a14 [net-_u4-pad2_ net-_u1-pad14_ ] net-_u10-pad2_ u6
+a15 net-_u1-pad13_ net-_u2-pad2_ u2
+a16 net-_u1-pad14_ net-_u3-pad2_ u3
+a17 net-_u1-pad13_ net-_u4-pad2_ u4
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.pro b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.sch b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.sch
new file mode 100644
index 00000000..717125ed
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.sch
@@ -0,0 +1,512 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U9
+U 1 1 68591A7D
+P 6000 2050
+F 0 "U9" H 6000 2050 60  0000 C CNN
+F 1 "d_and" H 6050 2150 60  0000 C CNN
+F 2 "" H 6000 2050 60  0000 C CNN
+F 3 "" H 6000 2050 60  0000 C CNN
+	1    6000 2050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U10
+U 1 1 68591AE6
+P 6000 2800
+F 0 "U10" H 6000 2800 60  0000 C CNN
+F 1 "d_and" H 6050 2900 60  0000 C CNN
+F 2 "" H 6000 2800 60  0000 C CNN
+F 3 "" H 6000 2800 60  0000 C CNN
+	1    6000 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U16
+U 1 1 68591B18
+P 7850 2350
+F 0 "U16" H 7850 2350 60  0000 C CNN
+F 1 "d_or" H 7850 2450 60  0000 C CNN
+F 2 "" H 7850 2350 60  0000 C CNN
+F 3 "" H 7850 2350 60  0000 C CNN
+	1    7850 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U11
+U 1 1 68591C0A
+P 6100 3400
+F 0 "U11" H 6100 3400 60  0000 C CNN
+F 1 "d_and" H 6150 3500 60  0000 C CNN
+F 2 "" H 6100 3400 60  0000 C CNN
+F 3 "" H 6100 3400 60  0000 C CNN
+	1    6100 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U12
+U 1 1 68591C10
+P 6100 4150
+F 0 "U12" H 6100 4150 60  0000 C CNN
+F 1 "d_and" H 6150 4250 60  0000 C CNN
+F 2 "" H 6100 4150 60  0000 C CNN
+F 3 "" H 6100 4150 60  0000 C CNN
+	1    6100 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U17
+U 1 1 68591C16
+P 7950 3700
+F 0 "U17" H 7950 3700 60  0000 C CNN
+F 1 "d_or" H 7950 3800 60  0000 C CNN
+F 2 "" H 7950 3700 60  0000 C CNN
+F 3 "" H 7950 3700 60  0000 C CNN
+	1    7950 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U13
+U 1 1 68591D55
+P 6200 4550
+F 0 "U13" H 6200 4550 60  0000 C CNN
+F 1 "d_and" H 6250 4650 60  0000 C CNN
+F 2 "" H 6200 4550 60  0000 C CNN
+F 3 "" H 6200 4550 60  0000 C CNN
+	1    6200 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U14
+U 1 1 68591D5B
+P 6200 5300
+F 0 "U14" H 6200 5300 60  0000 C CNN
+F 1 "d_and" H 6250 5400 60  0000 C CNN
+F 2 "" H 6200 5300 60  0000 C CNN
+F 3 "" H 6200 5300 60  0000 C CNN
+	1    6200 5300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U18
+U 1 1 68591D61
+P 8050 4850
+F 0 "U18" H 8050 4850 60  0000 C CNN
+F 1 "d_or" H 8050 4950 60  0000 C CNN
+F 2 "" H 8050 4850 60  0000 C CNN
+F 3 "" H 8050 4850 60  0000 C CNN
+	1    8050 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U7
+U 1 1 68591E52
+P 6000 1000
+F 0 "U7" H 6000 1000 60  0000 C CNN
+F 1 "d_and" H 6050 1100 60  0000 C CNN
+F 2 "" H 6000 1000 60  0000 C CNN
+F 3 "" H 6000 1000 60  0000 C CNN
+	1    6000 1000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U8
+U 1 1 68591E58
+P 6000 1750
+F 0 "U8" H 6000 1750 60  0000 C CNN
+F 1 "d_and" H 6050 1850 60  0000 C CNN
+F 2 "" H 6000 1750 60  0000 C CNN
+F 3 "" H 6000 1750 60  0000 C CNN
+	1    6000 1750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U15
+U 1 1 68591E5E
+P 7850 1300
+F 0 "U15" H 7850 1300 60  0000 C CNN
+F 1 "d_or" H 7850 1400 60  0000 C CNN
+F 2 "" H 7850 1300 60  0000 C CNN
+F 3 "" H 7850 1300 60  0000 C CNN
+	1    7850 1300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U5
+U 1 1 68591F04
+P 3600 6150
+F 0 "U5" H 3600 6150 60  0000 C CNN
+F 1 "d_and" H 3650 6250 60  0000 C CNN
+F 2 "" H 3600 6150 60  0000 C CNN
+F 3 "" H 3600 6150 60  0000 C CNN
+	1    3600 6150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U6
+U 1 1 68591FE5
+P 3600 6700
+F 0 "U6" H 3600 6700 60  0000 C CNN
+F 1 "d_and" H 3650 6800 60  0000 C CNN
+F 2 "" H 3600 6700 60  0000 C CNN
+F 3 "" H 3600 6700 60  0000 C CNN
+	1    3600 6700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 68592095
+P 2400 6050
+F 0 "U2" H 2400 5950 60  0000 C CNN
+F 1 "d_inverter" H 2400 6200 60  0000 C CNN
+F 2 "" H 2450 6000 60  0000 C CNN
+F 3 "" H 2450 6000 60  0000 C CNN
+	1    2400 6050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 68592131
+P 2400 6300
+F 0 "U3" H 2400 6200 60  0000 C CNN
+F 1 "d_inverter" H 2400 6450 60  0000 C CNN
+F 2 "" H 2450 6250 60  0000 C CNN
+F 3 "" H 2450 6250 60  0000 C CNN
+	1    2400 6300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 68592177
+P 2450 6600
+F 0 "U4" H 2450 6500 60  0000 C CNN
+F 1 "d_inverter" H 2450 6750 60  0000 C CNN
+F 2 "" H 2500 6550 60  0000 C CNN
+F 3 "" H 2500 6550 60  0000 C CNN
+	1    2450 6600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685927F2
+P 3400 3200
+F 0 "U1" H 3450 3300 30  0000 C CNN
+F 1 "PORT" H 3400 3200 30  0000 C CNN
+F 2 "" H 3400 3200 60  0000 C CNN
+F 3 "" H 3400 3200 60  0000 C CNN
+	7    3400 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68592D2B
+P 3500 4050
+F 0 "U1" H 3550 4150 30  0000 C CNN
+F 1 "PORT" H 3500 4050 30  0000 C CNN
+F 2 "" H 3500 4050 60  0000 C CNN
+F 3 "" H 3500 4050 60  0000 C CNN
+	8    3500 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68592E33
+P 9100 3600
+F 0 "U1" H 9150 3700 30  0000 C CNN
+F 1 "PORT" H 9100 3600 30  0000 C CNN
+F 2 "" H 9100 3600 60  0000 C CNN
+F 3 "" H 9100 3600 60  0000 C CNN
+	9    9100 3600
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68592E7A
+P 3100 1950
+F 0 "U1" H 3150 2050 30  0000 C CNN
+F 1 "PORT" H 3100 1950 30  0000 C CNN
+F 2 "" H 3100 1950 60  0000 C CNN
+F 3 "" H 3100 1950 60  0000 C CNN
+	4    3100 1950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68592ECF
+P 3250 2700
+F 0 "U1" H 3300 2800 30  0000 C CNN
+F 1 "PORT" H 3250 2700 30  0000 C CNN
+F 2 "" H 3250 2700 60  0000 C CNN
+F 3 "" H 3250 2700 60  0000 C CNN
+	5    3250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685930D2
+P 9150 2300
+F 0 "U1" H 9200 2400 30  0000 C CNN
+F 1 "PORT" H 9150 2300 30  0000 C CNN
+F 2 "" H 9150 2300 60  0000 C CNN
+F 3 "" H 9150 2300 60  0000 C CNN
+	6    9150 2300
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6859315B
+P 9300 1250
+F 0 "U1" H 9350 1350 30  0000 C CNN
+F 1 "PORT" H 9300 1250 30  0000 C CNN
+F 2 "" H 9300 1250 60  0000 C CNN
+F 3 "" H 9300 1250 60  0000 C CNN
+	3    9300 1250
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 10 1 68593284
+P 3650 4450
+F 0 "U1" H 3700 4550 30  0000 C CNN
+F 1 "PORT" H 3650 4450 30  0000 C CNN
+F 2 "" H 3650 4450 60  0000 C CNN
+F 3 "" H 3650 4450 60  0000 C CNN
+	10   3650 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68593403
+P 3200 900
+F 0 "U1" H 3250 1000 30  0000 C CNN
+F 1 "PORT" H 3200 900 30  0000 C CNN
+F 2 "" H 3200 900 60  0000 C CNN
+F 3 "" H 3200 900 60  0000 C CNN
+	1    3200 900 
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68593484
+P 3150 1600
+F 0 "U1" H 3200 1700 30  0000 C CNN
+F 1 "PORT" H 3150 1600 30  0000 C CNN
+F 2 "" H 3150 1600 60  0000 C CNN
+F 3 "" H 3150 1600 60  0000 C CNN
+	2    3150 1600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6859378C
+P 9200 4800
+F 0 "U1" H 9250 4900 30  0000 C CNN
+F 1 "PORT" H 9200 4800 30  0000 C CNN
+F 2 "" H 9200 4800 60  0000 C CNN
+F 3 "" H 9200 4800 60  0000 C CNN
+	12   9200 4800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685939AD
+P 3750 5200
+F 0 "U1" H 3800 5300 30  0000 C CNN
+F 1 "PORT" H 3750 5200 30  0000 C CNN
+F 2 "" H 3750 5200 60  0000 C CNN
+F 3 "" H 3750 5200 60  0000 C CNN
+	11   3750 5200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68593B88
+P 1000 6050
+F 0 "U1" H 1050 6150 30  0000 C CNN
+F 1 "PORT" H 1000 6050 30  0000 C CNN
+F 2 "" H 1000 6050 60  0000 C CNN
+F 3 "" H 1000 6050 60  0000 C CNN
+	13   1000 6050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 68593C95
+P 1000 6300
+F 0 "U1" H 1050 6400 30  0000 C CNN
+F 1 "PORT" H 1000 6300 30  0000 C CNN
+F 2 "" H 1000 6300 60  0000 C CNN
+F 3 "" H 1000 6300 60  0000 C CNN
+	14   1000 6300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6450 2000 6450 2250
+Wire Wire Line
+	6450 2250 7400 2250
+Wire Wire Line
+	6450 2750 6450 2350
+Wire Wire Line
+	6450 2350 7400 2350
+Wire Wire Line
+	6550 3350 6550 3600
+Wire Wire Line
+	6550 3600 7500 3600
+Wire Wire Line
+	6550 4100 6550 3700
+Wire Wire Line
+	6550 3700 7500 3700
+Wire Wire Line
+	6650 4500 6650 4750
+Wire Wire Line
+	6650 4750 7600 4750
+Wire Wire Line
+	6650 5250 6650 4850
+Wire Wire Line
+	6650 4850 7600 4850
+Wire Wire Line
+	6450 950  6450 1200
+Wire Wire Line
+	6450 1200 7400 1200
+Wire Wire Line
+	6450 1700 6450 1300
+Wire Wire Line
+	6450 1300 7400 1300
+Wire Wire Line
+	2750 6600 3150 6600
+Wire Wire Line
+	2700 6300 2700 6150
+Wire Wire Line
+	2700 6150 3150 6150
+Wire Wire Line
+	2700 6050 3150 6050
+Wire Wire Line
+	3450 900  5550 900 
+Wire Wire Line
+	5550 1650 3400 1650
+Wire Wire Line
+	3400 1650 3400 1600
+Wire Wire Line
+	5550 1950 3350 1950
+Wire Wire Line
+	5550 2700 3500 2700
+Wire Wire Line
+	3650 3200 5650 3200
+Wire Wire Line
+	5650 3200 5650 3300
+Wire Wire Line
+	5650 4050 3750 4050
+Wire Wire Line
+	5750 4450 3900 4450
+Wire Wire Line
+	5750 5200 4000 5200
+Wire Wire Line
+	1250 6050 2100 6050
+Wire Wire Line
+	2100 6300 1250 6300
+Wire Wire Line
+	1900 6050 1900 6600
+Wire Wire Line
+	1900 6600 2150 6600
+Connection ~ 1900 6050
+Wire Wire Line
+	1500 6700 3150 6700
+Wire Wire Line
+	1500 6700 1500 6300
+Connection ~ 1500 6300
+Wire Wire Line
+	5650 6650 4050 6650
+Wire Wire Line
+	5650 4150 5650 6650
+Wire Wire Line
+	5650 5300 5750 5300
+Connection ~ 5650 5300
+Wire Wire Line
+	5250 4150 5650 4150
+Wire Wire Line
+	5250 1750 5250 4150
+Wire Wire Line
+	5250 2800 5550 2800
+Wire Wire Line
+	5250 1750 5550 1750
+Connection ~ 5250 2800
+Wire Wire Line
+	5200 6100 4050 6100
+Wire Wire Line
+	5200 1000 5200 6100
+Wire Wire Line
+	5200 4550 5750 4550
+Wire Wire Line
+	5200 3400 5650 3400
+Connection ~ 5200 4550
+Wire Wire Line
+	5200 2050 5550 2050
+Connection ~ 5200 3400
+Wire Wire Line
+	5200 1000 5550 1000
+Connection ~ 5200 2050
+Wire Wire Line
+	8300 1250 9050 1250
+Wire Wire Line
+	8300 2300 8900 2300
+Wire Wire Line
+	8400 3650 8850 3650
+Wire Wire Line
+	8850 3650 8850 3600
+Wire Wire Line
+	8500 4800 8950 4800
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.sub b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.sub
new file mode 100644
index 00000000..982a7367
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A.sub
@@ -0,0 +1,74 @@
+* Subcircuit SN54LVC157A
+.subckt SN54LVC157A net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\fossee\esim\library\subcircuitlibrary\sn54lvc157a\sn54lvc157a.cir
+* u9  net-_u1-pad4_ net-_u11-pad2_ net-_u16-pad1_ d_and
+* u10  net-_u1-pad5_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u16  net-_u16-pad1_ net-_u10-pad3_ net-_u1-pad6_ d_or
+* u11  net-_u1-pad7_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u12  net-_u1-pad8_ net-_u10-pad2_ net-_u12-pad3_ d_and
+* u17  net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad9_ d_or
+* u13  net-_u1-pad10_ net-_u11-pad2_ net-_u13-pad3_ d_and
+* u14  net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ d_and
+* u18  net-_u13-pad3_ net-_u14-pad3_ net-_u1-pad12_ d_or
+* u7  net-_u1-pad1_ net-_u11-pad2_ net-_u15-pad1_ d_and
+* u8  net-_u1-pad2_ net-_u10-pad2_ net-_u15-pad2_ d_and
+* u15  net-_u15-pad1_ net-_u15-pad2_ net-_u1-pad3_ d_or
+* u5  net-_u2-pad2_ net-_u3-pad2_ net-_u11-pad2_ d_and
+* u6  net-_u4-pad2_ net-_u1-pad14_ net-_u10-pad2_ d_and
+* u2  net-_u1-pad13_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad14_ net-_u3-pad2_ d_inverter
+* u4  net-_u1-pad13_ net-_u4-pad2_ d_inverter
+a1 [net-_u1-pad4_ net-_u11-pad2_ ] net-_u16-pad1_ u9
+a2 [net-_u1-pad5_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a3 [net-_u16-pad1_ net-_u10-pad3_ ] net-_u1-pad6_ u16
+a4 [net-_u1-pad7_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a5 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u12-pad3_ u12
+a6 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad9_ u17
+a7 [net-_u1-pad10_ net-_u11-pad2_ ] net-_u13-pad3_ u13
+a8 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u14-pad3_ u14
+a9 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u1-pad12_ u18
+a10 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u15-pad1_ u7
+a11 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u15-pad2_ u8
+a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u1-pad3_ u15
+a13 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u11-pad2_ u5
+a14 [net-_u4-pad2_ net-_u1-pad14_ ] net-_u10-pad2_ u6
+a15 net-_u1-pad13_ net-_u2-pad2_ u2
+a16 net-_u1-pad14_ net-_u3-pad2_ u3
+a17 net-_u1-pad13_ net-_u4-pad2_ u4
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN54LVC157A
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A_Previous_Values.xml b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A_Previous_Values.xml
new file mode 100644
index 00000000..fa3f0aa8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54LVC157A/SN54LVC157A_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u9 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u16 name="type">d_or<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u16><u11 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u12><u17 name="type">d_or<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u14><u18 name="type">d_or<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u18><u7 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u8><u15 name="type">d_or<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u15><u5 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u6><u2 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54LVC157A/analysis b/library/SubcircuitLibrary/SN54LVC157A/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54LVC157A/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
-- 
cgit