From 5956f945cf4bd7a46b016c1cf1a60d96c586bc75 Mon Sep 17 00:00:00 2001 From: AmanShukla111 Date: Sun, 1 Jun 2025 19:46:23 +0530 Subject: Adding 74HC125-Quad Buffers with 3 State Outputs --- .../SubcircuitLibrary/74HC125/74HC125-cache.lib | 73 ++++++ library/SubcircuitLibrary/74HC125/74HC125.cir | 19 ++ library/SubcircuitLibrary/74HC125/74HC125.cir.out | 44 ++++ library/SubcircuitLibrary/74HC125/74HC125.pro | 73 ++++++ library/SubcircuitLibrary/74HC125/74HC125.sch | 280 +++++++++++++++++++++ library/SubcircuitLibrary/74HC125/74HC125.sub | 38 +++ .../74HC125/74HC125_Previous_Values.xml | 1 + library/SubcircuitLibrary/74HC125/analysis | 1 + 8 files changed, 529 insertions(+) create mode 100644 library/SubcircuitLibrary/74HC125/74HC125-cache.lib create mode 100644 library/SubcircuitLibrary/74HC125/74HC125.cir create mode 100644 library/SubcircuitLibrary/74HC125/74HC125.cir.out create mode 100644 library/SubcircuitLibrary/74HC125/74HC125.pro create mode 100644 library/SubcircuitLibrary/74HC125/74HC125.sch create mode 100644 library/SubcircuitLibrary/74HC125/74HC125.sub create mode 100644 library/SubcircuitLibrary/74HC125/74HC125_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/74HC125/analysis diff --git a/library/SubcircuitLibrary/74HC125/74HC125-cache.lib b/library/SubcircuitLibrary/74HC125/74HC125-cache.lib new file mode 100644 index 00000000..f8261399 --- /dev/null +++ b/library/SubcircuitLibrary/74HC125/74HC125-cache.lib @@ -0,0 +1,73 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74HC125/74HC125.cir b/library/SubcircuitLibrary/74HC125/74HC125.cir new file mode 100644 index 00000000..5fe521a1 --- /dev/null +++ b/library/SubcircuitLibrary/74HC125/74HC125.cir @@ -0,0 +1,19 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC125\74HC125.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 5/16/2025 10:09:01 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U1-Pad3_ Net-_U2-Pad2_ Net-_U1-Pad5_ d_tristate +U5 Net-_U1-Pad4_ Net-_U3-Pad2_ Net-_U1-Pad6_ d_tristate +U8 Net-_U1-Pad11_ Net-_U6-Pad2_ Net-_U1-Pad8_ d_tristate +U9 Net-_U1-Pad12_ Net-_U7-Pad2_ Net-_U1-Pad10_ d_tristate +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U6 Net-_U1-Pad7_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad9_ Net-_U7-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/74HC125/74HC125.cir.out b/library/SubcircuitLibrary/74HC125/74HC125.cir.out new file mode 100644 index 00000000..e5803879 --- /dev/null +++ b/library/SubcircuitLibrary/74HC125/74HC125.cir.out @@ -0,0 +1,44 @@ +* c:\fossee\esim\library\subcircuitlibrary\74hc125\74hc125.cir + +* u4 net-_u1-pad3_ net-_u2-pad2_ net-_u1-pad5_ d_tristate +* u5 net-_u1-pad4_ net-_u3-pad2_ net-_u1-pad6_ d_tristate +* u8 net-_u1-pad11_ net-_u6-pad2_ net-_u1-pad8_ d_tristate +* u9 net-_u1-pad12_ net-_u7-pad2_ net-_u1-pad10_ d_tristate +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u6 net-_u1-pad7_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad9_ net-_u7-pad2_ d_inverter +a1 net-_u1-pad3_ net-_u2-pad2_ net-_u1-pad5_ u4 +a2 net-_u1-pad4_ net-_u3-pad2_ net-_u1-pad6_ u5 +a3 net-_u1-pad11_ net-_u6-pad2_ net-_u1-pad8_ u8 +a4 net-_u1-pad12_ net-_u7-pad2_ net-_u1-pad10_ u9 +a5 net-_u1-pad1_ net-_u2-pad2_ u2 +a6 net-_u1-pad2_ net-_u3-pad2_ u3 +a7 net-_u1-pad7_ net-_u6-pad2_ u6 +a8 net-_u1-pad9_ net-_u7-pad2_ u7 +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74HC125/74HC125.pro b/library/SubcircuitLibrary/74HC125/74HC125.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/74HC125/74HC125.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74HC125/74HC125.sch b/library/SubcircuitLibrary/74HC125/74HC125.sch new file mode 100644 index 00000000..cb989e65 --- /dev/null +++ b/library/SubcircuitLibrary/74HC125/74HC125.sch @@ -0,0 +1,280 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_tristate U4 +U 1 1 682765A8 +P 3650 2800 +F 0 "U4" H 3400 3050 60 0000 C CNN +F 1 "d_tristate" H 3450 3250 60 0000 C CNN +F 2 "" H 3550 3150 60 0000 C CNN +F 3 "" H 3550 3150 60 0000 C CNN + 1 3650 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U5 +U 1 1 682765FE +P 3650 4450 +F 0 "U5" H 3400 4700 60 0000 C CNN +F 1 "d_tristate" H 3450 4900 60 0000 C CNN +F 2 "" H 3550 4800 60 0000 C CNN +F 3 "" H 3550 4800 60 0000 C CNN + 1 3650 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U8 +U 1 1 68276621 +P 7050 1950 +F 0 "U8" H 6800 2200 60 0000 C CNN +F 1 "d_tristate" H 6850 2400 60 0000 C CNN +F 2 "" H 6950 2300 60 0000 C CNN +F 3 "" H 6950 2300 60 0000 C CNN + 1 7050 1950 + -1 0 0 1 +$EndComp +$Comp +L d_tristate U9 +U 1 1 682766AC +P 7100 3700 +F 0 "U9" H 6850 3950 60 0000 C CNN +F 1 "d_tristate" H 6900 4150 60 0000 C CNN +F 2 "" H 7000 4050 60 0000 C CNN +F 3 "" H 7000 4050 60 0000 C CNN + 1 7100 3700 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68276705 +P 2700 2750 +F 0 "U2" H 2700 2650 60 0000 C CNN +F 1 "d_inverter" H 2700 2900 60 0000 C CNN +F 2 "" H 2750 2700 60 0000 C CNN +F 3 "" H 2750 2700 60 0000 C CNN + 1 2700 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2750 3600 2750 +$Comp +L PORT U1 +U 1 1 682767CD +P 2150 2750 +F 0 "U1" H 2200 2850 30 0000 C CNN +F 1 "PORT" H 2150 2750 30 0000 C CNN +F 2 "" H 2150 2750 60 0000 C CNN +F 3 "" H 2150 2750 60 0000 C CNN + 1 2150 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68276846 +P 2800 2450 +F 0 "U1" H 2850 2550 30 0000 C CNN +F 1 "PORT" H 2800 2450 30 0000 C CNN +F 2 "" H 2800 2450 60 0000 C CNN +F 3 "" H 2800 2450 60 0000 C CNN + 3 2800 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 682768BB +P 4450 2450 +F 0 "U1" H 4500 2550 30 0000 C CNN +F 1 "PORT" H 4450 2450 30 0000 C CNN +F 2 "" H 4450 2450 60 0000 C CNN +F 3 "" H 4450 2450 60 0000 C CNN + 5 4450 2450 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6827692E +P 2750 4400 +F 0 "U3" H 2750 4300 60 0000 C CNN +F 1 "d_inverter" H 2750 4550 60 0000 C CNN +F 2 "" H 2800 4350 60 0000 C CNN +F 3 "" H 2800 4350 60 0000 C CNN + 1 2750 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3050 4400 3600 4400 +$Comp +L PORT U1 +U 4 1 682769ED +P 2800 4100 +F 0 "U1" H 2850 4200 30 0000 C CNN +F 1 "PORT" H 2800 4100 30 0000 C CNN +F 2 "" H 2800 4100 60 0000 C CNN +F 3 "" H 2800 4100 60 0000 C CNN + 4 2800 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68276A5A +P 4450 4100 +F 0 "U1" H 4500 4200 30 0000 C CNN +F 1 "PORT" H 4450 4100 30 0000 C CNN +F 2 "" H 4450 4100 60 0000 C CNN +F 3 "" H 4450 4100 60 0000 C CNN + 6 4450 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 68276AB3 +P 2200 4400 +F 0 "U1" H 2250 4500 30 0000 C CNN +F 1 "PORT" H 2200 4400 30 0000 C CNN +F 2 "" H 2200 4400 60 0000 C CNN +F 3 "" H 2200 4400 60 0000 C CNN + 2 2200 4400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68276B0A +P 6800 2000 +F 0 "U6" H 6800 1900 60 0000 C CNN +F 1 "d_inverter" H 6800 2150 60 0000 C CNN +F 2 "" H 6850 1950 60 0000 C CNN +F 3 "" H 6850 1950 60 0000 C CNN + 1 6800 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68276B97 +P 6850 3750 +F 0 "U7" H 6850 3650 60 0000 C CNN +F 1 "d_inverter" H 6850 3900 60 0000 C CNN +F 2 "" H 6900 3700 60 0000 C CNN +F 3 "" H 6900 3700 60 0000 C CNN + 1 6850 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68276BD4 +P 6250 2000 +F 0 "U1" H 6300 2100 30 0000 C CNN +F 1 "PORT" H 6250 2000 30 0000 C CNN +F 2 "" H 6250 2000 60 0000 C CNN +F 3 "" H 6250 2000 60 0000 C CNN + 7 6250 2000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68276CC1 +P 6300 3750 +F 0 "U1" H 6350 3850 30 0000 C CNN +F 1 "PORT" H 6300 3750 30 0000 C CNN +F 2 "" H 6300 3750 60 0000 C CNN +F 3 "" H 6300 3750 60 0000 C CNN + 9 6300 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 68276D3E +P 7900 2300 +F 0 "U1" H 7950 2400 30 0000 C CNN +F 1 "PORT" H 7900 2300 30 0000 C CNN +F 2 "" H 7900 2300 60 0000 C CNN +F 3 "" H 7900 2300 60 0000 C CNN + 11 7900 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 68276DB4 +P 6250 2300 +F 0 "U1" H 6300 2400 30 0000 C CNN +F 1 "PORT" H 6250 2300 30 0000 C CNN +F 2 "" H 6250 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 8 6250 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 68276E19 +P 7950 4050 +F 0 "U1" H 8000 4150 30 0000 C CNN +F 1 "PORT" H 7950 4050 30 0000 C CNN +F 2 "" H 7950 4050 60 0000 C CNN +F 3 "" H 7950 4050 60 0000 C CNN + 12 7950 4050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 68276E94 +P 6300 4050 +F 0 "U1" H 6350 4150 30 0000 C CNN +F 1 "PORT" H 6300 4050 30 0000 C CNN +F 2 "" H 6300 4050 60 0000 C CNN +F 3 "" H 6300 4050 60 0000 C CNN + 10 6300 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74HC125/74HC125.sub b/library/SubcircuitLibrary/74HC125/74HC125.sub new file mode 100644 index 00000000..b4317883 --- /dev/null +++ b/library/SubcircuitLibrary/74HC125/74HC125.sub @@ -0,0 +1,38 @@ +* Subcircuit 74HC125 +.subckt 74HC125 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ +* c:\fossee\esim\library\subcircuitlibrary\74hc125\74hc125.cir +* u4 net-_u1-pad3_ net-_u2-pad2_ net-_u1-pad5_ d_tristate +* u5 net-_u1-pad4_ net-_u3-pad2_ net-_u1-pad6_ d_tristate +* u8 net-_u1-pad11_ net-_u6-pad2_ net-_u1-pad8_ d_tristate +* u9 net-_u1-pad12_ net-_u7-pad2_ net-_u1-pad10_ d_tristate +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u6 net-_u1-pad7_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad9_ net-_u7-pad2_ d_inverter +a1 net-_u1-pad3_ net-_u2-pad2_ net-_u1-pad5_ u4 +a2 net-_u1-pad4_ net-_u3-pad2_ net-_u1-pad6_ u5 +a3 net-_u1-pad11_ net-_u6-pad2_ net-_u1-pad8_ u8 +a4 net-_u1-pad12_ net-_u7-pad2_ net-_u1-pad10_ u9 +a5 net-_u1-pad1_ net-_u2-pad2_ u2 +a6 net-_u1-pad2_ net-_u3-pad2_ u3 +a7 net-_u1-pad7_ net-_u6-pad2_ u6 +a8 net-_u1-pad9_ net-_u7-pad2_ u7 +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74HC125 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC125/74HC125_Previous_Values.xml b/library/SubcircuitLibrary/74HC125/74HC125_Previous_Values.xml new file mode 100644 index 00000000..1b72f42c --- /dev/null +++ b/library/SubcircuitLibrary/74HC125/74HC125_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_tristated_tristated_tristated_tristated_inverterd_inverterd_inverterd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC125/analysis b/library/SubcircuitLibrary/74HC125/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74HC125/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit