From 432154bb698e2a47105af24d6f8dec44b04e06e3 Mon Sep 17 00:00:00 2001
From: AmanShukla111
Date: Sun, 1 Jun 2025 19:48:54 +0530
Subject: Adding 74HC175-Quad DFF with reset

---
 .../SubcircuitLibrary/74HC175/74HC175-cache.lib    |  76 +++++
 library/SubcircuitLibrary/74HC175/74HC175.cir      |  16 +
 library/SubcircuitLibrary/74HC175/74HC175.cir.out  |  32 ++
 library/SubcircuitLibrary/74HC175/74HC175.pro      |  73 +++++
 library/SubcircuitLibrary/74HC175/74HC175.sch      | 337 +++++++++++++++++++++
 library/SubcircuitLibrary/74HC175/74HC175.sub      |  26 ++
 .../74HC175/74HC175_Previous_Values.xml            |   1 +
 library/SubcircuitLibrary/74HC175/analysis         |   1 +
 8 files changed, 562 insertions(+)
 create mode 100644 library/SubcircuitLibrary/74HC175/74HC175-cache.lib
 create mode 100644 library/SubcircuitLibrary/74HC175/74HC175.cir
 create mode 100644 library/SubcircuitLibrary/74HC175/74HC175.cir.out
 create mode 100644 library/SubcircuitLibrary/74HC175/74HC175.pro
 create mode 100644 library/SubcircuitLibrary/74HC175/74HC175.sch
 create mode 100644 library/SubcircuitLibrary/74HC175/74HC175.sub
 create mode 100644 library/SubcircuitLibrary/74HC175/74HC175_Previous_Values.xml
 create mode 100644 library/SubcircuitLibrary/74HC175/analysis

diff --git a/library/SubcircuitLibrary/74HC175/74HC175-cache.lib b/library/SubcircuitLibrary/74HC175/74HC175-cache.lib
new file mode 100644
index 00000000..71585faf
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC175/74HC175-cache.lib
@@ -0,0 +1,76 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_dff
+#
+DEF d_dff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC175/74HC175.cir b/library/SubcircuitLibrary/74HC175/74HC175.cir
new file mode 100644
index 00000000..a56cd5c0
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC175/74HC175.cir
@@ -0,0 +1,16 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC175\74HC175.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 5/16/2025 9:47:11 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad15_ Net-_U2-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ d_dff		
+U3  Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad15_ Net-_U2-Pad4_ Net-_U1-Pad7_ Net-_U1-Pad8_ d_dff		
+U4  Net-_U1-Pad9_ Net-_U1-Pad1_ Net-_U1-Pad15_ Net-_U2-Pad4_ Net-_U1-Pad11_ Net-_U1-Pad12_ d_dff		
+U5  Net-_U1-Pad10_ Net-_U1-Pad1_ Net-_U1-Pad15_ Net-_U2-Pad4_ Net-_U1-Pad13_ Net-_U1-Pad14_ d_dff		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT		
+U6  Net-_U1-Pad2_ Net-_U2-Pad4_ d_inverter		
+
+.end
diff --git a/library/SubcircuitLibrary/74HC175/74HC175.cir.out b/library/SubcircuitLibrary/74HC175/74HC175.cir.out
new file mode 100644
index 00000000..4018e114
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC175/74HC175.cir.out
@@ -0,0 +1,32 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc175\74hc175.cir
+
+* u2  net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad5_ net-_u1-pad6_ d_dff
+* u3  net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad7_ net-_u1-pad8_ d_dff
+* u4  net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad11_ net-_u1-pad12_ d_dff
+* u5  net-_u1-pad10_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad13_ net-_u1-pad14_ d_dff
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port
+* u6  net-_u1-pad2_ net-_u2-pad4_ d_inverter
+a1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad5_ net-_u1-pad6_ u2
+a2 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad7_ net-_u1-pad8_ u3
+a3 net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad11_ net-_u1-pad12_ u4
+a4 net-_u1-pad10_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad13_ net-_u1-pad14_ u5
+a5 net-_u1-pad2_ net-_u2-pad4_ u6
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u2 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC175/74HC175.pro b/library/SubcircuitLibrary/74HC175/74HC175.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC175/74HC175.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC175/74HC175.sch b/library/SubcircuitLibrary/74HC175/74HC175.sch
new file mode 100644
index 00000000..7860f2b8
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC175/74HC175.sch
@@ -0,0 +1,337 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U2
+U 1 1 682760D2
+P 4650 2750
+F 0 "U2" H 4650 2750 60  0000 C CNN
+F 1 "d_dff" H 4650 2900 60  0000 C CNN
+F 2 "" H 4650 2750 60  0000 C CNN
+F 3 "" H 4650 2750 60  0000 C CNN
+	1    4650 2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U3
+U 1 1 6827626D
+P 4650 4700
+F 0 "U3" H 4650 4700 60  0000 C CNN
+F 1 "d_dff" H 4650 4850 60  0000 C CNN
+F 2 "" H 4650 4700 60  0000 C CNN
+F 3 "" H 4650 4700 60  0000 C CNN
+	1    4650 4700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U4
+U 1 1 6827628C
+P 6950 2750
+F 0 "U4" H 6950 2750 60  0000 C CNN
+F 1 "d_dff" H 6950 2900 60  0000 C CNN
+F 2 "" H 6950 2750 60  0000 C CNN
+F 3 "" H 6950 2750 60  0000 C CNN
+	1    6950 2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U5
+U 1 1 682762AB
+P 6950 4700
+F 0 "U5" H 6950 4700 60  0000 C CNN
+F 1 "d_dff" H 6950 4850 60  0000 C CNN
+F 2 "" H 6950 4700 60  0000 C CNN
+F 3 "" H 6950 4700 60  0000 C CNN
+	1    6950 4700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 682762D6
+P 1800 1500
+F 0 "U1" H 1850 1600 30  0000 C CNN
+F 1 "PORT" H 1800 1500 30  0000 C CNN
+F 2 "" H 1800 1500 60  0000 C CNN
+F 3 "" H 1800 1500 60  0000 C CNN
+	1    1800 1500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2050 1500 6000 1500
+Wire Wire Line
+	6000 1500 6000 5000
+Wire Wire Line
+	6000 5000 6400 5000
+Wire Wire Line
+	6400 3050 6000 3050
+Connection ~ 6000 3050
+Wire Wire Line
+	3550 1500 3550 5000
+Wire Wire Line
+	3550 5000 4100 5000
+Connection ~ 3550 1500
+Wire Wire Line
+	4100 3050 3550 3050
+Connection ~ 3550 3050
+$Comp
+L PORT U1
+U 2 1 68276396
+P 1300 6150
+F 0 "U1" H 1350 6250 30  0000 C CNN
+F 1 "PORT" H 1300 6150 30  0000 C CNN
+F 2 "" H 1300 6150 60  0000 C CNN
+F 3 "" H 1300 6150 60  0000 C CNN
+	2    1300 6150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2150 6150 3150 6150
+Wire Wire Line
+	3150 6150 3150 3600
+Wire Wire Line
+	3150 3600 6950 3600
+Wire Wire Line
+	6950 3600 6950 3350
+Wire Wire Line
+	4650 3350 4650 3600
+Connection ~ 4650 3600
+Wire Wire Line
+	3150 5600 6950 5600
+Wire Wire Line
+	6950 5600 6950 5300
+Connection ~ 3150 5600
+Wire Wire Line
+	4650 5300 4650 5600
+Connection ~ 4650 5600
+$Comp
+L PORT U1
+U 15 1 682764BF
+P 9450 1850
+F 0 "U1" H 9500 1950 30  0000 C CNN
+F 1 "PORT" H 9450 1850 30  0000 C CNN
+F 2 "" H 9450 1850 60  0000 C CNN
+F 3 "" H 9450 1850 60  0000 C CNN
+	15   9450 1850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	9200 1850 4650 1850
+Wire Wire Line
+	4650 1850 4650 2100
+Wire Wire Line
+	6950 2100 6950 1850
+Connection ~ 6950 1850
+Wire Wire Line
+	4650 4050 4650 3750
+Wire Wire Line
+	4650 3750 8400 3750
+Wire Wire Line
+	8400 3750 8400 1850
+Connection ~ 8400 1850
+Wire Wire Line
+	6950 4050 6950 3750
+Connection ~ 6950 3750
+$Comp
+L PORT U1
+U 3 1 68276668
+P 2600 2400
+F 0 "U1" H 2650 2500 30  0000 C CNN
+F 1 "PORT" H 2600 2400 30  0000 C CNN
+F 2 "" H 2600 2400 60  0000 C CNN
+F 3 "" H 2600 2400 60  0000 C CNN
+	3    2600 2400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2850 2400 4100 2400
+$Comp
+L PORT U1
+U 4 1 6827671C
+P 2600 4350
+F 0 "U1" H 2650 4450 30  0000 C CNN
+F 1 "PORT" H 2600 4350 30  0000 C CNN
+F 2 "" H 2600 4350 60  0000 C CNN
+F 3 "" H 2600 4350 60  0000 C CNN
+	4    2600 4350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2850 4350 4100 4350
+$Comp
+L PORT U1
+U 10 1 682767BE
+P 5800 4350
+F 0 "U1" H 5850 4450 30  0000 C CNN
+F 1 "PORT" H 5800 4350 30  0000 C CNN
+F 2 "" H 5800 4350 60  0000 C CNN
+F 3 "" H 5800 4350 60  0000 C CNN
+	10   5800 4350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6050 4350 6400 4350
+$Comp
+L PORT U1
+U 9 1 6827683C
+P 5800 2400
+F 0 "U1" H 5850 2500 30  0000 C CNN
+F 1 "PORT" H 5800 2400 30  0000 C CNN
+F 2 "" H 5800 2400 60  0000 C CNN
+F 3 "" H 5800 2400 60  0000 C CNN
+	9    5800 2400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6050 2400 6400 2400
+$Comp
+L PORT U1
+U 5 1 682768EC
+P 5450 2400
+F 0 "U1" H 5500 2500 30  0000 C CNN
+F 1 "PORT" H 5450 2400 30  0000 C CNN
+F 2 "" H 5450 2400 60  0000 C CNN
+F 3 "" H 5450 2400 60  0000 C CNN
+	5    5450 2400
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68276963
+P 5450 3050
+F 0 "U1" H 5500 3150 30  0000 C CNN
+F 1 "PORT" H 5450 3050 30  0000 C CNN
+F 2 "" H 5450 3050 60  0000 C CNN
+F 3 "" H 5450 3050 60  0000 C CNN
+	6    5450 3050
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 7 1 682769CC
+P 5450 4350
+F 0 "U1" H 5500 4450 30  0000 C CNN
+F 1 "PORT" H 5450 4350 30  0000 C CNN
+F 2 "" H 5450 4350 60  0000 C CNN
+F 3 "" H 5450 4350 60  0000 C CNN
+	7    5450 4350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68276A1B
+P 5450 5000
+F 0 "U1" H 5500 5100 30  0000 C CNN
+F 1 "PORT" H 5450 5000 30  0000 C CNN
+F 2 "" H 5450 5000 60  0000 C CNN
+F 3 "" H 5450 5000 60  0000 C CNN
+	8    5450 5000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68276A6A
+P 7750 2400
+F 0 "U1" H 7800 2500 30  0000 C CNN
+F 1 "PORT" H 7750 2400 30  0000 C CNN
+F 2 "" H 7750 2400 60  0000 C CNN
+F 3 "" H 7750 2400 60  0000 C CNN
+	11   7750 2400
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 12 1 68276AF3
+P 7750 3050
+F 0 "U1" H 7800 3150 30  0000 C CNN
+F 1 "PORT" H 7750 3050 30  0000 C CNN
+F 2 "" H 7750 3050 60  0000 C CNN
+F 3 "" H 7750 3050 60  0000 C CNN
+	12   7750 3050
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68276B68
+P 7750 4350
+F 0 "U1" H 7800 4450 30  0000 C CNN
+F 1 "PORT" H 7750 4350 30  0000 C CNN
+F 2 "" H 7750 4350 60  0000 C CNN
+F 3 "" H 7750 4350 60  0000 C CNN
+	13   7750 4350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 68276BD1
+P 7750 5000
+F 0 "U1" H 7800 5100 30  0000 C CNN
+F 1 "PORT" H 7750 5000 30  0000 C CNN
+F 2 "" H 7750 5000 60  0000 C CNN
+F 3 "" H 7750 5000 60  0000 C CNN
+	14   7750 5000
+	-1   0    0    1   
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 68277645
+P 1850 6150
+F 0 "U6" H 1850 6050 60  0000 C CNN
+F 1 "d_inverter" H 1850 6300 60  0000 C CNN
+F 2 "" H 1900 6100 60  0000 C CNN
+F 3 "" H 1900 6100 60  0000 C CNN
+	1    1850 6150
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC175/74HC175.sub b/library/SubcircuitLibrary/74HC175/74HC175.sub
new file mode 100644
index 00000000..fc8b08f7
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC175/74HC175.sub
@@ -0,0 +1,26 @@
+* Subcircuit 74HC175
+.subckt 74HC175 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ 
+* c:\fossee\esim\library\subcircuitlibrary\74hc175\74hc175.cir
+* u2  net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad5_ net-_u1-pad6_ d_dff
+* u3  net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad7_ net-_u1-pad8_ d_dff
+* u4  net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad11_ net-_u1-pad12_ d_dff
+* u5  net-_u1-pad10_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad13_ net-_u1-pad14_ d_dff
+* u6  net-_u1-pad2_ net-_u2-pad4_ d_inverter
+a1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad5_ net-_u1-pad6_ u2
+a2 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad7_ net-_u1-pad8_ u3
+a3 net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad11_ net-_u1-pad12_ u4
+a4 net-_u1-pad10_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad13_ net-_u1-pad14_ u5
+a5 net-_u1-pad2_ net-_u2-pad4_ u6
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u2 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC175
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC175/74HC175_Previous_Values.xml b/library/SubcircuitLibrary/74HC175/74HC175_Previous_Values.xml
new file mode 100644
index 00000000..1f11fdd7
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC175/74HC175_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_dff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for Data Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_dff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for Data Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_dff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for Data Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u4><u5 name="type">d_dff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for Data Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /><field43 name="Enter Input Load (default=1.0e-12)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC175/analysis b/library/SubcircuitLibrary/74HC175/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC175/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
-- 
cgit