From 42ff75fcbf7bc0ec42b054d0f7850b4ddddb3d63 Mon Sep 17 00:00:00 2001 From: E-KAMALESH Date: Sat, 5 Jul 2025 09:08:57 +0530 Subject: 1-of-10 (BCD-to-decimal) decoder 1-of-10 (BCD-to-decimal) decoder--- library/SubcircuitLibrary/DM9301/3_and-cache.lib | 61 ++ library/SubcircuitLibrary/DM9301/3_and.cir | 13 + library/SubcircuitLibrary/DM9301/3_and.cir.out | 20 + library/SubcircuitLibrary/DM9301/3_and.pro | 43 ++ library/SubcircuitLibrary/DM9301/3_and.sch | 130 ++++ library/SubcircuitLibrary/DM9301/3_and.sub | 14 + .../DM9301/3_and_Previous_Values.xml | 1 + library/SubcircuitLibrary/DM9301/4_and-cache.lib | 79 +++ library/SubcircuitLibrary/DM9301/4_and-rescue.lib | 22 + library/SubcircuitLibrary/DM9301/4_and.cir | 13 + library/SubcircuitLibrary/DM9301/4_and.cir.out | 18 + library/SubcircuitLibrary/DM9301/4_and.pro | 57 ++ library/SubcircuitLibrary/DM9301/4_and.sch | 151 +++++ library/SubcircuitLibrary/DM9301/4_and.sub | 12 + .../DM9301/4_and_Previous_Values.xml | 1 + library/SubcircuitLibrary/DM9301/9301-cache.lib | 77 +++ library/SubcircuitLibrary/DM9301/9301.cir | 39 ++ library/SubcircuitLibrary/DM9301/9301.cir.out | 95 +++ library/SubcircuitLibrary/DM9301/9301.pro | 73 +++ library/SubcircuitLibrary/DM9301/9301.sch | 698 +++++++++++++++++++++ library/SubcircuitLibrary/DM9301/9301.sub | 89 +++ .../DM9301/9301_Previous_Values.xml | 1 + library/SubcircuitLibrary/DM9301/analysis | 1 + 23 files changed, 1708 insertions(+) create mode 100644 library/SubcircuitLibrary/DM9301/3_and-cache.lib create mode 100644 library/SubcircuitLibrary/DM9301/3_and.cir create mode 100644 library/SubcircuitLibrary/DM9301/3_and.cir.out create mode 100644 library/SubcircuitLibrary/DM9301/3_and.pro create mode 100644 library/SubcircuitLibrary/DM9301/3_and.sch create mode 100644 library/SubcircuitLibrary/DM9301/3_and.sub create mode 100644 library/SubcircuitLibrary/DM9301/3_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/DM9301/4_and-cache.lib create mode 100644 library/SubcircuitLibrary/DM9301/4_and-rescue.lib create mode 100644 library/SubcircuitLibrary/DM9301/4_and.cir create mode 100644 library/SubcircuitLibrary/DM9301/4_and.cir.out create mode 100644 library/SubcircuitLibrary/DM9301/4_and.pro create mode 100644 library/SubcircuitLibrary/DM9301/4_and.sch create mode 100644 library/SubcircuitLibrary/DM9301/4_and.sub create mode 100644 library/SubcircuitLibrary/DM9301/4_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/DM9301/9301-cache.lib create mode 100644 library/SubcircuitLibrary/DM9301/9301.cir create mode 100644 library/SubcircuitLibrary/DM9301/9301.cir.out create mode 100644 library/SubcircuitLibrary/DM9301/9301.pro create mode 100644 library/SubcircuitLibrary/DM9301/9301.sch create mode 100644 library/SubcircuitLibrary/DM9301/9301.sub create mode 100644 library/SubcircuitLibrary/DM9301/9301_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/DM9301/analysis diff --git a/library/SubcircuitLibrary/DM9301/3_and-cache.lib b/library/SubcircuitLibrary/DM9301/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/DM9301/3_and.cir b/library/SubcircuitLibrary/DM9301/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/DM9301/3_and.cir.out b/library/SubcircuitLibrary/DM9301/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/DM9301/3_and.pro b/library/SubcircuitLibrary/DM9301/3_and.pro new file mode 100644 index 00000000..36e29799 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/DM9301/3_and.sch b/library/SubcircuitLibrary/DM9301/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/DM9301/3_and.sub b/library/SubcircuitLibrary/DM9301/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/DM9301/3_and_Previous_Values.xml b/library/SubcircuitLibrary/DM9301/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/DM9301/4_and-cache.lib b/library/SubcircuitLibrary/DM9301/4_and-cache.lib new file mode 100644 index 00000000..cb84d8f2 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/DM9301/4_and-rescue.lib b/library/SubcircuitLibrary/DM9301/4_and-rescue.lib new file mode 100644 index 00000000..6b2c17f7 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/DM9301/4_and.cir b/library/SubcircuitLibrary/DM9301/4_and.cir new file mode 100644 index 00000000..35e46097 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/DM9301/4_and.cir.out b/library/SubcircuitLibrary/DM9301/4_and.cir.out new file mode 100644 index 00000000..6e35b18a --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/DM9301/4_and.pro b/library/SubcircuitLibrary/DM9301/4_and.pro new file mode 100644 index 00000000..673ae0ac --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/DM9301/4_and.sch b/library/SubcircuitLibrary/DM9301/4_and.sch new file mode 100644 index 00000000..2d8296d4 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/DM9301/4_and.sub b/library/SubcircuitLibrary/DM9301/4_and.sub new file mode 100644 index 00000000..bf20b628 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/DM9301/4_and_Previous_Values.xml b/library/SubcircuitLibrary/DM9301/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/DM9301/9301-cache.lib b/library/SubcircuitLibrary/DM9301/9301-cache.lib new file mode 100644 index 00000000..a17518f5 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/9301-cache.lib @@ -0,0 +1,77 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/DM9301/9301.cir b/library/SubcircuitLibrary/DM9301/9301.cir new file mode 100644 index 00000000..4396a269 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/9301.cir @@ -0,0 +1,39 @@ +* C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\9301\9301.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/25 18:09:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U9-Pad1_ 4_and +U9 Net-_U9-Pad1_ Net-_U19-Pad13_ d_inverter +X2 Net-_U5-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad1_ 4_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +X3 Net-_U1-Pad2_ Net-_U6-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U11-Pad1_ 4_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +X4 Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U12-Pad1_ 4_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +X5 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_X5-Pad3_ Net-_U4-Pad2_ Net-_U13-Pad1_ 4_and +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +X6 Net-_U5-Pad2_ Net-_U2-Pad2_ Net-_X5-Pad3_ Net-_U4-Pad2_ Net-_U14-Pad1_ 4_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +X7 Net-_U1-Pad2_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U15-Pad1_ 4_and +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +X8 Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_X5-Pad3_ Net-_U4-Pad2_ Net-_U16-Pad1_ 4_and +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +X9 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U8-Pad2_ Net-_U17-Pad1_ 4_and +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter +X10 Net-_U5-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U8-Pad2_ Net-_U18-Pad1_ 4_and +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U5 Net-_U1-Pad2_ Net-_U5-Pad2_ d_inverter +U2 Net-_U19-Pad14_ Net-_U2-Pad2_ d_inverter +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ d_inverter +U3 Net-_U19-Pad1_ Net-_U3-Pad2_ d_inverter +U7 Net-_U3-Pad2_ Net-_U7-Pad2_ d_inverter +U4 Net-_U19-Pad2_ Net-_U4-Pad2_ d_inverter +U8 Net-_U4-Pad2_ Net-_U8-Pad2_ d_inverter +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U17-Pad2_ Net-_U18-Pad2_ ? Net-_U13-Pad2_ Net-_U12-Pad2_ Net-_U11-Pad2_ Net-_U10-Pad2_ Net-_U19-Pad13_ Net-_U19-Pad14_ Net-_U1-Pad1_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/DM9301/9301.cir.out b/library/SubcircuitLibrary/DM9301/9301.cir.out new file mode 100644 index 00000000..f5b3905e --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/9301.cir.out @@ -0,0 +1,95 @@ +* c:\users\public\music\fossee\esim\library\subcircuitlibrary\9301\9301.cir + +.include 4_and.sub +x1 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u9-pad1_ 4_and +* u9 net-_u9-pad1_ net-_u19-pad13_ d_inverter +x2 net-_u5-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u10-pad1_ 4_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +x3 net-_u1-pad2_ net-_u6-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u11-pad1_ 4_and +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +x4 net-_u5-pad2_ net-_u6-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u12-pad1_ 4_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +x5 net-_u1-pad2_ net-_u2-pad2_ net-_x5-pad3_ net-_u4-pad2_ net-_u13-pad1_ 4_and +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +x6 net-_u5-pad2_ net-_u2-pad2_ net-_x5-pad3_ net-_u4-pad2_ net-_u14-pad1_ 4_and +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +x7 net-_u1-pad2_ net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u15-pad1_ 4_and +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +x8 net-_u5-pad2_ net-_u6-pad2_ net-_x5-pad3_ net-_u4-pad2_ net-_u16-pad1_ 4_and +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +x9 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u17-pad1_ 4_and +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +x10 net-_u5-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u18-pad1_ 4_and +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u5 net-_u1-pad2_ net-_u5-pad2_ d_inverter +* u2 net-_u19-pad14_ net-_u2-pad2_ d_inverter +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u3 net-_u19-pad1_ net-_u3-pad2_ d_inverter +* u7 net-_u3-pad2_ net-_u7-pad2_ d_inverter +* u4 net-_u19-pad2_ net-_u4-pad2_ d_inverter +* u8 net-_u4-pad2_ net-_u8-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u17-pad2_ net-_u18-pad2_ ? net-_u13-pad2_ net-_u12-pad2_ net-_u11-pad2_ net-_u10-pad2_ net-_u19-pad13_ net-_u19-pad14_ net-_u1-pad1_ ? port +a1 net-_u9-pad1_ net-_u19-pad13_ u9 +a2 net-_u10-pad1_ net-_u10-pad2_ u10 +a3 net-_u11-pad1_ net-_u11-pad2_ u11 +a4 net-_u12-pad1_ net-_u12-pad2_ u12 +a5 net-_u13-pad1_ net-_u13-pad2_ u13 +a6 net-_u14-pad1_ net-_u14-pad2_ u14 +a7 net-_u15-pad1_ net-_u15-pad2_ u15 +a8 net-_u16-pad1_ net-_u16-pad2_ u16 +a9 net-_u17-pad1_ net-_u17-pad2_ u17 +a10 net-_u18-pad1_ net-_u18-pad2_ u18 +a11 net-_u1-pad1_ net-_u1-pad2_ u1 +a12 net-_u1-pad2_ net-_u5-pad2_ u5 +a13 net-_u19-pad14_ net-_u2-pad2_ u2 +a14 net-_u2-pad2_ net-_u6-pad2_ u6 +a15 net-_u19-pad1_ net-_u3-pad2_ u3 +a16 net-_u3-pad2_ net-_u7-pad2_ u7 +a17 net-_u19-pad2_ net-_u4-pad2_ u4 +a18 net-_u4-pad2_ net-_u8-pad2_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/DM9301/9301.pro b/library/SubcircuitLibrary/DM9301/9301.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/9301.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/DM9301/9301.sch b/library/SubcircuitLibrary/DM9301/9301.sch new file mode 100644 index 00000000..e2588a2b --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/9301.sch @@ -0,0 +1,698 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4_and X1 +U 1 1 6831B336 +P 4900 1050 +F 0 "X1" H 4950 1000 60 0000 C CNN +F 1 "4_and" H 5000 1150 60 0000 C CNN +F 2 "" H 4900 1050 60 0000 C CNN +F 3 "" H 4900 1050 60 0000 C CNN + 1 4900 1050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6831BD15 +P 5700 1050 +F 0 "U9" H 5700 950 60 0000 C CNN +F 1 "d_inverter" H 5700 1200 60 0000 C CNN +F 2 "" H 5750 1000 60 0000 C CNN +F 3 "" H 5750 1000 60 0000 C CNN + 1 5700 1050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 6831BF0B +P 4900 1800 +F 0 "X2" H 4950 1750 60 0000 C CNN +F 1 "4_and" H 5000 1900 60 0000 C CNN +F 2 "" H 4900 1800 60 0000 C CNN +F 3 "" H 4900 1800 60 0000 C CNN + 1 4900 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 6831BF11 +P 5700 1800 +F 0 "U10" H 5700 1700 60 0000 C CNN +F 1 "d_inverter" H 5700 1950 60 0000 C CNN +F 2 "" H 5750 1750 60 0000 C CNN +F 3 "" H 5750 1750 60 0000 C CNN + 1 5700 1800 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 6831BF7B +P 4900 2400 +F 0 "X3" H 4950 2350 60 0000 C CNN +F 1 "4_and" H 5000 2500 60 0000 C CNN +F 2 "" H 4900 2400 60 0000 C CNN +F 3 "" H 4900 2400 60 0000 C CNN + 1 4900 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 6831BF81 +P 5700 2400 +F 0 "U11" H 5700 2300 60 0000 C CNN +F 1 "d_inverter" H 5700 2550 60 0000 C CNN +F 2 "" H 5750 2350 60 0000 C CNN +F 3 "" H 5750 2350 60 0000 C CNN + 1 5700 2400 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 6831BF87 +P 4900 3150 +F 0 "X4" H 4950 3100 60 0000 C CNN +F 1 "4_and" H 5000 3250 60 0000 C CNN +F 2 "" H 4900 3150 60 0000 C CNN +F 3 "" H 4900 3150 60 0000 C CNN + 1 4900 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6831BF8D +P 5700 3150 +F 0 "U12" H 5700 3050 60 0000 C CNN +F 1 "d_inverter" H 5700 3300 60 0000 C CNN +F 2 "" H 5750 3100 60 0000 C CNN +F 3 "" H 5750 3100 60 0000 C CNN + 1 5700 3150 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 6831C17B +P 4900 3750 +F 0 "X5" H 4950 3700 60 0000 C CNN +F 1 "4_and" H 5000 3850 60 0000 C CNN +F 2 "" H 4900 3750 60 0000 C CNN +F 3 "" H 4900 3750 60 0000 C CNN + 1 4900 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 6831C181 +P 5700 3750 +F 0 "U13" H 5700 3650 60 0000 C CNN +F 1 "d_inverter" H 5700 3900 60 0000 C CNN +F 2 "" H 5750 3700 60 0000 C CNN +F 3 "" H 5750 3700 60 0000 C CNN + 1 5700 3750 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 6831C187 +P 4900 4500 +F 0 "X6" H 4950 4450 60 0000 C CNN +F 1 "4_and" H 5000 4600 60 0000 C CNN +F 2 "" H 4900 4500 60 0000 C CNN +F 3 "" H 4900 4500 60 0000 C CNN + 1 4900 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 6831C18D +P 5700 4500 +F 0 "U14" H 5700 4400 60 0000 C CNN +F 1 "d_inverter" H 5700 4650 60 0000 C CNN +F 2 "" H 5750 4450 60 0000 C CNN +F 3 "" H 5750 4450 60 0000 C CNN + 1 5700 4500 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 6831C193 +P 4900 5100 +F 0 "X7" H 4950 5050 60 0000 C CNN +F 1 "4_and" H 5000 5200 60 0000 C CNN +F 2 "" H 4900 5100 60 0000 C CNN +F 3 "" H 4900 5100 60 0000 C CNN + 1 4900 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 6831C199 +P 5700 5100 +F 0 "U15" H 5700 5000 60 0000 C CNN +F 1 "d_inverter" H 5700 5250 60 0000 C CNN +F 2 "" H 5750 5050 60 0000 C CNN +F 3 "" H 5750 5050 60 0000 C CNN + 1 5700 5100 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X8 +U 1 1 6831C19F +P 4900 5850 +F 0 "X8" H 4950 5800 60 0000 C CNN +F 1 "4_and" H 5000 5950 60 0000 C CNN +F 2 "" H 4900 5850 60 0000 C CNN +F 3 "" H 4900 5850 60 0000 C CNN + 1 4900 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6831C1A5 +P 5700 5850 +F 0 "U16" H 5700 5750 60 0000 C CNN +F 1 "d_inverter" H 5700 6000 60 0000 C CNN +F 2 "" H 5750 5800 60 0000 C CNN +F 3 "" H 5750 5800 60 0000 C CNN + 1 5700 5850 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X9 +U 1 1 6831C2F7 +P 4950 6400 +F 0 "X9" H 5000 6350 60 0000 C CNN +F 1 "4_and" H 5050 6500 60 0000 C CNN +F 2 "" H 4950 6400 60 0000 C CNN +F 3 "" H 4950 6400 60 0000 C CNN + 1 4950 6400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 6831C2FD +P 5750 6400 +F 0 "U17" H 5750 6300 60 0000 C CNN +F 1 "d_inverter" H 5750 6550 60 0000 C CNN +F 2 "" H 5800 6350 60 0000 C CNN +F 3 "" H 5800 6350 60 0000 C CNN + 1 5750 6400 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X10 +U 1 1 6831C303 +P 4950 7150 +F 0 "X10" H 5000 7100 60 0000 C CNN +F 1 "4_and" H 5050 7250 60 0000 C CNN +F 2 "" H 4950 7150 60 0000 C CNN +F 3 "" H 4950 7150 60 0000 C CNN + 1 4950 7150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 6831C309 +P 5750 7150 +F 0 "U18" H 5750 7050 60 0000 C CNN +F 1 "d_inverter" H 5750 7300 60 0000 C CNN +F 2 "" H 5800 7100 60 0000 C CNN +F 3 "" H 5800 7100 60 0000 C CNN + 1 5750 7150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 6831C645 +P 1700 1100 +F 0 "U1" H 1700 1000 60 0000 C CNN +F 1 "d_inverter" H 1700 1250 60 0000 C CNN +F 2 "" H 1750 1050 60 0000 C CNN +F 3 "" H 1750 1050 60 0000 C CNN + 1 1700 1100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6831C787 +P 2550 1750 +F 0 "U5" H 2550 1650 60 0000 C CNN +F 1 "d_inverter" H 2550 1900 60 0000 C CNN +F 2 "" H 2600 1700 60 0000 C CNN +F 3 "" H 2600 1700 60 0000 C CNN + 1 2550 1750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6831C828 +P 1700 2900 +F 0 "U2" H 1700 2800 60 0000 C CNN +F 1 "d_inverter" H 1700 3050 60 0000 C CNN +F 2 "" H 1750 2850 60 0000 C CNN +F 3 "" H 1750 2850 60 0000 C CNN + 1 1700 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6831C82E +P 2550 3550 +F 0 "U6" H 2550 3450 60 0000 C CNN +F 1 "d_inverter" H 2550 3700 60 0000 C CNN +F 2 "" H 2600 3500 60 0000 C CNN +F 3 "" H 2600 3500 60 0000 C CNN + 1 2550 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6831C88E +P 1850 4650 +F 0 "U3" H 1850 4550 60 0000 C CNN +F 1 "d_inverter" H 1850 4800 60 0000 C CNN +F 2 "" H 1900 4600 60 0000 C CNN +F 3 "" H 1900 4600 60 0000 C CNN + 1 1850 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6831C894 +P 2700 5200 +F 0 "U7" H 2700 5100 60 0000 C CNN +F 1 "d_inverter" H 2700 5350 60 0000 C CNN +F 2 "" H 2750 5150 60 0000 C CNN +F 3 "" H 2750 5150 60 0000 C CNN + 1 2700 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6831C9A0 +P 2000 6000 +F 0 "U4" H 2000 5900 60 0000 C CNN +F 1 "d_inverter" H 2000 6150 60 0000 C CNN +F 2 "" H 2050 5950 60 0000 C CNN +F 3 "" H 2050 5950 60 0000 C CNN + 1 2000 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6831C9A6 +P 2850 6600 +F 0 "U8" H 2850 6500 60 0000 C CNN +F 1 "d_inverter" H 2850 6750 60 0000 C CNN +F 2 "" H 2900 6550 60 0000 C CNN +F 3 "" H 2900 6550 60 0000 C CNN + 1 2850 6600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4500 900 3500 900 +Wire Wire Line + 4500 2250 3500 2250 +Connection ~ 3500 2250 +Wire Wire Line + 3500 3600 4500 3600 +Connection ~ 3500 3600 +Wire Wire Line + 3500 4950 4500 4950 +Connection ~ 3500 4950 +Wire Wire Line + 3500 900 3500 6250 +Wire Wire Line + 3500 6250 4550 6250 +Wire Wire Line + 4500 1000 3900 1000 +Wire Wire Line + 3900 1000 3900 7100 +Wire Wire Line + 3900 1750 4500 1750 +Wire Wire Line + 3900 3700 4500 3700 +Connection ~ 3900 1750 +Wire Wire Line + 3900 4450 4500 4450 +Connection ~ 3900 3700 +Wire Wire Line + 3900 6350 4550 6350 +Connection ~ 3900 4450 +Wire Wire Line + 3900 7100 4550 7100 +Connection ~ 3900 6350 +Wire Wire Line + 4500 1100 4100 1100 +Wire Wire Line + 4100 1100 4100 7200 +Wire Wire Line + 4100 1850 4500 1850 +Wire Wire Line + 4100 2450 4500 2450 +Connection ~ 4100 1850 +Wire Wire Line + 4100 3200 4500 3200 +Connection ~ 4100 2450 +Wire Wire Line + 4100 6450 4550 6450 +Connection ~ 4100 3200 +Wire Wire Line + 4100 7200 4550 7200 +Connection ~ 4100 6450 +Wire Wire Line + 4500 1200 4300 1200 +Wire Wire Line + 4300 1200 4300 6000 +Wire Wire Line + 4300 1950 4500 1950 +Wire Wire Line + 4300 2550 4500 2550 +Connection ~ 4300 1950 +Wire Wire Line + 4300 3300 4500 3300 +Connection ~ 4300 2550 +Wire Wire Line + 4300 3900 4500 3900 +Connection ~ 4300 3300 +Wire Wire Line + 4300 4650 4500 4650 +Connection ~ 4300 3900 +Wire Wire Line + 4300 5250 4500 5250 +Connection ~ 4300 4650 +Wire Wire Line + 2300 6000 4500 6000 +Connection ~ 4300 5250 +Wire Wire Line + 4500 1650 3650 1650 +Wire Wire Line + 3650 1650 3650 7000 +Wire Wire Line + 3650 3000 4500 3000 +Wire Wire Line + 3650 4350 4500 4350 +Connection ~ 3650 3000 +Wire Wire Line + 3650 5700 4500 5700 +Connection ~ 3650 4350 +Wire Wire Line + 3650 7000 4550 7000 +Connection ~ 3650 5700 +Wire Wire Line + 4500 2350 3800 2350 +Wire Wire Line + 3800 2350 3800 5800 +Wire Wire Line + 3800 3100 4500 3100 +Wire Wire Line + 3800 5050 4500 5050 +Connection ~ 3800 3100 +Wire Wire Line + 3800 5800 4500 5800 +Connection ~ 3800 5050 +Wire Wire Line + 4200 3800 4200 5900 +Wire Wire Line + 4500 3800 4200 3800 +Wire Wire Line + 4200 4550 4500 4550 +Wire Wire Line + 4200 5900 4500 5900 +Connection ~ 4200 4550 +Wire Wire Line + 3000 5200 4500 5200 +Wire Wire Line + 4500 5200 4500 5150 +Wire Wire Line + 4550 7300 4550 6550 +Wire Wire Line + 3150 6600 4550 6600 +Connection ~ 4550 6600 +Connection ~ 4300 6000 +Wire Wire Line + 2550 6600 2550 6000 +Connection ~ 2550 6000 +Wire Wire Line + 4100 4550 2150 4550 +Wire Wire Line + 2150 4550 2150 4650 +Connection ~ 4100 4550 +Wire Wire Line + 2400 5200 2400 4550 +Connection ~ 2400 4550 +Wire Wire Line + 3800 3550 2850 3550 +Connection ~ 3800 3550 +Wire Wire Line + 3900 2750 2000 2750 +Wire Wire Line + 2000 2750 2000 2900 +Connection ~ 3900 2750 +Wire Wire Line + 2250 3550 2250 2750 +Connection ~ 2250 2750 +Wire Wire Line + 2850 1750 3650 1750 +Connection ~ 3650 1750 +Wire Wire Line + 2000 1100 3500 1100 +Connection ~ 3500 1100 +Wire Wire Line + 2250 1750 2250 1100 +Connection ~ 2250 1100 +$Comp +L PORT U19 +U 6 1 68326CDB +P 6300 6400 +F 0 "U19" H 6350 6500 30 0000 C CNN +F 1 "PORT" H 6300 6400 30 0000 C CNN +F 2 "" H 6300 6400 60 0000 C CNN +F 3 "" H 6300 6400 60 0000 C CNN + 6 6300 6400 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 4 1 68326D2A +P 6250 5100 +F 0 "U19" H 6300 5200 30 0000 C CNN +F 1 "PORT" H 6250 5100 30 0000 C CNN +F 2 "" H 6250 5100 60 0000 C CNN +F 3 "" H 6250 5100 60 0000 C CNN + 4 6250 5100 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 8 1 68326F09 +P 9850 3900 +F 0 "U19" H 9900 4000 30 0000 C CNN +F 1 "PORT" H 9850 3900 30 0000 C CNN +F 2 "" H 9850 3900 60 0000 C CNN +F 3 "" H 9850 3900 60 0000 C CNN + 8 9850 3900 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 5 1 68326F66 +P 6250 5850 +F 0 "U19" H 6300 5950 30 0000 C CNN +F 1 "PORT" H 6250 5850 30 0000 C CNN +F 2 "" H 6250 5850 60 0000 C CNN +F 3 "" H 6250 5850 60 0000 C CNN + 5 6250 5850 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 11 1 68326FCD +P 6250 2400 +F 0 "U19" H 6300 2500 30 0000 C CNN +F 1 "PORT" H 6250 2400 30 0000 C CNN +F 2 "" H 6250 2400 60 0000 C CNN +F 3 "" H 6250 2400 60 0000 C CNN + 11 6250 2400 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 14 1 68327024 +P 1150 2900 +F 0 "U19" H 1200 3000 30 0000 C CNN +F 1 "PORT" H 1150 2900 30 0000 C CNN +F 2 "" H 1150 2900 60 0000 C CNN +F 3 "" H 1150 2900 60 0000 C CNN + 14 1150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 13 1 68327085 +P 6250 1050 +F 0 "U19" H 6300 1150 30 0000 C CNN +F 1 "PORT" H 6250 1050 30 0000 C CNN +F 2 "" H 6250 1050 60 0000 C CNN +F 3 "" H 6250 1050 60 0000 C CNN + 13 6250 1050 + -1 0 0 1 +$EndComp +$Comp +L PORT U19 +U 15 1 683270E6 +P 1150 1100 +F 0 "U19" H 1200 1200 30 0000 C CNN +F 1 "PORT" H 1150 1100 30 0000 C CNN +F 2 "" H 1150 1100 60 0000 C CNN +F 3 "" H 1150 1100 60 0000 C CNN + 15 1150 1100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 16 1 6832714D +P 8700 2550 +F 0 "U19" H 8750 2650 30 0000 C CNN +F 1 "PORT" H 8700 2550 30 0000 C CNN +F 2 "" H 8700 2550 60 0000 C CNN +F 3 "" H 8700 2550 60 0000 C CNN + 16 8700 2550 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 10 1 683271DC +P 6250 3150 +F 0 "U19" H 6300 3250 30 0000 C CNN +F 1 "PORT" H 6250 3150 30 0000 C CNN +F 2 "" H 6250 3150 60 0000 C CNN +F 3 "" H 6250 3150 60 0000 C CNN + 10 6250 3150 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 9 1 68327717 +P 6250 3750 +F 0 "U19" H 6300 3850 30 0000 C CNN +F 1 "PORT" H 6250 3750 30 0000 C CNN +F 2 "" H 6250 3750 60 0000 C CNN +F 3 "" H 6250 3750 60 0000 C CNN + 9 6250 3750 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 12 1 6832778C +P 6250 1800 +F 0 "U19" H 6300 1900 30 0000 C CNN +F 1 "PORT" H 6250 1800 30 0000 C CNN +F 2 "" H 6250 1800 60 0000 C CNN +F 3 "" H 6250 1800 60 0000 C CNN + 12 6250 1800 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 7 1 68327935 +P 6300 7150 +F 0 "U19" H 6350 7250 30 0000 C CNN +F 1 "PORT" H 6300 7150 30 0000 C CNN +F 2 "" H 6300 7150 60 0000 C CNN +F 3 "" H 6300 7150 60 0000 C CNN + 7 6300 7150 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 3 1 683279A6 +P 6250 4500 +F 0 "U19" H 6300 4600 30 0000 C CNN +F 1 "PORT" H 6250 4500 30 0000 C CNN +F 2 "" H 6250 4500 60 0000 C CNN +F 3 "" H 6250 4500 60 0000 C CNN + 3 6250 4500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 2 1 68327A15 +P 1450 6000 +F 0 "U19" H 1500 6100 30 0000 C CNN +F 1 "PORT" H 1450 6000 30 0000 C CNN +F 2 "" H 1450 6000 60 0000 C CNN +F 3 "" H 1450 6000 60 0000 C CNN + 2 1450 6000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 1 1 68327A8C +P 1300 4650 +F 0 "U19" H 1350 4750 30 0000 C CNN +F 1 "PORT" H 1300 4650 30 0000 C CNN +F 2 "" H 1300 4650 60 0000 C CNN +F 3 "" H 1300 4650 60 0000 C CNN + 1 1300 4650 + 1 0 0 -1 +$EndComp +NoConn ~ 8200 2550 +NoConn ~ 9500 3900 +Wire Wire Line + 8200 2550 8450 2550 +Wire Wire Line + 9500 3900 9600 3900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/DM9301/9301.sub b/library/SubcircuitLibrary/DM9301/9301.sub new file mode 100644 index 00000000..f05a4d81 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/9301.sub @@ -0,0 +1,89 @@ +* Subcircuit 9301 +.subckt 9301 net-_u19-pad1_ net-_u19-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u17-pad2_ net-_u18-pad2_ ? net-_u13-pad2_ net-_u12-pad2_ net-_u11-pad2_ net-_u10-pad2_ net-_u19-pad13_ net-_u19-pad14_ net-_u1-pad1_ ? +* c:\users\public\music\fossee\esim\library\subcircuitlibrary\9301\9301.cir +.include 4_and.sub +x1 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u9-pad1_ 4_and +* u9 net-_u9-pad1_ net-_u19-pad13_ d_inverter +x2 net-_u5-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u10-pad1_ 4_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +x3 net-_u1-pad2_ net-_u6-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u11-pad1_ 4_and +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +x4 net-_u5-pad2_ net-_u6-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u12-pad1_ 4_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +x5 net-_u1-pad2_ net-_u2-pad2_ net-_x5-pad3_ net-_u4-pad2_ net-_u13-pad1_ 4_and +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +x6 net-_u5-pad2_ net-_u2-pad2_ net-_x5-pad3_ net-_u4-pad2_ net-_u14-pad1_ 4_and +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +x7 net-_u1-pad2_ net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u15-pad1_ 4_and +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +x8 net-_u5-pad2_ net-_u6-pad2_ net-_x5-pad3_ net-_u4-pad2_ net-_u16-pad1_ 4_and +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +x9 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u17-pad1_ 4_and +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +x10 net-_u5-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u18-pad1_ 4_and +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u5 net-_u1-pad2_ net-_u5-pad2_ d_inverter +* u2 net-_u19-pad14_ net-_u2-pad2_ d_inverter +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u3 net-_u19-pad1_ net-_u3-pad2_ d_inverter +* u7 net-_u3-pad2_ net-_u7-pad2_ d_inverter +* u4 net-_u19-pad2_ net-_u4-pad2_ d_inverter +* u8 net-_u4-pad2_ net-_u8-pad2_ d_inverter +a1 net-_u9-pad1_ net-_u19-pad13_ u9 +a2 net-_u10-pad1_ net-_u10-pad2_ u10 +a3 net-_u11-pad1_ net-_u11-pad2_ u11 +a4 net-_u12-pad1_ net-_u12-pad2_ u12 +a5 net-_u13-pad1_ net-_u13-pad2_ u13 +a6 net-_u14-pad1_ net-_u14-pad2_ u14 +a7 net-_u15-pad1_ net-_u15-pad2_ u15 +a8 net-_u16-pad1_ net-_u16-pad2_ u16 +a9 net-_u17-pad1_ net-_u17-pad2_ u17 +a10 net-_u18-pad1_ net-_u18-pad2_ u18 +a11 net-_u1-pad1_ net-_u1-pad2_ u1 +a12 net-_u1-pad2_ net-_u5-pad2_ u5 +a13 net-_u19-pad14_ net-_u2-pad2_ u2 +a14 net-_u2-pad2_ net-_u6-pad2_ u6 +a15 net-_u19-pad1_ net-_u3-pad2_ u3 +a16 net-_u3-pad2_ net-_u7-pad2_ u7 +a17 net-_u19-pad2_ net-_u4-pad2_ u4 +a18 net-_u4-pad2_ net-_u8-pad2_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 9301 \ No newline at end of file diff --git a/library/SubcircuitLibrary/DM9301/9301_Previous_Values.xml b/library/SubcircuitLibrary/DM9301/9301_Previous_Values.xml new file mode 100644 index 00000000..85fd2840 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/9301_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterC:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/DM9301/analysis b/library/SubcircuitLibrary/DM9301/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/DM9301/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit