From 1937140f322210249deca5adc558ea4ed0a47a61 Mon Sep 17 00:00:00 2001 From: GanderlaChaithanya Date: Mon, 30 Jun 2025 11:39:48 +0530 Subject: ic163501 - 10-Bit Registered Transciever --- library/SubcircuitLibrary/ic163501/analysis | 1 + .../SubcircuitLibrary/ic163501/ic163501-cache.lib | 64 ++ library/SubcircuitLibrary/ic163501/ic163501.bck | 7 + library/SubcircuitLibrary/ic163501/ic163501.cir | 21 + .../SubcircuitLibrary/ic163501/ic163501.cir.out | 23 + library/SubcircuitLibrary/ic163501/ic163501.dcm | 7 + library/SubcircuitLibrary/ic163501/ic163501.lib | 1215 ++++++++++++++++++++ library/SubcircuitLibrary/ic163501/ic163501.pro | 73 ++ library/SubcircuitLibrary/ic163501/ic163501.sch | 997 ++++++++++++++++ library/SubcircuitLibrary/ic163501/ic163501.sub | 17 + .../ic163501/ic163501_Previous_Values.xml | 1 + .../ic163501/registered_transceiver-cache.lib | 107 ++ .../ic163501/registered_transceiver.cir | 24 + .../ic163501/registered_transceiver.cir.out | 64 ++ .../ic163501/registered_transceiver.pro | 73 ++ .../ic163501/registered_transceiver.sch | 410 +++++++ .../ic163501/registered_transceiver.sub | 58 + .../registered_transceiver_Previous_Values.xml | 1 + .../ic163501/registered_transciever-cache.lib | 107 ++ .../ic163501/registered_transciever.cir | 23 + .../ic163501/registered_transciever.cir.out | 60 + .../ic163501/registered_transciever.pro | 73 ++ .../ic163501/registered_transciever.sch | 387 +++++++ .../ic163501/registered_transciever.sub | 54 + .../ic163501/registered_transciever_IC.bck | 7 + .../ic163501/registered_transciever_IC.dcm | 7 + .../ic163501/registered_transciever_IC.lib | 1215 ++++++++++++++++++++ .../registered_transciever_Previous_Values.xml | 1 + library/SubcircuitLibrary/ic163501/transciever.bck | 7 + library/SubcircuitLibrary/ic163501/transciever.dcm | 7 + library/SubcircuitLibrary/ic163501/transciever.lib | 1157 +++++++++++++++++++ 31 files changed, 6268 insertions(+) create mode 100644 library/SubcircuitLibrary/ic163501/analysis create mode 100644 library/SubcircuitLibrary/ic163501/ic163501-cache.lib create mode 100644 library/SubcircuitLibrary/ic163501/ic163501.bck create mode 100644 library/SubcircuitLibrary/ic163501/ic163501.cir create mode 100644 library/SubcircuitLibrary/ic163501/ic163501.cir.out create mode 100644 library/SubcircuitLibrary/ic163501/ic163501.dcm create mode 100644 library/SubcircuitLibrary/ic163501/ic163501.lib create mode 100644 library/SubcircuitLibrary/ic163501/ic163501.pro create mode 100644 library/SubcircuitLibrary/ic163501/ic163501.sch create mode 100644 library/SubcircuitLibrary/ic163501/ic163501.sub create mode 100644 library/SubcircuitLibrary/ic163501/ic163501_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/ic163501/registered_transceiver-cache.lib create mode 100644 library/SubcircuitLibrary/ic163501/registered_transceiver.cir create mode 100644 library/SubcircuitLibrary/ic163501/registered_transceiver.cir.out create mode 100644 library/SubcircuitLibrary/ic163501/registered_transceiver.pro create mode 100644 library/SubcircuitLibrary/ic163501/registered_transceiver.sch create mode 100644 library/SubcircuitLibrary/ic163501/registered_transceiver.sub create mode 100644 library/SubcircuitLibrary/ic163501/registered_transceiver_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/ic163501/registered_transciever-cache.lib create mode 100644 library/SubcircuitLibrary/ic163501/registered_transciever.cir create mode 100644 library/SubcircuitLibrary/ic163501/registered_transciever.cir.out create mode 100644 library/SubcircuitLibrary/ic163501/registered_transciever.pro create mode 100644 library/SubcircuitLibrary/ic163501/registered_transciever.sch create mode 100644 library/SubcircuitLibrary/ic163501/registered_transciever.sub create mode 100644 library/SubcircuitLibrary/ic163501/registered_transciever_IC.bck create mode 100644 library/SubcircuitLibrary/ic163501/registered_transciever_IC.dcm create mode 100644 library/SubcircuitLibrary/ic163501/registered_transciever_IC.lib create mode 100644 library/SubcircuitLibrary/ic163501/registered_transciever_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/ic163501/transciever.bck create mode 100644 library/SubcircuitLibrary/ic163501/transciever.dcm create mode 100644 library/SubcircuitLibrary/ic163501/transciever.lib diff --git a/library/SubcircuitLibrary/ic163501/analysis b/library/SubcircuitLibrary/ic163501/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic163501/ic163501-cache.lib b/library/SubcircuitLibrary/ic163501/ic163501-cache.lib new file mode 100644 index 00000000..0c0d0ca2 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/ic163501-cache.lib @@ -0,0 +1,64 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# Registered_transceiver +# +DEF Registered_transceiver X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Registered_transceiver" 0 350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 250 400 -300 0 1 0 N +X a 1 -600 200 200 R 39 39 1 1 B +X OEAB 2 -600 50 200 R 39 39 1 1 I +X CLK 3 -600 -200 200 R 39 39 1 1 I +X LEAB 4 -600 -100 200 R 39 39 1 1 I +X b 5 600 200 200 L 39 39 1 1 B +X oeba_bar 6 600 100 200 L 39 39 1 1 I +X leba 7 600 -50 200 L 39 39 1 1 I +X clkba 8 600 -200 200 L 39 39 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ic163501/ic163501.bck b/library/SubcircuitLibrary/ic163501/ic163501.bck new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/ic163501.bck @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/ic163501/ic163501.cir b/library/SubcircuitLibrary/ic163501/ic163501.cir new file mode 100644 index 00000000..8c5d8e40 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/ic163501.cir @@ -0,0 +1,21 @@ +* C:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\ic163501\ic163501.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 6/9/2025 3:09:11 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad24_ Net-_U1-Pad25_ Net-_U1-Pad26_ PORT +X1 Net-_U1-Pad7_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad17_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Registered_transceiver +X3 Net-_U1-Pad8_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad18_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Registered_transceiver +X4 Net-_U1-Pad9_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad19_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Registered_transceiver +X10 Net-_U1-Pad10_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad20_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Registered_transceiver +X5 Net-_U1-Pad11_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Registered_transceiver +X6 Net-_U1-Pad12_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Registered_transceiver +X7 Net-_U1-Pad13_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad23_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Registered_transceiver +X2 Net-_U1-Pad14_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad24_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Registered_transceiver +X8 Net-_U1-Pad15_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad25_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Registered_transceiver +X9 Net-_U1-Pad16_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad26_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Registered_transceiver + +.end diff --git a/library/SubcircuitLibrary/ic163501/ic163501.cir.out b/library/SubcircuitLibrary/ic163501/ic163501.cir.out new file mode 100644 index 00000000..3b30bfc6 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/ic163501.cir.out @@ -0,0 +1,23 @@ +* c:\users\chaithu\fossee\esim\library\subcircuitlibrary\ic163501\ic163501.cir + +.include registered_transciever.sub +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ net-_u1-pad25_ net-_u1-pad26_ port +x1 net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad17_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ registered_transciever +x3 net-_u1-pad8_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad18_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ registered_transciever +x4 net-_u1-pad9_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad19_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ registered_transciever +x10 net-_u1-pad10_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad20_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ registered_transciever +x5 net-_u1-pad11_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad21_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ registered_transciever +x6 net-_u1-pad12_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad22_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ registered_transciever +x7 net-_u1-pad13_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad23_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ registered_transciever +x2 net-_u1-pad14_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad24_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ registered_transciever +x8 net-_u1-pad15_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad25_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ registered_transciever +x9 net-_u1-pad16_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad26_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ registered_transciever +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ic163501/ic163501.dcm b/library/SubcircuitLibrary/ic163501/ic163501.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/ic163501.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/ic163501/ic163501.lib b/library/SubcircuitLibrary/ic163501/ic163501.lib new file mode 100644 index 00000000..3fec1e78 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/ic163501.lib @@ -0,0 +1,1215 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 74194 +# +DEF 74194 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "74194" 0 250 60 H V C CNN +F2 "" 50 -50 60 H I C CNN +F3 "" 50 -50 60 H I C CNN +DRAW +S -150 150 200 -250 0 1 0 N +X clk 1 -350 100 200 R 31 31 1 1 I +X d0 2 -350 50 200 R 31 31 1 1 I +X dsr 3 -350 0 200 R 31 31 1 1 I +X d1 4 -350 -50 200 R 31 31 1 1 I +X d2 5 -350 -100 200 R 31 31 1 1 I +X d3 6 -350 -150 200 R 31 31 1 1 I +X dsl 7 -350 -200 200 R 31 31 1 1 I +X rst 8 400 100 200 L 31 31 1 1 I +X sel1 9 400 50 200 L 31 31 1 1 I +X sel0 10 400 0 200 L 31 31 1 1 I +X q0 11 400 -50 200 L 31 31 1 1 O +X q1 12 400 -100 200 L 31 31 1 1 O +X q2 13 400 -150 200 L 31 31 1 1 O +X q3 14 400 -200 200 L 31 31 1 1 O +ENDDRAW +ENDDEF +# +# 74hc194 +# +DEF 74hc194 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "74hc194" 0 0 39 H V C CNN +F2 "" 0 -200 60 H I C CNN +F3 "" 0 -200 60 H I C CNN +DRAW +S 300 -300 300 -300 0 1 0 N +S -300 250 300 -450 1 1 0 N +X dsr 1 -500 200 200 R 39 39 1 1 I +X s0 2 -500 100 200 R 39 39 1 1 I +X s1 3 -500 0 200 R 39 39 1 1 I +X d0 4 -500 -100 200 R 39 39 1 1 I +X clk 5 -500 -200 200 R 39 39 1 1 I +X rst 6 -500 -300 200 R 39 39 1 1 I +X q0 7 500 200 200 L 39 39 1 1 O +X d1 8 500 100 200 L 39 39 1 1 I +X q1 9 500 0 200 L 39 39 1 1 O +X d2 10 500 -100 200 L 39 39 1 1 I +X q2 11 500 -200 200 L 39 39 1 1 O +X d3 12 500 -300 200 L 39 39 1 1 I +X dsl 13 -500 -400 200 R 39 39 1 1 I +X q3 14 500 -400 200 L 39 39 1 1 O +ENDDRAW +ENDDEF +# +# CD4007 +# +DEF CD4007 X 0 40 Y Y 1 F N +F0 "X" 0 0 39 H V C CNN +F1 "CD4007" 0 100 39 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -250 250 250 -150 0 1 0 N +S 250 -200 250 -200 0 1 0 N +X G1 1 -450 200 200 R 31 31 1 1 I +X GND 2 -450 150 200 R 31 31 1 1 I +X vdd 3 -450 100 200 R 31 31 1 1 I +X Dp1 4 -450 50 200 R 31 31 1 1 B +X DN1 5 -450 0 200 R 31 31 1 1 B +X g2 6 -450 -50 200 R 31 31 1 1 I +X Dp2 7 -450 -100 200 R 31 31 1 1 B +X Sn2 8 450 200 200 L 31 31 1 1 B +X Sp2 9 450 150 200 L 31 31 1 1 B +X Dn2 10 450 100 200 L 31 31 1 1 B +X g3 11 450 50 200 L 31 31 1 1 I +X SN3 12 450 0 200 L 31 31 1 1 B +X SP3 13 450 -50 200 L 31 31 1 1 B +X DN3 14 450 -100 200 L 31 31 1 1 B +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X AB(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X AC:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transcieverC:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transcieverC:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transcieverC:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transcieverC:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transcieverC:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transcieverC:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transcieverC:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transcieverC:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transcieverC:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transcievertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic163501/registered_transceiver-cache.lib b/library/SubcircuitLibrary/ic163501/registered_transceiver-cache.lib new file mode 100644 index 00000000..d3d6a3a1 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transceiver-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_ff +# +DEF d_ff U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "d_ff" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X d0 1 2150 1900 200 R 50 50 1 1 I +X clk0 2 2150 1800 200 R 50 50 1 1 I +X q0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# tristate_buff +# +DEF tristate_buff U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "tristate_buff" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X a0 1 2150 1900 200 R 50 50 1 1 I +X enable0 2 2150 1800 200 R 50 50 1 1 I +X y0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ic163501/registered_transceiver.cir b/library/SubcircuitLibrary/ic163501/registered_transceiver.cir new file mode 100644 index 00000000..bc7978f2 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transceiver.cir @@ -0,0 +1,24 @@ +* C:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transceiver\registered_transceiver.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 6/7/2025 5:33:15 AM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U14 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U14-Pad3_ d_or +U12 Net-_U12-Pad1_ Net-_U1-Pad3_ Net-_U12-Pad3_ d_or +U19 Net-_U19-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad7_ tristate_buff +U8 Net-_U1-Pad1_ Net-_U12-Pad1_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_ff +U7 Net-_U1-Pad2_ Net-_U12-Pad3_ Net-_U5-Pad1_ d_ff +U18 Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U13-Pad2_ d_or +U20 Net-_U20-Pad1_ Net-_U1-Pad6_ Net-_U20-Pad3_ d_or +U22 Net-_U1-Pad8_ Net-_U20-Pad1_ d_inverter +U5 Net-_U5-Pad1_ Net-_U14-Pad3_ Net-_U19-Pad1_ d_ff +U24 Net-_U1-Pad7_ Net-_U20-Pad3_ Net-_U13-Pad1_ d_ff +U17 Net-_U13-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad2_ tristate_buff +U9 Net-_U1-Pad4_ Net-_U17-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT + +.end diff --git a/library/SubcircuitLibrary/ic163501/registered_transceiver.cir.out b/library/SubcircuitLibrary/ic163501/registered_transceiver.cir.out new file mode 100644 index 00000000..962d90c6 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transceiver.cir.out @@ -0,0 +1,64 @@ +* c:\users\chaithu\fossee\esim\library\subcircuitlibrary\registered_transceiver\registered_transceiver.cir + +* u14 net-_u1-pad1_ net-_u1-pad3_ net-_u14-pad3_ d_or +* u12 net-_u12-pad1_ net-_u1-pad3_ net-_u12-pad3_ d_or +* u19 net-_u19-pad1_ net-_u1-pad5_ net-_u1-pad7_ tristate_buff +* u8 net-_u1-pad1_ net-_u12-pad1_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_ff +* u7 net-_u1-pad2_ net-_u12-pad3_ net-_u5-pad1_ d_ff +* u18 net-_u1-pad6_ net-_u1-pad8_ net-_u13-pad2_ d_or +* u20 net-_u20-pad1_ net-_u1-pad6_ net-_u20-pad3_ d_or +* u22 net-_u1-pad8_ net-_u20-pad1_ d_inverter +* u5 net-_u5-pad1_ net-_u14-pad3_ net-_u19-pad1_ d_ff +* u24 net-_u1-pad7_ net-_u20-pad3_ net-_u13-pad1_ d_ff +* u17 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad2_ tristate_buff +* u9 net-_u1-pad4_ net-_u17-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u14-pad3_ u14 +a2 [net-_u12-pad1_ net-_u1-pad3_ ] net-_u12-pad3_ u12 +a3 [net-_u19-pad1_ ] [net-_u1-pad5_ ] [net-_u1-pad7_ ] u19 +a4 net-_u1-pad1_ net-_u12-pad1_ u8 +a5 [net-_u13-pad1_ ] [net-_u13-pad2_ ] [net-_u13-pad3_ ] u13 +a6 [net-_u1-pad2_ ] [net-_u12-pad3_ ] [net-_u5-pad1_ ] u7 +a7 [net-_u1-pad6_ net-_u1-pad8_ ] net-_u13-pad2_ u18 +a8 [net-_u20-pad1_ net-_u1-pad6_ ] net-_u20-pad3_ u20 +a9 net-_u1-pad8_ net-_u20-pad1_ u22 +a10 [net-_u5-pad1_ ] [net-_u14-pad3_ ] [net-_u19-pad1_ ] u5 +a11 [net-_u1-pad7_ ] [net-_u20-pad3_ ] [net-_u13-pad1_ ] u24 +a12 [net-_u13-pad3_ ] [net-_u17-pad2_ ] [net-_u1-pad2_ ] u17 +a13 net-_u1-pad4_ net-_u17-pad2_ u9 +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_buff, NgSpice Name: tristate_buff +.model u19 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u13 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u7 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u5 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u24 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buff, NgSpice Name: tristate_buff +.model u17 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ic163501/registered_transceiver.pro b/library/SubcircuitLibrary/ic163501/registered_transceiver.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transceiver.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ic163501/registered_transceiver.sch b/library/SubcircuitLibrary/ic163501/registered_transceiver.sch new file mode 100644 index 00000000..fafb8796 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transceiver.sch @@ -0,0 +1,410 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U14 +U 1 1 6841371D +P 4750 3300 +F 0 "U14" H 4750 3300 60 0000 C CNN +F 1 "d_or" H 4750 3400 60 0000 C CNN +F 2 "" H 4750 3300 60 0000 C CNN +F 3 "" H 4750 3300 60 0000 C CNN + 1 4750 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U12 +U 1 1 68413756 +P 3800 4200 +F 0 "U12" H 3800 4200 60 0000 C CNN +F 1 "d_or" H 3800 4300 60 0000 C CNN +F 2 "" H 3800 4200 60 0000 C CNN +F 3 "" H 3800 4200 60 0000 C CNN + 1 3800 4200 + 1 0 0 -1 +$EndComp +$Comp +L tristate_buff U19 +U 1 1 68413E29 +P 7050 5250 +F 0 "U19" H 9900 7050 60 0000 C CNN +F 1 "tristate_buff" H 9900 7250 60 0000 C CNN +F 2 "" H 9900 7200 60 0000 C CNN +F 3 "" H 9900 7200 60 0000 C CNN + 1 7050 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 684149B5 +P 2850 4100 +F 0 "U8" H 2850 4000 60 0000 C CNN +F 1 "d_inverter" H 2850 4250 60 0000 C CNN +F 2 "" H 2900 4050 60 0000 C CNN +F 3 "" H 2900 4050 60 0000 C CNN + 1 2850 4100 + 1 0 0 -1 +$EndComp +NoConn ~ 12800 5450 +$Comp +L d_ff U13 +U 1 1 6841B21F +P 8700 3900 +F 0 "U13" H 11550 5700 60 0000 C CNN +F 1 "d_ff" H 11550 5900 60 0000 C CNN +F 2 "" H 11550 5850 60 0000 C CNN +F 3 "" H 11550 5850 60 0000 C CNN + 1 8700 3900 + -1 0 0 1 +$EndComp +$Comp +L d_ff U7 +U 1 1 6841B8B5 +P 2400 5850 +F 0 "U7" H 5250 7650 60 0000 C CNN +F 1 "d_ff" H 5250 7850 60 0000 C CNN +F 2 "" H 5250 7800 60 0000 C CNN +F 3 "" H 5250 7800 60 0000 C CNN + 1 2400 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_or U18 +U 1 1 6841F704 +P 8000 4700 +F 0 "U18" H 8000 4700 60 0000 C CNN +F 1 "d_or" H 8000 4800 60 0000 C CNN +F 2 "" H 8000 4700 60 0000 C CNN +F 3 "" H 8000 4700 60 0000 C CNN + 1 8000 4700 + -1 0 0 1 +$EndComp +$Comp +L d_or U20 +U 1 1 6841F70A +P 9200 5550 +F 0 "U20" H 9200 5550 60 0000 C CNN +F 1 "d_or" H 9200 5650 60 0000 C CNN +F 2 "" H 9200 5550 60 0000 C CNN +F 3 "" H 9200 5550 60 0000 C CNN + 1 9200 5550 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 6841F710 +P 10150 5650 +F 0 "U22" H 10150 5550 60 0000 C CNN +F 1 "d_inverter" H 10150 5800 60 0000 C CNN +F 2 "" H 10200 5600 60 0000 C CNN +F 3 "" H 10200 5600 60 0000 C CNN + 1 10150 5650 + -1 0 0 1 +$EndComp +$Comp +L d_ff U5 +U 1 1 6841F716 +P 4450 5250 +F 0 "U5" H 7300 7050 60 0000 C CNN +F 1 "d_ff" H 7300 7250 60 0000 C CNN +F 2 "" H 7300 7200 60 0000 C CNN +F 3 "" H 7300 7200 60 0000 C CNN + 1 4450 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_ff U24 +U 1 1 6841F71C +P 10600 3900 +F 0 "U24" H 13450 5700 60 0000 C CNN +F 1 "d_ff" H 13450 5900 60 0000 C CNN +F 2 "" H 13450 5850 60 0000 C CNN +F 3 "" H 13450 5850 60 0000 C CNN + 1 10600 3900 + -1 0 0 1 +$EndComp +$Comp +L tristate_buff U17 +U 1 1 68421581 +P 6650 3900 +F 0 "U17" H 9500 5700 60 0000 C CNN +F 1 "tristate_buff" H 9500 5900 60 0000 C CNN +F 2 "" H 9500 5850 60 0000 C CNN +F 3 "" H 9500 5850 60 0000 C CNN + 1 6650 3900 + -1 0 0 1 +$EndComp +Wire Wire Line + 8750 1300 8750 3450 +Wire Wire Line + 8750 3450 9200 3450 +Wire Wire Line + 5950 3950 6300 3950 +Wire Wire Line + 3350 4100 3150 4100 +Wire Wire Line + 8000 3350 9200 3350 +Wire Wire Line + 3250 3300 4300 3300 +Wire Wire Line + 3250 3300 3250 4200 +Wire Wire Line + 3250 4200 3350 4200 +Wire Wire Line + 4550 3950 4350 3950 +Wire Wire Line + 4350 3950 4350 4350 +Wire Wire Line + 8750 1300 6950 1300 +Wire Wire Line + 6950 1300 6950 1250 +Wire Wire Line + 2300 3200 4300 3200 +Wire Wire Line + 2550 3200 2550 4100 +Connection ~ 2550 3200 +Wire Wire Line + 4350 4350 2650 4350 +Wire Wire Line + 2650 4350 2650 5700 +Wire Wire Line + 3750 2950 3750 3300 +Connection ~ 3750 3300 +Wire Wire Line + 10750 3000 10750 3800 +Wire Wire Line + 2650 5700 2500 5700 +Wire Wire Line + 10750 3350 10600 3350 +Wire Wire Line + 4550 4150 4550 4050 +Wire Wire Line + 4250 4150 4550 4150 +Wire Wire Line + 9650 5650 9850 5650 +Wire Wire Line + 8450 5800 8650 5800 +Wire Wire Line + 8450 5600 8450 5700 +Wire Wire Line + 8750 5600 8450 5600 +Wire Wire Line + 6300 3950 6300 3350 +Wire Wire Line + 6300 3350 6600 3350 +Wire Wire Line + 5200 3250 6200 3250 +Wire Wire Line + 6200 3250 6200 3450 +Wire Wire Line + 6200 3450 6600 3450 +Wire Wire Line + 5150 5800 4500 5800 +Wire Wire Line + 7050 5800 6550 5800 +Wire Wire Line + 7550 4750 7000 4750 +Wire Wire Line + 7000 4750 7000 5700 +Wire Wire Line + 7000 5700 6550 5700 +Wire Wire Line + 10450 5650 10950 5650 +Wire Wire Line + 8450 4700 10600 4700 +Wire Wire Line + 10600 4700 10600 5650 +Connection ~ 10600 5650 +Wire Wire Line + 9650 5550 10000 5550 +Wire Wire Line + 10000 5550 10000 4800 +Wire Wire Line + 10000 4800 8450 4800 +Wire Wire Line + 4500 5700 5000 5700 +Wire Wire Line + 3100 5800 3000 5800 +Wire Wire Line + 3000 5800 3000 5150 +Wire Wire Line + 3000 5150 2650 5150 +Connection ~ 2650 5150 +Wire Wire Line + 8650 5800 8650 3800 +Wire Wire Line + 8650 3800 10750 3800 +Connection ~ 10750 3350 +$Comp +L d_inverter U9 +U 1 1 6842614C +P 4700 6450 +F 0 "U9" H 4700 6350 60 0000 C CNN +F 1 "d_inverter" H 4700 6600 60 0000 C CNN +F 2 "" H 4750 6400 60 0000 C CNN +F 3 "" H 4750 6400 60 0000 C CNN + 1 4700 6450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4100 6450 4400 6450 +Wire Wire Line + 5000 5700 5000 6450 +Wire Wire Line + 9000 4250 9000 4800 +Connection ~ 9000 4800 +Wire Wire Line + 10950 5650 10950 6200 +$Comp +L transciever X1 +U 1 1 6843B68E +P 4650 1900 +F 0 "X1" H 4650 2000 60 0000 C CNN +F 1 "transciever" H 4650 2250 60 0000 C CNN +F 2 "" H 4650 2000 60 0001 C CNN +F 3 "" H 4650 2000 60 0001 C CNN + 1 4650 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6843B733 +P 2050 3200 +F 0 "U1" H 2100 3300 30 0000 C CNN +F 1 "PORT" H 2050 3200 30 0000 C CNN +F 2 "" H 2050 3200 60 0000 C CNN +F 3 "" H 2050 3200 60 0000 C CNN + 1 2050 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6843B76A +P 3850 6450 +F 0 "U1" H 3900 6550 30 0000 C CNN +F 1 "PORT" H 3850 6450 30 0000 C CNN +F 2 "" H 3850 6450 60 0000 C CNN +F 3 "" H 3850 6450 60 0000 C CNN + 4 3850 6450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6843B7A3 +P 2250 5700 +F 0 "U1" H 2300 5800 30 0000 C CNN +F 1 "PORT" H 2250 5700 30 0000 C CNN +F 2 "" H 2250 5700 60 0000 C CNN +F 3 "" H 2250 5700 60 0000 C CNN + 2 2250 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6843B7FE +P 6700 1250 +F 0 "U1" H 6750 1350 30 0000 C CNN +F 1 "PORT" H 6700 1250 30 0000 C CNN +F 2 "" H 6700 1250 60 0000 C CNN +F 3 "" H 6700 1250 60 0000 C CNN + 5 6700 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6843B84B +P 10500 3000 +F 0 "U1" H 10550 3100 30 0000 C CNN +F 1 "PORT" H 10500 3000 30 0000 C CNN +F 2 "" H 10500 3000 60 0000 C CNN +F 3 "" H 10500 3000 60 0000 C CNN + 7 10500 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6843B89A +P 3500 2950 +F 0 "U1" H 3550 3050 30 0000 C CNN +F 1 "PORT" H 3500 2950 30 0000 C CNN +F 2 "" H 3500 2950 60 0000 C CNN +F 3 "" H 3500 2950 60 0000 C CNN + 3 3500 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6843B8DD +P 8750 4250 +F 0 "U1" H 8800 4350 30 0000 C CNN +F 1 "PORT" H 8750 4250 30 0000 C CNN +F 2 "" H 8750 4250 60 0000 C CNN +F 3 "" H 8750 4250 60 0000 C CNN + 6 8750 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6843B920 +P 10700 6200 +F 0 "U1" H 10750 6300 30 0000 C CNN +F 1 "PORT" H 10700 6200 30 0000 C CNN +F 2 "" H 10700 6200 60 0000 C CNN +F 3 "" H 10700 6200 60 0000 C CNN + 8 10700 6200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ic163501/registered_transceiver.sub b/library/SubcircuitLibrary/ic163501/registered_transceiver.sub new file mode 100644 index 00000000..8b42e78a --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transceiver.sub @@ -0,0 +1,58 @@ +* Subcircuit registered_transceiver +.subckt registered_transceiver net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\users\chaithu\fossee\esim\library\subcircuitlibrary\registered_transceiver\registered_transceiver.cir +* u14 net-_u1-pad1_ net-_u1-pad3_ net-_u14-pad3_ d_or +* u12 net-_u12-pad1_ net-_u1-pad3_ net-_u12-pad3_ d_or +* u19 net-_u19-pad1_ net-_u1-pad5_ net-_u1-pad7_ tristate_buff +* u8 net-_u1-pad1_ net-_u12-pad1_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_ff +* u7 net-_u1-pad2_ net-_u12-pad3_ net-_u5-pad1_ d_ff +* u18 net-_u1-pad6_ net-_u1-pad8_ net-_u13-pad2_ d_or +* u20 net-_u20-pad1_ net-_u1-pad6_ net-_u20-pad3_ d_or +* u22 net-_u1-pad8_ net-_u20-pad1_ d_inverter +* u5 net-_u5-pad1_ net-_u14-pad3_ net-_u19-pad1_ d_ff +* u24 net-_u1-pad7_ net-_u20-pad3_ net-_u13-pad1_ d_ff +* u17 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad2_ tristate_buff +* u9 net-_u1-pad4_ net-_u17-pad2_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u14-pad3_ u14 +a2 [net-_u12-pad1_ net-_u1-pad3_ ] net-_u12-pad3_ u12 +a3 [net-_u19-pad1_ ] [net-_u1-pad5_ ] [net-_u1-pad7_ ] u19 +a4 net-_u1-pad1_ net-_u12-pad1_ u8 +a5 [net-_u13-pad1_ ] [net-_u13-pad2_ ] [net-_u13-pad3_ ] u13 +a6 [net-_u1-pad2_ ] [net-_u12-pad3_ ] [net-_u5-pad1_ ] u7 +a7 [net-_u1-pad6_ net-_u1-pad8_ ] net-_u13-pad2_ u18 +a8 [net-_u20-pad1_ net-_u1-pad6_ ] net-_u20-pad3_ u20 +a9 net-_u1-pad8_ net-_u20-pad1_ u22 +a10 [net-_u5-pad1_ ] [net-_u14-pad3_ ] [net-_u19-pad1_ ] u5 +a11 [net-_u1-pad7_ ] [net-_u20-pad3_ ] [net-_u13-pad1_ ] u24 +a12 [net-_u13-pad3_ ] [net-_u17-pad2_ ] [net-_u1-pad2_ ] u17 +a13 net-_u1-pad4_ net-_u17-pad2_ u9 +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_buff, NgSpice Name: tristate_buff +.model u19 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u13 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u7 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u5 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u24 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buff, NgSpice Name: tristate_buff +.model u17 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends registered_transceiver \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic163501/registered_transceiver_Previous_Values.xml b/library/SubcircuitLibrary/ic163501/registered_transceiver_Previous_Values.xml new file mode 100644 index 00000000..116663f7 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transceiver_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_inverterd_ffd_fftristate_buffd_ord_ord_inverterd_ffd_fftristate_buffd_inverterd_ord_ortristate_buffd_inverterd_ffd_ord_ord_inverterd_ffd_fftristate_buffd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic163501/registered_transciever-cache.lib b/library/SubcircuitLibrary/ic163501/registered_transciever-cache.lib new file mode 100644 index 00000000..d3d6a3a1 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transciever-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_ff +# +DEF d_ff U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "d_ff" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X d0 1 2150 1900 200 R 50 50 1 1 I +X clk0 2 2150 1800 200 R 50 50 1 1 I +X q0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# tristate_buff +# +DEF tristate_buff U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "tristate_buff" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X a0 1 2150 1900 200 R 50 50 1 1 I +X enable0 2 2150 1800 200 R 50 50 1 1 I +X y0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ic163501/registered_transciever.cir b/library/SubcircuitLibrary/ic163501/registered_transciever.cir new file mode 100644 index 00000000..c2cc1527 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transciever.cir @@ -0,0 +1,23 @@ +* C:\Users\Chaithu\FOSSEE\eSim\library\SubcircuitLibrary\registered_transciever\registered_transciever.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 6/9/2025 2:16:21 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U5-Pad3_ d_or +U4 Net-_U3-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad2_ d_or +U3 Net-_U1-Pad3_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_ff +U6 Net-_U2-Pad3_ Net-_U5-Pad3_ Net-_U6-Pad3_ d_ff +U7 Net-_U6-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad5_ tristate_buff +U10 Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U10-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U1-Pad7_ Net-_U11-Pad3_ d_or +U12 Net-_U1-Pad8_ Net-_U11-Pad1_ d_inverter +U13 Net-_U1-Pad5_ Net-_U11-Pad3_ Net-_U13-Pad3_ d_ff +U9 Net-_U13-Pad3_ Net-_U10-Pad3_ Net-_U8-Pad1_ d_ff +U8 Net-_U8-Pad1_ Net-_U1-Pad6_ Net-_U1-Pad1_ tristate_buff + +.end diff --git a/library/SubcircuitLibrary/ic163501/registered_transciever.cir.out b/library/SubcircuitLibrary/ic163501/registered_transciever.cir.out new file mode 100644 index 00000000..ec2b6716 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transciever.cir.out @@ -0,0 +1,60 @@ +* c:\users\chaithu\fossee\esim\library\subcircuitlibrary\registered_transciever\registered_transciever.cir + +* u5 net-_u1-pad3_ net-_u1-pad4_ net-_u5-pad3_ d_or +* u4 net-_u3-pad2_ net-_u1-pad4_ net-_u2-pad2_ d_or +* u3 net-_u1-pad3_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_ff +* u6 net-_u2-pad3_ net-_u5-pad3_ net-_u6-pad3_ d_ff +* u7 net-_u6-pad3_ net-_u1-pad2_ net-_u1-pad5_ tristate_buff +* u10 net-_u1-pad8_ net-_u1-pad7_ net-_u10-pad3_ d_or +* u11 net-_u11-pad1_ net-_u1-pad7_ net-_u11-pad3_ d_or +* u12 net-_u1-pad8_ net-_u11-pad1_ d_inverter +* u13 net-_u1-pad5_ net-_u11-pad3_ net-_u13-pad3_ d_ff +* u9 net-_u13-pad3_ net-_u10-pad3_ net-_u8-pad1_ d_ff +* u8 net-_u8-pad1_ net-_u1-pad6_ net-_u1-pad1_ tristate_buff +a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u5-pad3_ u5 +a2 [net-_u3-pad2_ net-_u1-pad4_ ] net-_u2-pad2_ u4 +a3 net-_u1-pad3_ net-_u3-pad2_ u3 +a4 [net-_u1-pad1_ ] [net-_u2-pad2_ ] [net-_u2-pad3_ ] u2 +a5 [net-_u2-pad3_ ] [net-_u5-pad3_ ] [net-_u6-pad3_ ] u6 +a6 [net-_u6-pad3_ ] [net-_u1-pad2_ ] [net-_u1-pad5_ ] u7 +a7 [net-_u1-pad8_ net-_u1-pad7_ ] net-_u10-pad3_ u10 +a8 [net-_u11-pad1_ net-_u1-pad7_ ] net-_u11-pad3_ u11 +a9 net-_u1-pad8_ net-_u11-pad1_ u12 +a10 [net-_u1-pad5_ ] [net-_u11-pad3_ ] [net-_u13-pad3_ ] u13 +a11 [net-_u13-pad3_ ] [net-_u10-pad3_ ] [net-_u8-pad1_ ] u9 +a12 [net-_u8-pad1_ ] [net-_u1-pad6_ ] [net-_u1-pad1_ ] u8 +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u2 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u6 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buff, NgSpice Name: tristate_buff +.model u7 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u13 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u9 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buff, NgSpice Name: tristate_buff +.model u8 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ic163501/registered_transciever.pro b/library/SubcircuitLibrary/ic163501/registered_transciever.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transciever.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ic163501/registered_transciever.sch b/library/SubcircuitLibrary/ic163501/registered_transciever.sch new file mode 100644 index 00000000..b108dac0 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transciever.sch @@ -0,0 +1,387 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:registered_transciever-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U5 +U 1 1 684421E7 +P 3700 1050 +F 0 "U5" H 3700 1050 60 0000 C CNN +F 1 "d_or" H 3700 1150 60 0000 C CNN +F 2 "" H 3700 1050 60 0000 C CNN +F 3 "" H 3700 1050 60 0000 C CNN + 1 3700 1050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 68442222 +P 3550 1900 +F 0 "U4" H 3550 1900 60 0000 C CNN +F 1 "d_or" H 3550 2000 60 0000 C CNN +F 2 "" H 3550 1900 60 0000 C CNN +F 3 "" H 3550 1900 60 0000 C CNN + 1 3550 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6844224D +P 2550 1800 +F 0 "U3" H 2550 1700 60 0000 C CNN +F 1 "d_inverter" H 2550 1950 60 0000 C CNN +F 2 "" H 2600 1750 60 0000 C CNN +F 3 "" H 2600 1750 60 0000 C CNN + 1 2550 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5800 2050 6650 2050 +Wire Wire Line + 4000 1850 4000 2150 +Wire Wire Line + 3100 1800 2850 1800 +Wire Wire Line + 1600 950 3250 950 +Wire Wire Line + 2150 950 2150 1800 +Wire Wire Line + 2150 1800 2250 1800 +Connection ~ 2150 950 +Wire Wire Line + 3100 1050 3100 1900 +Wire Wire Line + 3100 1050 3250 1050 +Wire Wire Line + 3100 1350 1650 1350 +Connection ~ 3100 1350 +Wire Wire Line + 8200 1350 8200 1100 +Wire Wire Line + 8200 1100 8700 1100 +Wire Wire Line + 1700 2150 3700 2150 +Wire Wire Line + 3700 2150 3700 2050 +Wire Wire Line + 3700 2050 4400 2050 +Wire Wire Line + 6450 1450 6800 1450 +Wire Wire Line + 6650 2050 6650 1350 +Wire Wire Line + 6650 1350 6800 1350 +Wire Wire Line + 8700 1200 8700 2650 +Wire Wire Line + 8700 2650 3750 2650 +$Comp +L PORT U1 +U 2 1 68447A8F +P 1500 2500 +F 0 "U1" H 1550 2600 30 0000 C CNN +F 1 "PORT" H 1500 2500 30 0000 C CNN +F 2 "" H 1500 2500 60 0000 C CNN +F 3 "" H 1500 2500 60 0000 C CNN + 2 1500 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68447B3A +P 1350 950 +F 0 "U1" H 1400 1050 30 0000 C CNN +F 1 "PORT" H 1350 950 30 0000 C CNN +F 2 "" H 1350 950 60 0000 C CNN +F 3 "" H 1350 950 60 0000 C CNN + 3 1350 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 68447BB1 +P 1450 2150 +F 0 "U1" H 1500 2250 30 0000 C CNN +F 1 "PORT" H 1450 2150 30 0000 C CNN +F 2 "" H 1450 2150 60 0000 C CNN +F 3 "" H 1450 2150 60 0000 C CNN + 1 1450 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68447C0A +P 1400 1350 +F 0 "U1" H 1450 1450 30 0000 C CNN +F 1 "PORT" H 1400 1350 30 0000 C CNN +F 2 "" H 1400 1350 60 0000 C CNN +F 3 "" H 1400 1350 60 0000 C CNN + 4 1400 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68447CDE +P 10750 1100 +F 0 "U1" H 10800 1200 30 0000 C CNN +F 1 "PORT" H 10750 1100 30 0000 C CNN +F 2 "" H 10750 1100 60 0000 C CNN +F 3 "" H 10750 1100 60 0000 C CNN + 5 10750 1100 + -1 0 0 1 +$EndComp +Wire Wire Line + 3750 2650 3750 2500 +Wire Wire Line + 3750 2500 1750 2500 +Wire Wire Line + 4000 2150 4400 2150 +Wire Wire Line + 4150 1000 6450 1000 +Wire Wire Line + 6450 1000 6450 1450 +$Comp +L d_ff U2 +U 1 1 68453EBA +P 2250 3950 +F 0 "U2" H 5100 5750 60 0000 C CNN +F 1 "d_ff" H 5100 5950 60 0000 C CNN +F 2 "" H 5100 5900 60 0000 C CNN +F 3 "" H 5100 5900 60 0000 C CNN + 1 2250 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_ff U6 +U 1 1 6845423A +P 4650 3250 +F 0 "U6" H 7500 5050 60 0000 C CNN +F 1 "d_ff" H 7500 5250 60 0000 C CNN +F 2 "" H 7500 5200 60 0000 C CNN +F 3 "" H 7500 5200 60 0000 C CNN + 1 4650 3250 + 1 0 0 -1 +$EndComp +$Comp +L tristate_buff U7 +U 1 1 684542D1 +P 6550 3000 +F 0 "U7" H 9400 4800 60 0000 C CNN +F 1 "tristate_buff" H 9400 5000 60 0000 C CNN +F 2 "" H 9400 4950 60 0000 C CNN +F 3 "" H 9400 4950 60 0000 C CNN + 1 6550 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_or U10 +U 1 1 6846A418 +P 8350 5050 +F 0 "U10" H 8350 5050 60 0000 C CNN +F 1 "d_or" H 8350 5150 60 0000 C CNN +F 2 "" H 8350 5050 60 0000 C CNN +F 3 "" H 8350 5050 60 0000 C CNN + 1 8350 5050 + -1 0 0 1 +$EndComp +$Comp +L d_or U11 +U 1 1 6846A41E +P 8500 4200 +F 0 "U11" H 8500 4200 60 0000 C CNN +F 1 "d_or" H 8500 4300 60 0000 C CNN +F 2 "" H 8500 4200 60 0000 C CNN +F 3 "" H 8500 4200 60 0000 C CNN + 1 8500 4200 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6846A424 +P 9500 4300 +F 0 "U12" H 9500 4200 60 0000 C CNN +F 1 "d_inverter" H 9500 4450 60 0000 C CNN +F 2 "" H 9550 4250 60 0000 C CNN +F 3 "" H 9550 4250 60 0000 C CNN + 1 9500 4300 + -1 0 0 1 +$EndComp +Wire Wire Line + 6250 4050 5400 4050 +Wire Wire Line + 8050 4250 8050 3950 +Wire Wire Line + 8950 4300 9200 4300 +Wire Wire Line + 10450 5150 8800 5150 +Wire Wire Line + 9900 5150 9900 4300 +Wire Wire Line + 9900 4300 9800 4300 +Connection ~ 9900 5150 +Wire Wire Line + 8950 5050 8950 4200 +Wire Wire Line + 8950 5050 8800 5050 +Wire Wire Line + 8950 4750 10400 4750 +Connection ~ 8950 4750 +Wire Wire Line + 3850 5000 3850 4750 +Wire Wire Line + 3100 5000 3850 5000 +Wire Wire Line + 8350 3950 10400 3950 +Wire Wire Line + 8350 3950 8350 4050 +Wire Wire Line + 8350 4050 7650 4050 +Wire Wire Line + 5600 4650 5250 4650 +Wire Wire Line + 5400 4050 5400 4750 +Wire Wire Line + 5400 4750 5250 4750 +Wire Wire Line + 8050 3950 7650 3950 +Wire Wire Line + 7900 5100 5600 5100 +Wire Wire Line + 5600 5100 5600 4650 +$Comp +L d_ff U13 +U 1 1 6846A444 +P 9800 2150 +F 0 "U13" H 12650 3950 60 0000 C CNN +F 1 "d_ff" H 12650 4150 60 0000 C CNN +F 2 "" H 12650 4100 60 0000 C CNN +F 3 "" H 12650 4100 60 0000 C CNN + 1 9800 2150 + -1 0 0 1 +$EndComp +$Comp +L d_ff U9 +U 1 1 6846A44A +P 7400 2850 +F 0 "U9" H 10250 4650 60 0000 C CNN +F 1 "d_ff" H 10250 4850 60 0000 C CNN +F 2 "" H 10250 4800 60 0000 C CNN +F 3 "" H 10250 4800 60 0000 C CNN + 1 7400 2850 + -1 0 0 1 +$EndComp +$Comp +L tristate_buff U8 +U 1 1 6846A450 +P 5250 3050 +F 0 "U8" H 8100 4850 60 0000 C CNN +F 1 "tristate_buff" H 8100 5050 60 0000 C CNN +F 2 "" H 8100 5000 60 0000 C CNN +F 3 "" H 8100 5000 60 0000 C CNN + 1 5250 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 3100 5000 3100 4950 +Wire Wire Line + 10100 1100 10500 1100 +Wire Wire Line + 10400 3950 10400 1100 +Connection ~ 10400 1100 +Wire Wire Line + 1700 4950 1700 3100 +Wire Wire Line + 1700 3100 2200 3100 +Wire Wire Line + 2200 3100 2200 2150 +Connection ~ 2200 2150 +Wire Wire Line + 3100 4850 3250 4850 +Wire Wire Line + 3250 4850 3250 4250 +$Comp +L PORT U1 +U 7 1 6846CA03 +P 10650 4750 +F 0 "U1" H 10700 4850 30 0000 C CNN +F 1 "PORT" H 10650 4750 30 0000 C CNN +F 2 "" H 10650 4750 60 0000 C CNN +F 3 "" H 10650 4750 60 0000 C CNN + 7 10650 4750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 6846CA86 +P 10700 5150 +F 0 "U1" H 10750 5250 30 0000 C CNN +F 1 "PORT" H 10700 5150 30 0000 C CNN +F 2 "" H 10700 5150 60 0000 C CNN +F 3 "" H 10700 5150 60 0000 C CNN + 8 10700 5150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 6846D099 +P 3250 4000 +F 0 "U1" H 3300 4100 30 0000 C CNN +F 1 "PORT" H 3250 4000 30 0000 C CNN +F 2 "" H 3250 4000 60 0000 C CNN +F 3 "" H 3250 4000 60 0000 C CNN + 6 3250 4000 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ic163501/registered_transciever.sub b/library/SubcircuitLibrary/ic163501/registered_transciever.sub new file mode 100644 index 00000000..a09cb4a0 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transciever.sub @@ -0,0 +1,54 @@ +* Subcircuit registered_transciever +.subckt registered_transciever net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\users\chaithu\fossee\esim\library\subcircuitlibrary\registered_transciever\registered_transciever.cir +* u5 net-_u1-pad3_ net-_u1-pad4_ net-_u5-pad3_ d_or +* u4 net-_u3-pad2_ net-_u1-pad4_ net-_u2-pad2_ d_or +* u3 net-_u1-pad3_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_ff +* u6 net-_u2-pad3_ net-_u5-pad3_ net-_u6-pad3_ d_ff +* u7 net-_u6-pad3_ net-_u1-pad2_ net-_u1-pad5_ tristate_buff +* u10 net-_u1-pad8_ net-_u1-pad7_ net-_u10-pad3_ d_or +* u11 net-_u11-pad1_ net-_u1-pad7_ net-_u11-pad3_ d_or +* u12 net-_u1-pad8_ net-_u11-pad1_ d_inverter +* u13 net-_u1-pad5_ net-_u11-pad3_ net-_u13-pad3_ d_ff +* u9 net-_u13-pad3_ net-_u10-pad3_ net-_u8-pad1_ d_ff +* u8 net-_u8-pad1_ net-_u1-pad6_ net-_u1-pad1_ tristate_buff +a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u5-pad3_ u5 +a2 [net-_u3-pad2_ net-_u1-pad4_ ] net-_u2-pad2_ u4 +a3 net-_u1-pad3_ net-_u3-pad2_ u3 +a4 [net-_u1-pad1_ ] [net-_u2-pad2_ ] [net-_u2-pad3_ ] u2 +a5 [net-_u2-pad3_ ] [net-_u5-pad3_ ] [net-_u6-pad3_ ] u6 +a6 [net-_u6-pad3_ ] [net-_u1-pad2_ ] [net-_u1-pad5_ ] u7 +a7 [net-_u1-pad8_ net-_u1-pad7_ ] net-_u10-pad3_ u10 +a8 [net-_u11-pad1_ net-_u1-pad7_ ] net-_u11-pad3_ u11 +a9 net-_u1-pad8_ net-_u11-pad1_ u12 +a10 [net-_u1-pad5_ ] [net-_u11-pad3_ ] [net-_u13-pad3_ ] u13 +a11 [net-_u13-pad3_ ] [net-_u10-pad3_ ] [net-_u8-pad1_ ] u9 +a12 [net-_u8-pad1_ ] [net-_u1-pad6_ ] [net-_u1-pad1_ ] u8 +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u2 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u6 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buff, NgSpice Name: tristate_buff +.model u7 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u13 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_ff, NgSpice Name: d_ff +.model u9 d_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: tristate_buff, NgSpice Name: tristate_buff +.model u8 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Control Statements + +.ends registered_transciever \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic163501/registered_transciever_IC.bck b/library/SubcircuitLibrary/ic163501/registered_transciever_IC.bck new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transciever_IC.bck @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/ic163501/registered_transciever_IC.dcm b/library/SubcircuitLibrary/ic163501/registered_transciever_IC.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transciever_IC.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/ic163501/registered_transciever_IC.lib b/library/SubcircuitLibrary/ic163501/registered_transciever_IC.lib new file mode 100644 index 00000000..3fec1e78 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/registered_transciever_IC.lib @@ -0,0 +1,1215 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 74194 +# +DEF 74194 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "74194" 0 250 60 H V C CNN +F2 "" 50 -50 60 H I C CNN +F3 "" 50 -50 60 H I C CNN +DRAW +S -150 150 200 -250 0 1 0 N +X clk 1 -350 100 200 R 31 31 1 1 I +X d0 2 -350 50 200 R 31 31 1 1 I +X dsr 3 -350 0 200 R 31 31 1 1 I +X d1 4 -350 -50 200 R 31 31 1 1 I +X d2 5 -350 -100 200 R 31 31 1 1 I +X d3 6 -350 -150 200 R 31 31 1 1 I +X dsl 7 -350 -200 200 R 31 31 1 1 I +X rst 8 400 100 200 L 31 31 1 1 I +X sel1 9 400 50 200 L 31 31 1 1 I +X sel0 10 400 0 200 L 31 31 1 1 I +X q0 11 400 -50 200 L 31 31 1 1 O +X q1 12 400 -100 200 L 31 31 1 1 O +X q2 13 400 -150 200 L 31 31 1 1 O +X q3 14 400 -200 200 L 31 31 1 1 O +ENDDRAW +ENDDEF +# +# 74hc194 +# +DEF 74hc194 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "74hc194" 0 0 39 H V C CNN +F2 "" 0 -200 60 H I C CNN +F3 "" 0 -200 60 H I C CNN +DRAW +S 300 -300 300 -300 0 1 0 N +S -300 250 300 -450 1 1 0 N +X dsr 1 -500 200 200 R 39 39 1 1 I +X s0 2 -500 100 200 R 39 39 1 1 I +X s1 3 -500 0 200 R 39 39 1 1 I +X d0 4 -500 -100 200 R 39 39 1 1 I +X clk 5 -500 -200 200 R 39 39 1 1 I +X rst 6 -500 -300 200 R 39 39 1 1 I +X q0 7 500 200 200 L 39 39 1 1 O +X d1 8 500 100 200 L 39 39 1 1 I +X q1 9 500 0 200 L 39 39 1 1 O +X d2 10 500 -100 200 L 39 39 1 1 I +X q2 11 500 -200 200 L 39 39 1 1 O +X d3 12 500 -300 200 L 39 39 1 1 I +X dsl 13 -500 -400 200 R 39 39 1 1 I +X q3 14 500 -400 200 L 39 39 1 1 O +ENDDRAW +ENDDEF +# +# CD4007 +# +DEF CD4007 X 0 40 Y Y 1 F N +F0 "X" 0 0 39 H V C CNN +F1 "CD4007" 0 100 39 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -250 250 250 -150 0 1 0 N +S 250 -200 250 -200 0 1 0 N +X G1 1 -450 200 200 R 31 31 1 1 I +X GND 2 -450 150 200 R 31 31 1 1 I +X vdd 3 -450 100 200 R 31 31 1 1 I +X Dp1 4 -450 50 200 R 31 31 1 1 B +X DN1 5 -450 0 200 R 31 31 1 1 B +X g2 6 -450 -50 200 R 31 31 1 1 I +X Dp2 7 -450 -100 200 R 31 31 1 1 B +X Sn2 8 450 200 200 L 31 31 1 1 B +X Sp2 9 450 150 200 L 31 31 1 1 B +X Dn2 10 450 100 200 L 31 31 1 1 B +X g3 11 450 50 200 L 31 31 1 1 I +X SN3 12 450 0 200 L 31 31 1 1 B +X SP3 13 450 -50 200 L 31 31 1 1 B +X DN3 14 450 -100 200 L 31 31 1 1 B +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X AB(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X Ad_ord_ord_inverterd_flopd_floptristate_bufd_ffd_fftristate_buffd_ord_ord_inverterd_ffd_fftristate_bufftruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/ic163501/transciever.bck b/library/SubcircuitLibrary/ic163501/transciever.bck new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/transciever.bck @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/ic163501/transciever.dcm b/library/SubcircuitLibrary/ic163501/transciever.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/transciever.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/ic163501/transciever.lib b/library/SubcircuitLibrary/ic163501/transciever.lib new file mode 100644 index 00000000..ee731c04 --- /dev/null +++ b/library/SubcircuitLibrary/ic163501/transciever.lib @@ -0,0 +1,1157 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 74194 +# +DEF 74194 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "74194" 0 250 60 H V C CNN +F2 "" 50 -50 60 H I C CNN +F3 "" 50 -50 60 H I C CNN +DRAW +S -150 150 200 -250 0 1 0 N +X clk 1 -350 100 200 R 31 31 1 1 I +X d0 2 -350 50 200 R 31 31 1 1 I +X dsr 3 -350 0 200 R 31 31 1 1 I +X d1 4 -350 -50 200 R 31 31 1 1 I +X d2 5 -350 -100 200 R 31 31 1 1 I +X d3 6 -350 -150 200 R 31 31 1 1 I +X dsl 7 -350 -200 200 R 31 31 1 1 I +X rst 8 400 100 200 L 31 31 1 1 I +X sel1 9 400 50 200 L 31 31 1 1 I +X sel0 10 400 0 200 L 31 31 1 1 I +X q0 11 400 -50 200 L 31 31 1 1 O +X q1 12 400 -100 200 L 31 31 1 1 O +X q2 13 400 -150 200 L 31 31 1 1 O +X q3 14 400 -200 200 L 31 31 1 1 O +ENDDRAW +ENDDEF +# +# 74hc194 +# +DEF 74hc194 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "74hc194" 0 0 39 H V C CNN +F2 "" 0 -200 60 H I C CNN +F3 "" 0 -200 60 H I C CNN +DRAW +S 300 -300 300 -300 0 1 0 N +S -300 250 300 -450 1 1 0 N +X dsr 1 -500 200 200 R 39 39 1 1 I +X s0 2 -500 100 200 R 39 39 1 1 I +X s1 3 -500 0 200 R 39 39 1 1 I +X d0 4 -500 -100 200 R 39 39 1 1 I +X clk 5 -500 -200 200 R 39 39 1 1 I +X rst 6 -500 -300 200 R 39 39 1 1 I +X q0 7 500 200 200 L 39 39 1 1 O +X d1 8 500 100 200 L 39 39 1 1 I +X q1 9 500 0 200 L 39 39 1 1 O +X d2 10 500 -100 200 L 39 39 1 1 I +X q2 11 500 -200 200 L 39 39 1 1 O +X d3 12 500 -300 200 L 39 39 1 1 I +X dsl 13 -500 -400 200 R 39 39 1 1 I +X q3 14 500 -400 200 L 39 39 1 1 O +ENDDRAW +ENDDEF +# +# CD4007 +# +DEF CD4007 X 0 40 Y Y 1 F N +F0 "X" 0 0 39 H V C CNN +F1 "CD4007" 0 100 39 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -250 250 250 -150 0 1 0 N +S 250 -200 250 -200 0 1 0 N +X G1 1 -450 200 200 R 31 31 1 1 I +X GND 2 -450 150 200 R 31 31 1 1 I +X vdd 3 -450 100 200 R 31 31 1 1 I +X Dp1 4 -450 50 200 R 31 31 1 1 B +X DN1 5 -450 0 200 R 31 31 1 1 B +X g2 6 -450 -50 200 R 31 31 1 1 I +X Dp2 7 -450 -100 200 R 31 31 1 1 B +X Sn2 8 450 200 200 L 31 31 1 1 B +X Sp2 9 450 150 200 L 31 31 1 1 B +X Dn2 10 450 100 200 L 31 31 1 1 B +X g3 11 450 50 200 L 31 31 1 1 I +X SN3 12 450 0 200 L 31 31 1 1 B +X SP3 13 450 -50 200 L 31 31 1 1 B +X DN3 14 450 -100 200 L 31 31 1 1 B +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X AB(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A