From 161ed8ce7658c6c4084dd0ba158b650ef909724e Mon Sep 17 00:00:00 2001
From: GanderlaChaithanya
Date: Mon, 30 Jun 2025 12:26:18 +0530
Subject: D Flip Flop Verilog code for Subcircuit - SN54HC164

---
 library/SubcircuitLibrary/SN54HC164/dff_rst.v | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 library/SubcircuitLibrary/SN54HC164/dff_rst.v

diff --git a/library/SubcircuitLibrary/SN54HC164/dff_rst.v b/library/SubcircuitLibrary/SN54HC164/dff_rst.v
new file mode 100644
index 00000000..da896fa8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54HC164/dff_rst.v
@@ -0,0 +1,12 @@
+module dff_rst(d,rst,clk,q);
+input d,clk,rst;
+output reg q;
+always @(posedge clk) begin
+if(rst) begin
+q<=1'b0;
+end
+else begin
+q<=d;
+end
+end
+endmodule
\ No newline at end of file
-- 
cgit