From 059d3c9d9f036e0415329432ad0a5aeb216aa64f Mon Sep 17 00:00:00 2001
From: AmanShukla111
Date: Sun, 1 Jun 2025 19:45:06 +0530
Subject: Adding 74HC86-Quad Two Input XOR

---
 .DS_Store                                          | Bin 6148 -> 6148 bytes
 library/SubcircuitLibrary/74HC86/74HC86-cache.lib  |  64 ++++++
 library/SubcircuitLibrary/74HC86/74HC86.cir        |  15 ++
 library/SubcircuitLibrary/74HC86/74HC86.cir.out    |  28 +++
 library/SubcircuitLibrary/74HC86/74HC86.pro        |  73 ++++++
 library/SubcircuitLibrary/74HC86/74HC86.sch        | 244 +++++++++++++++++++++
 library/SubcircuitLibrary/74HC86/74HC86.sub        |  22 ++
 .../74HC86/74HC86_Previous_Values.xml              |   1 +
 library/SubcircuitLibrary/74HC86/analysis          |   1 +
 9 files changed, 448 insertions(+)
 create mode 100644 library/SubcircuitLibrary/74HC86/74HC86-cache.lib
 create mode 100644 library/SubcircuitLibrary/74HC86/74HC86.cir
 create mode 100644 library/SubcircuitLibrary/74HC86/74HC86.cir.out
 create mode 100644 library/SubcircuitLibrary/74HC86/74HC86.pro
 create mode 100644 library/SubcircuitLibrary/74HC86/74HC86.sch
 create mode 100644 library/SubcircuitLibrary/74HC86/74HC86.sub
 create mode 100644 library/SubcircuitLibrary/74HC86/74HC86_Previous_Values.xml
 create mode 100644 library/SubcircuitLibrary/74HC86/analysis

diff --git a/.DS_Store b/.DS_Store
index 81cda701..e847f553 100644
Binary files a/.DS_Store and b/.DS_Store differ
diff --git a/library/SubcircuitLibrary/74HC86/74HC86-cache.lib b/library/SubcircuitLibrary/74HC86/74HC86-cache.lib
new file mode 100644
index 00000000..e5436a41
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC86/74HC86-cache.lib
@@ -0,0 +1,64 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC86/74HC86.cir b/library/SubcircuitLibrary/74HC86/74HC86.cir
new file mode 100644
index 00000000..8c27d35e
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC86/74HC86.cir
@@ -0,0 +1,15 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC86_subcircuit\74HC86_subcircuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 5/10/2025 7:52:45 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_xor		
+U3  Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad6_ d_xor		
+U4  Net-_U1-Pad9_ Net-_U1-Pad12_ Net-_U1-Pad7_ d_xor		
+U5  Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad8_ d_xor		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74HC86/74HC86.cir.out b/library/SubcircuitLibrary/74HC86/74HC86.cir.out
new file mode 100644
index 00000000..c472273e
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC86/74HC86.cir.out
@@ -0,0 +1,28 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc86_subcircuit\74hc86_subcircuit.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_xor
+* u3  net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ d_xor
+* u4  net-_u1-pad9_ net-_u1-pad12_ net-_u1-pad7_ d_xor
+* u5  net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad8_ d_xor
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u2
+a2 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u1-pad6_ u3
+a3 [net-_u1-pad9_ net-_u1-pad12_ ] net-_u1-pad7_ u4
+a4 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u1-pad8_ u5
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC86/74HC86.pro b/library/SubcircuitLibrary/74HC86/74HC86.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC86/74HC86.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC86/74HC86.sch b/library/SubcircuitLibrary/74HC86/74HC86.sch
new file mode 100644
index 00000000..b022ed81
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC86/74HC86.sch
@@ -0,0 +1,244 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xor U2
+U 1 1 681F3793
+P 3700 2300
+F 0 "U2" H 3700 2300 60  0000 C CNN
+F 1 "d_xor" H 3750 2400 47  0000 C CNN
+F 2 "" H 3700 2300 60  0000 C CNN
+F 3 "" H 3700 2300 60  0000 C CNN
+	1    3700 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xor U3
+U 1 1 681F3810
+P 3700 3650
+F 0 "U3" H 3700 3650 60  0000 C CNN
+F 1 "d_xor" H 3750 3750 47  0000 C CNN
+F 2 "" H 3700 3650 60  0000 C CNN
+F 3 "" H 3700 3650 60  0000 C CNN
+	1    3700 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xor U4
+U 1 1 681F3871
+P 6000 2800
+F 0 "U4" H 6000 2800 60  0000 C CNN
+F 1 "d_xor" H 6050 2900 47  0000 C CNN
+F 2 "" H 6000 2800 60  0000 C CNN
+F 3 "" H 6000 2800 60  0000 C CNN
+	1    6000 2800
+	-1   0    0    1   
+$EndComp
+$Comp
+L d_xor U5
+U 1 1 681F3930
+P 6000 4350
+F 0 "U5" H 6000 4350 60  0000 C CNN
+F 1 "d_xor" H 6050 4450 47  0000 C CNN
+F 2 "" H 6000 4350 60  0000 C CNN
+F 3 "" H 6000 4350 60  0000 C CNN
+	1    6000 4350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 1 1 681F3963
+P 2200 2200
+F 0 "U1" H 2250 2300 30  0000 C CNN
+F 1 "PORT" H 2200 2200 30  0000 C CNN
+F 2 "" H 2200 2200 60  0000 C CNN
+F 3 "" H 2200 2200 60  0000 C CNN
+	1    2200 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 681F3A41
+P 2800 2300
+F 0 "U1" H 2850 2400 30  0000 C CNN
+F 1 "PORT" H 2800 2300 30  0000 C CNN
+F 2 "" H 2800 2300 60  0000 C CNN
+F 3 "" H 2800 2300 60  0000 C CNN
+	3    2800 2300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2450 2200 3250 2200
+Wire Wire Line
+	3050 2300 3250 2300
+$Comp
+L PORT U1
+U 5 1 681F3ACF
+P 4400 2250
+F 0 "U1" H 4450 2350 30  0000 C CNN
+F 1 "PORT" H 4400 2250 30  0000 C CNN
+F 2 "" H 4400 2250 60  0000 C CNN
+F 3 "" H 4400 2250 60  0000 C CNN
+	5    4400 2250
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 2 1 681F3B64
+P 2200 3550
+F 0 "U1" H 2250 3650 30  0000 C CNN
+F 1 "PORT" H 2200 3550 30  0000 C CNN
+F 2 "" H 2200 3550 60  0000 C CNN
+F 3 "" H 2200 3550 60  0000 C CNN
+	2    2200 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 681F3BEF
+P 2800 3650
+F 0 "U1" H 2850 3750 30  0000 C CNN
+F 1 "PORT" H 2800 3650 30  0000 C CNN
+F 2 "" H 2800 3650 60  0000 C CNN
+F 3 "" H 2800 3650 60  0000 C CNN
+	4    2800 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 681F3C72
+P 4400 3600
+F 0 "U1" H 4450 3700 30  0000 C CNN
+F 1 "PORT" H 4400 3600 30  0000 C CNN
+F 2 "" H 4400 3600 60  0000 C CNN
+F 3 "" H 4400 3600 60  0000 C CNN
+	6    4400 3600
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	2450 3550 3250 3550
+Wire Wire Line
+	3050 3650 3250 3650
+$Comp
+L PORT U1
+U 8 1 681F3D06
+P 5300 4400
+F 0 "U1" H 5350 4500 30  0000 C CNN
+F 1 "PORT" H 5300 4400 30  0000 C CNN
+F 2 "" H 5300 4400 60  0000 C CNN
+F 3 "" H 5300 4400 60  0000 C CNN
+	8    5300 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 681F3D89
+P 6700 4450
+F 0 "U1" H 6750 4550 30  0000 C CNN
+F 1 "PORT" H 6700 4450 30  0000 C CNN
+F 2 "" H 6700 4450 60  0000 C CNN
+F 3 "" H 6700 4450 60  0000 C CNN
+	10   6700 4450
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	6450 4350 6950 4350
+$Comp
+L PORT U1
+U 11 1 681F3DFA
+P 7200 4350
+F 0 "U1" H 7250 4450 30  0000 C CNN
+F 1 "PORT" H 7200 4350 30  0000 C CNN
+F 2 "" H 7200 4350 60  0000 C CNN
+F 3 "" H 7200 4350 60  0000 C CNN
+	11   7200 4350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 7 1 681F3E81
+P 5300 2850
+F 0 "U1" H 5350 2950 30  0000 C CNN
+F 1 "PORT" H 5300 2850 30  0000 C CNN
+F 2 "" H 5300 2850 60  0000 C CNN
+F 3 "" H 5300 2850 60  0000 C CNN
+	7    5300 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 681F3EF2
+P 6700 2900
+F 0 "U1" H 6750 3000 30  0000 C CNN
+F 1 "PORT" H 6700 2900 30  0000 C CNN
+F 2 "" H 6700 2900 60  0000 C CNN
+F 3 "" H 6700 2900 60  0000 C CNN
+	9    6700 2900
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	6450 2800 7000 2800
+$Comp
+L PORT U1
+U 12 1 681F3FBE
+P 7250 2800
+F 0 "U1" H 7300 2900 30  0000 C CNN
+F 1 "PORT" H 7250 2800 30  0000 C CNN
+F 2 "" H 7250 2800 60  0000 C CNN
+F 3 "" H 7250 2800 60  0000 C CNN
+	12   7250 2800
+	-1   0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC86/74HC86.sub b/library/SubcircuitLibrary/74HC86/74HC86.sub
new file mode 100644
index 00000000..364f815a
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC86/74HC86.sub
@@ -0,0 +1,22 @@
+* Subcircuit 74HC86_subcircuit
+.subckt 74HC86_subcircuit net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 
+* c:\fossee\esim\library\subcircuitlibrary\74hc86_subcircuit\74hc86_subcircuit.cir
+* u2  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_xor
+* u3  net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ d_xor
+* u4  net-_u1-pad9_ net-_u1-pad12_ net-_u1-pad7_ d_xor
+* u5  net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad8_ d_xor
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u2
+a2 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u1-pad6_ u3
+a3 [net-_u1-pad9_ net-_u1-pad12_ ] net-_u1-pad7_ u4
+a4 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u1-pad8_ u5
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC86_subcircuit
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC86/74HC86_Previous_Values.xml b/library/SubcircuitLibrary/74HC86/74HC86_Previous_Values.xml
new file mode 100644
index 00000000..38a8bb2c
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC86/74HC86_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_xor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_xor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_xor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC86/analysis b/library/SubcircuitLibrary/74HC86/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC86/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
-- 
cgit