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2019-07-02Subcircuit added by ECE fellows 2019nilshah98
2019-07-02deviceModel Libraries added by ECE fellows 2019nilshah98
2019-07-02Examples added by ECE fellows 2019nilshah98
2019-07-01Merge pull request #114 from sunilshetye/masterfixesSunil Shetye
Master fixes
2019-07-01rename one of the versions of D.lib to userDiode.libSunil Shetye
2019-07-01remove extra + at the startSunil Shetye
2019-07-01update files from eSim-ExamplesSunil Shetye
2019-07-01add missing lib filesSunil Shetye
2019-07-01Half adder subcircuit filename conflict in WindowsSunil Shetye
Replaced Half_Adder example with renamed HalfAdder to avoid Windows case-only filename difference conflict with subcircuit half_adder. Based on contribution by https://github.com/MaxOLydian/eSim
2019-07-01remove temporary filesSunil Shetye
2019-07-01fix file permissionsSunil Shetye
2019-07-01Added missing .rst files. (#111)Anjali Jaiswal
* Added rst files
2019-07-01Merge pull request #113 from sunilshetye/subcircuitSunil Shetye
directly select filename
2019-07-01directly select filenameSunil Shetye
2019-07-01Merge pull request #112 from sunilshetye/kicadlibrarySunil Shetye
Increased the no of ports form 8 to 26 for designing sub-circuits
2019-07-01Increased the no of ports form 8 to 26 for designing sub-circuitsMudit Joshi
2019-07-01Merge pull request #110 from anjalijaiswal08/KicadLibrarySunil Shetye
KicadSchematicLibaray files changed.
2019-06-27Merge pull request #108 from sunilshetye/ignoreSunil Shetye
ignore
2019-06-27ignoreSunil Shetye
2019-06-27update esim subckt kicad schematic librarySunil Shetye
2019-06-27update esim pspice kicad schematic librarySunil Shetye
2019-06-27Merge pull request #104 from anjalijaiswal08/RenameProjectSunil Shetye
Rename project Done
2019-06-27Bug Fixedanjalijaiswal08
2019-06-27Merge pull request #107 from anjalijaiswal08/UploadSubcircuitSunil Shetye
Upload subcircuit
2019-06-27Removed extra print statementsanjalijaiswal08
2019-06-27Removed extra print statementsanjalijaiswal08
2019-06-27removed needless linesanjalijaiswal08
2019-06-27Speel errors removedanjalijaiswal08
2019-06-27Pep8 doneanjalijaiswal08
2019-06-27Pep8 changesanjalijaiswal08
2019-06-27uploading subcircuit doneanjalijaiswal08
2019-06-27doneanjalijaiswal08
2019-06-27changes need to be commitedanjalijaiswal08
2019-06-27second commitedanjalijaiswal08
2019-06-27second commitedanjalijaiswal08
2019-06-27half commitedanjalijaiswal08
2019-06-27Minor changesanjalijaiswal08
2019-06-27Uploading Subcircuit feature addedanjalijaiswal08
2019-06-27final changes doneanjalijaiswal08
2019-06-27Added loop and conditionanjalijaiswal08
2019-06-26Few Changesanjalijaiswal08
2019-06-26Changedanjalijaiswal08
2019-06-26Made pep8 complianceanjalijaiswal08
2019-06-26Removed unwanted codeanjalijaiswal08
2019-06-26Removed unwanted codeanjalijaiswal08
2019-06-26Update newProject.pyAnjali Jaiswal
2019-06-26Update Subcircuit.pyAnjali Jaiswal
2019-06-26Issue #82 solved: Renaming project addedanjalijaiswal08
2019-06-26Issue #82 solved: Renaming project addedanjalijaiswal08
2019-06-25Merge pull request #102 from sunilshetye/longlinesSunil Shetye
pep8: break long lines
generated by cgit (git 2.34.1) at 2024-12-21 07:43:06 +0000