Age | Commit message (Collapse) | Author | |
---|---|---|---|
2020-02-21 | restructured eSim libraries | rahulp13 | |
2020-02-16 | workspace functionality | rahulp13 | |
2020-02-16 | mode feature | rahulp13 | |
2020-02-15 | set modality to QErrorMessage | rahulp13 | |
2020-02-14 | pep8 compliant | rahulp13 | |
2020-02-14 | update README.md | rahulp13 | |
2020-02-14 | common code for Win and Linux, merged py2 changes | rahulp13 | |
2019-12-18 | removed appending dock windows to current_project | rahulp13 | |
2019-12-18 | changed debug statement | rahulp13 | |
2019-12-18 | restored OMEdit code, trigger for rename_project | rahulp13 | |
2019-07-02 | Merge pull request #115 from nilshah98/ese | saurabhb17 | |
Adding the work done by FSF 2019 eSim ECE Fellows | |||
2019-07-02 | kicadschematic libraries added by ECE fellows 2019 | nilshah98 | |
2019-07-02 | Subcircuit added by ECE fellows 2019 | nilshah98 | |
2019-07-02 | deviceModel Libraries added by ECE fellows 2019 | nilshah98 | |
2019-07-02 | Examples added by ECE fellows 2019 | nilshah98 | |
2019-07-01 | Merge pull request #114 from sunilshetye/masterfixes | Sunil Shetye | |
Master fixes | |||
2019-07-01 | rename one of the versions of D.lib to userDiode.lib | Sunil Shetye | |
2019-07-01 | remove extra + at the start | Sunil Shetye | |
2019-07-01 | update files from eSim-Examples | Sunil Shetye | |
2019-07-01 | add missing lib files | Sunil Shetye | |
2019-07-01 | Half adder subcircuit filename conflict in Windows | Sunil Shetye | |
Replaced Half_Adder example with renamed HalfAdder to avoid Windows case-only filename difference conflict with subcircuit half_adder. Based on contribution by https://github.com/MaxOLydian/eSim | |||
2019-07-01 | remove temporary files | Sunil Shetye | |
2019-07-01 | fix file permissions | Sunil Shetye | |
2019-07-01 | Added missing .rst files. (#111) | Anjali Jaiswal | |
* Added rst files | |||
2019-07-01 | Merge pull request #113 from sunilshetye/subcircuit | Sunil Shetye | |
directly select filename | |||
2019-07-01 | directly select filename | Sunil Shetye | |
2019-07-01 | Merge pull request #112 from sunilshetye/kicadlibrary | Sunil Shetye | |
Increased the no of ports form 8 to 26 for designing sub-circuits | |||
2019-07-01 | Increased the no of ports form 8 to 26 for designing sub-circuits | Mudit Joshi | |
2019-07-01 | Merge pull request #110 from anjalijaiswal08/KicadLibrary | Sunil Shetye | |
KicadSchematicLibaray files changed. | |||
2019-06-27 | Merge pull request #108 from sunilshetye/ignore | Sunil Shetye | |
ignore | |||
2019-06-27 | ignore | Sunil Shetye | |
2019-06-27 | update esim subckt kicad schematic library | Sunil Shetye | |
2019-06-27 | update esim pspice kicad schematic library | Sunil Shetye | |
2019-06-27 | Merge pull request #104 from anjalijaiswal08/RenameProject | Sunil Shetye | |
Rename project Done | |||
2019-06-27 | Bug Fixed | anjalijaiswal08 | |
2019-06-27 | Merge pull request #107 from anjalijaiswal08/UploadSubcircuit | Sunil Shetye | |
Upload subcircuit | |||
2019-06-27 | Removed extra print statements | anjalijaiswal08 | |
2019-06-27 | Removed extra print statements | anjalijaiswal08 | |
2019-06-27 | removed needless lines | anjalijaiswal08 | |
2019-06-27 | Speel errors removed | anjalijaiswal08 | |
2019-06-27 | Pep8 done | anjalijaiswal08 | |
2019-06-27 | Pep8 changes | anjalijaiswal08 | |
2019-06-27 | uploading subcircuit done | anjalijaiswal08 | |
2019-06-27 | done | anjalijaiswal08 | |
2019-06-27 | changes need to be commited | anjalijaiswal08 | |
2019-06-27 | second commited | anjalijaiswal08 | |
2019-06-27 | second commited | anjalijaiswal08 | |
2019-06-27 | half commited | anjalijaiswal08 | |
2019-06-27 | Minor changes | anjalijaiswal08 | |
2019-06-27 | Uploading Subcircuit feature added | anjalijaiswal08 | |