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-rwxr-xr-xsrc/maker/Appconfig.py6
-rwxr-xr-xsrc/maker/Maker.py2
-rwxr-xr-xsrc/maker/ModelGeneration.py42
-rwxr-xr-xsrc/maker/NgVeri.py18
4 files changed, 42 insertions, 26 deletions
diff --git a/src/maker/Appconfig.py b/src/maker/Appconfig.py
index 45d28e62..06758898 100755
--- a/src/maker/Appconfig.py
+++ b/src/maker/Appconfig.py
@@ -3,7 +3,11 @@ from configparser import ConfigParser
class Appconfig:
- home = os.path.expanduser("~")
+ if os.name == 'nt':
+ home = os.path.join('library', 'config')
+ else:
+ home = os.path.expanduser('~')
+
# Reading all variables from eSim config.ini
parser_esim = ConfigParser()
parser_esim.read(os.path.join(home, os.path.join('.esim', 'config.ini')))
diff --git a/src/maker/Maker.py b/src/maker/Maker.py
index 78fd13b2..60087018 100755
--- a/src/maker/Maker.py
+++ b/src/maker/Maker.py
@@ -82,7 +82,7 @@ class Maker(QtWidgets.QWidget):
# This function is to Add new verilog file
def addverilog(self):
- init_path = '../../../'
+ init_path = '../../'
if os.name == 'nt':
init_path = ''
self.verilogfile = QtCore.QDir.toNativeSeparators(
diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py
index 54b91d50..0f0f5c58 100755
--- a/src/maker/ModelGeneration.py
+++ b/src/maker/ModelGeneration.py
@@ -51,23 +51,31 @@ class ModelGeneration(QtWidgets.QWidget):
super().__init__()
self.obj_Appconfig = Appconfig.Appconfig()
print("Argument is : ", file)
- self.file = file
+
+ if os.name == 'nt':
+ self.file = file.replace('\\', '/')
+ else:
+ self.file = file
+
self.termedit = termedit
self.cur_dir = os.getcwd()
self.fname = os.path.basename(file)
self.fname = self.fname.lower()
print("Verilog/SystemVerilog/TL Verilog filename is : ", self.fname)
- self.home = os.path.expanduser("~")
+
+ if os.name == 'nt':
+ self.home = os.path.join('library', 'config')
+ else:
+ self.home = os.path.expanduser('~')
+
self.parser = ConfigParser()
self.parser.read(os.path.join(
self.home, os.path.join('.nghdl', 'config.ini')))
- self.ngspice_home = self.parser.get('NGSPICE', 'NGSPICE_HOME')
- self.release_dir = self.parser.get('NGSPICE', 'RELEASE')
+ self.nghdl_home = self.parser.get('NGHDL', 'NGHDL_HOME')
+ self.release_dir = self.parser.get('NGHDL', 'RELEASE')
self.src_home = self.parser.get('SRC', 'SRC_HOME')
self.licensefile = self.parser.get('SRC', 'LICENSE')
- self.digital_home = self.parser.get('NGSPICE', 'DIGITAL_MODEL')
-
- self.digital_home = self.digital_home.split("/ghdl")[0] + "/Ngveri"
+ self.digital_home = self.parser.get('NGHDL', 'DIGITAL_MODEL') + "/Ngveri"
# # #### Creating connection_info.txt file from verilog file #### #
# Readinf the file and performing operations and copying it in the Ngspice
@@ -441,7 +449,7 @@ and set the load for input ports */
cfunc.write("\n")
# if os.name == 'nt':
- # digital_home = parser.get('NGSPICE', 'DIGITAL_MODEL')
+ # digital_home = parser.get('NGHDL', 'DIGITAL_MODEL')
# msys_home = parser.get('COMPILER', 'MSYS_HOME')
# cmd_str2 = "/start_server.sh %d %s & read" + "\\" + "\"" + "\""
# cmd_str1 = os.path.normpath(
@@ -458,7 +466,7 @@ and set the load for input ports */
# else:
# cfunc.write(
# '\t\tsnprintf(command,1024,"' + home +
- # '/ngspice-nghdl/src/xspice/icm/ghdl/' +
+ # '/nghdl-simulator/src/xspice/icm/ghdl/' +
# fname.split('.')[0] +
# '/DUTghdl/start_server.sh %d %s &", sock_port, my_ip);'
# )
@@ -803,7 +811,7 @@ and set the load for input ports */
wno += " -Wno-" + item.strip("\n")
print("Running Verilator.............")
os.chdir(self.modelpath)
- self.release_home = self.parser.get('NGSPICE', 'RELEASE')
+ self.release_home = self.parser.get('NGHDL', 'RELEASE')
# print(self.modelpath)
self.cmd = "verilator -Wall " + wno + "\
@@ -865,8 +873,8 @@ and set the load for input ports */
self.cur_dir = os.getcwd()
print("Copying the required files to Release Folder.............")
os.chdir(self.modelpath)
- self.release_home = self.parser.get('NGSPICE', 'RELEASE')
- path_icm = os.path.join(self.release_home, "src/xspice/icm/Ngveri/")
+ self.release_home = self.parser.get('NGHDL', 'RELEASE')
+ path_icm = self.release_home + "/src/xspice/icm/Ngveri/"
if not os.path.isdir(path_icm + self.fname.split('.')[0]):
os.mkdir(path_icm + self.fname.split('.')[0])
path_icm = path_icm + self.fname.split('.')[0]
@@ -918,7 +926,7 @@ and set the load for input ports */
# Running the make command for Ngspice
def runMake(self):
print("run Make Called")
- self.release_home = self.parser.get('NGSPICE', 'RELEASE')
+ self.release_home = self.parser.get('NGHDL', 'RELEASE')
path_icm = os.path.join(self.release_home, "src/xspice/icm")
os.chdir(path_icm)
@@ -953,7 +961,7 @@ and set the load for input ports */
def runMakeInstall(self):
self.cur_dir = os.getcwd()
print("run Make Install Called")
- self.release_home = self.parser.get('NGSPICE', 'RELEASE')
+ self.release_home = self.parser.get('NGHDL', 'RELEASE')
path_icm = os.path.join(self.release_home, "src/xspice/icm")
os.chdir(path_icm)
@@ -994,7 +1002,7 @@ and set the load for input ports */
def addfile(self):
print("Adding the files required by the top level module file")
- init_path = '../../../'
+ init_path = '../../'
if os.name == 'nt':
init_path = ''
includefile = QtCore.QDir.toNativeSeparators(
@@ -1037,7 +1045,7 @@ and set the load for input ports */
# self.cur_dir = os.getcwd()
print("Adding the folder required by the top level module file")
- init_path = '../../../'
+ init_path = '../../'
if os.name == 'nt':
init_path = '' # noqa:F841
includefolder = QtCore.QDir.toNativeSeparators(
@@ -1152,7 +1160,7 @@ and set the load for input ports */
# Text += "</span>"
# self.termedit.append(Text+"\n")
- # init_path = '../../../'
+ # init_path = '../../'
# if os.name == 'nt':
# init_path = ''
# includefile = QtCore.QDir.toNativeSeparators(\
diff --git a/src/maker/NgVeri.py b/src/maker/NgVeri.py
index 4e3e37da..496782f9 100755
--- a/src/maker/NgVeri.py
+++ b/src/maker/NgVeri.py
@@ -46,16 +46,21 @@ class NgVeri(QtWidgets.QWidget):
QtWidgets.QWidget.__init__(self)
# Maker.addverilog(self)
self.obj_Appconfig = Appconfig()
- self.home = os.path.expanduser("~")
+
+ if os.name == 'nt':
+ self.home = os.path.join('library', 'config')
+ else:
+ self.home = os.path.expanduser('~')
+
self.parser = ConfigParser()
self.parser.read(os.path.join(
self.home, os.path.join('.nghdl', 'config.ini')))
- self.ngspice_home = self.parser.get('NGSPICE', 'NGSPICE_HOME')
- self.release_dir = self.parser.get('NGSPICE', 'RELEASE')
+ self.nghdl_home = self.parser.get('NGHDL', 'NGHDL_HOME')
+ self.release_dir = self.parser.get('NGHDL', 'RELEASE')
self.src_home = self.parser.get('SRC', 'SRC_HOME')
self.licensefile = self.parser.get('SRC', 'LICENSE')
- self.digital_home = self.parser.get('NGSPICE', 'DIGITAL_MODEL')
- self.digital_home = self.digital_home.split("/ghdl")[0] + "/Ngveri"
+ self.digital_home = self.parser.get('NGHDL', 'DIGITAL_MODEL')
+ self.digital_home = self.digital_home + "/Ngveri"
self.count = 0
self.text = ""
self.entry_var = {}
@@ -77,8 +82,7 @@ class NgVeri(QtWidgets.QWidget):
# Adding the verilog file in Maker tab to Ngveri Tab automatically
def addverilog(self):
-
- init_path = '../../../'
+ init_path = '../../'
if os.name == 'nt':
init_path = ''
# b=Maker.Maker(self)
generated by cgit (git 2.34.1) at 2024-12-22 19:16:21 +0000