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-rw-r--r--src/SubcircuitLibrary/diac/diac-cache.lib67
-rw-r--r--src/SubcircuitLibrary/diac/diac.bak138
-rw-r--r--src/SubcircuitLibrary/diac/diac.cir.ckt9
-rw-r--r--src/SubcircuitLibrary/diac/diac.cir.out~24
-rw-r--r--src/SubcircuitLibrary/diac/diac.sub~18
-rw-r--r--src/SubcircuitLibrary/full_adder/full_adder-cache.lib61
-rw-r--r--src/SubcircuitLibrary/full_adder/half_adder-cache.lib63
-rw-r--r--src/SubcircuitLibrary/half_adder/half_adder-cache.lib63
-rw-r--r--src/SubcircuitLibrary/lm555n/lm555n.bak435
-rw-r--r--src/SubcircuitLibrary/lm555n/lm555n.cir.ckt35
-rw-r--r--src/SubcircuitLibrary/lm555n/lm555n.cir.out~30
-rw-r--r--src/SubcircuitLibrary/lm555n/lm555n.cir~25
-rw-r--r--src/SubcircuitLibrary/scr/scr.bak243
-rw-r--r--src/SubcircuitLibrary/scr/scr.cir.ckt19
-rw-r--r--src/SubcircuitLibrary/scr/scr.cir.out~29
-rw-r--r--src/SubcircuitLibrary/scr/scr.sub~23
-rw-r--r--src/SubcircuitLibrary/triac/.triac.s.swpbin4096 -> 0 bytes
-rw-r--r--src/SubcircuitLibrary/triac/.triac.sub.swpbin12288 -> 0 bytes
-rw-r--r--src/SubcircuitLibrary/triac/triac.bak308
-rw-r--r--src/SubcircuitLibrary/triac/triac.cir.ckt26
-rw-r--r--src/SubcircuitLibrary/triac/triac.cir.out~41
-rw-r--r--src/SubcircuitLibrary/triac/triac.sub~35
-rw-r--r--src/SubcircuitLibrary/ua741/ua741-cache.bak100
-rw-r--r--src/SubcircuitLibrary/ua741/ua741.bak208
-rw-r--r--src/SubcircuitLibrary/ua741/ua741.cir.ckt9
25 files changed, 0 insertions, 2009 deletions
diff --git a/src/SubcircuitLibrary/diac/diac-cache.lib b/src/SubcircuitLibrary/diac/diac-cache.lib
deleted file mode 100644
index b15fdeec..00000000
--- a/src/SubcircuitLibrary/diac/diac-cache.lib
+++ /dev/null
@@ -1,67 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# GND
-#
-DEF GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "GND" 0 -150 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 95 50 H I C CNN
-F1 "PWR_FLAG" 0 180 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 20 20 0 0 w
-P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
-ENDDRAW
-ENDDEF
-#
-# aswitch
-#
-DEF aswitch U 0 40 Y Y 1 F N
-F0 "U" 450 300 60 H V C CNN
-F1 "aswitch" 450 200 60 H V C CNN
-F2 "" 450 100 60 H V C CNN
-F3 "" 450 100 60 H V C CNN
-DRAW
-S 200 250 650 100 0 1 0 N
-X ~ 2 0 150 200 R 50 50 1 1 O
-X ~ 3 850 150 200 L 50 50 1 1 O
-X ~ 1_IN 450 -100 200 U 50 20 1 1 I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/diac/diac.bak b/src/SubcircuitLibrary/diac/diac.bak
deleted file mode 100644
index 16009984..00000000
--- a/src/SubcircuitLibrary/diac/diac.bak
+++ /dev/null
@@ -1,138 +0,0 @@
-EESchema Schematic File Version 2 date 09/22/14 16:36:31
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:analogSpice
-LIBS:analogXSpice
-LIBS:convergenceAidSpice
-LIBS:converterSpice
-LIBS:digitalSpice
-LIBS:digitalXSpice
-LIBS:linearSpice
-LIBS:measurementSpice
-LIBS:portSpice
-LIBS:sourcesSpice
-LIBS:diac-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11700 8267
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "22 sep 2014"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-Wire Wire Line
- 4150 2750 4150 3450
-Connection ~ 4400 3750
-Wire Wire Line
- 4900 4250 4900 4450
-Wire Wire Line
- 4900 4450 4400 4450
-Wire Wire Line
- 4400 4450 4400 3450
-Wire Wire Line
- 5200 3400 5200 4050
-Connection ~ 4600 3400
-Wire Wire Line
- 4600 4050 4600 2750
-Wire Wire Line
- 4600 2750 4150 2750
-Wire Wire Line
- 4150 3250 4150 3600
-Wire Wire Line
- 4400 3450 4150 3450
-Connection ~ 4150 3450
-Wire Wire Line
- 4400 3750 4900 3750
-Wire Wire Line
- 4900 3750 4900 3600
-Wire Wire Line
- 4150 4100 4150 4300
-$Comp
-L PWR_FLAG #FLG01
-U 1 1 5417D647
-P 4150 4300
-F 0 "#FLG01" H 4150 4570 30 0001 C CNN
-F 1 "PWR_FLAG" H 4150 4530 30 0000 C CNN
- 1 4150 4300
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U3
-U 2 1 5417D62C
-P 5450 3400
-F 0 "U3" H 5450 3350 30 0000 C CNN
-F 1 "PORT" H 5450 3400 30 0000 C CNN
- 2 5450 3400
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U3
-U 1 1 5417D624
-P 4150 2500
-F 0 "U3" H 4150 2450 30 0000 C CNN
-F 1 "PORT" H 4150 2500 30 0000 C CNN
- 1 4150 2500
- 0 1 1 0
-$EndComp
-$Comp
-L GND #PWR02
-U 1 1 5417D5DC
-P 4150 4300
-F 0 "#PWR02" H 4150 4300 30 0001 C CNN
-F 1 "GND" H 4150 4230 30 0001 C CNN
- 1 4150 4300
- 1 0 0 -1
-$EndComp
-$Comp
-L ANALOGSWITCH U2
-U 1 1 5417D537
-P 4900 4050
-F 0 "U2" H 4700 4100 30 0000 C CNN
-F 1 "ANALOGSWITCH" H 4900 4050 30 0000 C CNN
- 1 4900 4050
- 1 0 0 -1
-$EndComp
-$Comp
-L ANALOGSWITCH U1
-U 1 1 5417D530
-P 4900 3400
-F 0 "U1" H 4700 3450 30 0000 C CNN
-F 1 "ANALOGSWITCH" H 4900 3400 30 0000 C CNN
- 1 4900 3400
- 1 0 0 -1
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/diac/diac.cir.ckt b/src/SubcircuitLibrary/diac/diac.cir.ckt
deleted file mode 100644
index e89f9cfb..00000000
--- a/src/SubcircuitLibrary/diac/diac.cir.ckt
+++ /dev/null
@@ -1,9 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: 09/22/14 16:36:23
-
-u3 1 2 port
-* Analog Switch analogswitch
-* Analog Switch analogswitch
-a1 1 (1 2) u2
-.model u2 aswitch(cntl_on=-25 cntl_off=-0.1 r_on=0.0125 r_off=1000000)
-a2 1 (1 2) u1
-.model u1 aswitch(cntl_on=25 cntl_off=0.1 r_on=0.0125 r_off=1000000)
diff --git a/src/SubcircuitLibrary/diac/diac.cir.out~ b/src/SubcircuitLibrary/diac/diac.cir.out~
deleted file mode 100644
index 89cc8142..00000000
--- a/src/SubcircuitLibrary/diac/diac.cir.out~
+++ /dev/null
@@ -1,24 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/diac/diac.cir
-
-* u3 1 2 port
-* u1 1 1 2 aswitch
-* u2 1 1 2 aswitch
-a1 1 [1 2 ] u1
-a2 1 [1 2 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/diac/diac.sub~ b/src/SubcircuitLibrary/diac/diac.sub~
deleted file mode 100644
index 43c2d279..00000000
--- a/src/SubcircuitLibrary/diac/diac.sub~
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit diac
-.subckt diac 1 2
-* /opt/esim/src/subcircuitlibrary/diac/diac.cir
-* u1 1 1 2 aswitch
-* u2 1 1 2 aswitch
-a1 1 [1 2 ] u1
-a2 1 [1 2 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-* Control Statements
-
-.ends diac \ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/full_adder-cache.lib b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib
deleted file mode 100644
index 623a7f41..00000000
--- a/src/SubcircuitLibrary/full_adder/full_adder-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_adder
-#
-DEF half_adder X 0 40 Y Y 1 F N
-F0 "X" 900 500 60 H V C CNN
-F1 "half_adder" 900 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 500 800 1250 0 0 1 0 N
-X IN1 1 300 700 200 R 50 50 1 1 I
-X IN2 2 300 100 200 R 50 50 1 1 I
-X SUM 3 1450 700 200 L 50 50 1 1 O
-X COUT 4 1450 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/full_adder/half_adder-cache.lib b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib
deleted file mode 100644
index 68785220..00000000
--- a/src/SubcircuitLibrary/full_adder/half_adder-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 150 -50 -200 -50 N
-P 2 0 1 0 150 150 -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/half_adder/half_adder-cache.lib b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib
deleted file mode 100644
index 68785220..00000000
--- a/src/SubcircuitLibrary/half_adder/half_adder-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 150 -50 -200 -50 N
-P 2 0 1 0 150 150 -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.bak b/src/SubcircuitLibrary/lm555n/lm555n.bak
deleted file mode 100644
index 92d1f7a7..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n.bak
+++ /dev/null
@@ -1,435 +0,0 @@
-EESchema Schematic File Version 2 date Monday 17 December 2012 10:48:46 AM IST
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:analogSpice
-LIBS:analogXSpice
-LIBS:converterSpice
-LIBS:digitalSpice
-LIBS:linearSpice
-LIBS:measurementSpice
-LIBS:portSpice
-LIBS:sourcesSpice
-LIBS:digitalXSpice
-LIBS:lm555n-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11700 8267
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "17 dec 2012"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L D_INVERTER U5
-U 1 1 50CEA9C5
-P 6700 4050
-F 0 "U5" H 6550 4150 40 0000 C CNN
-F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN
- 1 6700 4050
- 1 0 0 -1
-$EndComp
-$Comp
-L D_SRLATCH U6
-U 1 1 50CEA9AE
-P 7100 3400
-F 0 "U6" H 6900 3650 60 0000 C CNN
-F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN
- 1 7100 3400
- 1 0 0 -1
-$EndComp
-Text Notes 5750 3050 0 60 ~ 0
-IC 555
-Wire Wire Line
- 4700 3000 4900 3000
-Wire Wire Line
- 4700 4750 4700 4650
-Connection ~ 4400 3550
-Connection ~ 4400 4900
-Wire Wire Line
- 4300 4900 7700 4900
-Wire Wire Line
- 4400 4200 4400 4100
-Wire Wire Line
- 7700 4900 7700 4800
-Wire Wire Line
- 7700 3250 7850 3250
-Wire Wire Line
- 7400 4600 7100 4600
-Wire Wire Line
- 7100 4600 7100 4250
-Wire Wire Line
- 7700 3650 7700 3550
-Wire Wire Line
- 6350 4050 6450 4050
-Wire Wire Line
- 6950 3900 6950 4000
-Wire Wire Line
- 7150 4000 7150 4050
-Wire Wire Line
- 7150 4050 6950 4050
-Wire Wire Line
- 6500 3550 6200 3550
-Wire Wire Line
- 6350 3250 6500 3250
-Wire Wire Line
- 5400 3250 5100 3250
-Wire Wire Line
- 5100 3250 5100 3750
-Wire Wire Line
- 5550 4500 5550 4350
-Wire Wire Line
- 5700 3550 5800 3550
-Wire Wire Line
- 5900 3250 6000 3250
-Wire Wire Line
- 6000 3850 6350 3850
-Wire Wire Line
- 5800 4150 6200 4150
-Wire Wire Line
- 5200 3550 5200 3700
-Wire Wire Line
- 5200 3700 5550 3700
-Wire Wire Line
- 5550 3700 5550 3750
-Connection ~ 5550 4450
-Wire Wire Line
- 5750 4400 5750 4450
-Wire Wire Line
- 5100 4350 5100 4450
-Wire Wire Line
- 5100 4450 5750 4450
-Wire Wire Line
- 6500 3400 6450 3400
-Wire Wire Line
- 6450 3400 6450 4050
-Wire Wire Line
- 6950 4000 7250 4000
-Wire Wire Line
- 7250 4000 7250 3900
-Connection ~ 7150 4000
-Wire Wire Line
- 7600 4250 7700 4250
-Wire Wire Line
- 7700 4400 7700 4350
-Wire Wire Line
- 7700 4350 7800 4350
-Wire Wire Line
- 7850 3850 7900 3850
-Wire Wire Line
- 4400 4900 4400 4700
-Wire Wire Line
- 4400 3600 4400 3500
-Wire Wire Line
- 4300 3000 4400 3000
-Wire Wire Line
- 4400 4150 4700 4150
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diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt b/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt
deleted file mode 100644
index 90f04a32..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt
+++ /dev/null
@@ -1,35 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
-
-* Inverter d_inverter
-* SR Latch d_srlatch
-e2 18 0 23 14 10000
-* Limiter limit8
-* Digital to Analog converter dac8
-* Analog to Digital converter adc8
-u1 22 14 7 6 15 16 3 13 port
-r8 9 2 1500
-q1 3 2 22 qnom
-r7 18 20 25
-r6 17 19 25
-e1 17 0 16 15 10000
-r4 16 15 2e6
-r5 23 14 2e6
-r3 23 22 5000
-r2 15 23 5000
-r1 13 15 5000
-a1 5 21 u5
-.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12)
-a2 1 4 5 21 21 8 10 u6
-.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0
-+sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12
-+sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12)
-a3 19 11 u4
-a4 20 12 u4
-.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0)
-a5 [8] [7] u3
-a6 [10] [9] u3
-.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 )
-a7 [11] [4] u2
-a8 [12] [1] u2
-a9 [6] [5] u2
-.model u2 adc_bridge(in_low=0.8 in_high=2.0 )
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out~ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out~
deleted file mode 100644
index bc50c640..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n.cir.out~
+++ /dev/null
@@ -1,30 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
-
-* u5 5 21 d_inverter
-* u6 1 4 5 21 21 8 10 d_srlatch
-e2 18 0 23 14 10000
-r8 9 2 1500
-q1 22 2 3 qnom
-r7 18 20 25
-r6 17 19 25
-e1 17 0 16 15 10000
-r4 16 15 2e6
-r5 23 14 2e6
-r3 23 22 5000
-r2 15 23 5000
-r1 13 15 5000
-a1 5 21 u5
-a2 1 4 5 21 21 8 10 u6
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_srlatch, NgSpice Name: d_srlatch
-.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 )
-.ac lin 0 0Hz 0Hz
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir~ b/src/SubcircuitLibrary/lm555n/lm555n.cir~
deleted file mode 100644
index 7ef9e6a5..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n.cir~
+++ /dev/null
@@ -1,25 +0,0 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:49 AM IST
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U5 5 21 D_INVERTER
-U6 1 4 5 21 21 8 10 D_SRLATCH
-E2 18 0 23 14 10000
-*U4 19 20 11 12 LIMIT8
-*U3 8 10 7 9 DAC8
-*U2 11 12 6 4 1 5 ADC8
-*U1 22 14 7 6 15 16 3 13 PORT
-R8 9 2 1500
-Q1 22 2 3 QNOM
-R7 18 20 25
-R6 17 19 25
-E1 17 0 16 15 10000
-R4 16 15 2E6
-R5 23 14 2E6
-R3 23 22 5000
-R2 15 23 5000
-R1 13 15 5000
-
-.end
diff --git a/src/SubcircuitLibrary/scr/scr.bak b/src/SubcircuitLibrary/scr/scr.bak
deleted file mode 100644
index 58b985d9..00000000
--- a/src/SubcircuitLibrary/scr/scr.bak
+++ /dev/null
@@ -1,243 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:analogSpice
-LIBS:analogXSpice
-LIBS:convergenceAidSpice
-LIBS:converterSpice
-LIBS:digitalSpice
-LIBS:digitalXSpice
-LIBS:measurementSpice
-LIBS:portSpice
-LIBS:sourcesSpice
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:scr-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "21 aug 2014"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
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-$EndDescr
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-$Comp
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-F 2 "" H 6850 2200 60 0000 C CNN
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- 1 6400 2100
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-$EndComp
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diff --git a/src/SubcircuitLibrary/scr/scr.cir.ckt b/src/SubcircuitLibrary/scr/scr.cir.ckt
deleted file mode 100644
index b0e218fd..00000000
--- a/src/SubcircuitLibrary/scr/scr.cir.ckt
+++ /dev/null
@@ -1,19 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: 08/21/14 11:07:22
-.include diode.lib
-
-u2 5 8 1 port
-* f2
-* Analog Switch analogswitch
-d1 4 2 diode
-v2 3 4 dc 0
-c1 5 6 10u
-r2 5 6 1
-* f1
-v1 9 7 dc 0
-r1 8 9 50
-Vf2 2 5 0
-f2 5 6 Vf2 100
-Vf1 7 5 0
-f1 5 6 Vf1 10
-a1 6 (1 3) u1
-.model u1 aswitch(cntl_on=0.25 cntl_off=0.1 r_on=0.0125 r_off=1000000)
diff --git a/src/SubcircuitLibrary/scr/scr.cir.out~ b/src/SubcircuitLibrary/scr/scr.cir.out~
deleted file mode 100644
index d600f25d..00000000
--- a/src/SubcircuitLibrary/scr/scr.cir.out~
+++ /dev/null
@@ -1,29 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-
-.include PowerDiode.lib
-* u2 3 7 1 port
-* f2
-d1 5 2 PowerDiode
-c1 3 9 10u
-* f1
-v1 8 4 dc 0
-v2 6 5 dc 0
-* u1 9 1 6 aswitch
-r1 7 8 50
-r2 3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 (1 6) u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
-.tran 0e-12 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/scr/scr.sub~ b/src/SubcircuitLibrary/scr/scr.sub~
deleted file mode 100644
index 0fdddbf4..00000000
--- a/src/SubcircuitLibrary/scr/scr.sub~
+++ /dev/null
@@ -1,23 +0,0 @@
-* Subcircuit scr
-.subckt scr 3 7 1
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-.include PowerDiode.lib
-* f2
-d1 5 2 PowerDiode
-c1 3 9 10u
-* f1
-v1 8 4 dc 0
-v2 6 5 dc 0
-* u1 9 1 6 aswitch
-r1 7 8 50
-r2 3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 [1 6 ] u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
-* Control Statements
-
-.ends scr \ No newline at end of file
diff --git a/src/SubcircuitLibrary/triac/.triac.s.swp b/src/SubcircuitLibrary/triac/.triac.s.swp
deleted file mode 100644
index 1a4c2d0e..00000000
--- a/src/SubcircuitLibrary/triac/.triac.s.swp
+++ /dev/null
Binary files differ
diff --git a/src/SubcircuitLibrary/triac/.triac.sub.swp b/src/SubcircuitLibrary/triac/.triac.sub.swp
deleted file mode 100644
index 521ce758..00000000
--- a/src/SubcircuitLibrary/triac/.triac.sub.swp
+++ /dev/null
Binary files differ
diff --git a/src/SubcircuitLibrary/triac/triac.bak b/src/SubcircuitLibrary/triac/triac.bak
deleted file mode 100644
index f30533a0..00000000
--- a/src/SubcircuitLibrary/triac/triac.bak
+++ /dev/null
@@ -1,308 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
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diff --git a/src/SubcircuitLibrary/triac/triac.cir.ckt b/src/SubcircuitLibrary/triac/triac.cir.ckt
deleted file mode 100644
index 821b417b..00000000
--- a/src/SubcircuitLibrary/triac/triac.cir.ckt
+++ /dev/null
@@ -1,26 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: 09/20/14 11:23:24
-.include diode.lib
-
-u3 7 4 5 port
-* f3
-d2 3 2 diode
-v3 2 1 dc 0
-* Analog Switch analogswitch
-d1 11 7 diode
-* f2
-v2 8 10 dc 0
-* Analog Switch analogswitch
-c1 7 9 10u
-r1 7 9 1
-* f1
-v1 5 6 dc 0
-Vf3 3 7 0
-f3 7 9 Vf3 10
-Vf2 10 11 0
-f2 7 9 Vf2 10
-Vf1 6 7 0
-f1 7 9 Vf1 100
-a1 9 (1 4) u2
-.model u2 aswitch(cntl_on=-1 cntl_off=-0.1 r_on=0.0125 r_off=1000000)
-a2 9 (4 8) u1
-.model u1 aswitch(cntl_on=1 cntl_off=0.1 r_on=0.0125 r_off=1000000)
diff --git a/src/SubcircuitLibrary/triac/triac.cir.out~ b/src/SubcircuitLibrary/triac/triac.cir.out~
deleted file mode 100644
index 7bd15a7b..00000000
--- a/src/SubcircuitLibrary/triac/triac.cir.out~
+++ /dev/null
@@ -1,41 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/triac/triac.cir
-
-.include PowerDiode.lib
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-* f3
-v3 7 2 dc 0
-* f2
-v2 6 3 dc 0
-c1 8 9 10u
-* f1
-v1 10 4 dc 0
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-* u2 9 2 11 aswitch
-r1 8 9 1
-d1 5 8 PowerDiode
-d2 1 7 PowerDiode
-Vf3 1 8 0
-f3 8 9 Vf3 10
-Vf2 3 5 0
-f2 8 9 Vf2 10
-Vf1 4 8 0
-f1 8 9 Vf1 100
-a1 9 [11 6 ] u1
-a2 9 [2 11 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
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-* Schematic Name: aswitch, NgSpice Name: aswitch
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-.tran 0e-00 0e-00 0e-00
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-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
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-.end
diff --git a/src/SubcircuitLibrary/triac/triac.sub~ b/src/SubcircuitLibrary/triac/triac.sub~
deleted file mode 100644
index ebbed05e..00000000
--- a/src/SubcircuitLibrary/triac/triac.sub~
+++ /dev/null
@@ -1,35 +0,0 @@
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-.subckt triac 8 11 10
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diff --git a/src/SubcircuitLibrary/ua741/ua741-cache.bak b/src/SubcircuitLibrary/ua741/ua741-cache.bak
deleted file mode 100644
index eaad34ad..00000000
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diff --git a/src/SubcircuitLibrary/ua741/ua741.bak b/src/SubcircuitLibrary/ua741/ua741.bak
deleted file mode 100644
index 6be92803..00000000
--- a/src/SubcircuitLibrary/ua741/ua741.bak
+++ /dev/null
@@ -1,208 +0,0 @@
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-LIBS:power
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-LIBS:conn
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-LIBS:regul
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-LIBS:converterSpice
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diff --git a/src/SubcircuitLibrary/ua741/ua741.cir.ckt b/src/SubcircuitLibrary/ua741/ua741.cir.ckt
deleted file mode 100644
index 3661a9a2..00000000
--- a/src/SubcircuitLibrary/ua741/ua741.cir.ckt
+++ /dev/null
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-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
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generated by cgit (git 2.34.1) at 2024-12-22 12:03:45 +0000