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-rw-r--r--src/SubcircuitLibrary/triac/.triac.s.swpbin4096 -> 0 bytes
-rw-r--r--src/SubcircuitLibrary/triac/.triac.sub.swpbin12288 -> 0 bytes
-rw-r--r--src/SubcircuitLibrary/triac/PowerDiode.lib21
-rw-r--r--src/SubcircuitLibrary/triac/triac.bak308
-rw-r--r--src/SubcircuitLibrary/triac/triac.cir.ckt26
-rw-r--r--src/SubcircuitLibrary/triac/triac.cir.out~41
-rw-r--r--src/SubcircuitLibrary/triac/triac.sub~35
7 files changed, 1 insertions, 430 deletions
diff --git a/src/SubcircuitLibrary/triac/.triac.s.swp b/src/SubcircuitLibrary/triac/.triac.s.swp
deleted file mode 100644
index 1a4c2d0e..00000000
--- a/src/SubcircuitLibrary/triac/.triac.s.swp
+++ /dev/null
Binary files differ
diff --git a/src/SubcircuitLibrary/triac/.triac.sub.swp b/src/SubcircuitLibrary/triac/.triac.sub.swp
deleted file mode 100644
index 521ce758..00000000
--- a/src/SubcircuitLibrary/triac/.triac.sub.swp
+++ /dev/null
Binary files differ
diff --git a/src/SubcircuitLibrary/triac/PowerDiode.lib b/src/SubcircuitLibrary/triac/PowerDiode.lib
index a2f61dce..d6fb6469 100644
--- a/src/SubcircuitLibrary/triac/PowerDiode.lib
+++ b/src/SubcircuitLibrary/triac/PowerDiode.lib
@@ -1,20 +1 @@
-.MODEL PowerDiode D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ bv=1800
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=2.2E-15
-+ Xti=3
-+ Ibvl=1.9556m
-) \ No newline at end of file
+.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m )
diff --git a/src/SubcircuitLibrary/triac/triac.bak b/src/SubcircuitLibrary/triac/triac.bak
deleted file mode 100644
index f30533a0..00000000
--- a/src/SubcircuitLibrary/triac/triac.bak
+++ /dev/null
@@ -1,308 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:triac-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
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-$EndComp
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diff --git a/src/SubcircuitLibrary/triac/triac.cir.ckt b/src/SubcircuitLibrary/triac/triac.cir.ckt
deleted file mode 100644
index 821b417b..00000000
--- a/src/SubcircuitLibrary/triac/triac.cir.ckt
+++ /dev/null
@@ -1,26 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: 09/20/14 11:23:24
-.include diode.lib
-
-u3 7 4 5 port
-* f3
-d2 3 2 diode
-v3 2 1 dc 0
-* Analog Switch analogswitch
-d1 11 7 diode
-* f2
-v2 8 10 dc 0
-* Analog Switch analogswitch
-c1 7 9 10u
-r1 7 9 1
-* f1
-v1 5 6 dc 0
-Vf3 3 7 0
-f3 7 9 Vf3 10
-Vf2 10 11 0
-f2 7 9 Vf2 10
-Vf1 6 7 0
-f1 7 9 Vf1 100
-a1 9 (1 4) u2
-.model u2 aswitch(cntl_on=-1 cntl_off=-0.1 r_on=0.0125 r_off=1000000)
-a2 9 (4 8) u1
-.model u1 aswitch(cntl_on=1 cntl_off=0.1 r_on=0.0125 r_off=1000000)
diff --git a/src/SubcircuitLibrary/triac/triac.cir.out~ b/src/SubcircuitLibrary/triac/triac.cir.out~
deleted file mode 100644
index 7bd15a7b..00000000
--- a/src/SubcircuitLibrary/triac/triac.cir.out~
+++ /dev/null
@@ -1,41 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/triac/triac.cir
-
-.include PowerDiode.lib
-* u3 8 11 10 port
-* f3
-v3 7 2 dc 0
-* f2
-v2 6 3 dc 0
-c1 8 9 10u
-* f1
-v1 10 4 dc 0
-* u1 9 11 6 aswitch
-* u2 9 2 11 aswitch
-r1 8 9 1
-d1 5 8 PowerDiode
-d2 1 7 PowerDiode
-Vf3 1 8 0
-f3 8 9 Vf3 10
-Vf2 3 5 0
-f2 8 9 Vf2 10
-Vf1 4 8 0
-f1 8 9 Vf1 100
-a1 9 [11 6 ] u1
-a2 9 [2 11 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/triac/triac.sub~ b/src/SubcircuitLibrary/triac/triac.sub~
deleted file mode 100644
index ebbed05e..00000000
--- a/src/SubcircuitLibrary/triac/triac.sub~
+++ /dev/null
@@ -1,35 +0,0 @@
-* Subcircuit triac
-.subckt triac 8 11 10
-* /opt/esim/src/subcircuitlibrary/triac/triac.cir
-.include PowerDiode.lib
-* f3
-v3 7 2 dc 0
-* f2
-v2 6 3 dc 0
-c1 8 9 10u
-* f1
-v1 10 4 dc 0
-* u1 9 11 6 aswitch
-* u2 9 2 11 aswitch
-r1 8 9 1
-d1 5 8 PowerDiode
-d2 1 7 PowerDiode
-Vf3 1 8 0
-f3 8 9 Vf3 10
-Vf2 3 5 0
-f2 8 9 Vf2 10
-Vf1 4 8 0
-f1 8 9 Vf1 100
-a1 9 [11 6 ] u1
-a2 9 [2 11 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
-* Control Statements
-
-.ends triac \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-22 11:02:17 +0000