9 files changed, 470 insertions, 470 deletions
diff --git a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib
index f874f5e2..6949ac1a 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib
+++ b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib
@@ -1,79 +1,79 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_sub
-#
-DEF half_sub X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "half_sub" 0 0 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -300 300 300 -300 0 1 0 N
-X A 1 -500 200 200 R 50 50 1 1 I
-X B 2 -500 -100 200 R 50 50 1 1 I
-X D 3 500 150 200 L 50 50 1 1 O
-X BORROW 4 500 -100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# half_sub
+#
+DEF half_sub X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "half_sub" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 300 300 -300 0 1 0 N
+X A 1 -500 200 200 R 50 50 1 1 I
+X B 2 -500 -100 200 R 50 50 1 1 I
+X D 3 500 150 200 L 50 50 1 1 O
+X BORROW 4 500 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib
index 416747ef..803b5ece 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib
+++ b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib
@@ -1,20 +1,20 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# half_sub-RESCUE-full_sub
-#
-DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -1450 850 1550 -1050 0 1 0 N
-X A 1 -1100 850 200 R 50 50 1 1 I
-X B 2 -350 850 200 R 50 50 1 1 I
-X D 3 -800 -1050 200 L 50 50 1 1 O
-X BORROW 4 0 -1050 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# half_sub-RESCUE-full_sub
+#
+DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -1450 850 1550 -1050 0 1 0 N
+X A 1 -1100 850 200 R 50 50 1 1 I
+X B 2 -350 850 200 R 50 50 1 1 I
+X D 3 -800 -1050 200 L 50 50 1 1 O
+X BORROW 4 0 -1050 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir b/src/SubcircuitLibrary/full_sub/full_sub.cir
index 7d6f198f..67359421 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub.cir
+++ b/src/SubcircuitLibrary/full_sub/full_sub.cir
@@ -1,14 +1,14 @@
-* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or		
-U5  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT		
-X1  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub		
-X2  Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub		
-
-.end
+* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3  Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or		
+U5  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT		
+X1  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub		
+X2  Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub		
+
+.end
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir.out b/src/SubcircuitLibrary/full_sub/full_sub.cir.out
index e310dcd0..5e58cc0a 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub.cir.out
+++ b/src/SubcircuitLibrary/full_sub/full_sub.cir.out
@@ -1,19 +1,19 @@
-* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
-
-.include half_sub.sub
-* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
-* u5  net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port
-x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
-x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
-a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
+
+.include half_sub.sub
+* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
+* u5  net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port
+x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
+x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
+a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.pro b/src/SubcircuitLibrary/full_sub/full_sub.pro
index 3336e88e..1a0c3543 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub.pro
+++ b/src/SubcircuitLibrary/full_sub/full_sub.pro
@@ -1,74 +1,74 @@
-update=03/07/19 10:55:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=full_sub-rescue
-LibName2=adc-dac
-LibName3=memory
-LibName4=xilinx
-LibName5=microcontrollers
-LibName6=dsp
-LibName7=microchip
-LibName8=analog_switches
-LibName9=motorola
-LibName10=texas
-LibName11=intel
-LibName12=audio
-LibName13=interface
-LibName14=digital-audio
-LibName15=philips
-LibName16=display
-LibName17=cypress
-LibName18=siliconi
-LibName19=opto
-LibName20=atmel
-LibName21=contrib
-LibName22=power
-LibName23=device
-LibName24=transistors
-LibName25=conn
-LibName26=linear
-LibName27=regul
-LibName28=74xx
-LibName29=cmos4000
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Miscellaneous
-LibName35=eSim_Power
-LibName36=eSim_Sources
-LibName37=eSim_Subckt
-LibName38=eSim_User
-LibName39=eSim_Plot
-LibName40=eSim_PSpice
-
+update=03/07/19 10:55:03
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=full_sub-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=device
+LibName24=transistors
+LibName25=conn
+LibName26=linear
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_User
+LibName39=eSim_Plot
+LibName40=eSim_PSpice
+
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sch b/src/SubcircuitLibrary/full_sub/full_sub.sch
index ed8ac50d..99ca85e5 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub.sch
+++ b/src/SubcircuitLibrary/full_sub/full_sub.sch
@@ -1,211 +1,211 @@
-EESchema Schematic File Version 2
-LIBS:full_sub-rescue
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:full_sub-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U3
-U 1 1 5C80734A
-P 9350 4050
-F 0 "U3" H 9350 4050 60  0000 C CNN
-F 1 "d_or" H 9350 4150 60  0000 C CNN
-F 2 "" H 9350 4050 60  0000 C CNN
-F 3 "" H 9350 4050 60  0000 C CNN
-	1    9350 4050
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4850 3600 5800 3600
-Wire Wire Line
-	4650 2800 8600 2800
-Wire Wire Line
-	8600 2800 8600 3950
-Wire Wire Line
-	8600 3950 8900 3950
-Wire Wire Line
-	8100 4450 8650 4450
-Wire Wire Line
-	8650 4450 8650 4050
-Wire Wire Line
-	8650 4050 8900 4050
-Wire Wire Line
-	2800 3450 2800 3250
-Wire Wire Line
-	2800 3250 3300 3250
-Wire Wire Line
-	1450 3550 3300 3550
-Wire Wire Line
-	4050 5100 5200 5100
-Wire Wire Line
-	5800 3600 5800 5250
-Wire Wire Line
-	8250 5250 9350 5250
-Wire Wire Line
-	9350 5250 9350 4900
-Wire Wire Line
-	9350 4900 10750 4900
-Wire Wire Line
-	9800 4000 9800 4600
-Wire Wire Line
-	9800 4600 9550 4600
-Wire Wire Line
-	9550 4600 9550 4800
-Wire Wire Line
-	9550 4800 10750 4800
-$Comp
-L PORT U5
-U 1 1 5C80A4E8
-P 1200 3450
-F 0 "U5" H 1250 3550 30  0000 C CNN
-F 1 "PORT" H 1200 3450 30  0000 C CNN
-F 2 "" H 1200 3450 60  0000 C CNN
-F 3 "" H 1200 3450 60  0000 C CNN
-	1    1200 3450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 2 1 5C80A51E
-P 1200 3650
-F 0 "U5" H 1250 3750 30  0000 C CNN
-F 1 "PORT" H 1200 3650 30  0000 C CNN
-F 2 "" H 1200 3650 60  0000 C CNN
-F 3 "" H 1200 3650 60  0000 C CNN
-	2    1200 3650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 3 1 5C80A54E
-P 3800 5100
-F 0 "U5" H 3850 5200 30  0000 C CNN
-F 1 "PORT" H 3800 5100 30  0000 C CNN
-F 2 "" H 3800 5100 60  0000 C CNN
-F 3 "" H 3800 5100 60  0000 C CNN
-	3    3800 5100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 5 1 5C80A828
-P 11000 4800
-F 0 "U5" H 11050 4900 30  0000 C CNN
-F 1 "PORT" H 11000 4800 30  0000 C CNN
-F 2 "" H 11000 4800 60  0000 C CNN
-F 3 "" H 11000 4800 60  0000 C CNN
-	5    11000 4800
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 4 1 5C80AB2A
-P 11000 4950
-F 0 "U5" H 11050 5050 30  0000 C CNN
-F 1 "PORT" H 11000 4950 30  0000 C CNN
-F 2 "" H 11000 4950 60  0000 C CNN
-F 3 "" H 11000 4950 60  0000 C CNN
-	4    11000 4950
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	1450 3450 2800 3450
-Wire Wire Line
-	1450 3650 1450 3550
-Wire Wire Line
-	10750 4900 10750 4950
-$Comp
-L half_sub X1
-U 1 1 5C80AC4D
-P 3800 3450
-F 0 "X1" H 3800 3450 60  0000 C CNN
-F 1 "half_sub" H 3800 3450 60  0000 C CNN
-F 2 "" H 3800 3450 60  0001 C CNN
-F 3 "" H 3800 3450 60  0001 C CNN
-	1    3800 3450
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4300 3550 4650 3550
-Wire Wire Line
-	4650 3550 4650 2800
-Wire Wire Line
-	4300 3300 4850 3300
-Wire Wire Line
-	4850 3300 4850 3600
-$Comp
-L half_sub X2
-U 1 1 5C80AD72
-P 7300 5150
-F 0 "X2" H 7300 5150 60  0000 C CNN
-F 1 "half_sub" H 7300 5150 60  0000 C CNN
-F 2 "" H 7300 5150 60  0001 C CNN
-F 3 "" H 7300 5150 60  0001 C CNN
-	1    7300 5150
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5800 5250 6800 5250
-Wire Wire Line
-	5200 5100 5200 4950
-Wire Wire Line
-	5200 4950 6800 4950
-Wire Wire Line
-	7800 5000 8250 5000
-Wire Wire Line
-	8250 5000 8250 5250
-Wire Wire Line
-	7800 5250 8100 5250
-Wire Wire Line
-	8100 5250 8100 4450
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:full_sub-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+LIBS:full_sub-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U3
+U 1 1 5C80734A
+P 9350 4050
+F 0 "U3" H 9350 4050 60  0000 C CNN
+F 1 "d_or" H 9350 4150 60  0000 C CNN
+F 2 "" H 9350 4050 60  0000 C CNN
+F 3 "" H 9350 4050 60  0000 C CNN
+	1    9350 4050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4850 3600 5800 3600
+Wire Wire Line
+	4650 2800 8600 2800
+Wire Wire Line
+	8600 2800 8600 3950
+Wire Wire Line
+	8600 3950 8900 3950
+Wire Wire Line
+	8100 4450 8650 4450
+Wire Wire Line
+	8650 4450 8650 4050
+Wire Wire Line
+	8650 4050 8900 4050
+Wire Wire Line
+	2800 3450 2800 3250
+Wire Wire Line
+	2800 3250 3300 3250
+Wire Wire Line
+	1450 3550 3300 3550
+Wire Wire Line
+	4050 5100 5200 5100
+Wire Wire Line
+	5800 3600 5800 5250
+Wire Wire Line
+	8250 5250 9350 5250
+Wire Wire Line
+	9350 5250 9350 4900
+Wire Wire Line
+	9350 4900 10750 4900
+Wire Wire Line
+	9800 4000 9800 4600
+Wire Wire Line
+	9800 4600 9550 4600
+Wire Wire Line
+	9550 4600 9550 4800
+Wire Wire Line
+	9550 4800 10750 4800
+$Comp
+L PORT U5
+U 1 1 5C80A4E8
+P 1200 3450
+F 0 "U5" H 1250 3550 30  0000 C CNN
+F 1 "PORT" H 1200 3450 30  0000 C CNN
+F 2 "" H 1200 3450 60  0000 C CNN
+F 3 "" H 1200 3450 60  0000 C CNN
+	1    1200 3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 2 1 5C80A51E
+P 1200 3650
+F 0 "U5" H 1250 3750 30  0000 C CNN
+F 1 "PORT" H 1200 3650 30  0000 C CNN
+F 2 "" H 1200 3650 60  0000 C CNN
+F 3 "" H 1200 3650 60  0000 C CNN
+	2    1200 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 3 1 5C80A54E
+P 3800 5100
+F 0 "U5" H 3850 5200 30  0000 C CNN
+F 1 "PORT" H 3800 5100 30  0000 C CNN
+F 2 "" H 3800 5100 60  0000 C CNN
+F 3 "" H 3800 5100 60  0000 C CNN
+	3    3800 5100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 5 1 5C80A828
+P 11000 4800
+F 0 "U5" H 11050 4900 30  0000 C CNN
+F 1 "PORT" H 11000 4800 30  0000 C CNN
+F 2 "" H 11000 4800 60  0000 C CNN
+F 3 "" H 11000 4800 60  0000 C CNN
+	5    11000 4800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U5
+U 4 1 5C80AB2A
+P 11000 4950
+F 0 "U5" H 11050 5050 30  0000 C CNN
+F 1 "PORT" H 11000 4950 30  0000 C CNN
+F 2 "" H 11000 4950 60  0000 C CNN
+F 3 "" H 11000 4950 60  0000 C CNN
+	4    11000 4950
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	1450 3450 2800 3450
+Wire Wire Line
+	1450 3650 1450 3550
+Wire Wire Line
+	10750 4900 10750 4950
+$Comp
+L half_sub X1
+U 1 1 5C80AC4D
+P 3800 3450
+F 0 "X1" H 3800 3450 60  0000 C CNN
+F 1 "half_sub" H 3800 3450 60  0000 C CNN
+F 2 "" H 3800 3450 60  0001 C CNN
+F 3 "" H 3800 3450 60  0001 C CNN
+	1    3800 3450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4300 3550 4650 3550
+Wire Wire Line
+	4650 3550 4650 2800
+Wire Wire Line
+	4300 3300 4850 3300
+Wire Wire Line
+	4850 3300 4850 3600
+$Comp
+L half_sub X2
+U 1 1 5C80AD72
+P 7300 5150
+F 0 "X2" H 7300 5150 60  0000 C CNN
+F 1 "half_sub" H 7300 5150 60  0000 C CNN
+F 2 "" H 7300 5150 60  0001 C CNN
+F 3 "" H 7300 5150 60  0001 C CNN
+	1    7300 5150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5800 5250 6800 5250
+Wire Wire Line
+	5200 5100 5200 4950
+Wire Wire Line
+	5200 4950 6800 4950
+Wire Wire Line
+	7800 5000 8250 5000
+Wire Wire Line
+	8250 5000 8250 5250
+Wire Wire Line
+	7800 5250 8100 5250
+Wire Wire Line
+	8100 5250 8100 4450
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sub b/src/SubcircuitLibrary/full_sub/full_sub.sub
index ec5698b5..9c9dcc5a 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub.sub
+++ b/src/SubcircuitLibrary/full_sub/full_sub.sub
@@ -1,13 +1,13 @@
-* Subcircuit full_sub
-.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ 
-* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
-.include half_sub.sub
-* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
-x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
-x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
-a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit full_sub
+.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ 
+* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
+.include half_sub.sub
+* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
+x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
+x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
+a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends full_sub
 \ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir.out b/src/SubcircuitLibrary/full_sub/half_sub.cir.out
index 95e6e2bd..91816956 100644
--- a/src/SubcircuitLibrary/full_sub/half_sub.cir.out
+++ b/src/SubcircuitLibrary/full_sub/half_sub.cir.out
@@ -1,24 +1,24 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
+
+* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sub b/src/SubcircuitLibrary/full_sub/half_sub.sub
index 1931f76e..a61a3409 100644
--- a/src/SubcircuitLibrary/full_sub/half_sub.sub
+++ b/src/SubcircuitLibrary/full_sub/half_sub.sub
@@ -1,18 +1,18 @@
-* Subcircuit half_sub
-.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit half_sub
+.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
+* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends half_sub
 \ No newline at end of file