diff options
Diffstat (limited to 'src/SubcircuitLibrary/full_sub/full_sub.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/full_sub/full_sub.cir.out | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir.out b/src/SubcircuitLibrary/full_sub/full_sub.cir.out deleted file mode 100644 index 5e58cc0a..00000000 --- a/src/SubcircuitLibrary/full_sub/full_sub.cir.out +++ /dev/null @@ -1,19 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir - -.include half_sub.sub -* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or -* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port -x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub -x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub -a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 -* Schematic Name: d_or, NgSpice Name: d_or -.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 10e-03 100e-03 0e-03 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end |