diff options
Diffstat (limited to 'src/SubcircuitLibrary/full_adder/full_adder.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/full_adder/full_adder.cir.out | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir.out b/src/SubcircuitLibrary/full_adder/full_adder.cir.out deleted file mode 100644 index b90ce70d..00000000 --- a/src/SubcircuitLibrary/full_adder/full_adder.cir.out +++ /dev/null @@ -1,19 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 - -.include half_adder.sub -x1 8 7 6 2 half_adder -x2 5 6 4 3 half_adder -* u1 8 7 5 4 1 port -* u2 3 2 1 d_or -a1 [3 2 ] 1 u2 -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.ac lin 0 0Hz 0Hz - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end |