diff options
Diffstat (limited to 'src/SubcircuitLibrary/CSLA_BEC1_logic')
22 files changed, 1825 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib new file mode 100644 index 00000000..f7d63760 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib @@ -0,0 +1,185 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Logic_adder +# +DEF Logic_adder X 0 40 Y Y 1 F N +F0 "X" 0 -250 60 H V C CNN +F1 "Logic_adder" 50 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -550 550 550 -600 0 1 0 N +X IN1 1 -750 350 200 R 50 50 1 1 I +X IN2 2 -750 -50 200 R 50 50 1 1 I +X CIN 3 -750 -450 200 R 50 50 1 1 I +X SUM 4 750 350 200 L 50 50 1 1 O +X COUT 5 750 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# MUX +# +DEF MUX X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "MUX" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 350 250 -150 0 1 0 N +X sel 1 0 550 200 D 50 50 1 1 I +X a0 2 -500 150 200 R 50 50 1 1 I +X a1 3 -500 -50 200 R 50 50 1 1 I +X y 4 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir new file mode 100644 index 00000000..fee511ed --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir @@ -0,0 +1,29 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 8 18:40:34 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U3-Pad3_ d_and +U5 Net-_U2-Pad2_ Net-_U2-Pad1_ Net-_U5-Pad3_ d_xor +U6 Net-_U2-Pad3_ Net-_U3-Pad1_ Net-_U6-Pad3_ d_xor +U7 Net-_U3-Pad3_ Net-_U7-Pad2_ Net-_U7-Pad3_ d_xor +U8 Net-_U3-Pad3_ Net-_U8-Pad2_ Net-_U8-Pad3_ d_xor +U4 Net-_U2-Pad2_ Net-_U4-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +X3 Net-_U1-Pad1_ Net-_U1-Pad5_ Net-_U9-Pad2_ Net-_U2-Pad2_ Net-_X1-Pad3_ Logic_adder +X1 Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_X1-Pad3_ Net-_U2-Pad1_ Net-_X1-Pad5_ Logic_adder +X2 Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_X1-Pad5_ Net-_U3-Pad1_ Net-_X2-Pad5_ Logic_adder +X4 Net-_U1-Pad4_ Net-_U1-Pad8_ Net-_X2-Pad5_ Net-_U7-Pad2_ Net-_U8-Pad2_ Logic_adder +X7 Net-_U1-Pad9_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad10_ MUX +X5 Net-_U1-Pad9_ Net-_U2-Pad1_ Net-_U5-Pad3_ Net-_U1-Pad11_ MUX +X8 Net-_U1-Pad9_ Net-_U3-Pad1_ Net-_U6-Pad3_ Net-_U1-Pad12_ MUX +X6 Net-_U1-Pad9_ Net-_U7-Pad2_ Net-_U7-Pad3_ Net-_U1-Pad13_ MUX +X9 Net-_U1-Pad9_ Net-_U8-Pad2_ Net-_U8-Pad3_ Net-_U1-Pad14_ MUX +v1 Net-_U9-Pad1_ GND 0 +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ adc_bridge_1 + +.end diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out new file mode 100644 index 00000000..9bfd2402 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out @@ -0,0 +1,56 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/csla_bec1_logic/csla_bec1_logic.cir + +.include LOGIC_ADDER.sub +.include MUX.sub +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_and +* u5 net-_u2-pad2_ net-_u2-pad1_ net-_u5-pad3_ d_xor +* u6 net-_u2-pad3_ net-_u3-pad1_ net-_u6-pad3_ d_xor +* u7 net-_u3-pad3_ net-_u7-pad2_ net-_u7-pad3_ d_xor +* u8 net-_u3-pad3_ net-_u8-pad2_ net-_u8-pad3_ d_xor +* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +x3 net-_u1-pad1_ net-_u1-pad5_ net-_u9-pad2_ net-_u2-pad2_ net-_x1-pad3_ LOGIC_ADDER +x1 net-_u1-pad2_ net-_u1-pad6_ net-_x1-pad3_ net-_u2-pad1_ net-_x1-pad5_ LOGIC_ADDER +x2 net-_u1-pad3_ net-_u1-pad7_ net-_x1-pad5_ net-_u3-pad1_ net-_x2-pad5_ LOGIC_ADDER +x4 net-_u1-pad4_ net-_u1-pad8_ net-_x2-pad5_ net-_u7-pad2_ net-_u8-pad2_ LOGIC_ADDER +x7 net-_u1-pad9_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad10_ MUX +x5 net-_u1-pad9_ net-_u2-pad1_ net-_u5-pad3_ net-_u1-pad11_ MUX +x8 net-_u1-pad9_ net-_u3-pad1_ net-_u6-pad3_ net-_u1-pad12_ MUX +x6 net-_u1-pad9_ net-_u7-pad2_ net-_u7-pad3_ net-_u1-pad13_ MUX +x9 net-_u1-pad9_ net-_u8-pad2_ net-_u8-pad3_ net-_u1-pad14_ MUX +v1 net-_u9-pad1_ gnd 0 +* u9 net-_u9-pad1_ net-_u9-pad2_ adc_bridge_1 +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad2_ net-_u2-pad1_ ] net-_u5-pad3_ u5 +a4 [net-_u2-pad3_ net-_u3-pad1_ ] net-_u6-pad3_ u6 +a5 [net-_u3-pad3_ net-_u7-pad2_ ] net-_u7-pad3_ u7 +a6 [net-_u3-pad3_ net-_u8-pad2_ ] net-_u8-pad3_ u8 +a7 net-_u2-pad2_ net-_u4-pad2_ u4 +a8 [net-_u9-pad1_ ] [net-_u9-pad2_ ] u9 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u8 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro new file mode 100644 index 00000000..a546f71d --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro @@ -0,0 +1,46 @@ +update=Sat Jun 8 13:24:24 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User +LibName11=eSim_Subckt +LibName12=power + diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch new file mode 100644 index 00000000..e7eac906 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch @@ -0,0 +1,654 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_PSpice +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:power +LIBS:CSLA_BEC1_logic-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5CFB5959 +P 4800 3500 +F 0 "U2" H 4800 3500 60 0000 C CNN +F 1 "d_and" H 4850 3600 60 0000 C CNN +F 2 "" H 4800 3500 60 0000 C CNN +F 3 "" H 4800 3500 60 0000 C CNN + 1 4800 3500 + 0 1 1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5CFB595A +P 4850 5350 +F 0 "U3" H 4850 5350 60 0000 C CNN +F 1 "d_and" H 4900 5450 60 0000 C CNN +F 2 "" H 4850 5350 60 0000 C CNN +F 3 "" H 4850 5350 60 0000 C CNN + 1 4850 5350 + 0 1 1 0 +$EndComp +$Comp +L d_xor U5 +U 1 1 5CFB595B +P 5750 2900 +F 0 "U5" H 5750 2900 60 0000 C CNN +F 1 "d_xor" H 5800 3000 47 0000 C CNN +F 2 "" H 5750 2900 60 0000 C CNN +F 3 "" H 5750 2900 60 0000 C CNN + 1 5750 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U6 +U 1 1 5CFB595C +P 5800 4450 +F 0 "U6" H 5800 4450 60 0000 C CNN +F 1 "d_xor" H 5850 4550 47 0000 C CNN +F 2 "" H 5800 4450 60 0000 C CNN +F 3 "" H 5800 4450 60 0000 C CNN + 1 5800 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U7 +U 1 1 5CFB595D +P 5900 5250 +F 0 "U7" H 5900 5250 60 0000 C CNN +F 1 "d_xor" H 5950 5350 47 0000 C CNN +F 2 "" H 5900 5250 60 0000 C CNN +F 3 "" H 5900 5250 60 0000 C CNN + 1 5900 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U8 +U 1 1 5CFB595E +P 5900 6700 +F 0 "U8" H 5900 6700 60 0000 C CNN +F 1 "d_xor" H 5950 6800 47 0000 C CNN +F 2 "" H 5900 6700 60 0000 C CNN +F 3 "" H 5900 6700 60 0000 C CNN + 1 5900 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CFB595F +P 5600 1300 +F 0 "U4" H 5600 1200 60 0000 C CNN +F 1 "d_inverter" H 5600 1450 60 0000 C CNN +F 2 "" H 5650 1250 60 0000 C CNN +F 3 "" H 5650 1250 60 0000 C CNN + 1 5600 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CFB6267 +P 1950 1300 +F 0 "U1" H 2000 1400 30 0000 C CNN +F 1 "PORT" H 1950 1300 30 0000 C CNN +F 2 "" H 1950 1300 60 0000 C CNN +F 3 "" H 1950 1300 60 0000 C CNN + 1 1950 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CFB62F5 +P 1950 1700 +F 0 "U1" H 2000 1800 30 0000 C CNN +F 1 "PORT" H 1950 1700 30 0000 C CNN +F 2 "" H 1950 1700 60 0000 C CNN +F 3 "" H 1950 1700 60 0000 C CNN + 5 1950 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CFB6357 +P 1950 2100 +F 0 "U1" H 2000 2200 30 0000 C CNN +F 1 "PORT" H 1950 2100 30 0000 C CNN +F 2 "" H 1950 2100 60 0000 C CNN +F 3 "" H 1950 2100 60 0000 C CNN + 9 1950 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CFB63B0 +P 2150 2900 +F 0 "U1" H 2200 3000 30 0000 C CNN +F 1 "PORT" H 2150 2900 30 0000 C CNN +F 2 "" H 2150 2900 60 0000 C CNN +F 3 "" H 2150 2900 60 0000 C CNN + 2 2150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CFB641E +P 2300 3300 +F 0 "U1" H 2350 3400 30 0000 C CNN +F 1 "PORT" H 2300 3300 30 0000 C CNN +F 2 "" H 2300 3300 60 0000 C CNN +F 3 "" H 2300 3300 60 0000 C CNN + 6 2300 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CFB647F +P 1900 4450 +F 0 "U1" H 1950 4550 30 0000 C CNN +F 1 "PORT" H 1900 4450 30 0000 C CNN +F 2 "" H 1900 4450 60 0000 C CNN +F 3 "" H 1900 4450 60 0000 C CNN + 3 1900 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CFB6565 +P 2150 4850 +F 0 "U1" H 2200 4950 30 0000 C CNN +F 1 "PORT" H 2150 4850 30 0000 C CNN +F 2 "" H 2150 4850 60 0000 C CNN +F 3 "" H 2150 4850 60 0000 C CNN + 7 2150 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CFB65D4 +P 2000 5900 +F 0 "U1" H 2050 6000 30 0000 C CNN +F 1 "PORT" H 2000 5900 30 0000 C CNN +F 2 "" H 2000 5900 60 0000 C CNN +F 3 "" H 2000 5900 60 0000 C CNN + 4 2000 5900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CFB6660 +P 2300 6300 +F 0 "U1" H 2350 6400 30 0000 C CNN +F 1 "PORT" H 2300 6300 30 0000 C CNN +F 2 "" H 2300 6300 60 0000 C CNN +F 3 "" H 2300 6300 60 0000 C CNN + 8 2300 6300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CFB66D3 +P 8700 2250 +F 0 "U1" H 8750 2350 30 0000 C CNN +F 1 "PORT" H 8700 2250 30 0000 C CNN +F 2 "" H 8700 2250 60 0000 C CNN +F 3 "" H 8700 2250 60 0000 C CNN + 10 8700 2250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CFB6922 +P 8700 2600 +F 0 "U1" H 8750 2700 30 0000 C CNN +F 1 "PORT" H 8700 2600 30 0000 C CNN +F 2 "" H 8700 2600 60 0000 C CNN +F 3 "" H 8700 2600 60 0000 C CNN + 11 8700 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CFB6A11 +P 8700 3200 +F 0 "U1" H 8750 3300 30 0000 C CNN +F 1 "PORT" H 8700 3200 30 0000 C CNN +F 2 "" H 8700 3200 60 0000 C CNN +F 3 "" H 8700 3200 60 0000 C CNN + 12 8700 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CFB6AE5 +P 8700 3500 +F 0 "U1" H 8750 3600 30 0000 C CNN +F 1 "PORT" H 8700 3500 30 0000 C CNN +F 2 "" H 8700 3500 60 0000 C CNN +F 3 "" H 8700 3500 60 0000 C CNN + 13 8700 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CFB6B58 +P 8700 3800 +F 0 "U1" H 8750 3900 30 0000 C CNN +F 1 "PORT" H 8700 3800 30 0000 C CNN +F 2 "" H 8700 3800 60 0000 C CNN +F 3 "" H 8700 3800 60 0000 C CNN + 14 8700 3800 + -1 0 0 1 +$EndComp +$Comp +L Logic_adder X3 +U 1 1 5CFB6531 +P 3850 1650 +F 0 "X3" H 3850 1400 60 0000 C CNN +F 1 "Logic_adder" H 3900 1650 60 0000 C CNN +F 2 "" H 3850 1650 60 0000 C CNN +F 3 "" H 3850 1650 60 0000 C CNN + 1 3850 1650 + 1 0 0 -1 +$EndComp +$Comp +L Logic_adder X1 +U 1 1 5CFB6824 +P 3750 3250 +F 0 "X1" H 3750 3000 60 0000 C CNN +F 1 "Logic_adder" H 3800 3250 60 0000 C CNN +F 2 "" H 3750 3250 60 0000 C CNN +F 3 "" H 3750 3250 60 0000 C CNN + 1 3750 3250 + 1 0 0 -1 +$EndComp +$Comp +L Logic_adder X2 +U 1 1 5CFB691C +P 3800 4800 +F 0 "X2" H 3800 4550 60 0000 C CNN +F 1 "Logic_adder" H 3850 4800 60 0000 C CNN +F 2 "" H 3800 4800 60 0000 C CNN +F 3 "" H 3800 4800 60 0000 C CNN + 1 3800 4800 + 1 0 0 -1 +$EndComp +$Comp +L Logic_adder X4 +U 1 1 5CFB69DF +P 3850 6250 +F 0 "X4" H 3850 6000 60 0000 C CNN +F 1 "Logic_adder" H 3900 6250 60 0000 C CNN +F 2 "" H 3850 6250 60 0000 C CNN +F 3 "" H 3850 6250 60 0000 C CNN + 1 3850 6250 + 1 0 0 -1 +$EndComp +$Comp +L MUX X7 +U 1 1 5CFB6AF5 +P 7500 1450 +F 0 "X7" H 7500 1450 60 0000 C CNN +F 1 "MUX" H 7500 1550 60 0000 C CNN +F 2 "" H 7500 1450 60 0001 C CNN +F 3 "" H 7500 1450 60 0001 C CNN + 1 7500 1450 + 1 0 0 -1 +$EndComp +$Comp +L MUX X5 +U 1 1 5CFB6BC8 +P 7450 2950 +F 0 "X5" H 7450 2950 60 0000 C CNN +F 1 "MUX" H 7450 3050 60 0000 C CNN +F 2 "" H 7450 2950 60 0001 C CNN +F 3 "" H 7450 2950 60 0001 C CNN + 1 7450 2950 + 1 0 0 -1 +$EndComp +$Comp +L MUX X8 +U 1 1 5CFB6C73 +P 7500 4100 +F 0 "X8" H 7500 4100 60 0000 C CNN +F 1 "MUX" H 7500 4200 60 0000 C CNN +F 2 "" H 7500 4100 60 0001 C CNN +F 3 "" H 7500 4100 60 0001 C CNN + 1 7500 4100 + 1 0 0 -1 +$EndComp +$Comp +L MUX X6 +U 1 1 5CFB6D3F +P 7450 5250 +F 0 "X6" H 7450 5250 60 0000 C CNN +F 1 "MUX" H 7450 5350 60 0000 C CNN +F 2 "" H 7450 5250 60 0001 C CNN +F 3 "" H 7450 5250 60 0001 C CNN + 1 7450 5250 + 1 0 0 -1 +$EndComp +$Comp +L MUX X9 +U 1 1 5CFB6E26 +P 7550 6200 +F 0 "X9" H 7550 6200 60 0000 C CNN +F 1 "MUX" H 7550 6300 60 0000 C CNN +F 2 "" H 7550 6200 60 0001 C CNN +F 3 "" H 7550 6200 60 0001 C CNN + 1 7550 6200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR01 +U 1 1 5CFBB921 +P 800 2450 +F 0 "#PWR01" H 800 2200 50 0001 C CNN +F 1 "eSim_GND" H 800 2300 50 0000 C CNN +F 2 "" H 800 2450 50 0001 C CNN +F 3 "" H 800 2450 50 0001 C CNN + 1 800 2450 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5CFBBABC +P 1300 2300 +F 0 "v1" H 1100 2400 60 0000 C CNN +F 1 "0" H 1100 2250 60 0000 C CNN +F 2 "R1" H 1000 2300 60 0000 C CNN +F 3 "" H 1300 2300 60 0000 C CNN + 1 1300 2300 + 0 1 1 0 +$EndComp +$Comp +L adc_bridge_1 U9 +U 1 1 5CFBB81E +P 2500 2350 +F 0 "U9" H 2500 2350 60 0000 C CNN +F 1 "adc_bridge_1" H 2500 2500 60 0000 C CNN +F 2 "" H 2500 2350 60 0000 C CNN +F 3 "" H 2500 2350 60 0000 C CNN + 1 2500 2350 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5CFBBCDC +P 750 2350 +F 0 "#FLG02" H 750 2425 50 0001 C CNN +F 1 "PWR_FLAG" H 750 2500 50 0000 C CNN +F 2 "" H 750 2350 50 0001 C CNN +F 3 "" H 750 2350 50 0001 C CNN + 1 750 2350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 2300 1900 2300 +Wire Wire Line + 750 2400 850 2400 +Wire Wire Line + 850 2300 850 2450 +Connection ~ 850 2400 +Wire Wire Line + 850 2450 800 2450 +Wire Wire Line + 750 2350 750 2400 +Wire Wire Line + 3050 2300 3050 2100 +Wire Wire Line + 3050 2100 3100 2100 +Connection ~ 6600 2100 +Connection ~ 6600 600 +Wire Wire Line + 6600 600 6600 5650 +Connection ~ 6600 3550 +Wire Wire Line + 6600 2100 7450 2100 +Wire Wire Line + 6600 3550 7500 3550 +Wire Wire Line + 6600 4700 7450 4700 +Wire Wire Line + 4600 3700 4550 3700 +Wire Wire Line + 4700 2100 4650 2100 +Wire Wire Line + 7050 6300 7050 6250 +Wire Wire Line + 7050 6000 7050 6050 +Wire Wire Line + 6950 5350 6950 5300 +Wire Wire Line + 6950 5050 6950 5100 +Wire Wire Line + 7000 4150 6900 4150 +Wire Wire Line + 6900 3950 6900 3900 +Wire Wire Line + 7000 3950 6900 3950 +Wire Wire Line + 8150 4000 7950 4000 +Wire Wire Line + 6950 3050 6850 3050 +Wire Wire Line + 6950 3000 6950 3050 +Wire Wire Line + 6950 2750 6950 2800 +Wire Wire Line + 6950 1550 6900 1550 +Wire Wire Line + 6950 1500 6950 1550 +Wire Wire Line + 7000 1500 6950 1500 +Wire Wire Line + 7000 1250 6900 1250 +Wire Wire Line + 7000 1300 7000 1250 +Wire Wire Line + 4500 3550 4600 3550 +Wire Wire Line + 4700 6550 4600 6550 +Wire Wire Line + 4550 5100 4650 5100 +Wire Wire Line + 4700 1950 4600 1950 +Wire Wire Line + 6600 5650 7550 5650 +Wire Wire Line + 5400 6000 7050 6000 +Wire Wire Line + 5350 5050 6950 5050 +Wire Wire Line + 5350 5900 5350 5050 +Wire Wire Line + 6400 5350 6950 5350 +Wire Wire Line + 6400 5200 6400 5350 +Wire Wire Line + 6650 6650 6650 6300 +Wire Wire Line + 5400 6700 5400 6000 +Wire Wire Line + 6900 3900 5350 3900 +Wire Wire Line + 6900 4150 6900 4400 +Wire Wire Line + 6900 4400 6250 4400 +Connection ~ 5200 2900 +Wire Wire Line + 5200 2900 5200 2600 +Wire Wire Line + 5200 2600 6350 2600 +Wire Wire Line + 6350 2600 6350 2750 +Wire Wire Line + 6350 2750 6950 2750 +Wire Wire Line + 6850 3050 6850 2850 +Wire Wire Line + 6850 2850 6200 2850 +Wire Wire Line + 4550 4450 5350 4450 +Wire Wire Line + 4600 1300 5300 1300 +Wire Wire Line + 4500 2900 5300 2900 +Wire Wire Line + 4700 1950 4700 2100 +Wire Wire Line + 4600 3550 4600 3700 +Wire Wire Line + 4650 5250 4600 5250 +Wire Wire Line + 4650 5100 4650 5250 +Wire Wire Line + 4600 5900 5450 5900 +Wire Wire Line + 4700 6700 5450 6700 +Wire Wire Line + 4700 6550 4700 6700 +Wire Wire Line + 2200 1300 3100 1300 +Wire Wire Line + 2200 1700 3100 1700 +Wire Wire Line + 2700 2100 2700 600 +Wire Wire Line + 2550 3300 3000 3300 +Wire Wire Line + 2400 2900 3000 2900 +Wire Wire Line + 2200 2100 2700 2100 +Wire Wire Line + 8000 6100 8450 6100 +Wire Wire Line + 8450 6100 8450 3800 +Wire Wire Line + 8300 3500 8450 3500 +Wire Wire Line + 8300 5150 8300 3500 +Wire Wire Line + 7900 5150 8300 5150 +Wire Wire Line + 8150 3200 8450 3200 +Wire Wire Line + 8300 2600 8450 2600 +Wire Wire Line + 8300 2850 8300 2600 +Wire Wire Line + 7900 2850 8300 2850 +Wire Wire Line + 8450 1350 8450 2250 +Wire Wire Line + 7950 1350 8450 1350 +Wire Wire Line + 8150 3200 8150 4000 +Wire Wire Line + 6650 6300 7050 6300 +Wire Wire Line + 5350 4450 5350 3900 +Wire Wire Line + 7450 2100 7450 2400 +Wire Wire Line + 6900 1550 6900 1300 +Wire Wire Line + 6900 1300 5900 1300 +Wire Wire Line + 6900 1250 6900 1050 +Wire Wire Line + 7500 600 7500 900 +Wire Wire Line + 6350 5200 6400 5200 +Wire Wire Line + 2700 600 7500 600 +Wire Wire Line + 2250 5900 3100 5900 +Wire Wire Line + 2550 6300 3100 6300 +Wire Wire Line + 2400 4850 3050 4850 +Wire Wire Line + 2150 4450 3050 4450 +Wire Wire Line + 5450 5900 5450 5250 +Wire Wire Line + 5400 5150 5450 5150 +Wire Wire Line + 5400 5800 5400 5150 +Wire Wire Line + 6350 6650 6650 6650 +Connection ~ 5350 5900 +Connection ~ 5400 6700 +Wire Wire Line + 4900 6600 5450 6600 +Wire Wire Line + 4900 5800 4900 6600 +Wire Wire Line + 4900 5800 5400 5800 +Connection ~ 4950 4450 +Wire Wire Line + 4950 4450 4950 4900 +Wire Wire Line + 4850 3950 4850 4900 +Wire Wire Line + 2800 6700 3100 6700 +Wire Wire Line + 2800 5600 2800 6700 +Wire Wire Line + 4600 5600 2800 5600 +Wire Wire Line + 4600 5250 4600 5600 +Wire Wire Line + 2750 5250 3050 5250 +Wire Wire Line + 2750 4100 2750 5250 +Wire Wire Line + 4550 4100 2750 4100 +Wire Wire Line + 4550 3700 4550 4100 +Connection ~ 4850 4350 +Wire Wire Line + 4850 4350 5350 4350 +Connection ~ 4900 2900 +Wire Wire Line + 4900 2900 4900 3050 +Connection ~ 4800 2750 +Wire Wire Line + 5300 2750 5300 2800 +Wire Wire Line + 4800 2750 5300 2750 +Connection ~ 4800 1300 +Wire Wire Line + 4800 1300 4800 3050 +Wire Wire Line + 2700 3700 3000 3700 +Wire Wire Line + 2700 2500 2700 3700 +Wire Wire Line + 4650 2500 2700 2500 +Wire Wire Line + 4650 2100 4650 2500 +Wire Wire Line + 6900 1050 5300 1050 +Wire Wire Line + 5300 1050 5300 1300 +Connection ~ 6600 4700 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub new file mode 100644 index 00000000..fd844be7 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub @@ -0,0 +1,50 @@ +* Subcircuit CSLA_BEC1_logic +.subckt CSLA_BEC1_logic net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/csla_bec1_logic/csla_bec1_logic.cir +.include LOGIC_ADDER.sub +.include MUX.sub +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_and +* u5 net-_u2-pad2_ net-_u2-pad1_ net-_u5-pad3_ d_xor +* u6 net-_u2-pad3_ net-_u3-pad1_ net-_u6-pad3_ d_xor +* u7 net-_u3-pad3_ net-_u7-pad2_ net-_u7-pad3_ d_xor +* u8 net-_u3-pad3_ net-_u8-pad2_ net-_u8-pad3_ d_xor +* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter +x3 net-_u1-pad1_ net-_u1-pad5_ net-_u9-pad2_ net-_u2-pad2_ net-_x1-pad3_ LOGIC_ADDER +x1 net-_u1-pad2_ net-_u1-pad6_ net-_x1-pad3_ net-_u2-pad1_ net-_x1-pad5_ LOGIC_ADDER +x2 net-_u1-pad3_ net-_u1-pad7_ net-_x1-pad5_ net-_u3-pad1_ net-_x2-pad5_ LOGIC_ADDER +x4 net-_u1-pad4_ net-_u1-pad8_ net-_x2-pad5_ net-_u7-pad2_ net-_u8-pad2_ LOGIC_ADDER +x7 net-_u1-pad9_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad10_ MUX +x5 net-_u1-pad9_ net-_u2-pad1_ net-_u5-pad3_ net-_u1-pad11_ MUX +x8 net-_u1-pad9_ net-_u3-pad1_ net-_u6-pad3_ net-_u1-pad12_ MUX +x6 net-_u1-pad9_ net-_u7-pad2_ net-_u7-pad3_ net-_u1-pad13_ MUX +x9 net-_u1-pad9_ net-_u8-pad2_ net-_u8-pad3_ net-_u1-pad14_ MUX +v1 net-_u9-pad1_ gnd 0 +* u9 net-_u9-pad1_ net-_u9-pad2_ adc_bridge_1 +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad2_ net-_u2-pad1_ ] net-_u5-pad3_ u5 +a4 [net-_u2-pad3_ net-_u3-pad1_ ] net-_u6-pad3_ u6 +a5 [net-_u3-pad3_ net-_u7-pad2_ ] net-_u7-pad3_ u7 +a6 [net-_u3-pad3_ net-_u8-pad2_ ] net-_u8-pad3_ u8 +a7 net-_u2-pad2_ net-_u4-pad2_ u4 +a8 [net-_u9-pad1_ ] [net-_u9-pad2_ ] u9 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u8 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Control Statements + +.ends CSLA_BEC1_logic
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml new file mode 100644 index 00000000..55dd75da --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">0</v1></source><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_xor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_xor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u4><u9 name="type">adc_bridge<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter value for in_high (default=2.0)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /><field25 name="Enter value for in_low (default=1.0)" /></u9></model><devicemodel /><subcircuit><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x9><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x3><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib new file mode 100644 index 00000000..34588988 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir new file mode 100644 index 00000000..ec177d39 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir @@ -0,0 +1,16 @@ +* C:\eSim\eSim\src\SubcircuitLibrary\LOGIC_ADDER\LOGIC_ADDER.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:23:20 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 A B Net-_U2-Pad3_ d_and
+U4 Net-_U3-Pad3_ CIN Net-_U4-Pad3_ d_and
+U3 A B Net-_U3-Pad3_ d_xor
+U5 Net-_U3-Pad3_ CIN SUM d_xor
+U6 Net-_U2-Pad3_ Net-_U4-Pad3_ CARRY d_or
+U1 A B CIN SUM CARRY PORT
+
+.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out new file mode 100644 index 00000000..df9bcde6 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out @@ -0,0 +1,32 @@ +* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
+
+* u2 a b net-_u2-pad3_ d_and
+* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and
+* u3 a b net-_u3-pad3_ d_xor
+* u5 net-_u3-pad3_ cin sum d_xor
+* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or
+* u1 a b cin sum carry port
+a1 [a b ] net-_u2-pad3_ u2
+a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
+a3 [a b ] net-_u3-pad3_ u3
+a4 [net-_u3-pad3_ cin ] sum u5
+a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 10e-03 100e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro new file mode 100644 index 00000000..a2b9fa1f --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro @@ -0,0 +1,44 @@ +update=Sat Jun 8 13:01:54 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch new file mode 100644 index 00000000..d39a1b78 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch @@ -0,0 +1,245 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:LOGIC_ADDER-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5AB647D1
+P 4100 2200
+F 0 "U2" H 4100 2200 60 0000 C CNN
+F 1 "d_and" H 4150 2300 60 0000 C CNN
+F 2 "" H 4100 2200 60 0000 C CNN
+F 3 "" H 4100 2200 60 0000 C CNN
+ 1 4100 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 5AB648AD
+P 5250 2300
+F 0 "U4" H 5250 2300 60 0000 C CNN
+F 1 "d_and" H 5300 2400 60 0000 C CNN
+F 2 "" H 5250 2300 60 0000 C CNN
+F 3 "" H 5250 2300 60 0000 C CNN
+ 1 5250 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U3
+U 1 1 5AB648E7
+P 4100 2750
+F 0 "U3" H 4100 2750 60 0000 C CNN
+F 1 "d_xor" H 4150 2850 47 0000 C CNN
+F 2 "" H 4100 2750 60 0000 C CNN
+F 3 "" H 4100 2750 60 0000 C CNN
+ 1 4100 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U5
+U 1 1 5AB6498F
+P 5250 2600
+F 0 "U5" H 5250 2600 60 0000 C CNN
+F 1 "d_xor" H 5300 2700 47 0000 C CNN
+F 2 "" H 5250 2600 60 0000 C CNN
+F 3 "" H 5250 2600 60 0000 C CNN
+ 1 5250 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U6
+U 1 1 5AB64A11
+P 6250 2250
+F 0 "U6" H 6250 2250 60 0000 C CNN
+F 1 "d_or" H 6250 2350 60 0000 C CNN
+F 2 "" H 6250 2250 60 0000 C CNN
+F 3 "" H 6250 2250 60 0000 C CNN
+ 1 6250 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5AB64A78
+P 2650 2100
+F 0 "U1" H 2700 2200 30 0000 C CNN
+F 1 "PORT" H 2650 2100 30 0000 C CNN
+F 2 "" H 2650 2100 60 0000 C CNN
+F 3 "" H 2650 2100 60 0000 C CNN
+ 1 2650 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5AB64BE9
+P 2650 2300
+F 0 "U1" H 2700 2400 30 0000 C CNN
+F 1 "PORT" H 2650 2300 30 0000 C CNN
+F 2 "" H 2650 2300 60 0000 C CNN
+F 3 "" H 2650 2300 60 0000 C CNN
+ 2 2650 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5AB64C18
+P 6300 2550
+F 0 "U1" H 6350 2650 30 0000 C CNN
+F 1 "PORT" H 6300 2550 30 0000 C CNN
+F 2 "" H 6300 2550 60 0000 C CNN
+F 3 "" H 6300 2550 60 0000 C CNN
+ 4 6300 2550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5AB64C59
+P 2650 2900
+F 0 "U1" H 2700 3000 30 0000 C CNN
+F 1 "PORT" H 2650 2900 30 0000 C CNN
+F 2 "" H 2650 2900 60 0000 C CNN
+F 3 "" H 2650 2900 60 0000 C CNN
+ 3 2650 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5AB64C94
+P 7150 2200
+F 0 "U1" H 7200 2300 30 0000 C CNN
+F 1 "PORT" H 7150 2200 30 0000 C CNN
+F 2 "" H 7150 2200 60 0000 C CNN
+F 3 "" H 7150 2200 60 0000 C CNN
+ 5 7150 2200
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 2900 2100 3650 2100
+Wire Wire Line
+ 2900 2250 3650 2250
+Wire Wire Line
+ 3650 2250 3650 2200
+Wire Wire Line
+ 3400 2100 3400 2650
+Wire Wire Line
+ 3400 2650 3650 2650
+Connection ~ 3400 2100
+Wire Wire Line
+ 3150 2250 3150 2750
+Wire Wire Line
+ 3150 2750 3650 2750
+Connection ~ 3150 2250
+Wire Wire Line
+ 4550 2700 4550 2500
+Wire Wire Line
+ 4550 2500 4800 2500
+Wire Wire Line
+ 2900 2900 4800 2900
+Wire Wire Line
+ 4800 2900 4800 2600
+Wire Wire Line
+ 4700 2500 4700 2200
+Wire Wire Line
+ 4700 2200 4800 2200
+Connection ~ 4700 2500
+Wire Wire Line
+ 4800 2300 4600 2300
+Wire Wire Line
+ 4600 2300 4600 2900
+Connection ~ 4600 2900
+Wire Wire Line
+ 5700 2250 5800 2250
+Wire Wire Line
+ 4550 2150 4550 2000
+Wire Wire Line
+ 4550 2000 5800 2000
+Wire Wire Line
+ 5800 2000 5800 2150
+Wire Wire Line
+ 5700 2550 6050 2550
+Wire Wire Line
+ 6700 2200 6900 2200
+Wire Wire Line
+ 2900 2250 2900 2300
+Text GLabel 3000 1850 0 60 Input ~ 0
+A
+Text GLabel 3000 2500 0 60 Input ~ 0
+B
+Text GLabel 3000 3250 0 60 Input ~ 0
+CIN
+Wire Wire Line
+ 3000 3250 3050 3250
+Wire Wire Line
+ 3050 3250 3050 2900
+Connection ~ 3050 2900
+Wire Wire Line
+ 3000 1850 3100 1850
+Wire Wire Line
+ 3100 1850 3100 2100
+Connection ~ 3100 2100
+Wire Wire Line
+ 3000 2500 3000 2250
+Connection ~ 3000 2250
+Text GLabel 6750 1700 0 60 Output ~ 0
+CARRY
+Text GLabel 5950 2800 0 60 Output ~ 0
+SUM
+Wire Wire Line
+ 6750 1700 6800 1700
+Wire Wire Line
+ 6800 1700 6800 2200
+Connection ~ 6800 2200
+Wire Wire Line
+ 5950 2550 5950 2800
+Connection ~ 5950 2550
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub new file mode 100644 index 00000000..a1e1cfac --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub @@ -0,0 +1,26 @@ +* Subcircuit LOGIC_ADDER
+.subckt LOGIC_ADDER a b cin sum carry
+* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
+* u2 a b net-_u2-pad3_ d_and
+* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and
+* u3 a b net-_u3-pad3_ d_xor
+* u5 net-_u3-pad3_ cin sum d_xor
+* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or
+a1 [a b ] net-_u2-pad3_ u2
+a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
+a3 [a b ] net-_u3-pad3_ u3
+a4 [net-_u3-pad3_ cin ] sum u5
+a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends LOGIC_ADDER
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml new file mode 100644 index 00000000..ab59f216 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib new file mode 100644 index 00000000..9fa4b3f9 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir new file mode 100644 index 00000000..8d97f9a1 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir @@ -0,0 +1,15 @@ +* C:\eSim\eSim\src\SubcircuitLibrary\MUX\MUX.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:29:10 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_and
+U4 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and
+U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad4_ d_or
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out new file mode 100644 index 00000000..342293e7 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out @@ -0,0 +1,28 @@ +* c:\esim\esim\src\subcircuitlibrary\mux\mux.cir
+
+* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad1_ net-_u1-pad3_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
+a4 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 10e-03 100e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro new file mode 100644 index 00000000..07f53b67 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro @@ -0,0 +1,43 @@ +update=Sat Jun 8 12:53:13 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch new file mode 100644 index 00000000..eb095e0e --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch @@ -0,0 +1,172 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
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+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
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+$Comp
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+F 2 "" H 5050 2550 60 0000 C CNN
+F 3 "" H 5050 2550 60 0000 C CNN
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+ 1 0 0 -1
+$EndComp
+$Comp
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+U 1 1 5AB62D59
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+F 2 "" H 5050 3400 60 0000 C CNN
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+ 1 0 0 -1
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+$Comp
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+U 1 1 5AB62DBD
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+F 2 "" H 6300 2950 60 0000 C CNN
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+$Comp
+L d_inverter U2
+U 1 1 5AB62FFA
+P 4200 2550
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+F 2 "" H 4250 2500 60 0000 C CNN
+F 3 "" H 4250 2500 60 0000 C CNN
+ 1 4200 2550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
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+$Comp
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+ 1 0 0 -1
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+Wire Wire Line
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+Connection ~ 3900 3300
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+F 3 "" H 4100 2050 60 0000 C CNN
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+ 3 4200 3850
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diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub new file mode 100644 index 00000000..473dc907 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub @@ -0,0 +1,22 @@ +* Subcircuit MUX
+.subckt MUX net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\esim\esim\src\subcircuitlibrary\mux\mux.cir
+* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad1_ net-_u1-pad3_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
+a4 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends MUX
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml new file mode 100644 index 00000000..6f43d20b --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u2 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis b/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |