1 files changed, 0 insertions, 28 deletions
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out
deleted file mode 100644
index 342293e7..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out
+++ /dev/null
@@ -1,28 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\mux\mux.cir
-
-* u3  net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
-* u4  net-_u1-pad1_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u5  net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
-a2 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
-a4 net-_u1-pad1_ net-_u2-pad2_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end