diff options
Diffstat (limited to 'src/SubcircuitLibrary/AD620')
19 files changed, 1685 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/AD620/AD620-cache.lib b/src/SubcircuitLibrary/AD620/AD620-cache.lib new file mode 100644 index 00000000..b2ef0045 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -350 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X in- 2 -550 150 200 R 50 38 1 1 I +X in+ 3 -550 -100 200 R 50 38 1 1 I +X V- 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X V+ 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/AD620/AD620.cir b/src/SubcircuitLibrary/AD620/AD620.cir new file mode 100644 index 00000000..c82fdfd6 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620.cir @@ -0,0 +1,26 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\AD620\AD620.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/19 16:16:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X2 Net-_R8-Pad1_ Net-_R1-Pad2_ Net-_U1-Pad2_ Net-_R10-Pad2_ Net-_R10-Pad1_ Net-_R1-Pad1_ Net-_U1-Pad7_ ? lm_741
+X1 Net-_R7-Pad2_ Net-_R2-Pad1_ Net-_U1-Pad3_ Net-_R10-Pad2_ Net-_R9-Pad2_ Net-_R2-Pad2_ Net-_U1-Pad7_ ? lm_741
+X3 Net-_R11-Pad2_ Net-_R4-Pad1_ Net-_R3-Pad1_ Net-_R10-Pad2_ Net-_R12-Pad2_ Net-_R6-Pad1_ Net-_U1-Pad7_ ? lm_741
+R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 24.7k
+R2 Net-_R2-Pad1_ Net-_R2-Pad2_ 24.7k
+R4 Net-_R4-Pad1_ Net-_R1-Pad1_ 10k
+R3 Net-_R3-Pad1_ Net-_R2-Pad2_ 10k
+R6 Net-_R6-Pad1_ Net-_R4-Pad1_ 10k
+R5 Net-_R5-Pad1_ Net-_R3-Pad1_ 10k
+U1 Net-_R1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_R10-Pad2_ Net-_R5-Pad1_ Net-_R6-Pad1_ Net-_U1-Pad7_ Net-_R2-Pad1_ PORT
+R8 Net-_R8-Pad1_ Net-_R10-Pad2_ 0.297k
+R10 Net-_R10-Pad1_ Net-_R10-Pad2_ 1k
+R7 Net-_R10-Pad2_ Net-_R7-Pad2_ 0.297k
+R9 Net-_R10-Pad2_ Net-_R9-Pad2_ 1k
+R12 Net-_R10-Pad2_ Net-_R12-Pad2_ 1k
+R11 Net-_R10-Pad2_ Net-_R11-Pad2_ 0.75732k
+
+.end
diff --git a/src/SubcircuitLibrary/AD620/AD620.cir.out b/src/SubcircuitLibrary/AD620/AD620.cir.out new file mode 100644 index 00000000..082780e2 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620.cir.out @@ -0,0 +1,28 @@ +* c:\users\malli\esim\src\subcircuitlibrary\ad620\ad620.cir
+
+.include lm_741.sub
+x2 net-_r8-pad1_ net-_r1-pad2_ net-_u1-pad2_ net-_r10-pad2_ net-_r10-pad1_ net-_r1-pad1_ net-_u1-pad7_ ? lm_741
+x1 net-_r7-pad2_ net-_r2-pad1_ net-_u1-pad3_ net-_r10-pad2_ net-_r9-pad2_ net-_r2-pad2_ net-_u1-pad7_ ? lm_741
+x3 net-_r11-pad2_ net-_r4-pad1_ net-_r3-pad1_ net-_r10-pad2_ net-_r12-pad2_ net-_r6-pad1_ net-_u1-pad7_ ? lm_741
+r1 net-_r1-pad1_ net-_r1-pad2_ 24.7k
+r2 net-_r2-pad1_ net-_r2-pad2_ 24.7k
+r4 net-_r4-pad1_ net-_r1-pad1_ 10k
+r3 net-_r3-pad1_ net-_r2-pad2_ 10k
+r6 net-_r6-pad1_ net-_r4-pad1_ 10k
+r5 net-_r5-pad1_ net-_r3-pad1_ 10k
+* u1 net-_r1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r10-pad2_ net-_r5-pad1_ net-_r6-pad1_ net-_u1-pad7_ net-_r2-pad1_ port
+r8 net-_r8-pad1_ net-_r10-pad2_ 0.297k
+r10 net-_r10-pad1_ net-_r10-pad2_ 1k
+r7 net-_r10-pad2_ net-_r7-pad2_ 0.297k
+r9 net-_r10-pad2_ net-_r9-pad2_ 1k
+r12 net-_r10-pad2_ net-_r12-pad2_ 1k
+r11 net-_r10-pad2_ net-_r11-pad2_ 0.75732k
+.tran 0e-03 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/AD620/AD620.pro b/src/SubcircuitLibrary/AD620/AD620.pro new file mode 100644 index 00000000..21e55e98 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620.pro @@ -0,0 +1,44 @@ +update=Thu Jun 27 12:48:03 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_User +LibName11=eSim_Subckt diff --git a/src/SubcircuitLibrary/AD620/AD620.sch b/src/SubcircuitLibrary/AD620/AD620.sch new file mode 100644 index 00000000..8724fe19 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620.sch @@ -0,0 +1,424 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:AD620-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X2 +U 1 1 5CEE7415 +P 3800 2750 +F 0 "X2" H 3600 2750 60 0000 C CNN +F 1 "lm_741" H 3700 2500 60 0000 C CNN +F 2 "" H 3800 2750 60 0000 C CNN +F 3 "" H 3800 2750 60 0000 C CNN + 1 3800 2750 + 1 0 0 1 +$EndComp +$Comp +L lm_741 X1 +U 1 1 5CEE7416 +P 3750 5650 +F 0 "X1" H 3550 5650 60 0000 C CNN +F 1 "lm_741" H 3650 5400 60 0000 C CNN +F 2 "" H 3750 5650 60 0000 C CNN +F 3 "" H 3750 5650 60 0000 C CNN + 1 3750 5650 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X3 +U 1 1 5CEE7417 +P 6800 4050 +F 0 "X3" H 6600 4050 60 0000 C CNN +F 1 "lm_741" H 6700 3800 60 0000 C CNN +F 2 "" H 6800 4050 60 0000 C CNN +F 3 "" H 6800 4050 60 0000 C CNN + 1 6800 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 7150 1700 7150 +Wire Wire Line + 3600 6100 3600 7150 +Wire Wire Line + 6650 6700 3600 6700 +Wire Wire Line + 6650 4500 6650 6700 +Connection ~ 3600 6700 +$Comp +L eSim_R R1 +U 1 1 5CEE741A +P 4550 3350 +F 0 "R1" H 4600 3480 50 0000 C CNN +F 1 "24.7k" H 4600 3400 50 0000 C CNN +F 2 "" H 4600 3330 30 0000 C CNN +F 3 "" V 4600 3400 30 0000 C CNN + 1 4550 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CEE741C +P 4550 5000 +F 0 "R2" H 4600 5130 50 0000 C CNN +F 1 "24.7k" H 4600 5050 50 0000 C CNN +F 2 "" H 4600 4980 30 0000 C CNN +F 3 "" V 4600 5050 30 0000 C CNN + 1 4550 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 4600 5200 4600 5650 +Wire Wire Line + 4300 5650 4900 5650 +Wire Wire Line + 4600 4450 4600 4900 +Wire Wire Line + 4600 3550 4600 4150 +Wire Wire Line + 4600 3250 4600 2750 +Wire Wire Line + 4350 2750 5000 2750 +Wire Wire Line + 4600 3800 2900 3800 +Wire Wire Line + 2900 3800 2900 2900 +Wire Wire Line + 2900 2900 3250 2900 +Connection ~ 4600 3800 +Wire Wire Line + 4600 4700 2900 4700 +Wire Wire Line + 2900 4700 2900 5500 +Wire Wire Line + 2900 5500 3200 5500 +Connection ~ 4600 4700 +$Comp +L eSim_R R4 +U 1 1 5CEE741D +P 5200 2700 +F 0 "R4" H 5250 2830 50 0000 C CNN +F 1 "10k" H 5250 2750 50 0000 C CNN +F 2 "" H 5250 2680 30 0000 C CNN +F 3 "" V 5250 2750 30 0000 C CNN + 1 5200 2700 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CEE741E +P 5100 5600 +F 0 "R3" H 5150 5730 50 0000 C CNN +F 1 "10k" H 5150 5650 50 0000 C CNN +F 2 "" H 5150 5580 30 0000 C CNN +F 3 "" V 5150 5650 30 0000 C CNN + 1 5100 5600 + -1 0 0 1 +$EndComp +Connection ~ 4600 5650 +Wire Wire Line + 5200 5650 6200 5650 +Wire Wire Line + 5950 5650 5950 4150 +Wire Wire Line + 5950 4150 6250 4150 +Wire Wire Line + 6250 3900 5950 3900 +Wire Wire Line + 5950 3900 5950 2750 +Wire Wire Line + 5300 2750 6450 2750 +Connection ~ 4600 2750 +$Comp +L eSim_R R6 +U 1 1 5CEE741F +P 6650 2700 +F 0 "R6" H 6700 2830 50 0000 C CNN +F 1 "10k" H 6700 2750 50 0000 C CNN +F 2 "" H 6700 2680 30 0000 C CNN +F 3 "" V 6700 2750 30 0000 C CNN + 1 6650 2700 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CEE7420 +P 6400 5600 +F 0 "R5" H 6450 5730 50 0000 C CNN +F 1 "10k" H 6450 5650 50 0000 C CNN +F 2 "" H 6450 5580 30 0000 C CNN +F 3 "" V 6450 5650 30 0000 C CNN + 1 6400 5600 + -1 0 0 1 +$EndComp +Connection ~ 5950 5650 +Connection ~ 5950 2750 +Wire Wire Line + 6750 2750 7650 2750 +Wire Wire Line + 7350 4050 7850 4050 +Wire Wire Line + 2200 1150 6300 1150 +Wire Wire Line + 6300 1150 6300 3600 +Wire Wire Line + 6300 3600 6650 3600 +Wire Wire Line + 2700 1150 2700 3550 +Wire Wire Line + 2700 3550 3650 3550 +Wire Wire Line + 3650 3550 3650 3200 +Connection ~ 2700 1150 +Wire Wire Line + 3600 5200 3600 3550 +Connection ~ 3600 3550 +Wire Wire Line + 2000 1800 2000 7150 +Wire Wire Line + 2000 1800 3650 1800 +Wire Wire Line + 3650 1800 3650 2300 +Connection ~ 2000 7150 +Connection ~ 7650 4050 +Wire Wire Line + 6500 5650 7200 5650 +Wire Wire Line + 1850 2650 3250 2650 +$Comp +L PORT U1 +U 2 1 5CEE7CF8 +P 1600 2650 +F 0 "U1" H 1650 2750 30 0000 C CNN +F 1 "PORT" H 1600 2650 30 0000 C CNN +F 2 "" H 1600 2650 60 0000 C CNN +F 3 "" H 1600 2650 60 0000 C CNN + 2 1600 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE7E32 +P 1500 5800 +F 0 "U1" H 1550 5900 30 0000 C CNN +F 1 "PORT" H 1500 5800 30 0000 C CNN +F 2 "" H 1500 5800 60 0000 C CNN +F 3 "" H 1500 5800 60 0000 C CNN + 3 1500 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE7FF8 +P 1450 7150 +F 0 "U1" H 1500 7250 30 0000 C CNN +F 1 "PORT" H 1450 7150 30 0000 C CNN +F 2 "" H 1450 7150 60 0000 C CNN +F 3 "" H 1450 7150 60 0000 C CNN + 4 1450 7150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE80BC +P 1950 1150 +F 0 "U1" H 2000 1250 30 0000 C CNN +F 1 "PORT" H 1950 1150 30 0000 C CNN +F 2 "" H 1950 1150 60 0000 C CNN +F 3 "" H 1950 1150 60 0000 C CNN + 7 1950 1150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE8180 +P 4350 4150 +F 0 "U1" H 4400 4250 30 0000 C CNN +F 1 "PORT" H 4350 4150 30 0000 C CNN +F 2 "" H 4350 4150 60 0000 C CNN +F 3 "" H 4350 4150 60 0000 C CNN + 1 4350 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE8456 +P 4350 4450 +F 0 "U1" H 4400 4550 30 0000 C CNN +F 1 "PORT" H 4350 4450 30 0000 C CNN +F 2 "" H 4350 4450 60 0000 C CNN +F 3 "" H 4350 4450 60 0000 C CNN + 8 4350 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE84A1 +P 7450 5650 +F 0 "U1" H 7500 5750 30 0000 C CNN +F 1 "PORT" H 7450 5650 30 0000 C CNN +F 2 "" H 7450 5650 60 0000 C CNN +F 3 "" H 7450 5650 60 0000 C CNN + 5 7450 5650 + -1 0 0 1 +$EndComp +Wire Wire Line + 7650 2750 7650 4050 +$Comp +L PORT U1 +U 6 1 5CEE8938 +P 8100 4050 +F 0 "U1" H 8150 4150 30 0000 C CNN +F 1 "PORT" H 8100 4050 30 0000 C CNN +F 2 "" H 8100 4050 60 0000 C CNN +F 3 "" H 8100 4050 60 0000 C CNN + 6 8100 4050 + -1 0 0 1 +$EndComp +Wire Wire Line + 1750 5800 3200 5800 +Wire Wire Line + 3200 5800 3200 5750 +$Comp +L eSim_R R8 +U 1 1 5CEFB54F +P 3700 3350 +F 0 "R8" H 3750 3480 50 0000 C CNN +F 1 "0.297k" H 3750 3400 50 0000 C CNN +F 2 "" H 3750 3330 30 0000 C CNN +F 3 "" V 3750 3400 30 0000 C CNN + 1 3700 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CEFB5A3 +P 4000 3350 +F 0 "R10" H 4050 3480 50 0000 C CNN +F 1 "1k" H 4050 3400 50 0000 C CNN +F 2 "" H 4050 3330 30 0000 C CNN +F 3 "" V 4050 3400 30 0000 C CNN + 1 4000 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 4050 3250 4050 3100 +Wire Wire Line + 4050 3100 3850 3100 +Wire Wire Line + 3750 3150 3750 3250 +Wire Wire Line + 3750 3550 3750 3650 +Wire Wire Line + 3750 3650 4050 3650 +Wire Wire Line + 4050 3650 4050 3550 +Wire Wire Line + 3900 3650 3900 3950 +Wire Wire Line + 3900 3950 2000 3950 +Connection ~ 2000 3950 +Connection ~ 3900 3650 +$Comp +L eSim_R R7 +U 1 1 5CEFB900 +P 3650 4950 +F 0 "R7" H 3700 5080 50 0000 C CNN +F 1 "0.297k" H 3700 5000 50 0000 C CNN +F 2 "" H 3700 4930 30 0000 C CNN +F 3 "" V 3700 5000 30 0000 C CNN + 1 3650 4950 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CEFB962 +P 3950 4950 +F 0 "R9" H 4000 5080 50 0000 C CNN +F 1 "1k" H 4000 5000 50 0000 C CNN +F 2 "" H 4000 4930 30 0000 C CNN +F 3 "" V 4000 5000 30 0000 C CNN + 1 3950 4950 + 0 1 1 0 +$EndComp +Wire Wire Line + 4000 4800 4000 4850 +Wire Wire Line + 3700 4800 4000 4800 +Wire Wire Line + 3700 4800 3700 4850 +Wire Wire Line + 3700 5150 3700 5250 +Wire Wire Line + 3800 5300 3800 5150 +Wire Wire Line + 3800 5150 4000 5150 +Wire Wire Line + 3900 4800 3900 4500 +Wire Wire Line + 3900 4500 2000 4500 +Connection ~ 2000 4500 +Connection ~ 3900 4800 +$Comp +L eSim_R R12 +U 1 1 5CEFB846 +P 7050 3350 +F 0 "R12" H 7100 3480 50 0000 C CNN +F 1 "1k" H 7100 3400 50 0000 C CNN +F 2 "" H 7100 3330 30 0000 C CNN +F 3 "" V 7100 3400 30 0000 C CNN + 1 7050 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CEFB8CA +P 6700 3350 +F 0 "R11" H 6750 3480 50 0000 C CNN +F 1 "0.75732k" H 6750 3400 50 0000 C CNN +F 2 "" H 6750 3330 30 0000 C CNN +F 3 "" V 6750 3400 30 0000 C CNN + 1 6700 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 6750 3550 6750 3650 +Wire Wire Line + 6750 3250 6750 3100 +Wire Wire Line + 6750 3100 7500 3100 +Wire Wire Line + 7100 3100 7100 3250 +Wire Wire Line + 7100 3550 7100 3700 +Wire Wire Line + 7100 3700 6850 3700 +Wire Wire Line + 7500 3100 7500 4650 +Wire Wire Line + 7500 4650 6650 4650 +Connection ~ 6650 4650 +Connection ~ 7100 3100 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/AD620/AD620.sub b/src/SubcircuitLibrary/AD620/AD620.sub new file mode 100644 index 00000000..1be97dbd --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620.sub @@ -0,0 +1,22 @@ +* Subcircuit AD620
+.subckt AD620 net-_r1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r10-pad2_ net-_r5-pad1_ net-_r6-pad1_ net-_u1-pad7_ net-_r2-pad1_
+* c:\users\malli\esim\src\subcircuitlibrary\ad620\ad620.cir
+.include lm_741.sub
+x2 net-_r8-pad1_ net-_r1-pad2_ net-_u1-pad2_ net-_r10-pad2_ net-_r10-pad1_ net-_r1-pad1_ net-_u1-pad7_ ? lm_741
+x1 net-_r7-pad2_ net-_r2-pad1_ net-_u1-pad3_ net-_r10-pad2_ net-_r9-pad2_ net-_r2-pad2_ net-_u1-pad7_ ? lm_741
+x3 net-_r11-pad2_ net-_r4-pad1_ net-_r3-pad1_ net-_r10-pad2_ net-_r12-pad2_ net-_r6-pad1_ net-_u1-pad7_ ? lm_741
+r1 net-_r1-pad1_ net-_r1-pad2_ 24.7k
+r2 net-_r2-pad1_ net-_r2-pad2_ 24.7k
+r4 net-_r4-pad1_ net-_r1-pad1_ 10k
+r3 net-_r3-pad1_ net-_r2-pad2_ 10k
+r6 net-_r6-pad1_ net-_r4-pad1_ 10k
+r5 net-_r5-pad1_ net-_r3-pad1_ 10k
+r8 net-_r8-pad1_ net-_r10-pad2_ 0.297k
+r10 net-_r10-pad1_ net-_r10-pad2_ 1k
+r7 net-_r10-pad2_ net-_r7-pad2_ 0.297k
+r9 net-_r10-pad2_ net-_r9-pad2_ 1k
+r12 net-_r10-pad2_ net-_r12-pad2_ 1k
+r11 net-_r10-pad2_ net-_r11-pad2_ 0.75732k
+* Control Statements
+
+.ends AD620
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml b/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml new file mode 100644 index 00000000..3a4f8217 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/NPN.lib b/src/SubcircuitLibrary/AD620/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/AD620/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/AD620/PNP.lib b/src/SubcircuitLibrary/AD620/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/AD620/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/AD620/analysis b/src/SubcircuitLibrary/AD620/analysis new file mode 100644 index 00000000..cf94dd7f --- /dev/null +++ b/src/SubcircuitLibrary/AD620/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/lm_741-cache.lib b/src/SubcircuitLibrary/AD620/lm_741-cache.lib new file mode 100644 index 00000000..6e908886 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/AD620/lm_741.cir b/src/SubcircuitLibrary/AD620/lm_741.cir new file mode 100644 index 00000000..b7989199 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
+Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN
+Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP
+Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP
+Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN
+Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP
+Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP
+Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN
+Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN
+R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k
+R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k
+R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k
+Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN
+R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k
+R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP
+Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP
+Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN
+R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k
+R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p
+Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN
+Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN
+R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k
+R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50
+Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN
+Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN
+Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN
+R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25
+R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50
+Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP
+U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT
+
+.end
diff --git a/src/SubcircuitLibrary/AD620/lm_741.cir.out b/src/SubcircuitLibrary/AD620/lm_741.cir.out new file mode 100644 index 00000000..0184209e --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
+
+.include npn_1.lib
+.include pnp_1.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
+q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
+q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
+q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
+q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
+q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
+r1 net-_q7-pad3_ net-_q12-pad3_ 1k
+r2 net-_q3-pad3_ net-_q12-pad3_ 50k
+r3 net-_q8-pad3_ net-_q12-pad3_ 1k
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
+q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
+r4 net-_q13-pad3_ net-_q12-pad3_ 5k
+r11 net-_q10-pad1_ net-_q12-pad1_ 39k
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
+r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k
+r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k
+c1 net-_c1-pad1_ net-_c1-pad2_ 30p
+q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
+q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
+r5 net-_q15-pad2_ net-_q12-pad3_ 50k
+r6 net-_q15-pad3_ net-_q12-pad3_ 50
+q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
+q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
+q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
+r9 net-_q18-pad3_ net-_q20-pad3_ 25
+r10 net-_q20-pad3_ net-_q19-pad3_ 50
+q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
+* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/AD620/lm_741.pro b/src/SubcircuitLibrary/AD620/lm_741.pro new file mode 100644 index 00000000..d7d4217f --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741.pro @@ -0,0 +1,45 @@ +update=05/25/19 14:52:30
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/AD620/lm_741.sch b/src/SubcircuitLibrary/AD620/lm_741.sch new file mode 100644 index 00000000..6a74cf22 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:lm_741-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q1
+U 1 1 5CE90A7B
+P 2650 2700
+F 0 "Q1" H 2550 2750 50 0000 R CNN
+F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN
+F 2 "" H 2850 2800 29 0000 C CNN
+F 3 "" H 2650 2700 60 0000 C CNN
+ 1 2650 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 5CE90A7C
+P 4300 2700
+F 0 "Q2" H 4200 2750 50 0000 R CNN
+F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN
+F 2 "" H 4500 2800 29 0000 C CNN
+F 3 "" H 4300 2700 60 0000 C CNN
+ 1 4300 2700
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q6
+U 1 1 5CE90A7D
+P 3000 3200
+F 0 "Q6" H 2900 3250 50 0000 R CNN
+F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN
+F 2 "" H 3200 3300 29 0000 C CNN
+F 3 "" H 3000 3200 60 0000 C CNN
+ 1 3000 3200
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q5
+U 1 1 5CE90A7E
+P 3950 3200
+F 0 "Q5" H 3850 3250 50 0000 R CNN
+F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN
+F 2 "" H 4150 3300 29 0000 C CNN
+F 3 "" H 3950 3200 60 0000 C CNN
+ 1 3950 3200
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 5CE90A7F
+P 3300 4000
+F 0 "Q3" H 3200 4050 50 0000 R CNN
+F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN
+F 2 "" H 3500 4100 29 0000 C CNN
+F 3 "" H 3300 4000 60 0000 C CNN
+ 1 3300 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q4
+U 1 1 5CE90A80
+P 3850 2000
+F 0 "Q4" H 3750 2050 50 0000 R CNN
+F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN
+F 2 "" H 4050 2100 29 0000 C CNN
+F 3 "" H 3850 2000 60 0000 C CNN
+ 1 3850 2000
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q9
+U 1 1 5CE90A81
+P 5200 2000
+F 0 "Q9" H 5100 2050 50 0000 R CNN
+F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN
+F 2 "" H 5400 2100 29 0000 C CNN
+F 3 "" H 5200 2000 60 0000 C CNN
+ 1 5200 2000
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 5CE90A82
+P 3950 4600
+F 0 "Q8" H 3850 4650 50 0000 R CNN
+F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN
+F 2 "" H 4150 4700 29 0000 C CNN
+F 3 "" H 3950 4600 60 0000 C CNN
+ 1 3950 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 5CE90A83
+P 3000 4600
+F 0 "Q7" H 2900 4650 50 0000 R CNN
+F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN
+F 2 "" H 3200 4700 29 0000 C CNN
+F 3 "" H 3000 4600 60 0000 C CNN
+ 1 3000 4600
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R1
+U 1 1 5CE90A84
+P 2850 5200
+F 0 "R1" H 2900 5330 50 0000 C CNN
+F 1 "1k" H 2900 5250 50 0000 C CNN
+F 2 "" H 2900 5180 30 0000 C CNN
+F 3 "" V 2900 5250 30 0000 C CNN
+ 1 2850 5200
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_R R2
+U 1 1 5CE90A85
+P 3550 5200
+F 0 "R2" H 3600 5330 50 0000 C CNN
+F 1 "50k" H 3600 5250 50 0000 C CNN
+F 2 "" H 3600 5180 30 0000 C CNN
+F 3 "" V 3600 5250 30 0000 C CNN
+ 1 3550 5200
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_R R3
+U 1 1 5CE90A86
+P 4000 5200
+F 0 "R3" H 4050 5330 50 0000 C CNN
+F 1 "1k" H 4050 5250 50 0000 C CNN
+F 2 "" H 4050 5180 30 0000 C CNN
+F 3 "" V 4050 5250 30 0000 C CNN
+ 1 4000 5200
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q12
+U 1 1 5CE90A87
+P 6300 4700
+F 0 "Q12" H 6200 4750 50 0000 R CNN
+F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN
+F 2 "" H 6500 4800 29 0000 C CNN
+F 3 "" H 6300 4700 60 0000 C CNN
+ 1 6300 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q13
+U 1 1 5CE90A88
+P 5400 4700
+F 0 "Q13" H 5300 4750 50 0000 R CNN
+F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN
+F 2 "" H 5600 4800 29 0000 C CNN
+F 3 "" H 5400 4700 60 0000 C CNN
+ 1 5400 4700
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R4
+U 1 1 5CE90A89
+P 5250 5200
+F 0 "R4" H 5300 5330 50 0000 C CNN
+F 1 "5k" H 5300 5250 50 0000 C CNN
+F 2 "" H 5300 5180 30 0000 C CNN
+F 3 "" V 5300 5250 30 0000 C CNN
+ 1 5250 5200
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_R R11
+U 1 1 5CE90A8A
+P 6350 2750
+F 0 "R11" H 6400 2880 50 0000 C CNN
+F 1 "39k" H 6400 2800 50 0000 C CNN
+F 2 "" H 6400 2730 30 0000 C CNN
+F 3 "" V 6400 2800 30 0000 C CNN
+ 1 6350 2750
+ 0 1 1 0
+$EndComp
+$Comp
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diff --git a/src/SubcircuitLibrary/AD620/lm_741.sub b/src/SubcircuitLibrary/AD620/lm_741.sub new file mode 100644 index 00000000..3842c902 --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741
+.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
+.include npn_1.lib
+.include pnp_1.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
+q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
+q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
+q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
+q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
+q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
+r1 net-_q7-pad3_ net-_q12-pad3_ 1k
+r2 net-_q3-pad3_ net-_q12-pad3_ 50k
+r3 net-_q8-pad3_ net-_q12-pad3_ 1k
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
+q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
+r4 net-_q13-pad3_ net-_q12-pad3_ 5k
+r11 net-_q10-pad1_ net-_q12-pad1_ 39k
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
+r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k
+r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k
+c1 net-_c1-pad1_ net-_c1-pad2_ 30p
+q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
+q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
+r5 net-_q15-pad2_ net-_q12-pad3_ 50k
+r6 net-_q15-pad3_ net-_q12-pad3_ 50
+q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
+q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
+q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
+r9 net-_q18-pad3_ net-_q20-pad3_ 25
+r10 net-_q20-pad3_ net-_q19-pad3_ 50
+q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
+* Control Statements
+
+.ends lm_741
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml b/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/npn_1.lib b/src/SubcircuitLibrary/AD620/npn_1.lib new file mode 100644 index 00000000..4a863e3e --- /dev/null +++ b/src/SubcircuitLibrary/AD620/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN(
++ Vtf=1.7
++ Cjc=0.5p
++ Nc=2
++ Tr=46.91n
++ Ne=1.307
++ Cje=0.5p
++ Isc=0
++ Xtb=1.5
++ Rb=500
++ Rc=1
++ Tf=411.1p
++ Xti=3
++ Ikr=0
++ Bf=125
++ Fc=.5
++ Ise=14.34f
++ Br=6.092
++ Ikf=.2847
++ Mje=.377
++ Mjc=.3416
++ Vaf=74.03
++ Vjc=.75
++ Vje=.75
++ Xtf=3
++ Itf=.6
++ Is=14.34f
++ Eg=1.11
+)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/pnp_1.lib b/src/SubcircuitLibrary/AD620/pnp_1.lib new file mode 100644 index 00000000..c486429f --- /dev/null +++ b/src/SubcircuitLibrary/AD620/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP(
++ Vtf=1.7
++ Cjc=1.5p
++ Nc=2
++ Tr=46.91n
++ Ne=1.307
++ Cje=0.3p
++ Isc=0
++ Xtb=1.5
++ Rb=250
++ Rc=1
++ Tf=411.1p
++ Xti=3
++ Ikr=0
++ Bf=25
++ Fc=.5
++ Ise=14.34f
++ Br=6.092
++ Ikf=.2847
++ Mje=.377
++ Mjc=.3416
++ Vaf=74.03
++ Vjc=.75
++ Vje=.75
++ Xtf=3
++ Itf=.6
++ Is=14.34f
++ Eg=1.11
+)
\ No newline at end of file |