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-rw-r--r--src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib112
-rw-r--r--src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir56
-rw-r--r--src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out192
-rw-r--r--src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro85
-rw-r--r--src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sch1495
-rw-r--r--src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub186
-rw-r--r--src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml1
-rw-r--r--src/SubcircuitLibrary/9bit-Right_shift_register/analysis1
8 files changed, 0 insertions, 2128 deletions
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib
deleted file mode 100644
index f5944a63..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib
+++ /dev/null
@@ -1,112 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_dff
-#
-DEF d_dff U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_dff" 0 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 350 450 -350 -400 0 1 0 N
-X Din 1 -550 350 200 R 50 50 1 1 I
-X Clk 2 -550 -300 200 R 50 50 1 1 I C
-X Set 3 0 650 200 D 50 50 1 1 I
-X Reset 4 0 -600 200 U 50 50 1 1 I
-X Dout 5 550 350 200 L 50 50 1 1 O
-X Ndout 6 550 -300 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir
deleted file mode 100644
index 52ab8ff8..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir
+++ /dev/null
@@ -1,56 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\9bit-Right_shift_register\9bit-Right_shift_register.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/24/19 01:43:15
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3 Net-_U20-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U26-Pad2_ ? d_dff
-U4 Net-_U25-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U30-Pad2_ ? d_dff
-U6 Net-_U29-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U34-Pad2_ ? d_dff
-U15 Net-_U15-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U15-Pad5_ ? d_dff
-U2 Net-_U14-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U2-Pad5_ ? d_dff
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad5_ ? d_dff
-U18 Net-_U18-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U18-Pad5_ ? d_dff
-U11 Net-_U11-Pad1_ Net-_U10-Pad3_ Net-_U1-Pad1_ d_or
-U14 Net-_U14-Pad1_ Net-_U13-Pad3_ Net-_U14-Pad3_ d_or
-U20 Net-_U20-Pad1_ Net-_U19-Pad3_ Net-_U20-Pad3_ d_or
-U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and
-U8 Net-_U7-Pad2_ Net-_U5-Pad1_ Net-_U11-Pad1_ d_and
-U7 Net-_U10-Pad1_ Net-_U7-Pad2_ d_inverter
-U13 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and
-U16 Net-_U10-Pad1_ Net-_U1-Pad5_ Net-_U14-Pad1_ d_and
-U12 Net-_U10-Pad1_ Net-_U12-Pad2_ d_inverter
-U19 Net-_U17-Pad2_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_and
-U21 Net-_U10-Pad1_ Net-_U2-Pad5_ Net-_U20-Pad1_ d_and
-U17 Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter
-U25 Net-_U23-Pad3_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_or
-U23 Net-_U22-Pad2_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_and
-U26 Net-_U10-Pad1_ Net-_U26-Pad2_ Net-_U25-Pad2_ d_and
-U22 Net-_U10-Pad1_ Net-_U22-Pad2_ d_inverter
-U29 Net-_U28-Pad3_ Net-_U29-Pad2_ Net-_U29-Pad3_ d_or
-U28 Net-_U27-Pad2_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_and
-U30 Net-_U10-Pad1_ Net-_U30-Pad2_ Net-_U29-Pad2_ d_and
-U27 Net-_U10-Pad1_ Net-_U27-Pad2_ d_inverter
-U33 Net-_U32-Pad3_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_or
-U40 Net-_U38-Pad3_ Net-_U40-Pad2_ Net-_U15-Pad1_ d_or
-U32 Net-_U31-Pad2_ Net-_U32-Pad2_ Net-_U32-Pad3_ d_and
-U34 Net-_U10-Pad1_ Net-_U34-Pad2_ Net-_U33-Pad2_ d_and
-U38 Net-_U37-Pad2_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_and
-U42 Net-_U10-Pad1_ Net-_U42-Pad2_ Net-_U40-Pad2_ d_and
-U31 Net-_U10-Pad1_ Net-_U31-Pad2_ d_inverter
-U37 Net-_U10-Pad1_ Net-_U37-Pad2_ d_inverter
-U39 Net-_U36-Pad3_ Net-_U39-Pad2_ Net-_U18-Pad1_ d_or
-U36 Net-_U36-Pad1_ Net-_U35-Pad2_ Net-_U36-Pad3_ d_and
-U41 Net-_U15-Pad5_ Net-_U10-Pad1_ Net-_U39-Pad2_ d_and
-U9 Net-_U33-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U42-Pad2_ ? d_dff
-U35 Net-_U10-Pad1_ Net-_U35-Pad2_ d_inverter
-U24 Net-_U24-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U10-Pad2_ ? d_dff
-U45 Net-_U45-Pad1_ Net-_U44-Pad3_ Net-_U24-Pad1_ d_or
-U46 Net-_U18-Pad5_ Net-_U10-Pad1_ Net-_U45-Pad1_ d_and
-U44 Net-_U44-Pad1_ Net-_U43-Pad2_ Net-_U44-Pad3_ d_and
-U43 Net-_U10-Pad1_ Net-_U43-Pad2_ d_inverter
-U5 Net-_U5-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U13-Pad2_ Net-_U44-Pad1_ Net-_U19-Pad2_ Net-_U23-Pad2_ Net-_U10-Pad2_ Net-_U2-Pad5_ Net-_U30-Pad2_ Net-_U42-Pad2_ Net-_U18-Pad5_ Net-_U28-Pad2_ Net-_U1-Pad5_ Net-_U26-Pad2_ Net-_U34-Pad2_ Net-_U15-Pad5_ Net-_U36-Pad1_ Net-_U32-Pad2_ Net-_U38-Pad2_ Net-_U10-Pad1_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out
deleted file mode 100644
index cff41387..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out
+++ /dev/null
@@ -1,192 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\9bit-right_shift_register\9bit-right_shift_register.cir
-
-* u3 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? d_dff
-* u4 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? d_dff
-* u6 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? d_dff
-* u15 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? d_dff
-* u2 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? d_dff
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? d_dff
-* u18 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? d_dff
-* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u1-pad1_ d_or
-* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or
-* u20 net-_u20-pad1_ net-_u19-pad3_ net-_u20-pad3_ d_or
-* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u8 net-_u7-pad2_ net-_u5-pad1_ net-_u11-pad1_ d_and
-* u7 net-_u10-pad1_ net-_u7-pad2_ d_inverter
-* u13 net-_u12-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_and
-* u16 net-_u10-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and
-* u12 net-_u10-pad1_ net-_u12-pad2_ d_inverter
-* u19 net-_u17-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_and
-* u21 net-_u10-pad1_ net-_u2-pad5_ net-_u20-pad1_ d_and
-* u17 net-_u10-pad1_ net-_u17-pad2_ d_inverter
-* u25 net-_u23-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_or
-* u23 net-_u22-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and
-* u26 net-_u10-pad1_ net-_u26-pad2_ net-_u25-pad2_ d_and
-* u22 net-_u10-pad1_ net-_u22-pad2_ d_inverter
-* u29 net-_u28-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_or
-* u28 net-_u27-pad2_ net-_u28-pad2_ net-_u28-pad3_ d_and
-* u30 net-_u10-pad1_ net-_u30-pad2_ net-_u29-pad2_ d_and
-* u27 net-_u10-pad1_ net-_u27-pad2_ d_inverter
-* u33 net-_u32-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
-* u40 net-_u38-pad3_ net-_u40-pad2_ net-_u15-pad1_ d_or
-* u32 net-_u31-pad2_ net-_u32-pad2_ net-_u32-pad3_ d_and
-* u34 net-_u10-pad1_ net-_u34-pad2_ net-_u33-pad2_ d_and
-* u38 net-_u37-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_and
-* u42 net-_u10-pad1_ net-_u42-pad2_ net-_u40-pad2_ d_and
-* u31 net-_u10-pad1_ net-_u31-pad2_ d_inverter
-* u37 net-_u10-pad1_ net-_u37-pad2_ d_inverter
-* u39 net-_u36-pad3_ net-_u39-pad2_ net-_u18-pad1_ d_or
-* u36 net-_u36-pad1_ net-_u35-pad2_ net-_u36-pad3_ d_and
-* u41 net-_u15-pad5_ net-_u10-pad1_ net-_u39-pad2_ d_and
-* u9 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? d_dff
-* u35 net-_u10-pad1_ net-_u35-pad2_ d_inverter
-* u24 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? d_dff
-* u45 net-_u45-pad1_ net-_u44-pad3_ net-_u24-pad1_ d_or
-* u46 net-_u18-pad5_ net-_u10-pad1_ net-_u45-pad1_ d_and
-* u44 net-_u44-pad1_ net-_u43-pad2_ net-_u44-pad3_ d_and
-* u43 net-_u10-pad1_ net-_u43-pad2_ d_inverter
-* u5 net-_u5-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u13-pad2_ net-_u44-pad1_ net-_u19-pad2_ net-_u23-pad2_ net-_u10-pad2_ net-_u2-pad5_ net-_u30-pad2_ net-_u42-pad2_ net-_u18-pad5_ net-_u28-pad2_ net-_u1-pad5_ net-_u26-pad2_ net-_u34-pad2_ net-_u15-pad5_ net-_u36-pad1_ net-_u32-pad2_ net-_u38-pad2_ net-_u10-pad1_ port
-a1 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? u3
-a2 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? u4
-a3 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? u6
-a4 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? u15
-a5 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? u2
-a6 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? u1
-a7 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? u18
-a8 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u1-pad1_ u11
-a9 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14
-a10 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u20-pad3_ u20
-a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a12 [net-_u7-pad2_ net-_u5-pad1_ ] net-_u11-pad1_ u8
-a13 net-_u10-pad1_ net-_u7-pad2_ u7
-a14 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13
-a15 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u16
-a16 net-_u10-pad1_ net-_u12-pad2_ u12
-a17 [net-_u17-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19
-a18 [net-_u10-pad1_ net-_u2-pad5_ ] net-_u20-pad1_ u21
-a19 net-_u10-pad1_ net-_u17-pad2_ u17
-a20 [net-_u23-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25
-a21 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23
-a22 [net-_u10-pad1_ net-_u26-pad2_ ] net-_u25-pad2_ u26
-a23 net-_u10-pad1_ net-_u22-pad2_ u22
-a24 [net-_u28-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29
-a25 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u28-pad3_ u28
-a26 [net-_u10-pad1_ net-_u30-pad2_ ] net-_u29-pad2_ u30
-a27 net-_u10-pad1_ net-_u27-pad2_ u27
-a28 [net-_u32-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
-a29 [net-_u38-pad3_ net-_u40-pad2_ ] net-_u15-pad1_ u40
-a30 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u32-pad3_ u32
-a31 [net-_u10-pad1_ net-_u34-pad2_ ] net-_u33-pad2_ u34
-a32 [net-_u37-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38
-a33 [net-_u10-pad1_ net-_u42-pad2_ ] net-_u40-pad2_ u42
-a34 net-_u10-pad1_ net-_u31-pad2_ u31
-a35 net-_u10-pad1_ net-_u37-pad2_ u37
-a36 [net-_u36-pad3_ net-_u39-pad2_ ] net-_u18-pad1_ u39
-a37 [net-_u36-pad1_ net-_u35-pad2_ ] net-_u36-pad3_ u36
-a38 [net-_u15-pad5_ net-_u10-pad1_ ] net-_u39-pad2_ u41
-a39 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? u9
-a40 net-_u10-pad1_ net-_u35-pad2_ u35
-a41 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? u24
-a42 [net-_u45-pad1_ net-_u44-pad3_ ] net-_u24-pad1_ u45
-a43 [net-_u18-pad5_ net-_u10-pad1_ ] net-_u45-pad1_ u46
-a44 [net-_u44-pad1_ net-_u43-pad2_ ] net-_u44-pad3_ u44
-a45 net-_u10-pad1_ net-_u43-pad2_ u43
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u4 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u6 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u1 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u18 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u12 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u17 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u25 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u23 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u26 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u29 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u28 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u30 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u40 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u34 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u38 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u42 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u31 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u37 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u39 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u36 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u41 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u9 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u24 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u45 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u46 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u44 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.ac lin 0 0Hz 0Hz
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro
deleted file mode 100644
index ec294cbd..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro
+++ /dev/null
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-F 0 "U33" H 11150 5850 60 0000 C CNN
-F 1 "d_or" H 11150 5950 60 0000 C CNN
-F 2 "" H 11150 5850 60 0000 C CNN
-F 3 "" H 11150 5850 60 0000 C CNN
- 1 11150 5850
- -1 0 0 1
-$EndComp
-$Comp
-L d_or U40
-U 1 1 5C94FC89
-P 12450 5850
-F 0 "U40" H 12450 5850 60 0000 C CNN
-F 1 "d_or" H 12450 5950 60 0000 C CNN
-F 2 "" H 12450 5850 60 0000 C CNN
-F 3 "" H 12450 5850 60 0000 C CNN
- 1 12450 5850
- -1 0 0 1
-$EndComp
-$Comp
-L d_and U32
-U 1 1 5C94FD1B
-P 11000 6650
-F 0 "U32" H 11000 6650 60 0000 C CNN
-F 1 "d_and" H 11050 6750 60 0000 C CNN
-F 2 "" H 11000 6650 60 0000 C CNN
-F 3 "" H 11000 6650 60 0000 C CNN
- 1 11000 6650
- 0 -1 -1 0
-$EndComp
-$Comp
-L d_and U34
-U 1 1 5C94FDA6
-P 11350 6650
-F 0 "U34" H 11350 6650 60 0000 C CNN
-F 1 "d_and" H 11400 6750 60 0000 C CNN
-F 2 "" H 11350 6650 60 0000 C CNN
-F 3 "" H 11350 6650 60 0000 C CNN
- 1 11350 6650
- 0 -1 -1 0
-$EndComp
-$Comp
-L d_and U38
-U 1 1 5C94FE38
-P 12300 6650
-F 0 "U38" H 12300 6650 60 0000 C CNN
-F 1 "d_and" H 12350 6750 60 0000 C CNN
-F 2 "" H 12300 6650 60 0000 C CNN
-F 3 "" H 12300 6650 60 0000 C CNN
- 1 12300 6650
- 0 -1 -1 0
-$EndComp
-$Comp
-L d_and U42
-U 1 1 5C94FEC5
-P 12600 6650
-F 0 "U42" H 12600 6650 60 0000 C CNN
-F 1 "d_and" H 12650 6750 60 0000 C CNN
-F 2 "" H 12600 6650 60 0000 C CNN
-F 3 "" H 12600 6650 60 0000 C CNN
- 1 12600 6650
- 0 -1 -1 0
-$EndComp
-$Comp
-L d_inverter U31
-U 1 1 5C95027B
-P 10900 7600
-F 0 "U31" H 10900 7500 60 0000 C CNN
-F 1 "d_inverter" H 10900 7750 60 0000 C CNN
-F 2 "" H 10950 7550 60 0000 C CNN
-F 3 "" H 10950 7550 60 0000 C CNN
- 1 10900 7600
- 0 -1 -1 0
-$EndComp
-$Comp
-L d_inverter U37
-U 1 1 5C950310
-P 12200 7600
-F 0 "U37" H 12200 7500 60 0000 C CNN
-F 1 "d_inverter" H 12200 7750 60 0000 C CNN
-F 2 "" H 12250 7550 60 0000 C CNN
-F 3 "" H 12250 7550 60 0000 C CNN
- 1 12200 7600
- 0 -1 -1 0
-$EndComp
-$Comp
-L d_or U39
-U 1 1 5C956491
-P 12350 3100
-F 0 "U39" H 12350 3100 60 0000 C CNN
-F 1 "d_or" H 12350 3200 60 0000 C CNN
-F 2 "" H 12350 3100 60 0000 C CNN
-F 3 "" H 12350 3100 60 0000 C CNN
- 1 12350 3100
- -1 0 0 1
-$EndComp
-$Comp
-L d_and U36
-U 1 1 5C956C09
-P 12200 2550
-F 0 "U36" H 12200 2550 60 0000 C CNN
-F 1 "d_and" H 12250 2650 60 0000 C CNN
-F 2 "" H 12200 2550 60 0000 C CNN
-F 3 "" H 12200 2550 60 0000 C CNN
- 1 12200 2550
- 0 1 1 0
-$EndComp
-$Comp
-L d_and U41
-U 1 1 5C95766B
-P 12500 2550
-F 0 "U41" H 12500 2550 60 0000 C CNN
-F 1 "d_and" H 12550 2650 60 0000 C CNN
-F 2 "" H 12500 2550 60 0000 C CNN
-F 3 "" H 12500 2550 60 0000 C CNN
- 1 12500 2550
- 0 1 1 0
-$EndComp
-Text Notes 10300 2100 0 60 ~ 0
-IN0
-Text Notes 12050 9000 0 60 ~ 0
-IN1
-Text Notes 10700 9000 0 60 ~ 0
-IN2
-Text Notes 9500 9000 0 60 ~ 0
-IN3
-Text Notes 7500 9050 0 60 ~ 0
-IN4
-Text Notes 6150 9050 0 60 ~ 0
-IN5
-Text Notes 4050 9100 0 60 ~ 0
-IN6
-Text Notes 2750 9050 0 60 ~ 0
-IN7
-Text Notes 12850 8650 0 60 ~ 0
-CI
-Text Notes 8700 2850 0 60 ~ 0
-O0
-Text Notes 8500 2750 0 60 ~ 0
-O1
-Text Notes 8700 2650 0 60 ~ 0
-O2
-Text Notes 8500 2550 0 60 ~ 0
-O3
-Text Notes 8700 2450 0 60 ~ 0
-O4
-Text Notes 8500 2350 0 60 ~ 0
-O5
-Text Notes 8700 2250 0 60 ~ 0
-O6
-Text Notes 8500 2150 0 60 ~ 0
-O7
-$Comp
-L d_dff U9
-U 1 1 5C92973B
-P 9850 4850
-F 0 "U9" H 9850 4850 60 0000 C CNN
-F 1 "d_dff" H 9850 5000 60 0000 C CNN
-F 2 "" H 9850 4850 60 0000 C CNN
-F 3 "" H 9850 4850 60 0000 C CNN
- 1 9850 4850
- 1 0 0 -1
-$EndComp
-$Comp
-L d_inverter U35
-U 1 1 5C9582C3
-P 11500 2550
-F 0 "U35" H 11500 2450 60 0000 C CNN
-F 1 "d_inverter" H 11500 2700 60 0000 C CNN
-F 2 "" H 11550 2500 60 0000 C CNN
-F 3 "" H 11550 2500 60 0000 C CNN
- 1 11500 2550
- 0 1 1 0
-$EndComp
-$Comp
-L d_dff U24
-U 1 1 5C95D8E8
-P 3350 3000
-F 0 "U24" H 3350 3000 60 0000 C CNN
-F 1 "d_dff" H 3350 3150 60 0000 C CNN
-F 2 "" H 3350 3000 60 0000 C CNN
-F 3 "" H 3350 3000 60 0000 C CNN
- 1 3350 3000
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 3350 3600 3350 4200
-Wire Wire Line
- 2600 4000 12450 4000
-Wire Wire Line
- 12450 4000 12450 4200
-Connection ~ 11150 4000
-Wire Wire Line
- 11150 4200 11150 4000
-Wire Wire Line
- 9850 4200 9850 4000
-Connection ~ 9850 4000
-Wire Wire Line
- 8550 4200 8550 4000
-Connection ~ 8550 4000
-Wire Wire Line
- 5950 4200 5950 4000
-Connection ~ 5950 4000
-Wire Wire Line
- 7250 4200 7250 4000
-Connection ~ 7250 4000
-Wire Wire Line
- 4650 4200 4650 4000
-Connection ~ 4650 4000
-Wire Wire Line
- 3350 5450 3350 5600
-Wire Wire Line
- 2600 5600 12450 5600
-Wire Wire Line
- 4650 5600 4650 5450
-Wire Wire Line
- 5950 5600 5950 5450
-Connection ~ 4650 5600
-Wire Wire Line
- 7250 5600 7250 5450
-Connection ~ 5950 5600
-Wire Wire Line
- 8550 5600 8550 5450
-Connection ~ 7250 5600
-Wire Wire Line
- 9850 5600 9850 5450
-Connection ~ 8550 5600
-Wire Wire Line
- 11150 5600 11150 5450
-Connection ~ 9850 5600
-Wire Wire Line
- 12450 5600 12450 5450
-Connection ~ 11150 5600
-Wire Wire Line
- 2600 2050 2600 5600
-Connection ~ 3350 4000
-Connection ~ 3350 5600
-Connection ~ 2600 4000
-Wire Wire Line
- 3350 2350 3350 2250
-Wire Wire Line
- 3350 2250 2600 2250
-Wire Wire Line
- 2600 2050 2850 2050
-Connection ~ 2600 2250
-Wire Wire Line
- 2800 3300 2650 3300
-Wire Wire Line
- 2650 3300 2650 5500
-Wire Wire Line
- 2650 5150 2800 5150
-Wire Wire Line
- 2650 5500 11850 5500
-Wire Wire Line
- 4050 5500 4050 5150
-Wire Wire Line
- 4050 5150 4100 5150
-Connection ~ 2650 5150
-Wire Wire Line
- 5400 5150 5350 5150
-Wire Wire Line
- 5350 5150 5350 5500
-Connection ~ 4050 5500
-Wire Wire Line
- 6650 5500 6650 5150
-Wire Wire Line
- 6650 5150 6700 5150
-Connection ~ 5350 5500
-Wire Wire Line
- 7950 5500 7950 5150
-Wire Wire Line
- 7950 5150 8000 5150
-Connection ~ 6650 5500
-Wire Wire Line
- 9250 5500 9250 5150
-Wire Wire Line
- 9250 5150 9300 5150
-Connection ~ 7950 5500
-Wire Wire Line
- 10550 5500 10550 5150
-Wire Wire Line
- 10550 5150 10600 5150
-Connection ~ 9250 5500
-Wire Wire Line
- 11850 5500 11850 5150
-Wire Wire Line
- 11850 5150 11900 5150
-Connection ~ 10550 5500
-Wire Wire Line
- 2650 3500 3150 3500
-Wire Wire Line
- 3150 3500 3150 3650
-Connection ~ 2650 3500
-Wire Wire Line
- 3950 2650 3900 2650
-Wire Wire Line
- 3950 2250 3950 2650
-Wire Wire Line
- 3950 2250 3750 2250
-Wire Wire Line
- 3750 2250 3750 1950
-Text Notes 8700 2050 0 60 ~ 0
-O8
-Wire Wire Line
- 13000 4500 13100 4500
-Wire Wire Line
- 13100 4500 13100 3500
-Wire Wire Line
- 13100 3500 8200 3500
-Wire Wire Line
- 8100 3600 11750 3600
-Wire Wire Line
- 11750 3600 11750 4500
-Wire Wire Line
- 11750 4500 11700 4500
-Wire Wire Line
- 8000 3700 10450 3700
-Wire Wire Line
- 10450 3700 10450 4500
-Wire Wire Line
- 10450 4500 10400 4500
-Wire Wire Line
- 7900 3800 9150 3800
-Wire Wire Line
- 9150 3800 9150 4500
-Wire Wire Line
- 9150 4500 9100 4500
-Wire Wire Line
- 7800 2350 7800 4300
-Wire Wire Line
- 7800 4300 7850 4300
-Wire Wire Line
- 7850 4300 7850 4500
-Wire Wire Line
- 7850 4500 7800 4500
-Wire Wire Line
- 6500 2250 6500 4300
-Wire Wire Line
- 6500 4300 6550 4300
-Wire Wire Line
- 6550 4300 6550 4500
-Wire Wire Line
- 6550 4500 6500 4500
-Wire Wire Line
- 3900 2050 3900 2150
-Wire Wire Line
- 3900 2150 4100 2150
-Wire Wire Line
- 4100 2150 4100 4250
-Wire Wire Line
- 4100 4250 3950 4250
-Wire Wire Line
- 3950 4250 3950 4500
-Wire Wire Line
- 3950 4500 3900 4500
-$Comp
-L d_or U45
-U 1 1 5C9948BA
-P 4650 3350
-F 0 "U45" H 4650 3350 60 0000 C CNN
-F 1 "d_or" H 4650 3450 60 0000 C CNN
-F 2 "" H 4650 3350 60 0000 C CNN
-F 3 "" H 4650 3350 60 0000 C CNN
- 1 4650 3350
- -1 0 0 1
-$EndComp
-$Comp
-L d_and U46
-U 1 1 5C994A8D
-P 4850 2700
-F 0 "U46" H 4850 2700 60 0000 C CNN
-F 1 "d_and" H 4900 2800 60 0000 C CNN
-F 2 "" H 4850 2700 60 0000 C CNN
-F 3 "" H 4850 2700 60 0000 C CNN
- 1 4850 2700
- 0 1 1 0
-$EndComp
-$Comp
-L d_and U44
-U 1 1 5C994B61
-P 4550 2700
-F 0 "U44" H 4550 2700 60 0000 C CNN
-F 1 "d_and" H 4600 2800 60 0000 C CNN
-F 2 "" H 4550 2700 60 0000 C CNN
-F 3 "" H 4550 2700 60 0000 C CNN
- 1 4550 2700
- 0 1 1 0
-$EndComp
-$Comp
-L d_inverter U43
-U 1 1 5C994C4E
-P 4300 2650
-F 0 "U43" H 4300 2550 60 0000 C CNN
-F 1 "d_inverter" H 4300 2800 60 0000 C CNN
-F 2 "" H 4350 2600 60 0000 C CNN
-F 3 "" H 4350 2600 60 0000 C CNN
- 1 4300 2650
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 4300 2950 4400 2950
-Wire Wire Line
- 4400 2950 4400 2200
-Wire Wire Line
- 4400 2200 4550 2200
-Wire Wire Line
- 4550 2200 4550 2250
-Wire Wire Line
- 2850 7550 2850 7400
-Wire Wire Line
- 2850 8150 2850 8700
-Wire Wire Line
- 2850 8700 13000 8700
-Wire Wire Line
- 12200 7900 12200 8700
-Connection ~ 12200 8700
-Wire Wire Line
- 12200 7300 12200 7100
-Wire Wire Line
- 12500 7100 12500 8700
-Connection ~ 12500 8700
-Wire Wire Line
- 10900 7300 10900 7100
-Wire Wire Line
- 10900 7900 10900 8700
-Connection ~ 10900 8700
-Wire Wire Line
- 11250 7100 11250 8700
-Connection ~ 11250 8700
-Wire Wire Line
- 9650 7100 9650 7300
-Wire Wire Line
- 10000 7100 10000 8700
-Connection ~ 10000 8700
-Wire Wire Line
- 9650 7900 9650 8700
-Connection ~ 9650 8700
-Wire Wire Line
- 7700 7700 7700 7500
-Wire Wire Line
- 7700 8300 7700 8700
-Connection ~ 7700 8700
-Wire Wire Line
- 8050 7500 8050 8700
-Connection ~ 8050 8700
-Wire Wire Line
- 5650 8950 5650 8700
-Connection ~ 5650 8700
-Wire Wire Line
- 6250 8950 6250 8650
-Wire Wire Line
- 6600 8650 6600 8700
-Connection ~ 6600 8700
-Wire Wire Line
- 3200 7400 3200 8700
-Connection ~ 3200 8700
-Wire Wire Line
- 4250 8700 4250 8150
-Connection ~ 4250 8700
-Wire Wire Line
- 4250 7550 4250 7300
-Wire Wire Line
- 4600 7300 4600 8700
-Connection ~ 4600 8700
-Wire Wire Line
- 11500 2850 11500 2950
-Wire Wire Line
- 11500 2950 12050 2950
-Wire Wire Line
- 12050 2950 12050 2050
-Wire Wire Line
- 12050 2050 12200 2050
-Wire Wire Line
- 12200 2050 12200 2100
-Wire Wire Line
- 11500 2250 11300 2250
-Wire Wire Line
- 11300 1900 11300 3450
-Wire Wire Line
- 5650 3450 13250 3450
-Wire Wire Line
- 13250 3450 13250 8500
-Wire Wire Line
- 13250 8500 12750 8500
-Wire Wire Line
- 12750 8500 12750 8700
-Connection ~ 12750 8700
-Wire Wire Line
- 11300 1900 12500 1900
-Wire Wire Line
- 12500 1900 12500 2100
-Connection ~ 11300 2250
-Wire Wire Line
- 5650 2000 5650 3450
-Connection ~ 11300 3450
-Wire Wire Line
- 3750 1950 8900 1950
-Wire Wire Line
- 4300 2350 4300 2000
-Wire Wire Line
- 4300 2000 5650 2000
-Wire Wire Line
- 4850 2250 4850 2000
-Connection ~ 4850 2000
-Wire Wire Line
- 2800 2300 2800 2650
-Wire Wire Line
- 2800 2300 4050 2300
-Wire Wire Line
- 4050 2300 4050 3400
-Wire Wire Line
- 4050 3400 4200 3400
-Wire Wire Line
- 4600 3150 4600 3250
-Wire Wire Line
- 4600 3250 5100 3250
-Wire Wire Line
- 5100 3250 5100 3350
-Wire Wire Line
- 4900 3150 5150 3150
-Wire Wire Line
- 5150 3150 5150 3450
-Wire Wire Line
- 5150 3450 5100 3450
-Wire Wire Line
- 4650 2250 4650 2100
-Wire Wire Line
- 4650 2100 5450 2100
-Wire Wire Line
- 5450 2100 5450 2500
-Wire Wire Line
- 4950 2250 5100 2250
-Wire Wire Line
- 5100 2250 5100 3000
-Wire Wire Line
- 5100 3000 8200 3000
-Connection ~ 8200 3000
-Wire Wire Line
- 3950 2550 4000 2550
-Wire Wire Line
- 4000 2550 4000 7450
-Wire Wire Line
- 4000 7450 3300 7450
-Wire Wire Line
- 3300 7450 3300 7400
-Connection ~ 3950 2550
-Wire Wire Line
- 2800 4500 2750 4500
-Wire Wire Line
- 2750 4500 2750 6150
-Wire Wire Line
- 2750 6150 3000 6150
-Wire Wire Line
- 2900 6500 2900 6300
-Wire Wire Line
- 2900 6300 3900 6300
-Wire Wire Line
- 3900 6300 3900 6200
-Wire Wire Line
- 3900 6100 3950 6100
-Wire Wire Line
- 3950 6100 3950 6450
-Wire Wire Line
- 3950 6450 3250 6450
-Wire Wire Line
- 3250 6450 3250 6500
-Wire Wire Line
- 2950 7400 2950 9100
-Wire Wire Line
- 2950 9100 2700 9100
-Wire Wire Line
- 2700 9100 2700 9050
-Wire Wire Line
- 3950 9100 4350 9100
-Wire Wire Line
- 4350 9100 4350 7300
-Wire Wire Line
- 4100 4150 4400 4150
-Wire Wire Line
- 4400 4150 4400 5850
-Connection ~ 4100 4150
-Wire Wire Line
- 4400 5850 5300 5850
-Wire Wire Line
- 5300 5850 5300 7450
-Wire Wire Line
- 5300 7450 4700 7450
-Wire Wire Line
- 4700 7450 4700 7300
-Wire Wire Line
- 4650 6400 5150 6400
-Wire Wire Line
- 5150 6400 5150 6200
-Wire Wire Line
- 5150 6200 5000 6200
-Wire Wire Line
- 4100 6150 4100 5300
-Wire Wire Line
- 4100 5300 4200 5300
-Wire Wire Line
- 4200 5300 4200 4600
-Wire Wire Line
- 4200 4600 4050 4600
-Wire Wire Line
- 4050 4600 4050 4500
-Wire Wire Line
- 4050 4500 4100 4500
-Wire Wire Line
- 4300 6400 4300 6300
-Wire Wire Line
- 4300 6300 5100 6300
-Wire Wire Line
- 5100 6300 5100 6100
-Wire Wire Line
- 5100 6100 5000 6100
-Wire Wire Line
- 6350 8650 6350 9100
-Wire Wire Line
- 6350 9100 5850 9100
-Wire Wire Line
- 5400 4500 5350 4500
-Wire Wire Line
- 5350 4500 5350 5100
-Wire Wire Line
- 5350 5100 5300 5100
-Wire Wire Line
- 5300 5100 5300 5350
-Wire Wire Line
- 5300 5350 5600 5350
-Wire Wire Line
- 5600 5350 5600 7500
-Wire Wire Line
- 5600 7500 6000 7500
-Wire Wire Line
- 5250 4500 5200 4500
-Wire Wire Line
- 5200 2150 8900 2150
-Wire Wire Line
- 5200 2150 5200 4250
-Wire Wire Line
- 5200 4250 5250 4250
-Wire Wire Line
- 5250 4250 5250 4500
-Wire Wire Line
- 5250 4350 5750 4350
-Wire Wire Line
- 5750 4350 5750 7250
-Wire Wire Line
- 5750 7250 7250 7250
-Connection ~ 5250 4350
-Wire Wire Line
- 7250 7250 7250 8850
-Wire Wire Line
- 7250 8850 6700 8850
-Wire Wire Line
- 6700 8850 6700 8650
-Wire Wire Line
- 6650 7750 6650 7700
-Wire Wire Line
- 6650 7700 7050 7700
-Wire Wire Line
- 7050 7700 7050 7550
-Wire Wire Line
- 7050 7550 6900 7550
-Wire Wire Line
- 6300 7750 6300 7650
-Wire Wire Line
- 6300 7650 7150 7650
-Wire Wire Line
- 7150 7650 7150 7450
-Wire Wire Line
- 7150 7450 6900 7450
-Wire Wire Line
- 7450 9050 7800 9050
-Wire Wire Line
- 7800 9050 7800 7500
-Wire Wire Line
- 7750 6600 7750 6450
-Wire Wire Line
- 7750 6450 8550 6450
-Wire Wire Line
- 8550 6450 8550 6350
-Wire Wire Line
- 8550 6350 8400 6350
-Wire Wire Line
- 8400 6250 8600 6250
-Wire Wire Line
- 8600 6250 8600 6500
-Wire Wire Line
- 8600 6500 8100 6500
-Wire Wire Line
- 8100 6500 8100 6600
-Wire Wire Line
- 6600 4500 6700 4500
-Wire Wire Line
- 6600 4500 6600 6300
-Wire Wire Line
- 6600 6300 7500 6300
-Wire Wire Line
- 6500 4150 7100 4150
-Wire Wire Line
- 7100 4150 7100 6050
-Wire Wire Line
- 7100 6050 8800 6050
-Wire Wire Line
- 8800 6050 8800 7600
-Wire Wire Line
- 8800 7600 8150 7600
-Wire Wire Line
- 8150 7600 8150 7500
-Connection ~ 6500 4150
-Wire Wire Line
- 9750 7100 9750 9050
-Wire Wire Line
- 9750 9050 9400 9050
-Wire Wire Line
- 11000 7100 11000 9050
-Wire Wire Line
- 11000 9050 10650 9050
-Wire Wire Line
- 12300 7100 12300 9050
-Wire Wire Line
- 12300 9050 12050 9050
-Wire Wire Line
- 12250 6200 12250 6100
-Wire Wire Line
- 12250 6100 13000 6100
-Wire Wire Line
- 13000 6100 13000 5950
-Wire Wire Line
- 13000 5950 12900 5950
-Wire Wire Line
- 12900 5850 13100 5850
-Wire Wire Line
- 13100 5850 13100 6150
-Wire Wire Line
- 13100 6150 12550 6150
-Wire Wire Line
- 12550 6150 12550 6200
-Wire Wire Line
- 8000 4500 7900 4500
-Wire Wire Line
- 7900 4500 7900 5900
-Wire Wire Line
- 7900 5900 9450 5900
-Wire Wire Line
- 7800 4150 8400 4150
-Wire Wire Line
- 8400 4150 8400 5700
-Wire Wire Line
- 8400 5700 10550 5700
-Wire Wire Line
- 10550 5700 10550 7250
-Wire Wire Line
- 10550 7250 10100 7250
-Wire Wire Line
- 10100 7250 10100 7100
-Connection ~ 7800 4150
-Wire Wire Line
- 9700 6200 9700 6100
-Wire Wire Line
- 9700 6100 10450 6100
-Wire Wire Line
- 10450 6100 10450 5950
-Wire Wire Line
- 10450 5950 10350 5950
-Wire Wire Line
- 10350 5850 10500 5850
-Wire Wire Line
- 10500 5850 10500 6150
-Wire Wire Line
- 10500 6150 10050 6150
-Wire Wire Line
- 10050 6150 10050 6200
-Wire Wire Line
- 9300 4500 9200 4500
-Wire Wire Line
- 9200 4500 9200 5300
-Wire Wire Line
- 9200 5300 10650 5300
-Wire Wire Line
- 10650 5300 10650 5900
-Wire Wire Line
- 10650 5900 10700 5900
-Wire Wire Line
- 9150 4200 9650 4200
-Wire Wire Line
- 9650 4200 9650 4850
-Wire Wire Line
- 9650 4850 10450 4850
-Wire Wire Line
- 10450 4850 10450 5650
-Wire Wire Line
- 10450 5650 11750 5650
-Connection ~ 9150 4200
-Wire Wire Line
- 11750 5650 11750 7300
-Wire Wire Line
- 11750 7300 11350 7300
-Wire Wire Line
- 11350 7300 11350 7100
-Wire Wire Line
- 10950 6200 10950 6100
-Wire Wire Line
- 10950 6100 11650 6100
-Wire Wire Line
- 11650 6100 11650 5950
-Wire Wire Line
- 11650 5950 11600 5950
-Wire Wire Line
- 11600 5850 11700 5850
-Wire Wire Line
- 11700 5850 11700 6150
-Wire Wire Line
- 11700 6150 11300 6150
-Wire Wire Line
- 11300 6150 11300 6200
-Wire Wire Line
- 10600 4500 10600 4950
-Wire Wire Line
- 10600 4950 11350 4950
-Wire Wire Line
- 11350 4950 11350 5450
-Wire Wire Line
- 11350 5450 11950 5450
-Wire Wire Line
- 11950 5450 11950 5900
-Wire Wire Line
- 11950 5900 12000 5900
-Wire Wire Line
- 10450 4200 11000 4200
-Wire Wire Line
- 11000 4200 11000 4700
-Wire Wire Line
- 11000 4700 11800 4700
-Wire Wire Line
- 11800 4700 11800 5350
-Wire Wire Line
- 11800 5350 13150 5350
-Wire Wire Line
- 13150 5350 13150 7250
-Connection ~ 10450 4200
-Wire Wire Line
- 13150 7250 12600 7250
-Wire Wire Line
- 12600 7250 12600 7100
-Wire Wire Line
- 11900 4500 11800 4500
-Wire Wire Line
- 11800 4500 11800 3150
-Wire Wire Line
- 11800 3150 11900 3150
-Wire Wire Line
- 12550 3000 12900 3000
-Wire Wire Line
- 12900 3000 12900 3100
-Wire Wire Line
- 12900 3100 12800 3100
-Wire Wire Line
- 12250 3000 12400 3000
-Wire Wire Line
- 12400 3000 12400 2850
-Wire Wire Line
- 12400 2850 13200 2850
-Wire Wire Line
- 13200 2850 13200 3200
-Wire Wire Line
- 13200 3200 12800 3200
-Wire Wire Line
- 10200 2000 12300 2000
-Wire Wire Line
- 12300 2000 12300 2100
-Wire Wire Line
- 11650 3600 11650 1950
-Wire Wire Line
- 11650 1950 12600 1950
-Wire Wire Line
- 12600 1950 12600 2100
-Connection ~ 11650 3600
-$Comp
-L PORT U5
-U 12 1 5C982725
-P 9150 2750
-F 0 "U5" H 9200 2850 30 0000 C CNN
-F 1 "PORT" H 9150 2750 30 0000 C CNN
-F 2 "" H 9150 2750 60 0000 C CNN
-F 3 "" H 9150 2750 60 0000 C CNN
- 12 9150 2750
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 17 1 5C9827C2
-P 9550 2650
-F 0 "U5" H 9600 2750 30 0000 C CNN
-F 1 "PORT" H 9550 2650 30 0000 C CNN
-F 2 "" H 9550 2650 60 0000 C CNN
-F 3 "" H 9550 2650 60 0000 C CNN
- 17 9550 2650
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 11 1 5C98283D
-P 9150 2550
-F 0 "U5" H 9200 2650 30 0000 C CNN
-F 1 "PORT" H 9150 2550 30 0000 C CNN
-F 2 "" H 9150 2550 60 0000 C CNN
-F 3 "" H 9150 2550 60 0000 C CNN
- 11 9150 2550
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 16 1 5C9828CC
-P 9550 2450
-F 0 "U5" H 9600 2550 30 0000 C CNN
-F 1 "PORT" H 9550 2450 30 0000 C CNN
-F 2 "" H 9550 2450 60 0000 C CNN
-F 3 "" H 9550 2450 60 0000 C CNN
- 16 9550 2450
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 10 1 5C982957
-P 9150 2350
-F 0 "U5" H 9200 2450 30 0000 C CNN
-F 1 "PORT" H 9150 2350 30 0000 C CNN
-F 2 "" H 9150 2350 60 0000 C CNN
-F 3 "" H 9150 2350 60 0000 C CNN
- 10 9150 2350
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 15 1 5C9829D6
-P 9550 2250
-F 0 "U5" H 9600 2350 30 0000 C CNN
-F 1 "PORT" H 9550 2250 30 0000 C CNN
-F 2 "" H 9550 2250 60 0000 C CNN
-F 3 "" H 9550 2250 60 0000 C CNN
- 15 9550 2250
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 9 1 5C982A5D
-P 9150 2150
-F 0 "U5" H 9200 2250 30 0000 C CNN
-F 1 "PORT" H 9150 2150 30 0000 C CNN
-F 2 "" H 9150 2150 60 0000 C CNN
-F 3 "" H 9150 2150 60 0000 C CNN
- 9 9150 2150
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 14 1 5C982AE0
-P 9550 2050
-F 0 "U5" H 9600 2150 30 0000 C CNN
-F 1 "PORT" H 9550 2050 30 0000 C CNN
-F 2 "" H 9550 2050 60 0000 C CNN
-F 3 "" H 9550 2050 60 0000 C CNN
- 14 9550 2050
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 8 1 5C982B81
-P 9150 1950
-F 0 "U5" H 9200 2050 30 0000 C CNN
-F 1 "PORT" H 9150 1950 30 0000 C CNN
-F 2 "" H 9150 1950 60 0000 C CNN
-F 3 "" H 9150 1950 60 0000 C CNN
- 8 9150 1950
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 21 1 5C983602
-P 13250 8700
-F 0 "U5" H 13300 8800 30 0000 C CNN
-F 1 "PORT" H 13250 8700 30 0000 C CNN
-F 2 "" H 13250 8700 60 0000 C CNN
-F 3 "" H 13250 8700 60 0000 C CNN
- 21 13250 8700
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 18 1 5C983C2F
-P 9950 2000
-F 0 "U5" H 10000 2100 30 0000 C CNN
-F 1 "PORT" H 9950 2000 30 0000 C CNN
-F 2 "" H 9950 2000 60 0000 C CNN
-F 3 "" H 9950 2000 60 0000 C CNN
- 18 9950 2000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U5
-U 20 1 5C984048
-P 11800 9050
-F 0 "U5" H 11850 9150 30 0000 C CNN
-F 1 "PORT" H 11800 9050 30 0000 C CNN
-F 2 "" H 11800 9050 60 0000 C CNN
-F 3 "" H 11800 9050 60 0000 C CNN
- 20 11800 9050
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U5
-U 19 1 5C9840D3
-P 10400 9050
-F 0 "U5" H 10450 9150 30 0000 C CNN
-F 1 "PORT" H 10400 9050 30 0000 C CNN
-F 2 "" H 10400 9050 60 0000 C CNN
-F 3 "" H 10400 9050 60 0000 C CNN
- 19 10400 9050
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U5
-U 13 1 5C984164
-P 9150 9050
-F 0 "U5" H 9200 9150 30 0000 C CNN
-F 1 "PORT" H 9150 9050 30 0000 C CNN
-F 2 "" H 9150 9050 60 0000 C CNN
-F 3 "" H 9150 9050 60 0000 C CNN
- 13 9150 9050
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U5
-U 7 1 5C985678
-P 7200 9050
-F 0 "U5" H 7250 9150 30 0000 C CNN
-F 1 "PORT" H 7200 9050 30 0000 C CNN
-F 2 "" H 7200 9050 60 0000 C CNN
-F 3 "" H 7200 9050 60 0000 C CNN
- 7 7200 9050
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U5
-U 6 1 5C985709
-P 5600 9100
-F 0 "U5" H 5650 9200 30 0000 C CNN
-F 1 "PORT" H 5600 9100 30 0000 C CNN
-F 2 "" H 5600 9100 60 0000 C CNN
-F 3 "" H 5600 9100 60 0000 C CNN
- 6 5600 9100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U5
-U 4 1 5C98579A
-P 3700 9100
-F 0 "U5" H 3750 9200 30 0000 C CNN
-F 1 "PORT" H 3700 9100 30 0000 C CNN
-F 2 "" H 3700 9100 60 0000 C CNN
-F 3 "" H 3700 9100 60 0000 C CNN
- 4 3700 9100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U5
-U 1 1 5C98582D
-P 2700 8800
-F 0 "U5" H 2750 8900 30 0000 C CNN
-F 1 "PORT" H 2700 8800 30 0000 C CNN
-F 2 "" H 2700 8800 60 0000 C CNN
-F 3 "" H 2700 8800 60 0000 C CNN
- 1 2700 8800
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U5
-U 5 1 5C98694B
-P 5450 2750
-F 0 "U5" H 5500 2850 30 0000 C CNN
-F 1 "PORT" H 5450 2750 30 0000 C CNN
-F 2 "" H 5450 2750 60 0000 C CNN
-F 3 "" H 5450 2750 60 0000 C CNN
- 5 5450 2750
- 0 -1 -1 0
-$EndComp
-Text Notes 5400 2450 1 60 ~ 0
-IN8
-Text Notes 2650 2000 0 60 ~ 0
-GND
-$Comp
-L PORT U5
-U 2 1 5C986B72
-P 3100 2050
-F 0 "U5" H 3150 2150 30 0000 C CNN
-F 1 "PORT" H 3100 2050 30 0000 C CNN
-F 2 "" H 3100 2050 60 0000 C CNN
-F 3 "" H 3100 2050 60 0000 C CNN
- 2 3100 2050
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U5
-U 3 1 5C986C25
-P 3150 3900
-F 0 "U5" H 3200 4000 30 0000 C CNN
-F 1 "PORT" H 3150 3900 30 0000 C CNN
-F 2 "" H 3150 3900 60 0000 C CNN
-F 3 "" H 3150 3900 60 0000 C CNN
- 3 3150 3900
- 0 -1 -1 0
-$EndComp
-Text Notes 2850 3600 0 60 ~ 0
-CLK
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub
deleted file mode 100644
index e94cb0f4..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub
+++ /dev/null
@@ -1,186 +0,0 @@
-* Subcircuit 9bit-Right_shift_register
-.subckt 9bit-Right_shift_register net-_u5-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u13-pad2_ net-_u44-pad1_ net-_u19-pad2_ net-_u23-pad2_ net-_u10-pad2_ net-_u2-pad5_ net-_u30-pad2_ net-_u42-pad2_ net-_u18-pad5_ net-_u28-pad2_ net-_u1-pad5_ net-_u26-pad2_ net-_u34-pad2_ net-_u15-pad5_ net-_u36-pad1_ net-_u32-pad2_ net-_u38-pad2_ net-_u10-pad1_
-* c:\esim\esim\src\subcircuitlibrary\9bit-right_shift_register\9bit-right_shift_register.cir
-* u3 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? d_dff
-* u4 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? d_dff
-* u6 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? d_dff
-* u15 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? d_dff
-* u2 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? d_dff
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? d_dff
-* u18 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? d_dff
-* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u1-pad1_ d_or
-* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or
-* u20 net-_u20-pad1_ net-_u19-pad3_ net-_u20-pad3_ d_or
-* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u8 net-_u7-pad2_ net-_u5-pad1_ net-_u11-pad1_ d_and
-* u7 net-_u10-pad1_ net-_u7-pad2_ d_inverter
-* u13 net-_u12-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_and
-* u16 net-_u10-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and
-* u12 net-_u10-pad1_ net-_u12-pad2_ d_inverter
-* u19 net-_u17-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_and
-* u21 net-_u10-pad1_ net-_u2-pad5_ net-_u20-pad1_ d_and
-* u17 net-_u10-pad1_ net-_u17-pad2_ d_inverter
-* u25 net-_u23-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_or
-* u23 net-_u22-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and
-* u26 net-_u10-pad1_ net-_u26-pad2_ net-_u25-pad2_ d_and
-* u22 net-_u10-pad1_ net-_u22-pad2_ d_inverter
-* u29 net-_u28-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_or
-* u28 net-_u27-pad2_ net-_u28-pad2_ net-_u28-pad3_ d_and
-* u30 net-_u10-pad1_ net-_u30-pad2_ net-_u29-pad2_ d_and
-* u27 net-_u10-pad1_ net-_u27-pad2_ d_inverter
-* u33 net-_u32-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
-* u40 net-_u38-pad3_ net-_u40-pad2_ net-_u15-pad1_ d_or
-* u32 net-_u31-pad2_ net-_u32-pad2_ net-_u32-pad3_ d_and
-* u34 net-_u10-pad1_ net-_u34-pad2_ net-_u33-pad2_ d_and
-* u38 net-_u37-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_and
-* u42 net-_u10-pad1_ net-_u42-pad2_ net-_u40-pad2_ d_and
-* u31 net-_u10-pad1_ net-_u31-pad2_ d_inverter
-* u37 net-_u10-pad1_ net-_u37-pad2_ d_inverter
-* u39 net-_u36-pad3_ net-_u39-pad2_ net-_u18-pad1_ d_or
-* u36 net-_u36-pad1_ net-_u35-pad2_ net-_u36-pad3_ d_and
-* u41 net-_u15-pad5_ net-_u10-pad1_ net-_u39-pad2_ d_and
-* u9 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? d_dff
-* u35 net-_u10-pad1_ net-_u35-pad2_ d_inverter
-* u24 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? d_dff
-* u45 net-_u45-pad1_ net-_u44-pad3_ net-_u24-pad1_ d_or
-* u46 net-_u18-pad5_ net-_u10-pad1_ net-_u45-pad1_ d_and
-* u44 net-_u44-pad1_ net-_u43-pad2_ net-_u44-pad3_ d_and
-* u43 net-_u10-pad1_ net-_u43-pad2_ d_inverter
-a1 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? u3
-a2 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? u4
-a3 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? u6
-a4 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? u15
-a5 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? u2
-a6 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? u1
-a7 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? u18
-a8 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u1-pad1_ u11
-a9 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14
-a10 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u20-pad3_ u20
-a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a12 [net-_u7-pad2_ net-_u5-pad1_ ] net-_u11-pad1_ u8
-a13 net-_u10-pad1_ net-_u7-pad2_ u7
-a14 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13
-a15 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u16
-a16 net-_u10-pad1_ net-_u12-pad2_ u12
-a17 [net-_u17-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19
-a18 [net-_u10-pad1_ net-_u2-pad5_ ] net-_u20-pad1_ u21
-a19 net-_u10-pad1_ net-_u17-pad2_ u17
-a20 [net-_u23-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25
-a21 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23
-a22 [net-_u10-pad1_ net-_u26-pad2_ ] net-_u25-pad2_ u26
-a23 net-_u10-pad1_ net-_u22-pad2_ u22
-a24 [net-_u28-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29
-a25 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u28-pad3_ u28
-a26 [net-_u10-pad1_ net-_u30-pad2_ ] net-_u29-pad2_ u30
-a27 net-_u10-pad1_ net-_u27-pad2_ u27
-a28 [net-_u32-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
-a29 [net-_u38-pad3_ net-_u40-pad2_ ] net-_u15-pad1_ u40
-a30 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u32-pad3_ u32
-a31 [net-_u10-pad1_ net-_u34-pad2_ ] net-_u33-pad2_ u34
-a32 [net-_u37-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38
-a33 [net-_u10-pad1_ net-_u42-pad2_ ] net-_u40-pad2_ u42
-a34 net-_u10-pad1_ net-_u31-pad2_ u31
-a35 net-_u10-pad1_ net-_u37-pad2_ u37
-a36 [net-_u36-pad3_ net-_u39-pad2_ ] net-_u18-pad1_ u39
-a37 [net-_u36-pad1_ net-_u35-pad2_ ] net-_u36-pad3_ u36
-a38 [net-_u15-pad5_ net-_u10-pad1_ ] net-_u39-pad2_ u41
-a39 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? u9
-a40 net-_u10-pad1_ net-_u35-pad2_ u35
-a41 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? u24
-a42 [net-_u45-pad1_ net-_u44-pad3_ ] net-_u24-pad1_ u45
-a43 [net-_u18-pad5_ net-_u10-pad1_ ] net-_u45-pad1_ u46
-a44 [net-_u44-pad1_ net-_u43-pad2_ ] net-_u44-pad3_ u44
-a45 net-_u10-pad1_ net-_u43-pad2_ u43
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u4 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u6 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u1 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u18 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u12 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u17 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u25 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u23 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u26 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u29 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u28 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u30 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u40 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u34 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u38 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u42 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u31 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u37 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u39 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u36 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u41 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u9 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u24 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u45 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u46 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u44 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 9bit-Right_shift_register \ No newline at end of file
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml
deleted file mode 100644
index 28c290d4..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u3 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u4><u6 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u6><u15 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u15><u2 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u2><u1 name="type">d_dff<field51 name="Enter IC (default=0)" /><field52 name="Enter Set Delay (default=1.0e-9)" /><field53 name="Enter value for Set Load (default=1.0e-12)" /><field54 name="Enter Clk Delay (default=1.0e-9)" /><field55 name="Enter value for Clk Load (default=1.0e-12)" /><field56 name="Enter Reset Delay (default=1.0)" /><field57 name="Enter value for Data Load (default=1.0e-12)" /><field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter value for Reset Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u1><u18 name="type">d_dff<field61 name="Enter IC (default=0)" /><field62 name="Enter Set Delay (default=1.0e-9)" /><field63 name="Enter value for Set Load (default=1.0e-12)" /><field64 name="Enter Clk Delay (default=1.0e-9)" /><field65 name="Enter value for Clk Load (default=1.0e-12)" /><field66 name="Enter Reset Delay (default=1.0)" /><field67 name="Enter value for Data Load (default=1.0e-12)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter value for Reset Load (default=1.0e-12)" /><field70 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_or<field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /><field73 name="Enter Rise Delay (default=1.0e-9)" /></u11><u14 name="type">d_or<field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /><field76 name="Enter Rise Delay (default=1.0e-9)" /></u14><u20 name="type">d_or<field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /><field79 name="Enter Rise Delay (default=1.0e-9)" /></u20><u10 name="type">d_and<field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /><field82 name="Enter Rise Delay (default=1.0e-9)" /></u10><u8 name="type">d_and<field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /><field85 name="Enter Rise Delay (default=1.0e-9)" /></u8><u7 name="type">d_inverter<field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /><field88 name="Enter Rise Delay (default=1.0e-9)" /></u7><u13 name="type">d_and<field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /><field91 name="Enter Rise Delay (default=1.0e-9)" /></u13><u16 name="type">d_and<field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /><field94 name="Enter Rise Delay (default=1.0e-9)" /></u16><u12 name="type">d_inverter<field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /><field97 name="Enter Rise Delay (default=1.0e-9)" /></u12><u19 name="type">d_and<field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /><field100 name="Enter Rise Delay (default=1.0e-9)" /></u19><u21 name="type">d_and<field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /><field103 name="Enter Rise Delay (default=1.0e-9)" /></u21><u17 name="type">d_inverter<field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /><field106 name="Enter Rise Delay (default=1.0e-9)" /></u17><u25 name="type">d_or<field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /><field109 name="Enter Rise Delay (default=1.0e-9)" /></u25><u23 name="type">d_and<field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /><field112 name="Enter Rise Delay (default=1.0e-9)" /></u23><u26 name="type">d_and<field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /><field115 name="Enter Rise Delay (default=1.0e-9)" /></u26><u22 name="type">d_inverter<field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /><field118 name="Enter Rise Delay (default=1.0e-9)" /></u22><u29 name="type">d_or<field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /><field121 name="Enter Rise Delay (default=1.0e-9)" /></u29><u28 name="type">d_and<field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /><field124 name="Enter Rise Delay (default=1.0e-9)" /></u28><u30 name="type">d_and<field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /><field127 name="Enter Rise Delay (default=1.0e-9)" /></u30><u27 name="type">d_inverter<field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /><field130 name="Enter Rise Delay (default=1.0e-9)" /></u27><u33 name="type">d_or<field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /><field133 name="Enter Rise Delay (default=1.0e-9)" /></u33><u40 name="type">d_or<field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /><field136 name="Enter Rise Delay (default=1.0e-9)" /></u40><u32 name="type">d_and<field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /><field139 name="Enter Rise Delay (default=1.0e-9)" /></u32><u34 name="type">d_and<field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /><field142 name="Enter Rise Delay (default=1.0e-9)" /></u34><u38 name="type">d_and<field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /><field145 name="Enter Rise Delay (default=1.0e-9)" /></u38><u42 name="type">d_and<field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /><field148 name="Enter Rise Delay (default=1.0e-9)" /></u42><u31 name="type">d_inverter<field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /><field151 name="Enter Rise Delay (default=1.0e-9)" /></u31><u37 name="type">d_inverter<field152 name="Enter Fall Delay (default=1.0e-9)" /><field153 name="Enter Input Load (default=1.0e-12)" /><field154 name="Enter Rise Delay (default=1.0e-9)" /></u37><u39 name="type">d_or<field155 name="Enter Fall Delay (default=1.0e-9)" /><field156 name="Enter Input Load (default=1.0e-12)" /><field157 name="Enter Rise Delay (default=1.0e-9)" /></u39><u36 name="type">d_and<field158 name="Enter Fall Delay (default=1.0e-9)" /><field159 name="Enter Input Load (default=1.0e-12)" /><field160 name="Enter Rise Delay (default=1.0e-9)" /></u36><u41 name="type">d_and<field161 name="Enter Fall Delay (default=1.0e-9)" /><field162 name="Enter Input Load (default=1.0e-12)" /><field163 name="Enter Rise Delay (default=1.0e-9)" /></u41><u9 name="type">d_dff<field164 name="Enter IC (default=0)" /><field165 name="Enter Set Delay (default=1.0e-9)" /><field166 name="Enter value for Set Load (default=1.0e-12)" /><field167 name="Enter Clk Delay (default=1.0e-9)" /><field168 name="Enter value for Clk Load (default=1.0e-12)" /><field169 name="Enter Reset Delay (default=1.0)" /><field170 name="Enter value for Data Load (default=1.0e-12)" /><field171 name="Enter Fall Delay (default=1.0e-9)" /><field172 name="Enter value for Reset Load (default=1.0e-12)" /><field173 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field174 name="Enter Fall Delay (default=1.0e-9)" /><field175 name="Enter Input Load (default=1.0e-12)" /><field176 name="Enter Rise Delay (default=1.0e-9)" /></u35><u24 name="type">d_dff<field177 name="Enter IC (default=0)" /><field178 name="Enter Set Delay (default=1.0e-9)" /><field179 name="Enter value for Set Load (default=1.0e-12)" /><field180 name="Enter Clk Delay (default=1.0e-9)" /><field181 name="Enter value for Clk Load (default=1.0e-12)" /><field182 name="Enter Reset Delay (default=1.0)" /><field183 name="Enter value for Data Load (default=1.0e-12)" /><field184 name="Enter Fall Delay (default=1.0e-9)" /><field185 name="Enter value for Reset Load (default=1.0e-12)" /><field186 name="Enter Rise Delay (default=1.0e-9)" /></u24><u45 name="type">d_or<field187 name="Enter Fall Delay (default=1.0e-9)" /><field188 name="Enter Input Load (default=1.0e-12)" /><field189 name="Enter Rise Delay (default=1.0e-9)" /></u45><u46 name="type">d_and<field190 name="Enter Fall Delay (default=1.0e-9)" /><field191 name="Enter Input Load (default=1.0e-12)" /><field192 name="Enter Rise Delay (default=1.0e-9)" /></u46><u44 name="type">d_and<field193 name="Enter Fall Delay (default=1.0e-9)" /><field194 name="Enter Input Load (default=1.0e-12)" /><field195 name="Enter Rise Delay (default=1.0e-9)" /></u44><u43 name="type">d_inverter<field196 name="Enter Fall Delay (default=1.0e-9)" /><field197 name="Enter Input Load (default=1.0e-12)" /><field198 name="Enter Rise Delay (default=1.0e-9)" /></u43></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/analysis b/src/SubcircuitLibrary/9bit-Right_shift_register/analysis
deleted file mode 100644
index 52ccc5ec..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.ac lin 0 0Hz 0Hz \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-01-10 15:28:05 +0000