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diff --git a/src/SubcircuitLibrary/7485/5_nor.sub b/src/SubcircuitLibrary/7485/5_nor.sub
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-* Subcircuit 5_nor
-.subckt 5_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir
-.include 5_and.sub
-* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_nor \ No newline at end of file