diff options
Diffstat (limited to 'src/SubcircuitLibrary/74153/4_OR.sub')
| -rw-r--r-- | src/SubcircuitLibrary/74153/4_OR.sub | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/74153/4_OR.sub b/src/SubcircuitLibrary/74153/4_OR.sub new file mode 100644 index 00000000..53fc8b33 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file |