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-rw-r--r--src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib61
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/3_and.cir13
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/3_and.cir.out20
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/3_and.pro58
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/3_and.sch121
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/3_and.sub14
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml1
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib63
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_OR.cir14
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out24
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_OR.pro45
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_OR.sch150
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_OR.sub18
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml1
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib79
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_and.cir13
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_and.cir.out18
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_and.pro57
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_and.sch139
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_and.sub12
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml1
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib172
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir48
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out151
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro58
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch945
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub145
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml1
-rw-r--r--src/SubcircuitLibrary/4_bit_FA/analysis1
29 files changed, 2443 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib b/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib
new file mode 100644
index 00000000..0a3ccf7f
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.cir b/src/SubcircuitLibrary/4_bit_FA/3_and.cir
new file mode 100644
index 00000000..15f8954d
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out b/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out
new file mode 100644
index 00000000..e3c96645
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.pro b/src/SubcircuitLibrary/4_bit_FA/3_and.pro
new file mode 100644
index 00000000..1b535492
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/3_and.pro
@@ -0,0 +1,58 @@
+update=03/26/19 18:40:23
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_Subckt
+LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.sch b/src/SubcircuitLibrary/4_bit_FA/3_and.sch
new file mode 100644
index 00000000..6c8d3d4a
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/3_and.sch
@@ -0,0 +1,121 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.sub b/src/SubcircuitLibrary/4_bit_FA/3_and.sub
new file mode 100644
index 00000000..b949ae4f
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and \ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml
new file mode 100644
index 00000000..abc5faaa
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib
new file mode 100644
index 00000000..a3c1c972
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir
new file mode 100644
index 00000000..7adbf177
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out
new file mode 100644
index 00000000..4388b975
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.pro b/src/SubcircuitLibrary/4_bit_FA/4_OR.pro
new file mode 100644
index 00000000..8bd4bbf5
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.pro
@@ -0,0 +1,45 @@
+update=03/28/19 22:43:48
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sch b/src/SubcircuitLibrary/4_bit_FA/4_OR.sch
new file mode 100644
index 00000000..2f28896c
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
+ 4800 2900 4750 2900
+Wire Wire Line
+ 4800 3150 4800 3300
+Wire Wire Line
+ 4800 3300 4750 3300
+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
+ 3600 2950 3600 3000
+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sub b/src/SubcircuitLibrary/4_bit_FA/4_OR.sub
new file mode 100644
index 00000000..53fc8b33
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR \ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml
new file mode 100644
index 00000000..23698d37
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib
new file mode 100644
index 00000000..4cf915be
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.cir b/src/SubcircuitLibrary/4_bit_FA/4_and.cir
new file mode 100644
index 00000000..25e839cd
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out
new file mode 100644
index 00000000..6e35b18a
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.pro b/src/SubcircuitLibrary/4_bit_FA/4_and.pro
new file mode 100644
index 00000000..cc0f1b93
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_and.pro
@@ -0,0 +1,57 @@
+update=03/26/19 18:58:33
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=texas
+LibName2=intel
+LibName3=audio
+LibName4=interface
+LibName5=digital-audio
+LibName6=philips
+LibName7=display
+LibName8=cypress
+LibName9=siliconi
+LibName10=opto
+LibName11=atmel
+LibName12=contrib
+LibName13=valves
+LibName14=eSim_Analog
+LibName15=eSim_Devices
+LibName16=eSim_Digital
+LibName17=eSim_Hybrid
+LibName18=eSim_Miscellaneous
+LibName19=eSim_Plot
+LibName20=eSim_Power
+LibName21=eSim_PSpice
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.sch b/src/SubcircuitLibrary/4_bit_FA/4_and.sch
new file mode 100644
index 00000000..bcc3cecf
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_and.sch
@@ -0,0 +1,139 @@
+EESchema Schematic File Version 2
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.sub b/src/SubcircuitLibrary/4_bit_FA/4_and.sub
new file mode 100644
index 00000000..bf20b628
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and \ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml
new file mode 100644
index 00000000..f2ba0130
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib
new file mode 100644
index 00000000..f787854a
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib
@@ -0,0 +1,172 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 3900 3050 60 H V C CNN
+F1 "4_OR" 3900 3250 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900
+A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150
+A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150
+P 2 0 1 0 3550 2900 3900 2900 N
+P 2 0 1 0 3550 3400 3900 3400 N
+X in1 1 3400 3300 200 R 50 50 1 1 I
+X in2 2 3400 3200 200 R 50 50 1 1 I
+X in3 3 3400 3100 200 R 50 50 1 1 I
+X in4 4 3400 3000 200 R 50 50 1 1 I
+X out 5 4300 3150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 1500 1050 60 H V C CNN
+F1 "4_and" 1550 1200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
+P 2 0 1 0 1250 1300 1600 1300 N
+P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N
+X in1 1 1050 1250 200 R 50 50 1 1 I
+X in2 2 1050 1150 200 R 50 50 1 1 I
+X in3 3 1050 1050 200 R 50 50 1 1 I
+X in4 4 1050 950 200 R 50 50 1 1 I
+X out 5 1950 1100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir
new file mode 100644
index 00000000..8fe97f7e
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir
@@ -0,0 +1,48 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_bit_FA\4_bit_FA.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:04:20
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U16-Pad2_ d_or
+U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U24-Pad2_ d_and
+U4 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U17-Pad2_ d_or
+U5 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U26-Pad2_ d_and
+U6 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U18-Pad2_ d_or
+U7 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U10-Pad2_ d_and
+U8 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad1_ d_or
+U9 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U31-Pad2_ d_and
+U16 Net-_U1-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and
+U24 Net-_U16-Pad3_ Net-_U24-Pad2_ Net-_U17-Pad1_ d_or
+U33 Net-_U23-Pad2_ Net-_U24-Pad2_ Net-_U33-Pad3_ d_or
+U23 Net-_U16-Pad2_ Net-_U23-Pad2_ d_inverter
+U38 Net-_U1-Pad1_ Net-_U33-Pad3_ Net-_U38-Pad3_ d_xor
+U42 Net-_U38-Pad3_ Net-_U1-Pad13_ d_inverter
+U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and
+U26 Net-_U17-Pad3_ Net-_U26-Pad2_ Net-_U18-Pad1_ d_or
+U34 Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U34-Pad3_ d_or
+U25 Net-_U17-Pad2_ Net-_U25-Pad2_ d_inverter
+U39 Net-_U17-Pad1_ Net-_U34-Pad3_ Net-_U39-Pad3_ d_xor
+U44 Net-_U39-Pad3_ Net-_U1-Pad10_ d_inverter
+U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and
+U28 Net-_U18-Pad3_ Net-_U10-Pad2_ Net-_U28-Pad3_ d_or
+U35 Net-_U27-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad3_ d_or
+U27 Net-_U18-Pad2_ Net-_U27-Pad2_ d_inverter
+U40 Net-_U18-Pad1_ Net-_U35-Pad3_ Net-_U40-Pad3_ d_xor
+U45 Net-_U40-Pad3_ Net-_U1-Pad11_ d_inverter
+U31 Net-_U21-Pad2_ Net-_U31-Pad2_ Net-_U31-Pad3_ d_or
+U21 Net-_U10-Pad1_ Net-_U21-Pad2_ d_inverter
+U37 Net-_U28-Pad3_ Net-_U31-Pad3_ Net-_U37-Pad3_ d_xor
+U43 Net-_U37-Pad3_ Net-_U1-Pad12_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and
+U32 Net-_U1-Pad1_ Net-_U32-Pad2_ Net-_U32-Pad3_ d_and
+U41 Net-_U32-Pad3_ Net-_U41-Pad2_ Net-_U1-Pad14_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
+X1 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_U16-Pad2_ Net-_U32-Pad2_ 4_and
+X4 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U26-Pad2_ Net-_X3-Pad3_ 3_and
+X2 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_U24-Pad2_ Net-_X2-Pad5_ 4_and
+X3 Net-_U31-Pad2_ Net-_U10-Pad3_ Net-_X3-Pad3_ Net-_X2-Pad5_ Net-_U41-Pad2_ 4_OR
+
+.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out
new file mode 100644
index 00000000..4d05d64a
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out
@@ -0,0 +1,151 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir
+
+.include 4_and.sub
+.include 3_and.sub
+.include 4_OR.sub
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or
+* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and
+* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or
+* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and
+* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or
+* u7 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and
+* u8 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or
+* u9 net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and
+* u16 net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and
+* u24 net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or
+* u33 net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or
+* u23 net-_u16-pad2_ net-_u23-pad2_ d_inverter
+* u38 net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor
+* u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter
+* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and
+* u26 net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or
+* u34 net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or
+* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter
+* u39 net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor
+* u44 net-_u39-pad3_ net-_u1-pad10_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and
+* u28 net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or
+* u35 net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or
+* u27 net-_u18-pad2_ net-_u27-pad2_ d_inverter
+* u40 net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor
+* u45 net-_u40-pad3_ net-_u1-pad11_ d_inverter
+* u31 net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or
+* u21 net-_u10-pad1_ net-_u21-pad2_ d_inverter
+* u37 net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor
+* u43 net-_u37-pad3_ net-_u1-pad12_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u32 net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and
+* u41 net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and
+x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and
+x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and
+x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2
+a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3
+a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4
+a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5
+a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6
+a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7
+a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8
+a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9
+a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24
+a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33
+a12 net-_u16-pad2_ net-_u23-pad2_ u23
+a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38
+a14 net-_u38-pad3_ net-_u1-pad13_ u42
+a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26
+a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34
+a18 net-_u17-pad2_ net-_u25-pad2_ u25
+a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39
+a20 net-_u39-pad3_ net-_u1-pad10_ u44
+a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18
+a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28
+a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35
+a24 net-_u18-pad2_ net-_u27-pad2_ u27
+a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40
+a26 net-_u40-pad3_ net-_u1-pad11_ u45
+a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31
+a28 net-_u10-pad1_ net-_u21-pad2_ u21
+a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37
+a30 net-_u37-pad3_ net-_u1-pad12_ u43
+a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32
+a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro
new file mode 100644
index 00000000..2d0c38b5
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro
@@ -0,0 +1,58 @@
+update=03/28/19 23:02:17
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_User
+LibName25=eSim_Subckt
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch
new file mode 100644
index 00000000..d3507ac7
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch
@@ -0,0 +1,945 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:4_bit_FA-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C963B95
+P 3050 3050
+F 0 "U2" H 3050 3050 60 0000 C CNN
+F 1 "d_or" H 3050 3150 60 0000 C CNN
+F 2 "" H 3050 3050 60 0000 C CNN
+F 3 "" H 3050 3050 60 0000 C CNN
+ 1 3050 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C963C4C
+P 3050 3450
+F 0 "U3" H 3050 3450 60 0000 C CNN
+F 1 "d_and" H 3100 3550 60 0000 C CNN
+F 2 "" H 3050 3450 60 0000 C CNN
+F 3 "" H 3050 3450 60 0000 C CNN
+ 1 3050 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C963CD9
+P 3050 4000
+F 0 "U4" H 3050 4000 60 0000 C CNN
+F 1 "d_or" H 3050 4100 60 0000 C CNN
+F 2 "" H 3050 4000 60 0000 C CNN
+F 3 "" H 3050 4000 60 0000 C CNN
+ 1 3050 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 5C963CDF
+P 3050 4400
+F 0 "U5" H 3050 4400 60 0000 C CNN
+F 1 "d_and" H 3100 4500 60 0000 C CNN
+F 2 "" H 3050 4400 60 0000 C CNN
+F 3 "" H 3050 4400 60 0000 C CNN
+ 1 3050 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U6
+U 1 1 5C963D79
+P 3050 4850
+F 0 "U6" H 3050 4850 60 0000 C CNN
+F 1 "d_or" H 3050 4950 60 0000 C CNN
+F 2 "" H 3050 4850 60 0000 C CNN
+F 3 "" H 3050 4850 60 0000 C CNN
+ 1 3050 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U7
+U 1 1 5C963D7F
+P 3050 5250
+F 0 "U7" H 3050 5250 60 0000 C CNN
+F 1 "d_and" H 3100 5350 60 0000 C CNN
+F 2 "" H 3050 5250 60 0000 C CNN
+F 3 "" H 3050 5250 60 0000 C CNN
+ 1 3050 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U8
+U 1 1 5C963D85
+P 3050 5800
+F 0 "U8" H 3050 5800 60 0000 C CNN
+F 1 "d_or" H 3050 5900 60 0000 C CNN
+F 2 "" H 3050 5800 60 0000 C CNN
+F 3 "" H 3050 5800 60 0000 C CNN
+ 1 3050 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U9
+U 1 1 5C963D8B
+P 3050 6200
+F 0 "U9" H 3050 6200 60 0000 C CNN
+F 1 "d_and" H 3100 6300 60 0000 C CNN
+F 2 "" H 3050 6200 60 0000 C CNN
+F 3 "" H 3050 6200 60 0000 C CNN
+ 1 3050 6200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U16
+U 1 1 5C963D9B
+P 5550 3200
+F 0 "U16" H 5550 3200 60 0000 C CNN
+F 1 "d_and" H 5600 3300 60 0000 C CNN
+F 2 "" H 5550 3200 60 0000 C CNN
+F 3 "" H 5550 3200 60 0000 C CNN
+ 1 5550 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U24
+U 1 1 5C963DFB
+P 6450 3400
+F 0 "U24" H 6450 3400 60 0000 C CNN
+F 1 "d_or" H 6450 3500 60 0000 C CNN
+F 2 "" H 6450 3400 60 0000 C CNN
+F 3 "" H 6450 3400 60 0000 C CNN
+ 1 6450 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U33
+U 1 1 5C963F8F
+P 7800 3450
+F 0 "U33" H 7800 3450 60 0000 C CNN
+F 1 "d_or" H 7800 3550 60 0000 C CNN
+F 2 "" H 7800 3450 60 0000 C CNN
+F 3 "" H 7800 3450 60 0000 C CNN
+ 1 7800 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U23
+U 1 1 5C963FFF
+P 6450 2950
+F 0 "U23" H 6450 2850 60 0000 C CNN
+F 1 "d_inverter" H 6450 3100 60 0000 C CNN
+F 2 "" H 6500 2900 60 0000 C CNN
+F 3 "" H 6500 2900 60 0000 C CNN
+ 1 6450 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U38
+U 1 1 5C9640A4
+P 8900 3400
+F 0 "U38" H 8900 3400 60 0000 C CNN
+F 1 "d_xor" H 8950 3500 47 0000 C CNN
+F 2 "" H 8900 3400 60 0000 C CNN
+F 3 "" H 8900 3400 60 0000 C CNN
+ 1 8900 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U42
+U 1 1 5C96410A
+P 9750 3350
+F 0 "U42" H 9750 3250 60 0000 C CNN
+F 1 "d_inverter" H 9750 3500 60 0000 C CNN
+F 2 "" H 9800 3300 60 0000 C CNN
+F 3 "" H 9800 3300 60 0000 C CNN
+ 1 9750 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U17
+U 1 1 5C964222
+P 5550 4150
+F 0 "U17" H 5550 4150 60 0000 C CNN
+F 1 "d_and" H 5600 4250 60 0000 C CNN
+F 2 "" H 5550 4150 60 0000 C CNN
+F 3 "" H 5550 4150 60 0000 C CNN
+ 1 5550 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U26
+U 1 1 5C964228
+P 6450 4350
+F 0 "U26" H 6450 4350 60 0000 C CNN
+F 1 "d_or" H 6450 4450 60 0000 C CNN
+F 2 "" H 6450 4350 60 0000 C CNN
+F 3 "" H 6450 4350 60 0000 C CNN
+ 1 6450 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U34
+U 1 1 5C96422E
+P 7800 4400
+F 0 "U34" H 7800 4400 60 0000 C CNN
+F 1 "d_or" H 7800 4500 60 0000 C CNN
+F 2 "" H 7800 4400 60 0000 C CNN
+F 3 "" H 7800 4400 60 0000 C CNN
+ 1 7800 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U25
+U 1 1 5C964234
+P 6450 3900
+F 0 "U25" H 6450 3800 60 0000 C CNN
+F 1 "d_inverter" H 6450 4050 60 0000 C CNN
+F 2 "" H 6500 3850 60 0000 C CNN
+F 3 "" H 6500 3850 60 0000 C CNN
+ 1 6450 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U39
+U 1 1 5C96423A
+P 8900 4350
+F 0 "U39" H 8900 4350 60 0000 C CNN
+F 1 "d_xor" H 8950 4450 47 0000 C CNN
+F 2 "" H 8900 4350 60 0000 C CNN
+F 3 "" H 8900 4350 60 0000 C CNN
+ 1 8900 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U44
+U 1 1 5C964240
+P 9800 4300
+F 0 "U44" H 9800 4200 60 0000 C CNN
+F 1 "d_inverter" H 9800 4450 60 0000 C CNN
+F 2 "" H 9850 4250 60 0000 C CNN
+F 3 "" H 9850 4250 60 0000 C CNN
+ 1 9800 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U18
+U 1 1 5C964304
+P 5600 4950
+F 0 "U18" H 5600 4950 60 0000 C CNN
+F 1 "d_and" H 5650 5050 60 0000 C CNN
+F 2 "" H 5600 4950 60 0000 C CNN
+F 3 "" H 5600 4950 60 0000 C CNN
+ 1 5600 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U28
+U 1 1 5C96430A
+P 6500 5150
+F 0 "U28" H 6500 5150 60 0000 C CNN
+F 1 "d_or" H 6500 5250 60 0000 C CNN
+F 2 "" H 6500 5150 60 0000 C CNN
+F 3 "" H 6500 5150 60 0000 C CNN
+ 1 6500 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U35
+U 1 1 5C964310
+P 7850 5200
+F 0 "U35" H 7850 5200 60 0000 C CNN
+F 1 "d_or" H 7850 5300 60 0000 C CNN
+F 2 "" H 7850 5200 60 0000 C CNN
+F 3 "" H 7850 5200 60 0000 C CNN
+ 1 7850 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U27
+U 1 1 5C964316
+P 6500 4700
+F 0 "U27" H 6500 4600 60 0000 C CNN
+F 1 "d_inverter" H 6500 4850 60 0000 C CNN
+F 2 "" H 6550 4650 60 0000 C CNN
+F 3 "" H 6550 4650 60 0000 C CNN
+ 1 6500 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U40
+U 1 1 5C96431C
+P 8950 5150
+F 0 "U40" H 8950 5150 60 0000 C CNN
+F 1 "d_xor" H 9000 5250 47 0000 C CNN
+F 2 "" H 8950 5150 60 0000 C CNN
+F 3 "" H 8950 5150 60 0000 C CNN
+ 1 8950 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U45
+U 1 1 5C964322
+P 9850 5100
+F 0 "U45" H 9850 5000 60 0000 C CNN
+F 1 "d_inverter" H 9850 5250 60 0000 C CNN
+F 2 "" H 9900 5050 60 0000 C CNN
+F 3 "" H 9900 5050 60 0000 C CNN
+ 1 9850 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U31
+U 1 1 5C964476
+P 7750 6200
+F 0 "U31" H 7750 6200 60 0000 C CNN
+F 1 "d_or" H 7750 6300 60 0000 C CNN
+F 2 "" H 7750 6200 60 0000 C CNN
+F 3 "" H 7750 6200 60 0000 C CNN
+ 1 7750 6200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U21
+U 1 1 5C96447C
+P 6400 5700
+F 0 "U21" H 6400 5600 60 0000 C CNN
+F 1 "d_inverter" H 6400 5850 60 0000 C CNN
+F 2 "" H 6450 5650 60 0000 C CNN
+F 3 "" H 6450 5650 60 0000 C CNN
+ 1 6400 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U37
+U 1 1 5C964482
+P 8850 6150
+F 0 "U37" H 8850 6150 60 0000 C CNN
+F 1 "d_xor" H 8900 6250 47 0000 C CNN
+F 2 "" H 8850 6150 60 0000 C CNN
+F 3 "" H 8850 6150 60 0000 C CNN
+ 1 8850 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U43
+U 1 1 5C964488
+P 9750 6100
+F 0 "U43" H 9750 6000 60 0000 C CNN
+F 1 "d_inverter" H 9750 6250 60 0000 C CNN
+F 2 "" H 9800 6050 60 0000 C CNN
+F 3 "" H 9800 6050 60 0000 C CNN
+ 1 9750 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U10
+U 1 1 5C966120
+P 5450 1650
+F 0 "U10" H 5450 1650 60 0000 C CNN
+F 1 "d_and" H 5500 1750 60 0000 C CNN
+F 2 "" H 5450 1650 60 0000 C CNN
+F 3 "" H 5450 1650 60 0000 C CNN
+ 1 5450 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U32
+U 1 1 5C968A9C
+P 7800 1150
+F 0 "U32" H 7800 1150 60 0000 C CNN
+F 1 "d_and" H 7850 1250 60 0000 C CNN
+F 2 "" H 7800 1150 60 0000 C CNN
+F 3 "" H 7800 1150 60 0000 C CNN
+ 1 7800 1150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U41
+U 1 1 5C968DBD
+P 9400 1500
+F 0 "U41" H 9400 1500 60 0000 C CNN
+F 1 "d_or" H 9400 1600 60 0000 C CNN
+F 2 "" H 9400 1500 60 0000 C CNN
+F 3 "" H 9400 1500 60 0000 C CNN
+ 1 9400 1500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9450 3350 9350 3350
+Wire Wire Line
+ 6750 2950 7350 2950
+Wire Wire Line
+ 7350 2950 7350 3350
+Wire Wire Line
+ 6000 3150 6000 3300
+Wire Wire Line
+ 9500 4300 9350 4300
+Wire Wire Line
+ 9550 5100 9400 5100
+Wire Wire Line
+ 9450 6100 9300 6100
+Wire Wire Line
+ 7350 4300 7350 3900
+Wire Wire Line
+ 7350 3900 6750 3900
+Wire Wire Line
+ 7400 5100 7400 4700
+Wire Wire Line
+ 7400 4700 6800 4700
+Wire Wire Line
+ 7300 6100 7300 5700
+Wire Wire Line
+ 7300 5700 6700 5700
+Wire Wire Line
+ 6050 4900 6050 5050
+Wire Wire Line
+ 6000 4100 6000 4250
+Wire Wire Line
+ 8250 3400 8450 3400
+Wire Wire Line
+ 8250 4350 8450 4350
+Wire Wire Line
+ 8200 6150 8400 6150
+Wire Wire Line
+ 8500 5150 8300 5150
+Wire Wire Line
+ 8450 2700 8450 3300
+Wire Wire Line
+ 3400 2700 8450 2700
+Wire Wire Line
+ 4950 2700 4950 3100
+Wire Wire Line
+ 4950 3100 5100 3100
+Wire Wire Line
+ 3500 2950 6150 2950
+Wire Wire Line
+ 3500 2950 3500 3000
+Wire Wire Line
+ 5100 3200 4850 3200
+Wire Wire Line
+ 4850 3200 4850 2950
+Connection ~ 4850 2950
+Wire Wire Line
+ 3500 3400 6000 3400
+Wire Wire Line
+ 5850 3400 5850 3500
+Wire Wire Line
+ 5850 3500 7350 3500
+Wire Wire Line
+ 7350 3500 7350 3450
+Connection ~ 5850 3400
+Wire Wire Line
+ 5100 4050 5000 4050
+Wire Wire Line
+ 5000 4050 5000 3700
+Wire Wire Line
+ 5000 3700 8400 3700
+Wire Wire Line
+ 8400 3700 8400 4250
+Wire Wire Line
+ 8400 4250 8450 4250
+Wire Wire Line
+ 6900 3350 6900 3700
+Connection ~ 6900 3700
+Wire Wire Line
+ 3500 3900 6150 3900
+Wire Wire Line
+ 3500 3900 3500 3950
+Wire Wire Line
+ 5100 4150 4950 4150
+Wire Wire Line
+ 4950 4150 4950 3900
+Connection ~ 4950 3900
+Wire Wire Line
+ 3500 4350 6000 4350
+Wire Wire Line
+ 7350 4400 7350 4450
+Wire Wire Line
+ 7350 4450 5850 4450
+Wire Wire Line
+ 5850 4450 5850 4350
+Connection ~ 5850 4350
+Wire Wire Line
+ 8500 5050 8400 5050
+Wire Wire Line
+ 8400 5050 8400 4500
+Wire Wire Line
+ 8400 4500 5050 4500
+Wire Wire Line
+ 5050 4500 5050 4850
+Wire Wire Line
+ 5050 4850 5150 4850
+Wire Wire Line
+ 6900 4300 7000 4300
+Wire Wire Line
+ 7000 4300 7000 4500
+Connection ~ 7000 4500
+Wire Wire Line
+ 3500 4700 6200 4700
+Wire Wire Line
+ 3500 4700 3500 4800
+Wire Wire Line
+ 5150 4950 4950 4950
+Wire Wire Line
+ 4950 4950 4950 4700
+Connection ~ 4950 4700
+Wire Wire Line
+ 3500 5150 6050 5150
+Wire Wire Line
+ 3500 5150 3500 5200
+Wire Wire Line
+ 7400 5200 7400 5250
+Wire Wire Line
+ 7400 5250 5900 5250
+Wire Wire Line
+ 5900 5250 5900 5150
+Connection ~ 5900 5150
+Wire Wire Line
+ 3500 5700 6100 5700
+Wire Wire Line
+ 3500 5700 3500 5750
+Wire Wire Line
+ 3500 6150 7100 6150
+Wire Wire Line
+ 8250 5500 8250 6050
+Wire Wire Line
+ 8250 6050 8400 6050
+Wire Wire Line
+ 7100 6150 7100 6200
+Wire Wire Line
+ 7100 6200 7300 6200
+Wire Wire Line
+ 8250 5500 7050 5500
+Wire Wire Line
+ 7050 5500 7050 5100
+Wire Wire Line
+ 7050 5100 6950 5100
+Wire Wire Line
+ 2000 2950 2600 2950
+Wire Wire Line
+ 2000 3450 2600 3450
+Wire Wire Line
+ 2600 3050 2350 3050
+Wire Wire Line
+ 2350 3050 2350 3450
+Connection ~ 2350 3450
+Wire Wire Line
+ 2600 3350 2500 3350
+Wire Wire Line
+ 2500 3350 2500 2950
+Connection ~ 2500 2950
+Wire Wire Line
+ 2000 3900 2600 3900
+Wire Wire Line
+ 2000 4400 2600 4400
+Wire Wire Line
+ 2600 4300 2450 4300
+Wire Wire Line
+ 2450 4300 2450 3900
+Connection ~ 2450 3900
+Wire Wire Line
+ 2600 4000 2350 4000
+Wire Wire Line
+ 2350 4000 2350 4400
+Connection ~ 2350 4400
+Wire Wire Line
+ 2000 4750 2600 4750
+Wire Wire Line
+ 2000 5250 2600 5250
+Wire Wire Line
+ 2600 4850 2350 4850
+Wire Wire Line
+ 2350 4850 2350 5250
+Connection ~ 2350 5250
+Wire Wire Line
+ 2600 5150 2450 5150
+Wire Wire Line
+ 2450 5150 2450 4750
+Connection ~ 2450 4750
+Wire Wire Line
+ 2050 5700 2600 5700
+Wire Wire Line
+ 2100 6200 2600 6200
+Wire Wire Line
+ 2600 6100 2450 6100
+Wire Wire Line
+ 2450 6100 2450 5700
+Connection ~ 2450 5700
+Wire Wire Line
+ 2600 5800 2500 5800
+Wire Wire Line
+ 2500 5800 2500 6200
+Connection ~ 2500 6200
+Wire Wire Line
+ 4600 3400 4600 2500
+Wire Wire Line
+ 4600 2500 5450 2500
+Connection ~ 4600 3400
+Wire Wire Line
+ 4400 2400 5450 2400
+Wire Wire Line
+ 4400 1200 4400 3900
+Wire Wire Line
+ 4500 2950 4500 1300
+Wire Wire Line
+ 4500 1300 5450 1300
+Connection ~ 4500 2950
+Wire Wire Line
+ 4100 2300 5450 2300
+Wire Wire Line
+ 3800 2200 5450 2200
+Wire Wire Line
+ 3800 1000 3800 5700
+Connection ~ 3800 5700
+Wire Wire Line
+ 5950 2100 4300 2100
+Wire Wire Line
+ 4300 2100 4300 4350
+Connection ~ 4300 4350
+Connection ~ 4400 3900
+Wire Wire Line
+ 4100 2300 4100 4700
+Connection ~ 4100 4700
+Wire Wire Line
+ 4100 2000 5950 2000
+Wire Wire Line
+ 4100 1100 4100 2350
+Connection ~ 4100 2350
+Wire Wire Line
+ 3800 1900 5950 1900
+Connection ~ 3800 2200
+Wire Wire Line
+ 5000 1550 3800 1550
+Connection ~ 3800 1900
+Wire Wire Line
+ 5000 1650 3950 1650
+Wire Wire Line
+ 3950 1650 3950 5150
+Connection ~ 3950 5150
+Wire Wire Line
+ 4400 1200 5450 1200
+Connection ~ 4400 2400
+Wire Wire Line
+ 4100 1100 5450 1100
+Connection ~ 4100 2000
+Wire Wire Line
+ 3800 1000 5450 1000
+Connection ~ 3800 1550
+Wire Wire Line
+ 5900 1600 7550 1600
+Wire Wire Line
+ 7150 900 7150 1500
+Wire Wire Line
+ 7150 900 3700 900
+Wire Wire Line
+ 3700 900 3700 6150
+Connection ~ 3700 6150
+Wire Wire Line
+ 6350 1150 7350 1150
+Wire Wire Line
+ 7350 750 7350 1050
+Wire Wire Line
+ 2000 750 7350 750
+Wire Wire Line
+ 8950 1500 8950 1750
+Wire Wire Line
+ 8950 1400 8950 1100
+Wire Wire Line
+ 8950 1100 8250 1100
+Wire Wire Line
+ 9850 1450 10500 1450
+Wire Wire Line
+ 10050 3350 10450 3350
+Wire Wire Line
+ 3400 750 3400 2700
+Connection ~ 4950 2700
+Connection ~ 3400 750
+Wire Wire Line
+ 10100 4300 10400 4300
+Wire Wire Line
+ 10150 5100 10400 5100
+Wire Wire Line
+ 10050 6100 10400 6100
+$Comp
+L PORT U1
+U 1 1 5C969A23
+P 1750 750
+F 0 "U1" H 1800 850 30 0000 C CNN
+F 1 "PORT" H 1750 750 30 0000 C CNN
+F 2 "" H 1750 750 60 0000 C CNN
+F 3 "" H 1750 750 60 0000 C CNN
+ 1 1750 750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C969AF9
+P 1750 2950
+F 0 "U1" H 1800 3050 30 0000 C CNN
+F 1 "PORT" H 1750 2950 30 0000 C CNN
+F 2 "" H 1750 2950 60 0000 C CNN
+F 3 "" H 1750 2950 60 0000 C CNN
+ 2 1750 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C969BCD
+P 1750 3450
+F 0 "U1" H 1800 3550 30 0000 C CNN
+F 1 "PORT" H 1750 3450 30 0000 C CNN
+F 2 "" H 1750 3450 60 0000 C CNN
+F 3 "" H 1750 3450 60 0000 C CNN
+ 3 1750 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C969C7A
+P 1750 3900
+F 0 "U1" H 1800 4000 30 0000 C CNN
+F 1 "PORT" H 1750 3900 30 0000 C CNN
+F 2 "" H 1750 3900 60 0000 C CNN
+F 3 "" H 1750 3900 60 0000 C CNN
+ 4 1750 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C969D28
+P 1750 4400
+F 0 "U1" H 1800 4500 30 0000 C CNN
+F 1 "PORT" H 1750 4400 30 0000 C CNN
+F 2 "" H 1750 4400 60 0000 C CNN
+F 3 "" H 1750 4400 60 0000 C CNN
+ 5 1750 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C969DDF
+P 1750 4750
+F 0 "U1" H 1800 4850 30 0000 C CNN
+F 1 "PORT" H 1750 4750 30 0000 C CNN
+F 2 "" H 1750 4750 60 0000 C CNN
+F 3 "" H 1750 4750 60 0000 C CNN
+ 6 1750 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5C969E93
+P 1750 5250
+F 0 "U1" H 1800 5350 30 0000 C CNN
+F 1 "PORT" H 1750 5250 30 0000 C CNN
+F 2 "" H 1750 5250 60 0000 C CNN
+F 3 "" H 1750 5250 60 0000 C CNN
+ 7 1750 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5C969F4E
+P 1800 5700
+F 0 "U1" H 1850 5800 30 0000 C CNN
+F 1 "PORT" H 1800 5700 30 0000 C CNN
+F 2 "" H 1800 5700 60 0000 C CNN
+F 3 "" H 1800 5700 60 0000 C CNN
+ 8 1800 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5C96A00E
+P 1850 6200
+F 0 "U1" H 1900 6300 30 0000 C CNN
+F 1 "PORT" H 1850 6200 30 0000 C CNN
+F 2 "" H 1850 6200 60 0000 C CNN
+F 3 "" H 1850 6200 60 0000 C CNN
+ 9 1850 6200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5C96A0CF
+P 10750 1450
+F 0 "U1" H 10800 1550 30 0000 C CNN
+F 1 "PORT" H 10750 1450 30 0000 C CNN
+F 2 "" H 10750 1450 60 0000 C CNN
+F 3 "" H 10750 1450 60 0000 C CNN
+ 14 10750 1450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5C96A273
+P 10700 3350
+F 0 "U1" H 10750 3450 30 0000 C CNN
+F 1 "PORT" H 10700 3350 30 0000 C CNN
+F 2 "" H 10700 3350 60 0000 C CNN
+F 3 "" H 10700 3350 60 0000 C CNN
+ 13 10700 3350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5C96A464
+P 10650 4300
+F 0 "U1" H 10700 4400 30 0000 C CNN
+F 1 "PORT" H 10650 4300 30 0000 C CNN
+F 2 "" H 10650 4300 60 0000 C CNN
+F 3 "" H 10650 4300 60 0000 C CNN
+ 10 10650 4300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5C96A53A
+P 10650 5100
+F 0 "U1" H 10700 5200 30 0000 C CNN
+F 1 "PORT" H 10650 5100 30 0000 C CNN
+F 2 "" H 10650 5100 60 0000 C CNN
+F 3 "" H 10650 5100 60 0000 C CNN
+ 11 10650 5100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5C96A619
+P 10650 6100
+F 0 "U1" H 10700 6200 30 0000 C CNN
+F 1 "PORT" H 10650 6100 30 0000 C CNN
+F 2 "" H 10650 6100 60 0000 C CNN
+F 3 "" H 10650 6100 60 0000 C CNN
+ 12 10650 6100
+ -1 0 0 1
+$EndComp
+Text Notes 10200 3350 0 60 ~ 12
+S0
+Text Notes 10200 4300 0 60 ~ 12
+S1\n
+Text Notes 10200 5100 0 60 ~ 12
+S2
+Text Notes 10150 6100 0 60 ~ 12
+S3
+Text Notes 10050 1450 0 60 ~ 12
+Cout\n
+Text Notes 2250 750 0 60 ~ 12
+Cin\n
+Text Notes 2050 2950 0 60 ~ 12
+A0\n
+Text Notes 2050 3450 0 60 ~ 12
+B0\n
+Text Notes 2050 3900 0 60 ~ 12
+A1
+Text Notes 2050 4400 0 60 ~ 12
+B1
+Text Notes 2050 4750 0 60 ~ 12
+A2
+Text Notes 2050 5250 0 60 ~ 12
+B2
+Text Notes 2100 5700 0 60 ~ 12
+A3
+Text Notes 2150 6200 0 60 ~ 12
+B3
+$Comp
+L 4_and X1
+U 1 1 5C9D037C
+P 4400 2250
+F 0 "X1" H 5900 3300 60 0000 C CNN
+F 1 "4_and" H 5950 3450 60 0000 C CNN
+F 2 "" H 4400 2250 60 0000 C CNN
+F 3 "" H 4400 2250 60 0000 C CNN
+ 1 4400 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X4
+U 1 1 5C9D0A45
+P 5500 2400
+F 0 "X4" H 6400 2700 60 0000 C CNN
+F 1 "3_and" H 6450 2900 60 0000 C CNN
+F 2 "" H 5500 2400 60 0000 C CNN
+F 3 "" H 5500 2400 60 0000 C CNN
+ 1 5500 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X2
+U 1 1 5C9D0E20
+P 4400 3450
+F 0 "X2" H 5900 4500 60 0000 C CNN
+F 1 "4_and" H 5950 4650 60 0000 C CNN
+F 2 "" H 4400 3450 60 0000 C CNN
+F 3 "" H 4400 3450 60 0000 C CNN
+ 1 4400 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X3
+U 1 1 5C9D1513
+P 4450 4900
+F 0 "X3" H 8350 7950 60 0000 C CNN
+F 1 "4_OR" H 8350 8150 60 0000 C CNN
+F 2 "" H 4450 4900 60 0000 C CNN
+F 3 "" H 4450 4900 60 0000 C CNN
+ 1 4450 4900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8950 1750 8750 1750
+Wire Wire Line
+ 7150 1500 7850 1500
+Wire Wire Line
+ 7850 1500 7850 1600
+Wire Wire Line
+ 7550 1600 7550 1700
+Wire Wire Line
+ 7550 1700 7850 1700
+Wire Wire Line
+ 6800 2000 6800 1800
+Wire Wire Line
+ 6800 1800 7850 1800
+Wire Wire Line
+ 6350 2350 7850 2350
+Wire Wire Line
+ 7850 2350 7850 1900
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub
new file mode 100644
index 00000000..2f2bc4ef
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub
@@ -0,0 +1,145 @@
+* Subcircuit 4_bit_FA
+.subckt 4_bit_FA net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
+* c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir
+.include 4_and.sub
+.include 3_and.sub
+.include 4_OR.sub
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or
+* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and
+* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or
+* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and
+* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or
+* u7 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and
+* u8 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or
+* u9 net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and
+* u16 net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and
+* u24 net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or
+* u33 net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or
+* u23 net-_u16-pad2_ net-_u23-pad2_ d_inverter
+* u38 net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor
+* u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter
+* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and
+* u26 net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or
+* u34 net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or
+* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter
+* u39 net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor
+* u44 net-_u39-pad3_ net-_u1-pad10_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and
+* u28 net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or
+* u35 net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or
+* u27 net-_u18-pad2_ net-_u27-pad2_ d_inverter
+* u40 net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor
+* u45 net-_u40-pad3_ net-_u1-pad11_ d_inverter
+* u31 net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or
+* u21 net-_u10-pad1_ net-_u21-pad2_ d_inverter
+* u37 net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor
+* u43 net-_u37-pad3_ net-_u1-pad12_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u32 net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and
+* u41 net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or
+x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and
+x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and
+x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and
+x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2
+a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3
+a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4
+a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5
+a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6
+a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7
+a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8
+a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9
+a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24
+a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33
+a12 net-_u16-pad2_ net-_u23-pad2_ u23
+a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38
+a14 net-_u38-pad3_ net-_u1-pad13_ u42
+a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26
+a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34
+a18 net-_u17-pad2_ net-_u25-pad2_ u25
+a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39
+a20 net-_u39-pad3_ net-_u1-pad10_ u44
+a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18
+a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28
+a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35
+a24 net-_u18-pad2_ net-_u27-pad2_ u27
+a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40
+a26 net-_u40-pad3_ net-_u1-pad11_ u45
+a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31
+a28 net-_u10-pad1_ net-_u21-pad2_ u21
+a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37
+a30 net-_u37-pad3_ net-_u1-pad12_ u43
+a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32
+a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_bit_FA \ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml
new file mode 100644
index 00000000..49a53e5c
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_or<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u9><u16 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u16><u24 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u24><u33 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u33><u23 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u23><u38 name="type">d_xor<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u38><u42 name="type">d_inverter<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u42><u17 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u17><u26 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u26><u34 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u34><u25 name="type">d_inverter<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u25><u39 name="type">d_xor<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u39><u44 name="type">d_inverter<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u44><u18 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u18><u28 name="type">d_or<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u28><u35 name="type">d_or<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u35><u27 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u27><u40 name="type">d_xor<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u40><u45 name="type">d_inverter<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u45><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u21 name="type">d_inverter<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u21><u37 name="type">d_xor<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u37><u43 name="type">d_inverter<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u43><u14 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u14><u15 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_and<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u13><u20 name="type">d_and<field115 name="Enter Fall Delay (default=1.0e-9)" /><field116 name="Enter Input Load (default=1.0e-12)" /><field117 name="Enter Rise Delay (default=1.0e-9)" /></u20><u29 name="type">d_or<field118 name="Enter Fall Delay (default=1.0e-9)" /><field119 name="Enter Input Load (default=1.0e-12)" /><field120 name="Enter Rise Delay (default=1.0e-9)" /></u29><u36 name="type">d_or<field121 name="Enter Fall Delay (default=1.0e-9)" /><field122 name="Enter Input Load (default=1.0e-12)" /><field123 name="Enter Rise Delay (default=1.0e-9)" /></u36><u30 name="type">d_or<field124 name="Enter Fall Delay (default=1.0e-9)" /><field125 name="Enter Input Load (default=1.0e-12)" /><field126 name="Enter Rise Delay (default=1.0e-9)" /></u30><u32 name="type">d_and<field127 name="Enter Fall Delay (default=1.0e-9)" /><field128 name="Enter Input Load (default=1.0e-12)" /><field129 name="Enter Rise Delay (default=1.0e-9)" /></u32><u41 name="type">d_or<field130 name="Enter Fall Delay (default=1.0e-9)" /><field131 name="Enter Input Load (default=1.0e-12)" /><field132 name="Enter Rise Delay (default=1.0e-9)" /></u41></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x1><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/analysis b/src/SubcircuitLibrary/4_bit_FA/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/4_bit_FA/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file