diff options
Diffstat (limited to 'src/SubcircuitLibrary/4_and')
| -rw-r--r-- | src/SubcircuitLibrary/4_and/3_and-cache.lib | 61 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/3_and.cir | 13 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/3_and.cir.out | 20 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/3_and.pro | 44 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/3_and.sch | 130 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/3_and.sub | 14 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/4_and-cache.lib | 79 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/4_and-rescue.lib | 22 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/4_and.cir | 13 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/4_and.cir.out | 18 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/4_and.pro | 58 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/4_and.sch | 151 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/4_and.sub | 12 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/4_and/analysis | 1 |
16 files changed, 638 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/4_and/3_and-cache.lib b/src/SubcircuitLibrary/4_and/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_and/3_and.cir b/src/SubcircuitLibrary/4_and/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/4_and/3_and.cir.out b/src/SubcircuitLibrary/4_and/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4_and/3_and.pro b/src/SubcircuitLibrary/4_and/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4_and/3_and.sch b/src/SubcircuitLibrary/4_and/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_and/3_and.sub b/src/SubcircuitLibrary/4_and/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/4_and-cache.lib b/src/SubcircuitLibrary/4_and/4_and-cache.lib new file mode 100644 index 00000000..cb84d8f2 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_and/4_and-rescue.lib b/src/SubcircuitLibrary/4_and/4_and-rescue.lib new file mode 100644 index 00000000..6b2c17f7 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_and/4_and.cir b/src/SubcircuitLibrary/4_and/4_and.cir new file mode 100644 index 00000000..35e46097 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/4_and/4_and.cir.out b/src/SubcircuitLibrary/4_and/4_and.cir.out new file mode 100644 index 00000000..6e35b18a --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4_and/4_and.pro b/src/SubcircuitLibrary/4_and/4_and.pro new file mode 100644 index 00000000..814ad76a --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.pro @@ -0,0 +1,58 @@ +update=06/01/19 15:08:42
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_Subckt
+LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/4_and/4_and.sch b/src/SubcircuitLibrary/4_and/4_and.sch new file mode 100644 index 00000000..2d8296d4 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_and/4_and.sub b/src/SubcircuitLibrary/4_and/4_and.sub new file mode 100644 index 00000000..bf20b628 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml b/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/analysis b/src/SubcircuitLibrary/4_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |