15 files changed, 0 insertions, 781 deletions
diff --git a/src/SubcircuitLibrary/4023/3_and-cache.lib b/src/SubcircuitLibrary/4023/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/4023/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4023/3_and.cir b/src/SubcircuitLibrary/4023/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/4023/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4023/3_and.cir.out b/src/SubcircuitLibrary/4023/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/4023/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4023/3_and.pro b/src/SubcircuitLibrary/4023/3_and.pro
deleted file mode 100644
index 76df4655..00000000
--- a/src/SubcircuitLibrary/4023/3_and.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4023/3_and.sch b/src/SubcircuitLibrary/4023/3_and.sch
deleted file mode 100644
index d6ac89f9..00000000
--- a/src/SubcircuitLibrary/4023/3_and.sch
+++ /dev/null
@@ -1,130 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4023/3_and.sub b/src/SubcircuitLibrary/4023/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/4023/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
-\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
-\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/4023-cache.lib b/src/SubcircuitLibrary/4023/4023-cache.lib
deleted file mode 100644
index c989d8c7..00000000
--- a/src/SubcircuitLibrary/4023/4023-cache.lib
+++ /dev/null
@@ -1,76 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 100 -50 60 H V C CNN
-F1 "3_and" 150 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
-P 2 0 1 0  -150 200  200 200 N
-P 3 0 1 0  -150 200  -150 -100  200 -100 N
-X in1 1 -350 150 200 R 50 50 1 1 I
-X in2 2 -350 50 200 R 50 50 1 1 I
-X in3 3 -350 -50 200 R 50 50 1 1 I
-X out 4 500 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4023/4023.cir b/src/SubcircuitLibrary/4023/4023.cir
deleted file mode 100644
index 6aad9b84..00000000
--- a/src/SubcircuitLibrary/4023/4023.cir
+++ /dev/null
@@ -1,17 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4023\4023.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 15:33:14
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X3  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and		
-U4  Net-_U4-Pad1_ Net-_U1-Pad10_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
-X2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
-U3  Net-_U3-Pad1_ Net-_U1-Pad6_ d_inverter		
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U2-Pad1_ 3_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad9_ d_inverter		
-
-.end
diff --git a/src/SubcircuitLibrary/4023/4023.cir.out b/src/SubcircuitLibrary/4023/4023.cir.out
deleted file mode 100644
index 7f48d16f..00000000
--- a/src/SubcircuitLibrary/4023/4023.cir.out
+++ /dev/null
@@ -1,28 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir
-
-.include 3_and.sub
-x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
-* u4  net-_u4-pad1_ net-_u1-pad10_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u3  net-_u3-pad1_ net-_u1-pad6_ d_inverter
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad9_ d_inverter
-a1 net-_u4-pad1_ net-_u1-pad10_ u4
-a2 net-_u3-pad1_ net-_u1-pad6_ u3
-a3 net-_u2-pad1_ net-_u1-pad9_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4023/4023.pro b/src/SubcircuitLibrary/4023/4023.pro
deleted file mode 100644
index 5a5ce355..00000000
--- a/src/SubcircuitLibrary/4023/4023.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:32:35
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4023/4023.sch b/src/SubcircuitLibrary/4023/4023.sch
deleted file mode 100644
index 57dd7868..00000000
--- a/src/SubcircuitLibrary/4023/4023.sch
+++ /dev/null
@@ -1,309 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X3
-U 1 1 5CF0FA82
-P 4800 2500
-F 0 "X3" H 4900 2450 60  0000 C CNN
-F 1 "3_and" H 4950 2650 60  0000 C CNN
-F 2 "" H 4800 2500 60  0000 C CNN
-F 3 "" H 4800 2500 60  0000 C CNN
-	1    4800 2500
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U4
-U 1 1 5CF0FB13
-P 6150 2450
-F 0 "U4" H 6150 2350 60  0000 C CNN
-F 1 "d_inverter" H 6150 2600 60  0000 C CNN
-F 2 "" H 6200 2400 60  0000 C CNN
-F 3 "" H 6200 2400 60  0000 C CNN
-	1    6150 2450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5CF0FB34
-P 3100 1950
-F 0 "U1" H 3150 2050 30  0000 C CNN
-F 1 "PORT" H 3100 1950 30  0000 C CNN
-F 2 "" H 3100 1950 60  0000 C CNN
-F 3 "" H 3100 1950 60  0000 C CNN
-	11   3100 1950
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5CF0FB90
-P 3100 2350
-F 0 "U1" H 3150 2450 30  0000 C CNN
-F 1 "PORT" H 3100 2350 30  0000 C CNN
-F 2 "" H 3100 2350 60  0000 C CNN
-F 3 "" H 3100 2350 60  0000 C CNN
-	12   3100 2350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5CF0FBB8
-P 3100 2750
-F 0 "U1" H 3150 2850 30  0000 C CNN
-F 1 "PORT" H 3100 2750 30  0000 C CNN
-F 2 "" H 3100 2750 60  0000 C CNN
-F 3 "" H 3100 2750 60  0000 C CNN
-	13   3100 2750
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CF0FBED
-P 7800 2450
-F 0 "U1" H 7850 2550 30  0000 C CNN
-F 1 "PORT" H 7800 2450 30  0000 C CNN
-F 2 "" H 7800 2450 60  0000 C CNN
-F 3 "" H 7800 2450 60  0000 C CNN
-	10   7800 2450
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	7550 2450 6450 2450
-Wire Wire Line
-	5850 2450 5300 2450
-Wire Wire Line
-	4450 2350 4450 1950
-Wire Wire Line
-	4450 1950 3350 1950
-Wire Wire Line
-	4450 2450 4100 2450
-Wire Wire Line
-	4100 2450 4100 2350
-Wire Wire Line
-	4100 2350 3350 2350
-Wire Wire Line
-	3350 2750 3950 2750
-Wire Wire Line
-	3950 2750 3950 2550
-Wire Wire Line
-	3950 2550 4450 2550
-$Comp
-L 3_and X2
-U 1 1 5CF0FF35
-P 4700 3800
-F 0 "X2" H 4800 3750 60  0000 C CNN
-F 1 "3_and" H 4850 3950 60  0000 C CNN
-F 2 "" H 4700 3800 60  0000 C CNN
-F 3 "" H 4700 3800 60  0000 C CNN
-	1    4700 3800
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U3
-U 1 1 5CF0FF3B
-P 6050 3750
-F 0 "U3" H 6050 3650 60  0000 C CNN
-F 1 "d_inverter" H 6050 3900 60  0000 C CNN
-F 2 "" H 6100 3700 60  0000 C CNN
-F 3 "" H 6100 3700 60  0000 C CNN
-	1    6050 3750
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CF0FF41
-P 3000 3250
-F 0 "U1" H 3050 3350 30  0000 C CNN
-F 1 "PORT" H 3000 3250 30  0000 C CNN
-F 2 "" H 3000 3250 60  0000 C CNN
-F 3 "" H 3000 3250 60  0000 C CNN
-	4    3000 3250
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5CF0FF47
-P 3000 3650
-F 0 "U1" H 3050 3750 30  0000 C CNN
-F 1 "PORT" H 3000 3650 30  0000 C CNN
-F 2 "" H 3000 3650 60  0000 C CNN
-F 3 "" H 3000 3650 60  0000 C CNN
-	5    3000 3650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CF0FF4D
-P 3000 4050
-F 0 "U1" H 3050 4150 30  0000 C CNN
-F 1 "PORT" H 3000 4050 30  0000 C CNN
-F 2 "" H 3000 4050 60  0000 C CNN
-F 3 "" H 3000 4050 60  0000 C CNN
-	3    3000 4050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5CF0FF53
-P 7700 3750
-F 0 "U1" H 7750 3850 30  0000 C CNN
-F 1 "PORT" H 7700 3750 30  0000 C CNN
-F 2 "" H 7700 3750 60  0000 C CNN
-F 3 "" H 7700 3750 60  0000 C CNN
-	6    7700 3750
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	7450 3750 6350 3750
-Wire Wire Line
-	5750 3750 5200 3750
-Wire Wire Line
-	4350 3650 4350 3250
-Wire Wire Line
-	4350 3250 3250 3250
-Wire Wire Line
-	4350 3750 4000 3750
-Wire Wire Line
-	4000 3750 4000 3650
-Wire Wire Line
-	4000 3650 3250 3650
-Wire Wire Line
-	3250 4050 3850 4050
-Wire Wire Line
-	3850 4050 3850 3850
-Wire Wire Line
-	3850 3850 4350 3850
-$Comp
-L 3_and X1
-U 1 1 5CF100B9
-P 4650 5100
-F 0 "X1" H 4750 5050 60  0000 C CNN
-F 1 "3_and" H 4800 5250 60  0000 C CNN
-F 2 "" H 4650 5100 60  0000 C CNN
-F 3 "" H 4650 5100 60  0000 C CNN
-	1    4650 5100
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U2
-U 1 1 5CF100BF
-P 6000 5050
-F 0 "U2" H 6000 4950 60  0000 C CNN
-F 1 "d_inverter" H 6000 5200 60  0000 C CNN
-F 2 "" H 6050 5000 60  0000 C CNN
-F 3 "" H 6050 5000 60  0000 C CNN
-	1    6000 5050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CF100C5
-P 2950 4550
-F 0 "U1" H 3000 4650 30  0000 C CNN
-F 1 "PORT" H 2950 4550 30  0000 C CNN
-F 2 "" H 2950 4550 60  0000 C CNN
-F 3 "" H 2950 4550 60  0000 C CNN
-	1    2950 4550
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CF100CB
-P 2950 4950
-F 0 "U1" H 3000 5050 30  0000 C CNN
-F 1 "PORT" H 2950 4950 30  0000 C CNN
-F 2 "" H 2950 4950 60  0000 C CNN
-F 3 "" H 2950 4950 60  0000 C CNN
-	2    2950 4950
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5CF100D1
-P 2950 5350
-F 0 "U1" H 3000 5450 30  0000 C CNN
-F 1 "PORT" H 2950 5350 30  0000 C CNN
-F 2 "" H 2950 5350 60  0000 C CNN
-F 3 "" H 2950 5350 60  0000 C CNN
-	8    2950 5350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5CF100D7
-P 7650 5050
-F 0 "U1" H 7700 5150 30  0000 C CNN
-F 1 "PORT" H 7650 5050 30  0000 C CNN
-F 2 "" H 7650 5050 60  0000 C CNN
-F 3 "" H 7650 5050 60  0000 C CNN
-	9    7650 5050
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	7400 5050 6300 5050
-Wire Wire Line
-	5700 5050 5150 5050
-Wire Wire Line
-	4300 4950 4300 4550
-Wire Wire Line
-	4300 4550 3200 4550
-Wire Wire Line
-	4300 5050 3950 5050
-Wire Wire Line
-	3950 5050 3950 4950
-Wire Wire Line
-	3950 4950 3200 4950
-Wire Wire Line
-	3200 5350 3800 5350
-Wire Wire Line
-	3800 5350 3800 5150
-Wire Wire Line
-	3800 5150 4300 5150
-$Comp
-L PORT U1
-U 7 1 5CF101BF
-P 9950 3350
-F 0 "U1" H 10000 3450 30  0000 C CNN
-F 1 "PORT" H 9950 3350 30  0000 C CNN
-F 2 "" H 9950 3350 60  0000 C CNN
-F 3 "" H 9950 3350 60  0000 C CNN
-	7    9950 3350
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5CF1025C
-P 9950 3900
-F 0 "U1" H 10000 4000 30  0000 C CNN
-F 1 "PORT" H 9950 3900 30  0000 C CNN
-F 2 "" H 9950 3900 60  0000 C CNN
-F 3 "" H 9950 3900 60  0000 C CNN
-	14   9950 3900
-	-1   0    0    1   
-$EndComp
-NoConn ~ 9700 3350
-NoConn ~ 9700 3900
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4023/4023.sub b/src/SubcircuitLibrary/4023/4023.sub
deleted file mode 100644
index b953da2e..00000000
--- a/src/SubcircuitLibrary/4023/4023.sub
+++ /dev/null
@@ -1,22 +0,0 @@
-* Subcircuit 4023
-.subckt 4023 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
-* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir
-.include 3_and.sub
-x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
-* u4  net-_u4-pad1_ net-_u1-pad10_ d_inverter
-x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u3  net-_u3-pad1_ net-_u1-pad6_ d_inverter
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad9_ d_inverter
-a1 net-_u4-pad1_ net-_u1-pad10_ u4
-a2 net-_u3-pad1_ net-_u1-pad6_ u3
-a3 net-_u2-pad1_ net-_u1-pad9_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4023
-\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/4023_Previous_Values.xml b/src/SubcircuitLibrary/4023/4023_Previous_Values.xml
deleted file mode 100644
index ad900de2..00000000
--- a/src/SubcircuitLibrary/4023/4023_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u4 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
-\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/analysis b/src/SubcircuitLibrary/4023/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4023/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
-\ No newline at end of file