diff options
Diffstat (limited to 'src/SubcircuitLibrary/4012/4012.cir.out')
-rw-r--r-- | src/SubcircuitLibrary/4012/4012.cir.out | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/src/SubcircuitLibrary/4012/4012.cir.out b/src/SubcircuitLibrary/4012/4012.cir.out deleted file mode 100644 index c43dda8c..00000000 --- a/src/SubcircuitLibrary/4012/4012.cir.out +++ /dev/null @@ -1,44 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir - -* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter -* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port -* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and -* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and -* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and -* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and -* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and -* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and -a1 net-_u6-pad3_ net-_u1-pad1_ u8 -a2 net-_u7-pad3_ net-_u1-pad13_ u9 -a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 -a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 -a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 -a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 -a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 -a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end |