diff options
Diffstat (limited to 'library')
66 files changed, 5371 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib b/library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.cir b/library/SubcircuitLibrary/74V1G14/74V1G14.cir new file mode 100644 index 00000000..58637c1a --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74V1G14\74V1G14.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 8/3/2022 1:17:12 AM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 /Vout /Inp Net-_M1-Pad3_ /GND mosfet_n +M2 Net-_M1-Pad3_ /Inp /GND /GND mosfet_n +M3 /Vcc /Inp Net-_M3-Pad3_ /Vcc mosfet_p +M4 Net-_M3-Pad3_ /Inp /Vout /Vcc mosfet_p +M5 /GND /Vout Net-_M3-Pad3_ /Vcc mosfet_p +M6 /Vcc /Vout Net-_M1-Pad3_ /GND mosfet_n +U1 ? /Inp /GND /Vout /Vcc PORT + +.end diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.cir.out b/library/SubcircuitLibrary/74V1G14/74V1G14.cir.out new file mode 100644 index 00000000..43a6987d --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.cir.out @@ -0,0 +1,20 @@ +* c:\fossee\esim\library\subcircuitlibrary\74v1g14\74v1g14.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 /vout /inp net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +m2 net-_m1-pad3_ /inp /gnd /gnd CMOSN W=25u L=0.25u M=1 +m3 /vcc /inp net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m4 net-_m3-pad3_ /inp /vout /vcc CMOSP W=25u L=0.25u M=1 +m5 /gnd /vout net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m6 /vcc /vout net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +* u1 ? /inp /gnd /vout /vcc port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.pro b/library/SubcircuitLibrary/74V1G14/74V1G14.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.sch b/library/SubcircuitLibrary/74V1G14/74V1G14.sch new file mode 100644 index 00000000..3cab975e --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.sch @@ -0,0 +1,278 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:74V1G14-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_n M1 +U 1 1 62E8D877 +P 3550 3950 +F 0 "M1" H 3550 3800 50 0000 R CNN +F 1 "mosfet_n" H 3650 3900 50 0000 R CNN +F 2 "" H 3850 3650 29 0000 C CNN +F 3 "" H 3650 3750 60 0000 C CNN + 1 3550 3950 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M2 +U 1 1 62E8D878 +P 3550 5300 +F 0 "M2" H 3550 5150 50 0000 R CNN +F 1 "mosfet_n" H 3650 5250 50 0000 R CNN +F 2 "" H 3850 5000 29 0000 C CNN +F 3 "" H 3650 5100 60 0000 C CNN + 1 3550 5300 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M3 +U 1 1 62E8D879 +P 3650 1600 +F 0 "M3" H 3600 1650 50 0000 R CNN +F 1 "mosfet_p" H 3700 1750 50 0000 R CNN +F 2 "" H 3900 1700 29 0000 C CNN +F 3 "" H 3700 1600 60 0000 C CNN + 1 3650 1600 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M4 +U 1 1 62E8D87A +P 3650 2650 +F 0 "M4" H 3600 2700 50 0000 R CNN +F 1 "mosfet_p" H 3700 2800 50 0000 R CNN +F 2 "" H 3900 2750 29 0000 C CNN +F 3 "" H 3700 2650 60 0000 C CNN + 1 3650 2650 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M5 +U 1 1 62E8D87B +P 7250 2100 +F 0 "M5" H 7200 2150 50 0000 R CNN +F 1 "mosfet_p" H 7300 2250 50 0000 R CNN +F 2 "" H 7500 2200 29 0000 C CNN +F 3 "" H 7300 2100 60 0000 C CNN + 1 7250 2100 + 0 1 -1 0 +$EndComp +$Comp +L mosfet_n M6 +U 1 1 62E8D87C +P 7450 4850 +F 0 "M6" H 7450 4700 50 0000 R CNN +F 1 "mosfet_n" H 7550 4800 50 0000 R CNN +F 2 "" H 7750 4550 29 0000 C CNN +F 3 "" H 7550 4650 60 0000 C CNN + 1 7450 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 3800 1800 3800 2450 +Wire Wire Line + 3800 2850 3800 3950 +Wire Wire Line + 3800 3950 3750 3950 +Wire Wire Line + 3750 4350 3750 5300 +Wire Wire Line + 7050 1950 3800 1950 +Connection ~ 3800 1950 +Wire Wire Line + 7100 1750 7100 1850 +Wire Wire Line + 3800 850 3800 1400 +Wire Wire Line + 3800 1300 4550 1300 +Wire Wire Line + 4550 1300 4550 2900 +Wire Wire Line + 4550 2900 3900 2900 +Wire Wire Line + 3900 2900 3900 2800 +Connection ~ 3800 1300 +Wire Wire Line + 3900 1750 7100 1750 +Connection ~ 4550 1750 +Wire Wire Line + 3750 5700 3750 6200 +Wire Wire Line + 3850 5650 3850 5850 +Wire Wire Line + 3850 5850 3750 5850 +Connection ~ 3750 5850 +Wire Wire Line + 3850 5700 4150 5700 +Wire Wire Line + 4150 5700 4150 4300 +Wire Wire Line + 4150 4300 3850 4300 +Connection ~ 3850 5700 +Wire Wire Line + 4150 5250 7100 5250 +Wire Wire Line + 7100 5250 7100 5150 +Connection ~ 4150 5250 +Wire Wire Line + 7050 5050 3750 5050 +Connection ~ 3750 5050 +Wire Wire Line + 7450 5050 9450 5050 +Wire Wire Line + 3800 3350 9200 3350 +Connection ~ 3800 3350 +Wire Wire Line + 2750 1600 2750 5500 +Wire Wire Line + 2750 5500 3450 5500 +Wire Wire Line + 3500 2650 3500 2550 +Wire Wire Line + 3500 2550 2750 2550 +Connection ~ 2750 2550 +Connection ~ 2750 4150 +Wire Wire Line + 2100 3300 2750 3300 +Connection ~ 2750 3300 +Wire Wire Line + 7450 1950 9700 1950 +Wire Wire Line + 9700 1950 9700 6050 +Wire Wire Line + 9700 6050 3750 6050 +Connection ~ 3750 6050 +Wire Wire Line + 3500 1600 2750 1600 +Wire Wire Line + 3450 4150 2750 4150 +Wire Wire Line + 3600 850 9450 850 +Wire Wire Line + 9450 850 9450 5050 +Connection ~ 3800 850 +Text Label 3600 850 0 60 ~ 0 +Vcc +Text Label 9100 3350 0 60 ~ 0 +Vout +Text Label 3750 6150 0 60 ~ 0 +GND +Text Label 2300 3300 0 60 ~ 0 +Inp +Text Label 2300 4100 0 60 ~ 0 +NC +NoConn ~ 2300 4100 +$Comp +L PORT U1 +U 2 1 62E8E2E7 +P 1850 3300 +F 0 "U1" H 1900 3400 30 0000 C CNN +F 1 "PORT" H 1850 3300 30 0000 C CNN +F 2 "" H 1850 3300 60 0000 C CNN +F 3 "" H 1850 3300 60 0000 C CNN + 2 1850 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62E8E33C +P 2050 4100 +F 0 "U1" H 2100 4200 30 0000 C CNN +F 1 "PORT" H 2050 4100 30 0000 C CNN +F 2 "" H 2050 4100 60 0000 C CNN +F 3 "" H 2050 4100 60 0000 C CNN + 1 2050 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62E8E47F +P 9450 3350 +F 0 "U1" H 9500 3450 30 0000 C CNN +F 1 "PORT" H 9450 3350 30 0000 C CNN +F 2 "" H 9450 3350 60 0000 C CNN +F 3 "" H 9450 3350 60 0000 C CNN + 4 9450 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62E8E9EE +P 3350 850 +F 0 "U1" H 3400 950 30 0000 C CNN +F 1 "PORT" H 3350 850 30 0000 C CNN +F 2 "" H 3350 850 60 0000 C CNN +F 3 "" H 3350 850 60 0000 C CNN + 5 3350 850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62E8ECBB +P 3500 6200 +F 0 "U1" H 3550 6300 30 0000 C CNN +F 1 "PORT" H 3500 6200 30 0000 C CNN +F 2 "" H 3500 6200 60 0000 C CNN +F 3 "" H 3500 6200 60 0000 C CNN + 3 3500 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7250 2250 6900 2250 +Wire Wire Line + 6900 2250 6900 3350 +Connection ~ 6900 3350 +Wire Wire Line + 7250 4750 7250 3350 +Connection ~ 7250 3350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.sub b/library/SubcircuitLibrary/74V1G14/74V1G14.sub new file mode 100644 index 00000000..37c8151d --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.sub @@ -0,0 +1,14 @@ +* Subcircuit 74V1G14 +.subckt 74V1G14 ? /inp /gnd /vout /vcc +* c:\fossee\esim\library\subcircuitlibrary\74v1g14\74v1g14.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 /vout /inp net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +m2 net-_m1-pad3_ /inp /gnd /gnd CMOSN W=25u L=0.25u M=1 +m3 /vcc /inp net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m4 net-_m3-pad3_ /inp /vout /vcc CMOSP W=25u L=0.25u M=1 +m5 /gnd /vout net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m6 /vcc /vout net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +* Control Statements + +.ends 74V1G14
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml b/library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml new file mode 100644 index 00000000..b08ed607 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field>25u</field><field>0.25u</field><field>1</field></m1><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field>25u</field><field>0.25u</field><field>1</field></m2><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field>75u</field><field>0.25u</field><field>1</field></m3><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field>75u</field><field>0.25u</field><field>1</field></m4><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field>75u</field><field>0.25u</field><field>1</field></m5><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field>25u</field><field>0.25u</field><field>1</field></m6></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib b/library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib b/library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/74V1G14/README.md b/library/SubcircuitLibrary/74V1G14/README.md new file mode 100644 index 00000000..6d0656e5 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/README.md @@ -0,0 +1,24 @@ +# Sch_trig IC + +Schmitt trigger is a general purpose IC. It is the circuit that is used to convert any type of input signal into a square waveform + +## Usage/Examples + +It is used in simple oscillators. + +It is used in Switch Debouncing. + +## Documentation + +To know the details of 74V1G14 IC please refer to this link [74V1G14_datasheet.](https://www.st.com/resource/en/datasheet/74v1g14.pdf) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Vanshika Tanwar +Email: vanshikatanwar30@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/74V1G14/analysis b/library/SubcircuitLibrary/74V1G14/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106-cache.lib b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106-cache.lib new file mode 100644 index 00000000..d1bbdfdd --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106-cache.lib @@ -0,0 +1,83 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir new file mode 100644 index 00000000..ca9bf959 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir @@ -0,0 +1,16 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\Diffamp_INA106\Diffamp_INA106.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 7/20/2022 1:33:22 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_R1-Pad2_ Net-_R2-Pad2_ /V- ? /Output /V+ ? lm_741 +R1 /-IN Net-_R1-Pad2_ 100k +R2 /+IN Net-_R2-Pad2_ 100k +R4 Net-_R1-Pad2_ /Sense 10k +R3 Net-_R2-Pad2_ /REF 10k +U1 /REF /-IN /+IN /V- /Sense /Output /V+ ? PORT + +.end diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir.out b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir.out new file mode 100644 index 00000000..464817c3 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir.out @@ -0,0 +1,18 @@ +* c:\fossee\esim\library\subcircuitlibrary\diffamp_ina106\diffamp_ina106.cir + +.include lm_741.sub +x1 ? net-_r1-pad2_ net-_r2-pad2_ /v- ? /output /v+ ? lm_741 +r1 /-in net-_r1-pad2_ 100k +r2 /+in net-_r2-pad2_ 100k +r4 net-_r1-pad2_ /sense 10k +r3 net-_r2-pad2_ /ref 10k +* u1 /ref /-in /+in /v- /sense /output /v+ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.pro b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sch b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sch new file mode 100644 index 00000000..19e9c3bb --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sch @@ -0,0 +1,247 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:Diffamp_INA106-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X1 +U 1 1 62D11E03 +P 5050 3650 +F 0 "X1" H 4850 3650 60 0000 C CNN +F 1 "lm_741" H 4950 3400 60 0000 C CNN +F 2 "" H 5050 3650 60 0000 C CNN +F 3 "" H 5050 3650 60 0000 C CNN + 1 5050 3650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 62D11E04 +P 3450 3550 +F 0 "R1" H 3500 3680 50 0000 C CIB +F 1 "100k" H 3500 3500 50 0000 C CNN +F 2 "" H 3500 3530 30 0000 C CNN +F 3 "" V 3500 3600 30 0000 C CNN + 1 3450 3550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 62D11E05 +P 3450 3800 +F 0 "R2" H 3500 3930 50 0000 C CIB +F 1 "100k" H 3500 3750 50 0000 C CNN +F 2 "" H 3500 3780 30 0000 C CNN +F 3 "" V 3500 3850 30 0000 C CNN + 1 3450 3800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 62D11E06 +P 5300 3050 +F 0 "R4" H 5350 3180 50 0000 C CIB +F 1 "10k" H 5350 3000 50 0000 C CNN +F 2 "" H 5350 3030 30 0000 C CNN +F 3 "" V 5350 3100 30 0000 C CNN + 1 5300 3050 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 62D11E07 +P 4200 4400 +F 0 "R3" H 4250 4530 50 0000 C CIB +F 1 "10k" H 4250 4350 50 0000 C CNN +F 2 "" H 4250 4380 30 0000 C CNN +F 3 "" V 4250 4450 30 0000 C CNN + 1 4200 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 5500 3000 6650 3000 +Wire Wire Line + 3650 3750 4500 3750 +Wire Wire Line + 3650 3500 4500 3500 +Wire Wire Line + 4900 4100 4900 4350 +Wire Wire Line + 4250 3000 5200 3000 +Wire Wire Line + 4250 3000 4250 3500 +Connection ~ 4250 3500 +Wire Wire Line + 4250 4300 4250 3750 +Connection ~ 4250 3750 +Wire Wire Line + 4800 3150 4900 3150 +Wire Wire Line + 4900 3150 4900 3200 +Wire Wire Line + 2700 3500 3350 3500 +Wire Wire Line + 2700 3750 3350 3750 +Wire Wire Line + 3750 4650 4250 4650 +Wire Wire Line + 4250 4650 4250 4600 +Text Label 2900 3500 0 60 Italic 0 +-IN +Text Label 2900 3750 0 60 Italic 0 ++IN +Text Label 4850 3150 0 60 ~ 12 +V+ +Text Label 4900 4200 0 60 ~ 12 +V- +Text Label 6350 3000 0 60 ~ 0 +Sense +Text Label 3900 4650 0 60 ~ 0 +REF +Text Label 6350 3650 0 49 Italic 0 +Output +NoConn ~ 5000 3250 +NoConn ~ 5100 3300 +Wire Wire Line + 4900 4350 4850 4350 +$Comp +L PORT U1 +U 3 1 62D11F12 +P 2450 3750 +F 0 "U1" H 2500 3850 30 0000 C CNN +F 1 "PORT" H 2450 3750 30 0000 C CNN +F 2 "" H 2450 3750 60 0000 C CNN +F 3 "" H 2450 3750 60 0000 C CNN + 3 2450 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62D11F93 +P 3500 4650 +F 0 "U1" H 3550 4750 30 0000 C CNN +F 1 "PORT" H 3500 4650 30 0000 C CNN +F 2 "" H 3500 4650 60 0000 C CNN +F 3 "" H 3500 4650 60 0000 C CNN + 1 3500 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62D1202E +P 2450 3500 +F 0 "U1" H 2500 3600 30 0000 C CNN +F 1 "PORT" H 2450 3500 30 0000 C CNN +F 2 "" H 2450 3500 60 0000 C CNN +F 3 "" H 2450 3500 60 0000 C CNN + 2 2450 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62D12099 +P 6900 3000 +F 0 "U1" H 6950 3100 30 0000 C CNN +F 1 "PORT" H 6900 3000 30 0000 C CNN +F 2 "" H 6900 3000 60 0000 C CNN +F 3 "" H 6900 3000 60 0000 C CNN + 5 6900 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 62D12114 +P 4550 3150 +F 0 "U1" H 4600 3250 30 0000 C CNN +F 1 "PORT" H 4550 3150 30 0000 C CNN +F 2 "" H 4550 3150 60 0000 C CNN +F 3 "" H 4550 3150 60 0000 C CNN + 7 4550 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 62D121A7 +P 6200 4250 +F 0 "U1" H 6250 4350 30 0000 C CNN +F 1 "PORT" H 6200 4250 30 0000 C CNN +F 2 "" H 6200 4250 60 0000 C CNN +F 3 "" H 6200 4250 60 0000 C CNN + 8 6200 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62D121EE +P 4600 4350 +F 0 "U1" H 4650 4450 30 0000 C CNN +F 1 "PORT" H 4600 4350 30 0000 C CNN +F 2 "" H 4600 4350 60 0000 C CNN +F 3 "" H 4600 4350 60 0000 C CNN + 4 4600 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62D1221F +P 6900 3650 +F 0 "U1" H 6950 3750 30 0000 C CNN +F 1 "PORT" H 6900 3650 30 0000 C CNN +F 2 "" H 6900 3650 60 0000 C CNN +F 3 "" H 6900 3650 60 0000 C CNN + 6 6900 3650 + -1 0 0 1 +$EndComp +NoConn ~ 5950 4250 +Wire Wire Line + 5600 3650 6650 3650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sub b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sub new file mode 100644 index 00000000..18c305cf --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sub @@ -0,0 +1,12 @@ +* Subcircuit Diffamp_INA106 +.subckt Diffamp_INA106 /ref /-in /+in /v- /sense /output /v+ ? +* c:\fossee\esim\library\subcircuitlibrary\diffamp_ina106\diffamp_ina106.cir +.include lm_741.sub +x1 ? net-_r1-pad2_ net-_r2-pad2_ /v- ? /output /v+ ? lm_741 +r1 /-in net-_r1-pad2_ 100k +r2 /+in net-_r2-pad2_ 100k +r4 net-_r1-pad2_ /sense 10k +r3 net-_r2-pad2_ /ref 10k +* Control Statements + +.ends Diffamp_INA106
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106_Previous_Values.xml b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106_Previous_Values.xml new file mode 100644 index 00000000..a7f22b8a --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/NPN.lib b/library/SubcircuitLibrary/Diffamp_INA106/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/Diffamp_INA106/PNP.lib b/library/SubcircuitLibrary/Diffamp_INA106/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/Diffamp_INA106/README.md b/library/SubcircuitLibrary/Diffamp_INA106/README.md new file mode 100644 index 00000000..e95e5fc5 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/README.md @@ -0,0 +1,36 @@ + +## Differential Amplifier IC + +Differential Amplifier is a type of amplifier circuit which is used to amplify the difference of input and give the output respectively. It is used to remove noise which is present in input signal. + +## Usage/Examples + +It is used in Amplitude Modulation. + +It is used in Audio Amplifier for exact and noiseless volume control. + +It is used in Digital and Analog data transmission system for noise cancellation. + +It is used for audio and video processing. + +It is used as an automatic gain control circuit. + +It is used as an electronic switch. + +It is used for motor control. + + +## Documentation + +To know the details of INA106 Differential Amplifier IC please refer to this link [INA106_Differential_Amplifier_datasheet.](https://www.ti.com/lit/ds/symlink/ina106.pdf?ts=1659516896123&ref_url=https%253A%252F%252Fwww.google.co.in%252F) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Vanshika Tanwar +Email: vanshikatanwar30@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/Diffamp_INA106/analysis b/library/SubcircuitLibrary/Diffamp_INA106/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741-cache.lib b/library/SubcircuitLibrary/Diffamp_INA106/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir.out b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741.pro b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.pro new file mode 100644 index 00000000..b56de1b0 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.pro @@ -0,0 +1,44 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741.sch b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 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CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741.sub b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/Diffamp_INA106/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/npn_1.lib b/library/SubcircuitLibrary/Diffamp_INA106/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/pnp_1.lib b/library/SubcircuitLibrary/Diffamp_INA106/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/D.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/NPN.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/PNP.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier-cache.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier-cache.lib new file mode 100644 index 00000000..92e46ff3 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier-cache.lib @@ -0,0 +1,139 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier.sch b/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier.sch new file mode 100644 index 00000000..ac46ef65 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier.sch @@ -0,0 +1,412 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:TINA_TI_Rectifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X1 +U 1 1 630DEBC8 +P 4000 3500 +F 0 "X1" H 3800 3500 60 0000 C CNN +F 1 "lm_741" H 3900 3250 60 0000 C CNN +F 2 "" H 4000 3500 60 0000 C CNN +F 3 "" H 4000 3500 60 0000 C CNN + 1 4000 3500 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X2 +U 1 1 630DEC2E +P 6700 3400 +F 0 "X2" H 6500 3400 60 0000 C CNN +F 1 "lm_741" H 6600 3150 60 0000 C CNN +F 2 "" H 6700 3400 60 0000 C CNN +F 3 "" H 6700 3400 60 0000 C CNN + 1 6700 3400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 630DED64 +P 3250 4100 +F 0 "R1" H 3300 4230 50 0000 C CNN +F 1 "49.9" H 3300 4050 50 0000 C CNN +F 2 "" H 3300 4080 30 0000 C CNN +F 3 "" V 3300 4150 30 0000 C CNN + 1 3250 4100 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 630DEE0E +P 5900 4100 +F 0 "R3" H 5950 4230 50 0000 C CNN +F 1 "1k" H 5950 4050 50 0000 C CNN +F 2 "" H 5950 4080 30 0000 C CNN +F 3 "" V 5950 4150 30 0000 C CNN + 1 5900 4100 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 630DEEA8 +P 5400 3500 +F 0 "D2" H 5400 3600 50 0000 C CNN +F 1 "eSim_Diode" H 5400 3400 50 0000 C CNN +F 2 "" H 5400 3500 60 0000 C CNN +F 3 "" H 5400 3500 60 0000 C CNN + 1 5400 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 630DEF23 +P 5000 2600 +F 0 "D1" H 5000 2700 50 0000 C CNN +F 1 "eSim_Diode" H 5000 2500 50 0000 C CNN +F 2 "" H 5000 2600 60 0000 C CNN +F 3 "" H 5000 2600 60 0000 C CNN + 1 5000 2600 + 0 1 1 0 +$EndComp +$Comp +L capacitor C1 +U 1 1 630DEF6B +P 4600 2600 +F 0 "C1" H 4625 2700 50 0000 L CNN +F 1 "47p" H 4625 2500 50 0000 L CNN +F 2 "" H 4638 2450 30 0000 C CNN +F 3 "" H 4600 2600 60 0000 C CNN + 1 4600 2600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 630DF05D +P 5550 2050 +F 0 "R2" H 5600 2180 50 0000 C CNN +F 1 "1k" H 5600 2000 50 0000 C CNN +F 2 "" H 5600 2030 30 0000 C CNN +F 3 "" V 5600 2100 30 0000 C CNN + 1 5550 2050 + -1 0 0 1 +$EndComp +$Comp +L resistor R4 +U 1 1 630DF101 +P 6500 2050 +F 0 "R4" H 6550 2180 50 0000 C CNN +F 1 "1k" H 6550 2000 50 0000 C CNN +F 2 "" H 6550 2030 30 0000 C CNN +F 3 "" V 6550 2100 30 0000 C CNN + 1 6500 2050 + -1 0 0 1 +$EndComp +$Comp +L capacitor C3 +U 1 1 630DF148 +P 7100 2700 +F 0 "C3" H 7125 2800 50 0000 L CNN +F 1 "100p" H 7125 2600 50 0000 L CNN +F 2 "" H 7138 2550 30 0000 C CNN +F 3 "" H 7100 2700 60 0000 C CNN + 1 7100 2700 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C5 +U 1 1 630DF1F2 +P 7500 2700 +F 0 "C5" H 7525 2800 50 0000 L CNN +F 1 "100n" H 7525 2600 50 0000 L CNN +F 2 "" H 7538 2550 30 0000 C CNN +F 3 "" H 7500 2700 60 0000 C CNN + 1 7500 2700 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 630DF244 +P 6800 4550 +F 0 "C2" H 6825 4650 50 0000 L CNN +F 1 "100p" H 6825 4450 50 0000 L CNN +F 2 "" H 6838 4400 30 0000 C CNN +F 3 "" H 6800 4550 60 0000 C CNN + 1 6800 4550 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C4 +U 1 1 630DF2AA +P 7250 4550 +F 0 "C4" H 7275 4650 50 0000 L CNN +F 1 "100n" H 7275 4450 50 0000 L CNN +F 2 "" H 7288 4400 30 0000 C CNN +F 3 "" H 7250 4550 60 0000 C CNN + 1 7250 4550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 630DF502 +P 3350 5050 +F 0 "#PWR01" H 3350 4800 50 0001 C CNN +F 1 "GND" H 3350 4900 50 0000 C CNN +F 2 "" H 3350 5050 50 0001 C CNN +F 3 "" H 3350 5050 50 0001 C CNN + 1 3350 5050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 630DFA95 +P 5950 4800 +F 0 "#PWR02" H 5950 4550 50 0001 C CNN +F 1 "GND" H 5950 4650 50 0000 C CNN +F 2 "" H 5950 4800 50 0001 C CNN +F 3 "" H 5950 4800 50 0001 C CNN + 1 5950 4800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 630DFAD1 +P 6800 4900 +F 0 "#PWR03" H 6800 4650 50 0001 C CNN +F 1 "GND" H 6800 4750 50 0000 C CNN +F 2 "" H 6800 4900 50 0001 C CNN +F 3 "" H 6800 4900 50 0001 C CNN + 1 6800 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 630DFB06 +P 7250 4900 +F 0 "#PWR04" H 7250 4650 50 0001 C CNN +F 1 "GND" H 7250 4750 50 0000 C CNN +F 2 "" H 7250 4900 50 0001 C CNN +F 3 "" H 7250 4900 50 0001 C CNN + 1 7250 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 630DFB3B +P 7100 3050 +F 0 "#PWR05" H 7100 2800 50 0001 C CNN +F 1 "GND" H 7100 2900 50 0000 C CNN +F 2 "" H 7100 3050 50 0001 C CNN +F 3 "" H 7100 3050 50 0001 C CNN + 1 7100 3050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 630DFB70 +P 7500 3050 +F 0 "#PWR06" H 7500 2800 50 0001 C CNN +F 1 "GND" H 7500 2900 50 0000 C CNN +F 2 "" H 7500 3050 50 0001 C CNN +F 3 "" H 7500 3050 50 0001 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +Text Label 8350 2350 0 60 Italic 12 +Vpos +Text Label 7950 4150 0 60 Italic 12 +Vneg +$Comp +L PORT U1 +U 1 1 631276E6 +P 2550 4000 +F 0 "U1" H 2600 4100 30 0000 C CNN +F 1 "PORT" H 2550 4000 30 0000 C CNN +F 2 "" H 2550 4000 60 0000 C CNN +F 3 "" H 2550 4000 60 0000 C CNN + 1 2550 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 3500 5250 3500 +Wire Wire Line + 5550 3500 6150 3500 +Wire Wire Line + 5950 4000 5950 3500 +Connection ~ 5950 3500 +Wire Wire Line + 5950 4300 5950 4800 +Wire Wire Line + 6550 3850 6550 4150 +Wire Wire Line + 6450 4150 8150 4150 +Wire Wire Line + 6800 4400 6800 4150 +Connection ~ 6800 4150 +Wire Wire Line + 7250 4400 7250 4150 +Connection ~ 7250 4150 +Wire Wire Line + 6800 4700 6800 4900 +Wire Wire Line + 7250 4900 7250 4700 +Wire Wire Line + 6550 2350 6550 2950 +Wire Wire Line + 6550 2450 7950 2450 +Wire Wire Line + 7950 2450 7950 2350 +Wire Wire Line + 7100 2550 7100 2450 +Connection ~ 7100 2450 +Wire Wire Line + 7500 2550 7500 2450 +Connection ~ 7500 2450 +Wire Wire Line + 7100 2850 7100 3050 +Wire Wire Line + 7500 2850 7500 3050 +Wire Wire Line + 7250 3400 8450 3400 +Wire Wire Line + 6600 2100 8250 2100 +Wire Wire Line + 8250 2100 8250 3400 +Connection ~ 8250 3400 +Wire Wire Line + 6300 2100 5650 2100 +Wire Wire Line + 5350 2100 3250 2100 +Wire Wire Line + 3250 2100 3250 3350 +Wire Wire Line + 3250 3350 3450 3350 +Wire Wire Line + 5000 2450 5000 2100 +Connection ~ 5000 2100 +Wire Wire Line + 5000 2750 5000 3500 +Connection ~ 5000 3500 +Wire Wire Line + 4600 2750 4600 3500 +Connection ~ 4600 3500 +Wire Wire Line + 4600 2450 4600 2100 +Connection ~ 4600 2100 +Wire Wire Line + 3450 3600 2800 3600 +Wire Wire Line + 2800 3600 2800 4000 +Wire Wire Line + 3300 4300 3300 5050 +Wire Wire Line + 3300 5050 3350 5050 +Wire Wire Line + 3300 4000 3300 3600 +Connection ~ 3300 3600 +Wire Wire Line + 6150 3250 5850 3250 +Wire Wire Line + 5850 3250 5850 2100 +Wire Wire Line + 5850 2100 5900 2100 +Connection ~ 5900 2100 +Text Label 2800 3950 0 60 Italic 12 +Vin +Text Label 8300 3400 0 60 Italic 12 +Vout +$Comp +L PORT U1 +U 2 1 63128122 +P 8400 4150 +F 0 "U1" H 8450 4250 30 0000 C CNN +F 1 "PORT" H 8400 4150 30 0000 C CNN +F 2 "" H 8400 4150 60 0000 C CNN +F 3 "" H 8400 4150 60 0000 C CNN + 2 8400 4150 + -1 0 0 1 +$EndComp +Wire Wire Line + 3850 3050 3850 2350 +Wire Wire Line + 3850 2350 6550 2350 +Connection ~ 6550 2450 +Wire Wire Line + 3850 3950 6450 3950 +Wire Wire Line + 6450 3950 6450 4150 +Connection ~ 6550 4150 +$Comp +L PORT U1 +U 4 1 631984C4 +P 8800 2350 +F 0 "U1" H 8850 2450 30 0000 C CNN +F 1 "PORT" H 8800 2350 30 0000 C CNN +F 2 "" H 8800 2350 60 0000 C CNN +F 3 "" H 8800 2350 60 0000 C CNN + 4 8800 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 63198559 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 3 8700 3400 + -1 0 0 1 +$EndComp +Wire Wire Line + 7950 2350 8550 2350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/README.md b/library/SubcircuitLibrary/TINA_TI_Rectifier/README.md new file mode 100644 index 00000000..d61b9e7d --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/README.md @@ -0,0 +1,24 @@ + +# Precision_Rectifier IC + +Precision Rectifier is a general purpose IC. The major drawback of the normal diode is that it can not be able to rectify the voltages below (0.6 v) which is the cut-in voltage. So, a special type of diode is used which is a precision diode that is capable of rectifying the input voltage signals in the order of milli volt. So, a circuit that uses this special type of diode(precision diode) is called a precision rectifie + +## Usage/Examples + +It is used in high-precision signal processing with few modification it can be used as Peak Detector. + + +## Documentation + +To know the details of Precision Rectifier IC please refer to this link [Precision_Rectifier_datasheet.](https://www.ti.com/lit/ug/tidu030/tidu030.pdf?ts=1661742834491&ref_url=https%253A%252F%252Fwww.google.com%252F) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Vanshika Tanwar +Email: vanshikatanwar30@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier-cache.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier-cache.lib new file mode 100644 index 00000000..92e46ff3 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier-cache.lib @@ -0,0 +1,139 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir new file mode 100644 index 00000000..f945869f --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir @@ -0,0 +1,24 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\TINA_TI_Rectifier\TINA_TI_Rectifier.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 9/8/2022 12:13:00 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_C1-Pad1_ /Vin /Vneg ? Net-_C1-Pad2_ /Vpos ? lm_741 +X2 ? Net-_R2-Pad1_ Net-_D2-Pad2_ /Vneg ? /Vout /Vpos ? lm_741 +R1 /Vin GND 49.9 +R3 Net-_D2-Pad2_ GND 1k +D2 Net-_C1-Pad2_ Net-_D2-Pad2_ eSim_Diode +D1 Net-_C1-Pad1_ Net-_C1-Pad2_ eSim_Diode +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 47p +R2 Net-_R2-Pad1_ Net-_C1-Pad1_ 1k +R4 /Vout Net-_R2-Pad1_ 1k +C3 /Vpos GND 100p +C5 /Vpos GND 100n +C2 /Vneg GND 100p +C4 /Vneg GND 100n +U1 /Vin /Vneg /Vout /Vpos PORT + +.end diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir.out b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir.out new file mode 100644 index 00000000..433a1bdd --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir.out @@ -0,0 +1,27 @@ +* c:\fossee\esim\library\subcircuitlibrary\tina_ti_rectifier\tina_ti_rectifier.cir + +.include lm_741.sub +.include D.lib +x1 ? net-_c1-pad1_ /vin /vneg ? net-_c1-pad2_ /vpos ? lm_741 +x2 ? net-_r2-pad1_ net-_d2-pad2_ /vneg ? /vout /vpos ? lm_741 +r1 /vin gnd 49.9 +r3 net-_d2-pad2_ gnd 1k +d2 net-_c1-pad2_ net-_d2-pad2_ 1N4148 +d1 net-_c1-pad1_ net-_c1-pad2_ 1N4148 +c1 net-_c1-pad1_ net-_c1-pad2_ 47p +r2 net-_r2-pad1_ net-_c1-pad1_ 1k +r4 /vout net-_r2-pad1_ 1k +c3 /vpos gnd 100p +c5 /vpos gnd 100n +c2 /vneg gnd 100p +c4 /vneg gnd 100n +* u1 /vin /vneg /vout /vpos port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.pro b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sch b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sch new file mode 100644 index 00000000..ac46ef65 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sch @@ -0,0 +1,412 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:TINA_TI_Rectifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X1 +U 1 1 630DEBC8 +P 4000 3500 +F 0 "X1" H 3800 3500 60 0000 C CNN +F 1 "lm_741" H 3900 3250 60 0000 C CNN +F 2 "" H 4000 3500 60 0000 C CNN +F 3 "" H 4000 3500 60 0000 C CNN + 1 4000 3500 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X2 +U 1 1 630DEC2E +P 6700 3400 +F 0 "X2" H 6500 3400 60 0000 C CNN +F 1 "lm_741" H 6600 3150 60 0000 C CNN +F 2 "" H 6700 3400 60 0000 C CNN +F 3 "" H 6700 3400 60 0000 C CNN + 1 6700 3400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 630DED64 +P 3250 4100 +F 0 "R1" H 3300 4230 50 0000 C CNN +F 1 "49.9" H 3300 4050 50 0000 C CNN +F 2 "" H 3300 4080 30 0000 C CNN +F 3 "" V 3300 4150 30 0000 C CNN + 1 3250 4100 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 630DEE0E +P 5900 4100 +F 0 "R3" H 5950 4230 50 0000 C CNN +F 1 "1k" H 5950 4050 50 0000 C CNN +F 2 "" H 5950 4080 30 0000 C CNN +F 3 "" V 5950 4150 30 0000 C CNN + 1 5900 4100 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 630DEEA8 +P 5400 3500 +F 0 "D2" H 5400 3600 50 0000 C CNN +F 1 "eSim_Diode" H 5400 3400 50 0000 C CNN +F 2 "" H 5400 3500 60 0000 C CNN +F 3 "" H 5400 3500 60 0000 C CNN + 1 5400 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 630DEF23 +P 5000 2600 +F 0 "D1" H 5000 2700 50 0000 C CNN +F 1 "eSim_Diode" H 5000 2500 50 0000 C CNN +F 2 "" H 5000 2600 60 0000 C CNN +F 3 "" H 5000 2600 60 0000 C CNN + 1 5000 2600 + 0 1 1 0 +$EndComp +$Comp +L capacitor C1 +U 1 1 630DEF6B +P 4600 2600 +F 0 "C1" H 4625 2700 50 0000 L CNN +F 1 "47p" H 4625 2500 50 0000 L CNN +F 2 "" H 4638 2450 30 0000 C CNN +F 3 "" H 4600 2600 60 0000 C CNN + 1 4600 2600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 630DF05D +P 5550 2050 +F 0 "R2" H 5600 2180 50 0000 C CNN +F 1 "1k" H 5600 2000 50 0000 C CNN +F 2 "" H 5600 2030 30 0000 C CNN +F 3 "" V 5600 2100 30 0000 C CNN + 1 5550 2050 + -1 0 0 1 +$EndComp +$Comp +L resistor R4 +U 1 1 630DF101 +P 6500 2050 +F 0 "R4" H 6550 2180 50 0000 C CNN +F 1 "1k" H 6550 2000 50 0000 C CNN +F 2 "" H 6550 2030 30 0000 C CNN +F 3 "" V 6550 2100 30 0000 C CNN + 1 6500 2050 + -1 0 0 1 +$EndComp +$Comp +L capacitor C3 +U 1 1 630DF148 +P 7100 2700 +F 0 "C3" H 7125 2800 50 0000 L CNN +F 1 "100p" H 7125 2600 50 0000 L CNN +F 2 "" H 7138 2550 30 0000 C CNN +F 3 "" H 7100 2700 60 0000 C CNN + 1 7100 2700 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C5 +U 1 1 630DF1F2 +P 7500 2700 +F 0 "C5" H 7525 2800 50 0000 L CNN +F 1 "100n" H 7525 2600 50 0000 L CNN +F 2 "" H 7538 2550 30 0000 C CNN +F 3 "" H 7500 2700 60 0000 C CNN + 1 7500 2700 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 630DF244 +P 6800 4550 +F 0 "C2" H 6825 4650 50 0000 L CNN +F 1 "100p" H 6825 4450 50 0000 L CNN +F 2 "" H 6838 4400 30 0000 C CNN +F 3 "" H 6800 4550 60 0000 C CNN + 1 6800 4550 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C4 +U 1 1 630DF2AA +P 7250 4550 +F 0 "C4" H 7275 4650 50 0000 L CNN +F 1 "100n" H 7275 4450 50 0000 L CNN +F 2 "" H 7288 4400 30 0000 C CNN +F 3 "" H 7250 4550 60 0000 C CNN + 1 7250 4550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 630DF502 +P 3350 5050 +F 0 "#PWR01" H 3350 4800 50 0001 C CNN +F 1 "GND" H 3350 4900 50 0000 C CNN +F 2 "" H 3350 5050 50 0001 C CNN +F 3 "" H 3350 5050 50 0001 C CNN + 1 3350 5050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 630DFA95 +P 5950 4800 +F 0 "#PWR02" H 5950 4550 50 0001 C CNN +F 1 "GND" H 5950 4650 50 0000 C CNN +F 2 "" H 5950 4800 50 0001 C CNN +F 3 "" H 5950 4800 50 0001 C CNN + 1 5950 4800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 630DFAD1 +P 6800 4900 +F 0 "#PWR03" H 6800 4650 50 0001 C CNN +F 1 "GND" H 6800 4750 50 0000 C CNN +F 2 "" H 6800 4900 50 0001 C CNN +F 3 "" H 6800 4900 50 0001 C CNN + 1 6800 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 630DFB06 +P 7250 4900 +F 0 "#PWR04" H 7250 4650 50 0001 C CNN +F 1 "GND" H 7250 4750 50 0000 C CNN +F 2 "" H 7250 4900 50 0001 C CNN +F 3 "" H 7250 4900 50 0001 C CNN + 1 7250 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 630DFB3B +P 7100 3050 +F 0 "#PWR05" H 7100 2800 50 0001 C CNN +F 1 "GND" H 7100 2900 50 0000 C CNN +F 2 "" H 7100 3050 50 0001 C CNN +F 3 "" H 7100 3050 50 0001 C CNN + 1 7100 3050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 630DFB70 +P 7500 3050 +F 0 "#PWR06" H 7500 2800 50 0001 C CNN +F 1 "GND" H 7500 2900 50 0000 C CNN +F 2 "" H 7500 3050 50 0001 C CNN +F 3 "" H 7500 3050 50 0001 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +Text Label 8350 2350 0 60 Italic 12 +Vpos +Text Label 7950 4150 0 60 Italic 12 +Vneg +$Comp +L PORT U1 +U 1 1 631276E6 +P 2550 4000 +F 0 "U1" H 2600 4100 30 0000 C CNN +F 1 "PORT" H 2550 4000 30 0000 C CNN +F 2 "" H 2550 4000 60 0000 C CNN +F 3 "" H 2550 4000 60 0000 C CNN + 1 2550 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 3500 5250 3500 +Wire Wire Line + 5550 3500 6150 3500 +Wire Wire Line + 5950 4000 5950 3500 +Connection ~ 5950 3500 +Wire Wire Line + 5950 4300 5950 4800 +Wire Wire Line + 6550 3850 6550 4150 +Wire Wire Line + 6450 4150 8150 4150 +Wire Wire Line + 6800 4400 6800 4150 +Connection ~ 6800 4150 +Wire Wire Line + 7250 4400 7250 4150 +Connection ~ 7250 4150 +Wire Wire Line + 6800 4700 6800 4900 +Wire Wire Line + 7250 4900 7250 4700 +Wire Wire Line + 6550 2350 6550 2950 +Wire Wire Line + 6550 2450 7950 2450 +Wire Wire Line + 7950 2450 7950 2350 +Wire Wire Line + 7100 2550 7100 2450 +Connection ~ 7100 2450 +Wire Wire Line + 7500 2550 7500 2450 +Connection ~ 7500 2450 +Wire Wire Line + 7100 2850 7100 3050 +Wire Wire Line + 7500 2850 7500 3050 +Wire Wire Line + 7250 3400 8450 3400 +Wire Wire Line + 6600 2100 8250 2100 +Wire Wire Line + 8250 2100 8250 3400 +Connection ~ 8250 3400 +Wire Wire Line + 6300 2100 5650 2100 +Wire Wire Line + 5350 2100 3250 2100 +Wire Wire Line + 3250 2100 3250 3350 +Wire Wire Line + 3250 3350 3450 3350 +Wire Wire Line + 5000 2450 5000 2100 +Connection ~ 5000 2100 +Wire Wire Line + 5000 2750 5000 3500 +Connection ~ 5000 3500 +Wire Wire Line + 4600 2750 4600 3500 +Connection ~ 4600 3500 +Wire Wire Line + 4600 2450 4600 2100 +Connection ~ 4600 2100 +Wire Wire Line + 3450 3600 2800 3600 +Wire Wire Line + 2800 3600 2800 4000 +Wire Wire Line + 3300 4300 3300 5050 +Wire Wire Line + 3300 5050 3350 5050 +Wire Wire Line + 3300 4000 3300 3600 +Connection ~ 3300 3600 +Wire Wire Line + 6150 3250 5850 3250 +Wire Wire Line + 5850 3250 5850 2100 +Wire Wire Line + 5850 2100 5900 2100 +Connection ~ 5900 2100 +Text Label 2800 3950 0 60 Italic 12 +Vin +Text Label 8300 3400 0 60 Italic 12 +Vout +$Comp +L PORT U1 +U 2 1 63128122 +P 8400 4150 +F 0 "U1" H 8450 4250 30 0000 C CNN +F 1 "PORT" H 8400 4150 30 0000 C CNN +F 2 "" H 8400 4150 60 0000 C CNN +F 3 "" H 8400 4150 60 0000 C CNN + 2 8400 4150 + -1 0 0 1 +$EndComp +Wire Wire Line + 3850 3050 3850 2350 +Wire Wire Line + 3850 2350 6550 2350 +Connection ~ 6550 2450 +Wire Wire Line + 3850 3950 6450 3950 +Wire Wire Line + 6450 3950 6450 4150 +Connection ~ 6550 4150 +$Comp +L PORT U1 +U 4 1 631984C4 +P 8800 2350 +F 0 "U1" H 8850 2450 30 0000 C CNN +F 1 "PORT" H 8800 2350 30 0000 C CNN +F 2 "" H 8800 2350 60 0000 C CNN +F 3 "" H 8800 2350 60 0000 C CNN + 4 8800 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 63198559 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 3 8700 3400 + -1 0 0 1 +$EndComp +Wire Wire Line + 7950 2350 8550 2350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sub b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sub new file mode 100644 index 00000000..dc6cb480 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sub @@ -0,0 +1,21 @@ +* Subcircuit TINA_TI_Rectifier +.subckt TINA_TI_Rectifier /vin /vneg /vout /vpos +* c:\fossee\esim\library\subcircuitlibrary\tina_ti_rectifier\tina_ti_rectifier.cir +.include lm_741.sub +.include D.lib +x1 ? net-_c1-pad1_ /vin /vneg ? net-_c1-pad2_ /vpos ? lm_741 +x2 ? net-_r2-pad1_ net-_d2-pad2_ /vneg ? /vout /vpos ? lm_741 +r1 /vin gnd 49.9 +r3 net-_d2-pad2_ gnd 1k +d2 net-_c1-pad2_ net-_d2-pad2_ 1N4148 +d1 net-_c1-pad1_ net-_c1-pad2_ 1N4148 +c1 net-_c1-pad1_ net-_c1-pad2_ 47p +r2 net-_r2-pad1_ net-_c1-pad1_ 1k +r4 /vout net-_r2-pad1_ 1k +c3 /vpos gnd 100p +c5 /vpos gnd 100n +c2 /vneg gnd 100p +c4 /vneg gnd 100n +* Control Statements + +.ends TINA_TI_Rectifier
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier_Previous_Values.xml b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier_Previous_Values.xml new file mode 100644 index 00000000..b1ddedd6 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">sine<field1 name="Offset Value" /><field2 name="Amplitude" /><field3 name="Frequency" /><field4 name="Delay Time" /><field5 name="Damping Factor" /></v1><v1 name="Source type">15</v1><v2 name="Source type">15</v2></source><model /><devicemodel><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x2></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/analysis b/library/SubcircuitLibrary/TINA_TI_Rectifier/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741-cache.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir.out b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.pro b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.pro new file mode 100644 index 00000000..b56de1b0 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.pro @@ -0,0 +1,44 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sch b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 0000 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE90A88 +P 5400 4700 +F 0 "Q13" H 5300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CE90A89 +P 5250 5200 +F 0 "R4" H 5300 5330 50 0000 C CNN +F 1 "5k" H 5300 5250 50 0000 C CNN +F 2 "" H 5300 5180 30 0000 C CNN +F 3 "" V 5300 5250 30 0000 C CNN + 1 5250 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CE90A8A +P 6350 2750 +F 0 "R11" H 6400 2880 50 0000 C CNN +F 1 "39k" H 6400 2800 50 0000 C CNN +F 2 "" H 6400 2730 30 0000 C CNN +F 3 "" V 6400 2800 30 0000 C CNN + 1 6350 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 5CE90A8B +P 6500 1950 +F 0 "Q10" H 6400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN +F 2 "" H 6700 2050 29 0000 C CNN +F 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1650 +Wire Wire Line + 7550 1650 9500 1650 +Connection ~ 7550 1650 +Connection ~ 8900 1650 +Wire Wire Line + 8900 2500 8900 2900 +Wire Wire Line + 8900 2750 8600 2750 +Connection ~ 8900 2750 +Wire Wire Line + 8300 2950 8300 3350 +Wire Wire Line + 8300 3350 8900 3350 +Wire Wire Line + 8900 3200 8900 3650 +Wire Wire Line + 8900 4400 8900 3950 +Connection ~ 8900 3350 +Wire Wire Line + 8900 3500 9500 3500 +Connection ~ 8900 3500 +Wire Wire Line + 8900 5550 8900 4800 +Connection ~ 7600 5550 +Connection ~ 8900 5550 +Wire Wire Line + 8600 4600 8100 4600 +Wire Wire Line + 8100 4600 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +Connection ~ 4050 3950 +Connection ~ 6600 3950 +Wire Wire Line + 4500 2700 4750 2700 +Wire Wire Line + 4750 2700 4750 1050 +Wire Wire Line + 2450 2700 2150 2700 +Wire Wire Line + 2150 2700 2150 1200 +$Comp +L PORT U1 +U 5 1 5CE90AA0 +P 1850 4850 +F 0 "U1" H 1900 4950 30 0000 C CNN +F 1 "PORT" H 1850 4850 30 0000 C CNN +F 2 "" H 1850 4850 60 0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sub b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/npn_1.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/pnp_1.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/demux/NMOS-180nm.lib b/library/SubcircuitLibrary/demux/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/demux/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/demux/PMOS-180nm.lib b/library/SubcircuitLibrary/demux/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/demux/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/demux/README.md b/library/SubcircuitLibrary/demux/README.md new file mode 100644 index 00000000..b2bb3cb4 --- /dev/null +++ b/library/SubcircuitLibrary/demux/README.md @@ -0,0 +1,28 @@ + +# Demux IC + +Demux is the de-multiplexer circuit that takes one input line and gives multiple output lines. Basically, it’s a combinational circuit and It always takes one input +line and gives 2n output line, where n is the number of select lines. It is also, known as a serial to parallel converter or data distributor circuit. The 1:2 Demux consist of 1 input line, 1 select line, and produces 2 output line. as, according to the formula no. of the output line is depends on no. of select line, here, in 1:2 demux, no. of output line = 2^n = 2^1 = 2. + + +## Usage/Examples + +It is used in communication systems. + +It is used in serial to parallel converter. + + +## Documentation + +To know the details of 74LVC1G19 IC please refer to this link [74LVC1G19_IC_datasheet.](https://assets.nexperia.com/documents/data-sheet/74LVC1G19.pdf) + +## Comments/Notes + +Please note this is a complete Digital IC. It works fine at the time of simulation. + +## Contributor + +Name: Vanshika Tanwar +Email: vanshikatanwar30@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/demux/analysis b/library/SubcircuitLibrary/demux/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/demux/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/demux/demux-cache.lib b/library/SubcircuitLibrary/demux/demux-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/demux/demux.cir b/library/SubcircuitLibrary/demux/demux.cir new file mode 100644 index 00000000..720a8dff --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux.cir @@ -0,0 +1,25 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\demux\demux.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 8/18/2022 2:01:37 AM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 /Vcc /Ebar Net-_M1-Pad1_ /Vcc mosfet_p +M1 Net-_M1-Pad1_ /Ebar /GND /GND mosfet_n +M3 /Vcc Net-_M1-Pad1_ Net-_M11-Pad2_ /Vcc mosfet_p +M9 /Vcc /A Net-_M11-Pad2_ /Vcc mosfet_p +M4 /Vcc /Ebar Net-_M10-Pad3_ /Vcc mosfet_p +M10 /Vcc /A Net-_M10-Pad3_ /Vcc mosfet_p +M5 Net-_M11-Pad2_ Net-_M1-Pad1_ Net-_M5-Pad3_ /GND mosfet_n +M6 Net-_M5-Pad3_ /A /GND /GND mosfet_n +M7 Net-_M10-Pad3_ /Ebar Net-_M7-Pad3_ /GND mosfet_n +M8 Net-_M7-Pad3_ /A /GND /GND mosfet_n +M13 /Vcc Net-_M11-Pad2_ /Y1 /Vcc mosfet_p +M11 /Y1 Net-_M11-Pad2_ /GND /GND mosfet_n +M14 /Vcc Net-_M10-Pad3_ /Y2 /Vcc mosfet_p +M12 /Y2 Net-_M10-Pad3_ /GND /GND mosfet_n +U1 /A /GND /Ebar /Y2 /Vcc /Y1 PORT + +.end diff --git a/library/SubcircuitLibrary/demux/demux.cir.out b/library/SubcircuitLibrary/demux/demux.cir.out new file mode 100644 index 00000000..d5837005 --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux.cir.out @@ -0,0 +1,28 @@ +* c:\fossee\esim\library\subcircuitlibrary\demux\demux.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m2 /vcc /ebar net-_m1-pad1_ /vcc CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ /ebar /gnd /gnd CMOSN W=100u L=100u M=1 +m3 /vcc net-_m1-pad1_ net-_m11-pad2_ /vcc CMOSP W=100u L=100u M=1 +m9 /vcc /a net-_m11-pad2_ /vcc CMOSP W=100u L=100u M=1 +m4 /vcc /ebar net-_m10-pad3_ /vcc CMOSP W=100u L=100u M=1 +m10 /vcc /a net-_m10-pad3_ /vcc CMOSP W=100u L=100u M=1 +m5 net-_m11-pad2_ net-_m1-pad1_ net-_m5-pad3_ /gnd CMOSN W=100u L=100u M=1 +m6 net-_m5-pad3_ /a /gnd /gnd CMOSN W=100u L=100u M=1 +m7 net-_m10-pad3_ /ebar net-_m7-pad3_ /gnd CMOSN W=100u L=100u M=1 +m8 net-_m7-pad3_ /a /gnd /gnd CMOSN W=100u L=100u M=1 +m13 /vcc net-_m11-pad2_ /y1 /vcc CMOSP W=100u L=100u M=1 +m11 /y1 net-_m11-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m14 /vcc net-_m10-pad3_ /y2 /vcc CMOSP W=100u L=100u M=1 +m12 /y2 net-_m10-pad3_ /gnd /gnd CMOSN W=100u L=100u M=1 +* u1 /a /gnd /ebar /y2 /vcc /y1 port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/demux/demux.pro b/library/SubcircuitLibrary/demux/demux.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/demux/demux.sch b/library/SubcircuitLibrary/demux/demux.sch new file mode 100644 index 00000000..90d6f38d --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux.sch @@ -0,0 +1,569 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:demux-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M2 +U 1 1 62F8023F +P 3000 2500 +F 0 "M2" H 2950 2550 50 0000 R CNN +F 1 "mosfet_p" H 3050 2650 50 0000 R CNN +F 2 "" H 3250 2600 29 0000 C CNN +F 3 "" H 3050 2500 60 0000 C CNN + 1 3000 2500 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 62F80240 +P 2950 3000 +F 0 "M1" H 2950 2850 50 0000 R CNN +F 1 "mosfet_n" H 3050 2950 50 0000 R CNN +F 2 "" H 3250 2700 29 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 1 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M3 +U 1 1 62F80242 +P 4850 1900 +F 0 "M3" H 4800 1950 50 0000 R CNN +F 1 "mosfet_p" H 4900 2050 50 0000 R CNN +F 2 "" H 5100 2000 29 0000 C CNN +F 3 "" H 4900 1900 60 0000 C CNN + 1 4850 1900 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M9 +U 1 1 62F80243 +P 5850 1900 +F 0 "M9" H 5800 1950 50 0000 R CNN +F 1 "mosfet_p" H 5900 2050 50 0000 R CNN +F 2 "" H 6100 2000 29 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M4 +U 1 1 62F80244 +P 4950 5100 +F 0 "M4" H 4900 5150 50 0000 R CNN +F 1 "mosfet_p" H 5000 5250 50 0000 R CNN +F 2 "" H 5200 5200 29 0000 C CNN +F 3 "" H 5000 5100 60 0000 C CNN + 1 4950 5100 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M10 +U 1 1 62F80245 +P 5950 5100 +F 0 "M10" H 5900 5150 50 0000 R CNN +F 1 "mosfet_p" H 6000 5250 50 0000 R CNN +F 2 "" H 6200 5200 29 0000 C CNN +F 3 "" H 6000 5100 60 0000 C CNN + 1 5950 5100 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M5 +U 1 1 62F80246 +P 5300 2750 +F 0 "M5" H 5300 2600 50 0000 R CNN +F 1 "mosfet_n" H 5400 2700 50 0000 R CNN +F 2 "" H 5600 2450 29 0000 C CNN +F 3 "" H 5400 2550 60 0000 C CNN + 1 5300 2750 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M6 +U 1 1 62F80247 +P 5300 3550 +F 0 "M6" H 5300 3400 50 0000 R CNN +F 1 "mosfet_n" H 5400 3500 50 0000 R CNN +F 2 "" H 5600 3250 29 0000 C CNN +F 3 "" H 5400 3350 60 0000 C CNN + 1 5300 3550 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M7 +U 1 1 62F80249 +P 5450 5800 +F 0 "M7" H 5450 5650 50 0000 R CNN +F 1 "mosfet_n" H 5550 5750 50 0000 R CNN +F 2 "" H 5750 5500 29 0000 C CNN +F 3 "" H 5550 5600 60 0000 C CNN + 1 5450 5800 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M8 +U 1 1 62F8024A +P 5450 6500 +F 0 "M8" H 5450 6350 50 0000 R CNN +F 1 "mosfet_n" H 5550 6450 50 0000 R CNN +F 2 "" H 5750 6200 29 0000 C CNN +F 3 "" H 5550 6300 60 0000 C CNN + 1 5450 6500 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M13 +U 1 1 62F80250 +P 8000 2150 +F 0 "M13" H 7950 2200 50 0000 R CNN +F 1 "mosfet_p" H 8050 2300 50 0000 R CNN +F 2 "" H 8250 2250 29 0000 C CNN +F 3 "" H 8050 2150 60 0000 C CNN + 1 8000 2150 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M11 +U 1 1 62F80251 +P 7950 2800 +F 0 "M11" H 7950 2650 50 0000 R CNN +F 1 "mosfet_n" H 8050 2750 50 0000 R CNN +F 2 "" H 8250 2500 29 0000 C CNN +F 3 "" H 8050 2600 60 0000 C CNN + 1 7950 2800 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M14 +U 1 1 62F80252 +P 8000 5150 +F 0 "M14" H 7950 5200 50 0000 R CNN +F 1 "mosfet_p" H 8050 5300 50 0000 R CNN +F 2 "" H 8250 5250 29 0000 C CNN +F 3 "" H 8050 5150 60 0000 C CNN + 1 8000 5150 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M12 +U 1 1 62F80253 +P 7950 5750 +F 0 "M12" H 7950 5600 50 0000 R CNN +F 1 "mosfet_n" H 8050 5700 50 0000 R CNN +F 2 "" H 8250 5450 29 0000 C CNN +F 3 "" H 8050 5550 60 0000 C CNN + 1 7950 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62F8236C +P 5950 7600 +F 0 "U1" H 6000 7700 30 0000 C CNN +F 1 "PORT" H 5950 7600 30 0000 C CNN +F 2 "" H 5950 7600 60 0000 C CNN +F 3 "" H 5950 7600 60 0000 C CNN + 2 5950 7600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62F82472 +P 9200 5600 +F 0 "U1" H 9250 5700 30 0000 C CNN +F 1 "PORT" H 9200 5600 30 0000 C CNN +F 2 "" H 9200 5600 60 0000 C CNN +F 3 "" H 9200 5600 60 0000 C CNN + 4 9200 5600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 62F824AB +P 1850 5300 +F 0 "U1" H 1900 5400 30 0000 C CNN +F 1 "PORT" H 1850 5300 30 0000 C CNN +F 2 "" H 1850 5300 60 0000 C CNN +F 3 "" H 1850 5300 60 0000 C CNN + 1 1850 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62F824F0 +P 5700 950 +F 0 "U1" H 5750 1050 30 0000 C CNN +F 1 "PORT" H 5700 950 30 0000 C CNN +F 2 "" H 5700 950 60 0000 C CNN +F 3 "" H 5700 950 60 0000 C CNN + 5 5700 950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 62F825BB +P 1550 2700 +F 0 "U1" H 1600 2800 30 0000 C CNN +F 1 "PORT" H 1550 2700 30 0000 C CNN +F 2 "" H 1550 2700 60 0000 C CNN +F 3 "" H 1550 2700 60 0000 C CNN + 3 1550 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62F8264A +P 9400 2450 +F 0 "U1" H 9450 2550 30 0000 C CNN +F 1 "PORT" H 9400 2450 30 0000 C CNN +F 2 "" H 9400 2450 60 0000 C CNN +F 3 "" H 9400 2450 60 0000 C CNN + 6 9400 2450 + -1 0 0 1 +$EndComp +Wire Wire Line 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Line + 8150 4200 6400 4200 +Wire Wire Line + 6400 4200 6400 7350 +Wire Wire Line + 6400 7350 5700 7350 +Wire Wire Line + 5700 7350 5700 7550 +Wire Wire Line + 3150 7400 5650 7400 +Wire Wire Line + 2350 4150 2350 7450 +Wire Wire Line + 2350 7450 5650 7450 +Wire Wire Line + 5650 7600 5700 7600 +Connection ~ 5650 7450 +Wire Wire Line + 5700 7550 5650 7550 +Connection ~ 5650 7550 +Wire Wire Line + 5800 7400 5800 7500 +Wire Wire Line + 5800 7500 5650 7500 +Connection ~ 5650 7500 +Connection ~ 5650 7400 +Text Label 2200 5300 0 60 ~ 12 +A +Text Label 5700 7600 0 60 ~ 12 +GND +Text Label 1900 2700 0 60 ~ 12 +Ebar +Text Label 8800 5600 0 60 ~ 12 +Y2 +Text Label 5450 1100 0 60 ~ 12 +Vcc +Text Label 9050 2550 0 60 ~ 12 +Y1 +Wire Wire Line + 5500 4150 2350 4150 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/demux/demux.sub b/library/SubcircuitLibrary/demux/demux.sub new file mode 100644 index 00000000..d96316ba --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux.sub @@ -0,0 +1,22 @@ +* Subcircuit demux +.subckt demux /a /gnd /ebar /y2 /vcc /y1 +* c:\fossee\esim\library\subcircuitlibrary\demux\demux.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m2 /vcc /ebar net-_m1-pad1_ /vcc CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ /ebar /gnd /gnd CMOSN W=100u L=100u M=1 +m3 /vcc net-_m1-pad1_ net-_m11-pad2_ /vcc CMOSP W=100u L=100u M=1 +m9 /vcc /a net-_m11-pad2_ /vcc CMOSP W=100u L=100u M=1 +m4 /vcc /ebar net-_m10-pad3_ /vcc CMOSP W=100u L=100u M=1 +m10 /vcc /a net-_m10-pad3_ /vcc CMOSP W=100u L=100u M=1 +m5 net-_m11-pad2_ net-_m1-pad1_ net-_m5-pad3_ /gnd CMOSN W=100u L=100u M=1 +m6 net-_m5-pad3_ /a /gnd /gnd CMOSN W=100u L=100u M=1 +m7 net-_m10-pad3_ /ebar net-_m7-pad3_ /gnd CMOSN W=100u L=100u M=1 +m8 net-_m7-pad3_ /a /gnd /gnd CMOSN W=100u L=100u M=1 +m13 /vcc net-_m11-pad2_ /y1 /vcc CMOSP W=100u L=100u M=1 +m11 /y1 net-_m11-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m14 /vcc net-_m10-pad3_ /y2 /vcc CMOSP W=100u L=100u M=1 +m12 /y2 net-_m10-pad3_ /gnd /gnd CMOSN W=100u L=100u M=1 +* Control Statements + +.ends demux
\ No newline at end of file diff --git a/library/SubcircuitLibrary/demux/demux_Previous_Values.xml b/library/SubcircuitLibrary/demux/demux_Previous_Values.xml new file mode 100644 index 00000000..5e4bb29c --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m2><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m9><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m10><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m6><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m7><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m8><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m13><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m11><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m14><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib index cb462b9b..306cff3f 100644 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib @@ -1104,4 +1104,86 @@ X ByP 7 0 550 200 D 50 50 1 1 I X GAIN 8 -200 550 200 D 50 50 1 1 I ENDDRAW ENDDEF +# +# Precision_Rectifier +# +DEF Precision_Rectifier X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "Precision_Rectifier" 50 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 200 500 -200 0 1 0 N +X Vin 1 -600 150 200 R 50 50 1 1 I +X Vneg 2 -600 -150 200 R 50 50 1 1 I +X Vout 3 700 -150 200 L 50 50 1 1 O +X Vpos 4 700 150 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# Diffamp_INA106 +# +DEF Diffamp_INA106 X 0 40 Y Y 1 F N +F0 "X" 0 -100 40 H V C CIN +F1 "Diffamp_INA106" 0 0 40 H V C CIN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -850 1000 -850 1000 0 1 0 N +S -250 200 250 -250 0 1 0 N +S -250 250 -250 250 0 1 0 N +X REF 1 -450 150 200 R 50 22 1 1 I +X -IN 2 -450 50 200 R 50 22 1 1 I +X +IN 3 -450 -100 200 R 50 22 1 1 I +X V- 4 -450 -200 200 R 50 22 1 1 I +X SENSE 5 450 -200 200 L 50 22 1 1 I +X Output 6 450 -100 200 L 50 22 1 1 O +X V+ 7 450 50 200 L 50 22 1 1 I +X NC 8 450 150 200 L 50 22 1 1 N +ENDDRAW +ENDDEF +# +# 74V1G14 +# +DEF 74V1G14 X 0 40 Y Y 1 F N +F0 "X" -50 50 31 H V C CNN +F1 "74V1G14" 0 0 35 H V C CNB +F2 "" -100 50 60 H I C CNN +F3 "" -100 50 60 H I C CNN +DRAW +T 0 0 250 31 0 0 0 Sch_Trig Italic 0 C C +C 250 0 50 0 1 0 N +C 1450 0 0 0 1 0 N +C 1900 150 0 0 1 0 N +S -250 300 350 -250 0 1 0 N +P 5 0 1 0 200 0 -150 -150 -150 100 -150 150 200 0 N +X NC 1 -200 -450 200 U 50 39 1 1 N +X Inp 2 50 -450 200 U 50 39 1 1 I +X GND 3 250 -450 200 U 50 39 1 1 I +X Vout 4 200 500 200 D 50 39 1 1 O +X Vcc 5 -200 500 200 D 50 39 1 1 I +ENDDRAW +ENDDEF +# +# 74LVC1G19 +# +DEF 74LVC1G19 X 0 40 Y Y 1 F N +F0 "X" 0 -150 60 H V C CNN +F1 "74LVC1G19" 0 200 39 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +T 0 0 0 39 0 0 0 1:2~Demux Italic 0 C C +S -400 450 -400 450 0 1 0 N +S -300 500 -300 500 0 1 0 N +S 300 -250 -300 400 0 1 0 N +X A 1 -500 350 200 R 50 50 1 1 I +X GND 2 -500 100 200 R 50 50 1 1 I +X Ebar 3 -500 -200 200 R 50 50 1 1 I +X Y2 4 500 -200 200 L 50 50 1 1 O +X Vcc 5 500 100 200 L 50 50 1 1 I +X Y1 6 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# #End Library |