diff options
Diffstat (limited to 'library')
644 files changed, 32303 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul-cache.lib b/library/SubcircuitLibrary/2bitmul/2bitmul-cache.lib new file mode 100644 index 00000000..e16831e4 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul-cache.lib @@ -0,0 +1,77 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul.cir b/library/SubcircuitLibrary/2bitmul/2bitmul.cir new file mode 100644 index 00000000..0f4deb6c --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul.cir @@ -0,0 +1,17 @@ +* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and +U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and +U3 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and +U2 Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and +X2 Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder +X1 Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT + +.end diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/library/SubcircuitLibrary/2bitmul/2bitmul.cir.out new file mode 100644 index 00000000..71766bd8 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul.cir.out @@ -0,0 +1,31 @@ +* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir + +.include half_adder.sub +* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and +x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder +x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul.pro b/library/SubcircuitLibrary/2bitmul/2bitmul.pro new file mode 100644 index 00000000..eafbfb80 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul.pro @@ -0,0 +1,74 @@ +update=03/07/19 09:55:40 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul.sch b/library/SubcircuitLibrary/2bitmul/2bitmul.sch new file mode 100644 index 00000000..0ba61912 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul.sch @@ -0,0 +1,284 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:2bitmul-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U5 +U 1 1 5C7FC048 +P 8150 2950 +F 0 "U5" H 8150 2950 60 0000 C CNN +F 1 "d_and" H 8200 3050 60 0000 C CNN +F 2 "" H 8150 2950 60 0000 C CNN +F 3 "" H 8150 2950 60 0000 C CNN + 1 8150 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FC0BC +P 7450 2950 +F 0 "U4" H 7450 2950 60 0000 C CNN +F 1 "d_and" H 7500 3050 60 0000 C CNN +F 2 "" H 7450 2950 60 0000 C CNN +F 3 "" H 7450 2950 60 0000 C CNN + 1 7450 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5C7FC0F4 +P 6950 2950 +F 0 "U3" H 6950 2950 60 0000 C CNN +F 1 "d_and" H 7000 3050 60 0000 C CNN +F 2 "" H 6950 2950 60 0000 C CNN +F 3 "" H 6950 2950 60 0000 C CNN + 1 6950 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U2 +U 1 1 5C7FC11D +P 6400 2950 +F 0 "U2" H 6400 2950 60 0000 C CNN +F 1 "d_and" H 6450 3050 60 0000 C CNN +F 2 "" H 6400 2950 60 0000 C CNN +F 3 "" H 6400 2950 60 0000 C CNN + 1 6400 2950 + 0 1 1 0 +$EndComp +Wire Wire Line + 8150 2500 8150 2350 +Wire Wire Line + 8150 2350 7450 2350 +Wire Wire Line + 7450 2100 7450 2500 +Wire Wire Line + 6950 2500 6950 2350 +Wire Wire Line + 6950 2350 6400 2350 +Wire Wire Line + 6400 2350 6400 2500 +Wire Wire Line + 8250 1100 8250 2500 +Wire Wire Line + 8250 2250 7050 2250 +Wire Wire Line + 7050 2250 7050 2500 +Wire Wire Line + 7550 2150 7550 2500 +Wire Wire Line + 7550 2450 6500 2450 +Wire Wire Line + 6500 2450 6500 2500 +$Comp +L half_adder X2 +U 1 1 5C7FC23A +P 7200 3350 +F 0 "X2" H 8100 3850 60 0000 C CNN +F 1 "half_adder" H 8100 3750 60 0000 C CNN +F 2 "" H 7200 3350 60 0000 C CNN +F 3 "" H 7200 3350 60 0000 C CNN + 1 7200 3350 + 0 1 1 0 +$EndComp +$Comp +L half_adder X1 +U 1 1 5C7FC324 +P 6050 3350 +F 0 "X1" H 6950 3850 60 0000 C CNN +F 1 "half_adder" H 6950 3750 60 0000 C CNN +F 2 "" H 6050 3350 60 0000 C CNN +F 3 "" H 6050 3350 60 0000 C CNN + 1 6050 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 7500 3400 7900 3400 +Wire Wire Line + 7900 3400 7900 3650 +Wire Wire Line + 7000 3400 7300 3400 +Wire Wire Line + 7300 3400 7300 3650 +Wire Wire Line + 7300 4800 7050 4800 +Wire Wire Line + 7050 4800 7050 3600 +Wire Wire Line + 7050 3600 6750 3600 +Wire Wire Line + 6750 3600 6750 3650 +Wire Wire Line + 6450 3400 6450 3650 +Wire Wire Line + 6450 3650 6150 3650 +$Comp +L PORT U1 +U 5 1 5C7FC4F8 +P 8200 5300 +F 0 "U1" H 8250 5400 30 0000 C CNN +F 1 "PORT" H 8200 5300 30 0000 C CNN +F 2 "" H 8200 5300 60 0000 C CNN +F 3 "" H 8200 5300 60 0000 C CNN + 5 8200 5300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 5C7FC5D7 +P 7300 5300 +F 0 "U1" H 7350 5400 30 0000 C CNN +F 1 "PORT" H 7300 5300 30 0000 C CNN +F 2 "" H 7300 5300 60 0000 C CNN +F 3 "" H 7300 5300 60 0000 C CNN + 6 7300 5300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C7FC641 +P 6750 5150 +F 0 "U1" H 6800 5250 30 0000 C CNN +F 1 "PORT" H 6750 5150 30 0000 C CNN +F 2 "" H 6750 5150 60 0000 C CNN +F 3 "" H 6750 5150 60 0000 C CNN + 7 6750 5150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C7FC698 +P 6150 5250 +F 0 "U1" H 6200 5350 30 0000 C CNN +F 1 "PORT" H 6150 5250 30 0000 C CNN +F 2 "" H 6150 5250 60 0000 C CNN +F 3 "" H 6150 5250 60 0000 C CNN + 8 6150 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5C7FC6EC +P 8250 850 +F 0 "U1" H 8300 950 30 0000 C CNN +F 1 "PORT" H 8250 850 30 0000 C CNN +F 2 "" H 8250 850 60 0000 C CNN +F 3 "" H 8250 850 60 0000 C CNN + 1 8250 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FC815 +P 7900 850 +F 0 "U1" H 7950 950 30 0000 C CNN +F 1 "PORT" H 7900 850 30 0000 C CNN +F 2 "" H 7900 850 60 0000 C CNN +F 3 "" H 7900 850 60 0000 C CNN + 2 7900 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FC857 +P 7550 850 +F 0 "U1" H 7600 950 30 0000 C CNN +F 1 "PORT" H 7550 850 30 0000 C CNN +F 2 "" H 7550 850 60 0000 C CNN +F 3 "" H 7550 850 60 0000 C CNN + 3 7550 850 + 0 1 1 0 +$EndComp +Connection ~ 8250 2250 +Wire Wire Line + 7900 1100 7900 2150 +Wire Wire Line + 7900 2150 7550 2150 +Connection ~ 7550 2450 +Wire Wire Line + 7550 1100 7550 2100 +Wire Wire Line + 7550 2100 7450 2100 +Connection ~ 7450 2350 +Wire Wire Line + 7200 1050 7200 2100 +Wire Wire Line + 7200 2100 6800 2100 +Wire Wire Line + 6800 2100 6800 2350 +Connection ~ 6800 2350 +Wire Wire Line + 8200 3400 8200 5050 +$Comp +L PORT U1 +U 4 1 5C7FC898 +P 7200 800 +F 0 "U1" H 7250 900 30 0000 C CNN +F 1 "PORT" H 7200 800 30 0000 C CNN +F 2 "" H 7200 800 60 0000 C CNN +F 3 "" H 7200 800 60 0000 C CNN + 4 7200 800 + 0 1 1 0 +$EndComp +Wire Wire Line + 7300 5050 7300 4850 +Wire Wire Line + 7300 4850 7900 4850 +Wire Wire Line + 7900 4850 7900 4800 +Wire Wire Line + 6750 4800 6750 4900 +Wire Wire Line + 6150 4800 6150 5000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul.sub b/library/SubcircuitLibrary/2bitmul/2bitmul.sub new file mode 100644 index 00000000..e77495a6 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul.sub @@ -0,0 +1,25 @@ +* Subcircuit 2bitmul +.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir +.include half_adder.sub +* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and +x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder +x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 2bitmul
\ No newline at end of file diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml b/library/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml new file mode 100644 index 00000000..8a55af97 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u5 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/2bitmul/analysis b/library/SubcircuitLibrary/2bitmul/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/2bitmul/half_adder-cache.lib b/library/SubcircuitLibrary/2bitmul/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.cir b/library/SubcircuitLibrary/2bitmul/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.cir.out b/library/SubcircuitLibrary/2bitmul/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.pro b/library/SubcircuitLibrary/2bitmul/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.sch b/library/SubcircuitLibrary/2bitmul/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.sub b/library/SubcircuitLibrary/2bitmul/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml b/library/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/3_and/3_and-cache.lib b/library/SubcircuitLibrary/3_and/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/3_and/3_and.cir b/library/SubcircuitLibrary/3_and/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/3_and/3_and.cir.out b/library/SubcircuitLibrary/3_and/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/3_and/3_and.pro b/library/SubcircuitLibrary/3_and/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/3_and/3_and.sch b/library/SubcircuitLibrary/3_and/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/3_and/3_and.sub b/library/SubcircuitLibrary/3_and/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/3_and/3_and_Previous_Values.xml b/library/SubcircuitLibrary/3_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/3_and/analysis b/library/SubcircuitLibrary/3_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4002/4002-cache.lib b/library/SubcircuitLibrary/4002/4002-cache.lib new file mode 100644 index 00000000..677411a9 --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4002/4002.cir b/library/SubcircuitLibrary/4002/4002.cir new file mode 100644 index 00000000..5d5c1ed7 --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or +U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor + +.end diff --git a/library/SubcircuitLibrary/4002/4002.cir.out b/library/SubcircuitLibrary/4002/4002.cir.out new file mode 100644 index 00000000..e9cc6862 --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir + +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or +* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 +a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4002/4002.pro b/library/SubcircuitLibrary/4002/4002.pro new file mode 100644 index 00000000..225ef82a --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002.pro @@ -0,0 +1,44 @@ +update=05/31/19 09:35:41 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog +LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices +LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital +LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid +LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot +LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power +LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources +LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt +LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User +LibName11=power diff --git a/library/SubcircuitLibrary/4002/4002.sch b/library/SubcircuitLibrary/4002/4002.sch new file mode 100644 index 00000000..545f46fe --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002.sch @@ -0,0 +1,315 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5CEE059A +P 4750 2900 +F 0 "U2" H 4750 2900 60 0000 C CNN +F 1 "d_or" H 4750 3000 60 0000 C CNN +F 2 "" H 4750 2900 60 0000 C CNN +F 3 "" H 4750 2900 60 0000 C CNN + 1 4750 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5CEE0629 +P 4750 3450 +F 0 "U3" H 4750 3450 60 0000 C CNN +F 1 "d_or" H 4750 3550 60 0000 C CNN +F 2 "" H 4750 3450 60 0000 C CNN +F 3 "" H 4750 3450 60 0000 C CNN + 1 4750 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 5CEE0663 +P 6000 3100 +F 0 "U6" H 6000 3100 60 0000 C CNN +F 1 "d_nor" H 6050 3200 60 0000 C CNN +F 2 "" H 6000 3100 60 0000 C CNN +F 3 "" H 6000 3100 60 0000 C CNN + 1 6000 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 2850 5400 2850 +Wire Wire Line + 5400 2850 5400 3000 +Wire Wire Line + 5400 3000 5550 3000 +Wire Wire Line + 5200 3400 5400 3400 +Wire Wire Line + 5400 3400 5400 3100 +Wire Wire Line + 5400 3100 5550 3100 +Wire Wire Line + 5650 5350 6050 5350 +Wire Wire Line + 5650 5550 6050 5550 +Wire Wire Line + 5650 5800 6050 5800 +Wire Wire Line + 5650 6000 6050 6000 +NoConn ~ 5650 5350 +NoConn ~ 5650 5550 +NoConn ~ 5650 5800 +NoConn ~ 5650 6000 +$Comp +L PORT U1 +U 2 1 5CEE1C41 +P 3850 2800 +F 0 "U1" H 3900 2900 30 0000 C CNN +F 1 "PORT" H 3850 2800 30 0000 C CNN +F 2 "" H 3850 2800 60 0000 C CNN +F 3 "" H 3850 2800 60 0000 C CNN + 2 3850 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE22EE +P 3900 3050 +F 0 "U1" H 3950 3150 30 0000 C CNN +F 1 "PORT" H 3900 3050 30 0000 C CNN +F 2 "" H 3900 3050 60 0000 C CNN +F 3 "" H 3900 3050 60 0000 C CNN + 3 3900 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE2322 +P 3900 3250 +F 0 "U1" H 3950 3350 30 0000 C CNN +F 1 "PORT" H 3900 3250 30 0000 C CNN +F 2 "" H 3900 3250 60 0000 C CNN +F 3 "" H 3900 3250 60 0000 C CNN + 5 3900 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE2351 +P 3900 3550 +F 0 "U1" H 3950 3650 30 0000 C CNN +F 1 "PORT" H 3900 3550 30 0000 C CNN +F 2 "" H 3900 3550 60 0000 C CNN +F 3 "" H 3900 3550 60 0000 C CNN + 4 3900 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE2387 +P 6950 3050 +F 0 "U1" H 7000 3150 30 0000 C CNN +F 1 "PORT" H 6950 3050 30 0000 C CNN +F 2 "" H 6950 3050 60 0000 C CNN +F 3 "" H 6950 3050 60 0000 C CNN + 1 6950 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 4100 2800 4300 2800 +Wire Wire Line + 4150 3050 4150 2900 +Wire Wire Line + 4150 2900 4300 2900 +Wire Wire Line + 4150 3250 4300 3250 +Wire Wire Line + 4300 3250 4300 3350 +Wire Wire Line + 4150 3550 4150 3450 +Wire Wire Line + 4150 3450 4300 3450 +Wire Wire Line + 6700 3050 6450 3050 +$Comp +L d_or U4 +U 1 1 5CEE4ED7 +P 4900 4100 +F 0 "U4" H 4900 4100 60 0000 C CNN +F 1 "d_or" H 4900 4200 60 0000 C CNN +F 2 "" H 4900 4100 60 0000 C CNN +F 3 "" H 4900 4100 60 0000 C CNN + 1 4900 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U5 +U 1 1 5CEE4EDD +P 4900 4650 +F 0 "U5" H 4900 4650 60 0000 C CNN +F 1 "d_or" H 4900 4750 60 0000 C CNN +F 2 "" H 4900 4650 60 0000 C CNN +F 3 "" H 4900 4650 60 0000 C CNN + 1 4900 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 5CEE4EE3 +P 6150 4300 +F 0 "U7" H 6150 4300 60 0000 C CNN +F 1 "d_nor" H 6200 4400 60 0000 C CNN +F 2 "" H 6150 4300 60 0000 C CNN +F 3 "" H 6150 4300 60 0000 C CNN + 1 6150 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 4050 5550 4050 +Wire Wire Line + 5550 4050 5550 4200 +Wire Wire Line + 5550 4200 5700 4200 +Wire Wire Line + 5350 4600 5550 4600 +Wire Wire Line + 5550 4600 5550 4300 +Wire Wire Line + 5550 4300 5700 4300 +$Comp +L PORT U1 +U 9 1 5CEE4EEF +P 4000 4000 +F 0 "U1" H 4050 4100 30 0000 C CNN +F 1 "PORT" H 4000 4000 30 0000 C CNN +F 2 "" H 4000 4000 60 0000 C CNN +F 3 "" H 4000 4000 60 0000 C CNN + 9 4000 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE4EF5 +P 4050 4250 +F 0 "U1" H 4100 4350 30 0000 C CNN +F 1 "PORT" H 4050 4250 30 0000 C CNN +F 2 "" H 4050 4250 60 0000 C CNN +F 3 "" H 4050 4250 60 0000 C CNN + 10 4050 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE4EFB +P 4050 4450 +F 0 "U1" H 4100 4550 30 0000 C CNN +F 1 "PORT" H 4050 4450 30 0000 C CNN +F 2 "" H 4050 4450 60 0000 C CNN +F 3 "" H 4050 4450 60 0000 C CNN + 11 4050 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE4F01 +P 4050 4750 +F 0 "U1" H 4100 4850 30 0000 C CNN +F 1 "PORT" H 4050 4750 30 0000 C CNN +F 2 "" H 4050 4750 60 0000 C CNN +F 3 "" H 4050 4750 60 0000 C CNN + 12 4050 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CEE4F07 +P 7100 4250 +F 0 "U1" H 7150 4350 30 0000 C CNN +F 1 "PORT" H 7100 4250 30 0000 C CNN +F 2 "" H 7100 4250 60 0000 C CNN +F 3 "" H 7100 4250 60 0000 C CNN + 13 7100 4250 + -1 0 0 1 +$EndComp +Wire Wire Line + 4250 4000 4450 4000 +Wire Wire Line + 4300 4250 4300 4100 +Wire Wire Line + 4300 4100 4450 4100 +Wire Wire Line + 4300 4450 4450 4450 +Wire Wire Line + 4450 4450 4450 4550 +Wire Wire Line + 4300 4750 4300 4650 +Wire Wire Line + 4300 4650 4450 4650 +Wire Wire Line + 6850 4250 6600 4250 +$Comp +L PORT U1 +U 6 1 5CEE51A5 +P 6300 5350 +F 0 "U1" H 6350 5450 30 0000 C CNN +F 1 "PORT" H 6300 5350 30 0000 C CNN +F 2 "" H 6300 5350 60 0000 C CNN +F 3 "" H 6300 5350 60 0000 C CNN + 6 6300 5350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE522C +P 6300 5550 +F 0 "U1" H 6350 5650 30 0000 C CNN +F 1 "PORT" H 6300 5550 30 0000 C CNN +F 2 "" H 6300 5550 60 0000 C CNN +F 3 "" H 6300 5550 60 0000 C CNN + 7 6300 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE5276 +P 6300 5800 +F 0 "U1" H 6350 5900 30 0000 C CNN +F 1 "PORT" H 6300 5800 30 0000 C CNN +F 2 "" H 6300 5800 60 0000 C CNN +F 3 "" H 6300 5800 60 0000 C CNN + 8 6300 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CEE52C5 +P 6300 6000 +F 0 "U1" H 6350 6100 30 0000 C CNN +F 1 "PORT" H 6300 6000 30 0000 C CNN +F 2 "" H 6300 6000 60 0000 C CNN +F 3 "" H 6300 6000 60 0000 C CNN + 14 6300 6000 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4002/4002.sub b/library/SubcircuitLibrary/4002/4002.sub new file mode 100644 index 00000000..b9726625 --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002.sub @@ -0,0 +1,30 @@ +* Subcircuit 4002 +.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or +* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 +a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4002
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4002/4002_Previous_Values.xml b/library/SubcircuitLibrary/4002/4002_Previous_Values.xml new file mode 100644 index 00000000..75360e5e --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4002/analysis b/library/SubcircuitLibrary/4002/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4002/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4012/4012-cache.lib b/library/SubcircuitLibrary/4012/4012-cache.lib new file mode 100644 index 00000000..ea0d2d70 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4012/4012.cir b/library/SubcircuitLibrary/4012/4012.cir new file mode 100644 index 00000000..a88a9da4 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter +U9 Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and +U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and +U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and + +.end diff --git a/library/SubcircuitLibrary/4012/4012.cir.out b/library/SubcircuitLibrary/4012/4012.cir.out new file mode 100644 index 00000000..c43dda8c --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.cir.out @@ -0,0 +1,44 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir + +* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter +* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +a1 net-_u6-pad3_ net-_u1-pad1_ u8 +a2 net-_u7-pad3_ net-_u1-pad13_ u9 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4012/4012.pro b/library/SubcircuitLibrary/4012/4012.pro new file mode 100644 index 00000000..0f76f4bb --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.pro @@ -0,0 +1,44 @@ +update=06/01/19 13:10:32 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_User +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/4012/4012.sch b/library/SubcircuitLibrary/4012/4012.sch new file mode 100644 index 00000000..b3320871 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.sch @@ -0,0 +1,342 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4012-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3350 2600 2550 2600 +Wire Wire Line + 3350 2700 3150 2700 +Wire Wire Line + 3150 2700 3150 2850 +Wire Wire Line + 3150 2850 2550 2850 +Wire Wire Line + 3350 3200 3150 3200 +Wire Wire Line + 3150 3200 3150 3100 +Wire Wire Line + 3150 3100 2550 3100 +Wire Wire Line + 3350 3300 2550 3300 +Wire Wire Line + 5200 2950 5500 2950 +$Comp +L d_inverter U8 +U 1 1 5CEE55AB +P 5800 2950 +F 0 "U8" H 5800 2850 60 0000 C CNN +F 1 "d_inverter" H 5800 3100 60 0000 C CNN +F 2 "" H 5850 2900 60 0000 C CNN +F 3 "" H 5850 2900 60 0000 C CNN + 1 5800 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 2950 6500 2950 +Wire Wire Line + 3400 3950 2600 3950 +Wire Wire Line + 3400 4050 3200 4050 +Wire Wire Line + 3200 4050 3200 4200 +Wire Wire Line + 3200 4200 2600 4200 +Wire Wire Line + 3400 4550 3200 4550 +Wire Wire Line + 3200 4550 3200 4450 +Wire Wire Line + 3200 4450 2600 4450 +Wire Wire Line + 3400 4650 2600 4650 +Wire Wire Line + 5250 4300 5550 4300 +$Comp +L d_inverter U9 +U 1 1 5CEE5715 +P 5850 4300 +F 0 "U9" H 5850 4200 60 0000 C CNN +F 1 "d_inverter" H 5850 4450 60 0000 C CNN +F 2 "" H 5900 4250 60 0000 C CNN +F 3 "" H 5900 4250 60 0000 C CNN + 1 5850 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 4300 6550 4300 +$Comp +L PORT U1 +U 2 1 5CEE57D6 +P 2300 2600 +F 0 "U1" H 2350 2700 30 0000 C CNN +F 1 "PORT" H 2300 2600 30 0000 C CNN +F 2 "" H 2300 2600 60 0000 C CNN +F 3 "" H 2300 2600 60 0000 C CNN + 2 2300 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE587B +P 2300 2850 +F 0 "U1" H 2350 2950 30 0000 C CNN +F 1 "PORT" H 2300 2850 30 0000 C CNN +F 2 "" H 2300 2850 60 0000 C CNN +F 3 "" H 2300 2850 60 0000 C CNN + 3 2300 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE58AF +P 2300 3100 +F 0 "U1" H 2350 3200 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN +F 2 "" H 2300 3100 60 0000 C CNN +F 3 "" H 2300 3100 60 0000 C CNN + 4 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CEE58E6 +P 6800 4300 +F 0 "U1" H 6850 4400 30 0000 C CNN +F 1 "PORT" H 6800 4300 30 0000 C CNN +F 2 "" H 6800 4300 60 0000 C CNN +F 3 "" H 6800 4300 60 0000 C CNN + 13 6800 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE5922 +P 2300 3300 +AR Path="/5CEE58E6" Ref="U1" Part="1" +AR Path="/5CEE5922" Ref="U1" Part="5" +F 0 "U1" H 2350 3400 30 0000 C CNN +F 1 "PORT" H 2300 3300 30 0000 C CNN +F 2 "" H 2300 3300 60 0000 C CNN +F 3 "" H 2300 3300 60 0000 C CNN + 5 2300 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CEE596F +P 2350 3950 +AR Path="/5CEE5922" Ref="U1" Part="5" +AR Path="/5CEE596F" Ref="U1" Part="9" +F 0 "U1" H 2400 4050 30 0000 C CNN +F 1 "PORT" H 2350 3950 30 0000 C CNN +F 2 "" H 2350 3950 60 0000 C CNN +F 3 "" H 2350 3950 60 0000 C CNN + 9 2350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE59AF +P 2350 4200 +AR Path="/5CEE596F" Ref="U1" Part="6" +AR Path="/5CEE59AF" Ref="U1" Part="10" +F 0 "U1" H 2400 4300 30 0000 C CNN +F 1 "PORT" H 2350 4200 30 0000 C CNN +F 2 "" H 2350 4200 60 0000 C CNN +F 3 "" H 2350 4200 60 0000 C CNN + 10 2350 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE59F6 +P 2350 4450 +AR Path="/5CEE59AF" Ref="U1" Part="7" +AR Path="/5CEE59F6" Ref="U1" Part="11" +F 0 "U1" H 2400 4550 30 0000 C CNN +F 1 "PORT" H 2350 4450 30 0000 C CNN +F 2 "" H 2350 4450 60 0000 C CNN +F 3 "" H 2350 4450 60 0000 C CNN + 11 2350 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE5A6A +P 2350 4650 +AR Path="/5CEE59F6" Ref="U1" Part="8" +AR Path="/5CEE5A6A" Ref="U1" Part="12" +F 0 "U1" H 2400 4750 30 0000 C CNN +F 1 "PORT" H 2350 4650 30 0000 C CNN +F 2 "" H 2350 4650 60 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 12 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE5BF8 +P 6750 2950 +AR Path="/5CEE5A6A" Ref="U1" Part="9" +AR Path="/5CEE5BF8" Ref="U1" Part="1" +F 0 "U1" H 6800 3050 30 0000 C CNN +F 1 "PORT" H 6750 2950 30 0000 C CNN +F 2 "" H 6750 2950 60 0000 C CNN +F 3 "" H 6750 2950 60 0000 C CNN + 1 6750 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CEE5C72 +P 7850 1450 +F 0 "U1" H 7900 1550 30 0000 C CNN +F 1 "PORT" H 7850 1450 30 0000 C CNN +F 2 "" H 7850 1450 60 0000 C CNN +F 3 "" H 7850 1450 60 0000 C CNN + 6 7850 1450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE5D23 +P 7850 1700 +F 0 "U1" H 7900 1800 30 0000 C CNN +F 1 "PORT" H 7850 1700 30 0000 C CNN +F 2 "" H 7850 1700 60 0000 C CNN +F 3 "" H 7850 1700 60 0000 C CNN + 7 7850 1700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CEE5D75 +P 7850 1950 +F 0 "U1" H 7900 2050 30 0000 C CNN +F 1 "PORT" H 7850 1950 30 0000 C CNN +F 2 "" H 7850 1950 60 0000 C CNN +F 3 "" H 7850 1950 60 0000 C CNN + 14 7850 1950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE5DCA +P 7850 2250 +F 0 "U1" H 7900 2350 30 0000 C CNN +F 1 "PORT" H 7850 2250 30 0000 C CNN +F 2 "" H 7850 2250 60 0000 C CNN +F 3 "" H 7850 2250 60 0000 C CNN + 8 7850 2250 + -1 0 0 1 +$EndComp +NoConn ~ 7600 1450 +NoConn ~ 7600 1700 +NoConn ~ 7600 1950 +NoConn ~ 7600 2250 +$Comp +L d_and U4 +U 1 1 5CEE56F6 +P 3850 4050 +F 0 "U4" H 3850 4050 60 0000 C CNN +F 1 "d_and" H 3900 4150 60 0000 C CNN +F 2 "" H 3850 4050 60 0000 C CNN +F 3 "" H 3850 4050 60 0000 C CNN + 1 3850 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5CEE56FC +P 3850 4650 +F 0 "U5" H 3850 4650 60 0000 C CNN +F 1 "d_and" H 3900 4750 60 0000 C CNN +F 2 "" H 3850 4650 60 0000 C CNN +F 3 "" H 3850 4650 60 0000 C CNN + 1 3850 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 4600 4300 4600 +Wire Wire Line + 4350 4350 4350 4600 +Wire Wire Line + 4350 4000 4350 4250 +Wire Wire Line + 4300 4000 4350 4000 +$Comp +L d_and U7 +U 1 1 5CEE5702 +P 4800 4350 +F 0 "U7" H 4800 4350 60 0000 C CNN +F 1 "d_and" H 4850 4450 60 0000 C CNN +F 2 "" H 4800 4350 60 0000 C CNN +F 3 "" H 4800 4350 60 0000 C CNN + 1 4800 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4250 2650 4300 2650 +Wire Wire Line + 4300 3250 4250 3250 +Wire Wire Line + 4300 2650 4300 2900 +Wire Wire Line + 4300 3000 4300 3250 +$Comp +L d_and U6 +U 1 1 5CEE5432 +P 4750 3000 +F 0 "U6" H 4750 3000 60 0000 C CNN +F 1 "d_and" H 4800 3100 60 0000 C CNN +F 2 "" H 4750 3000 60 0000 C CNN +F 3 "" H 4750 3000 60 0000 C CNN + 1 4750 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5CEE540C +P 3800 3300 +F 0 "U3" H 3800 3300 60 0000 C CNN +F 1 "d_and" H 3850 3400 60 0000 C CNN +F 2 "" H 3800 3300 60 0000 C CNN +F 3 "" H 3800 3300 60 0000 C CNN + 1 3800 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5CEE53DC +P 3800 2700 +F 0 "U2" H 3800 2700 60 0000 C CNN +F 1 "d_and" H 3850 2800 60 0000 C CNN +F 2 "" H 3800 2700 60 0000 C CNN +F 3 "" H 3800 2700 60 0000 C CNN + 1 3800 2700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4012/4012.sub b/library/SubcircuitLibrary/4012/4012.sub new file mode 100644 index 00000000..65263f03 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.sub @@ -0,0 +1,38 @@ +* Subcircuit 4012 +.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir +* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter +* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +a1 net-_u6-pad3_ net-_u1-pad1_ u8 +a2 net-_u7-pad3_ net-_u1-pad13_ u9 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4012
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4012/4012_Previous_Values.xml b/library/SubcircuitLibrary/4012/4012_Previous_Values.xml new file mode 100644 index 00000000..4e7e73b2 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4012/analysis b/library/SubcircuitLibrary/4012/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4012/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4017/4017-cache.lib b/library/SubcircuitLibrary/4017/4017-cache.lib new file mode 100644 index 00000000..efa6746f --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4017/4017.cir b/library/SubcircuitLibrary/4017/4017.cir new file mode 100644 index 00000000..67ac9971 --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017.cir @@ -0,0 +1,26 @@ +* C:\esim\eSim\src\SubcircuitLibrary\4017\4017.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/19 11:20:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U7 Net-_U2-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad1_ Net-_U2-Pad2_ d_dff +U11 Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad5_ Net-_U10-Pad1_ d_dff +U15 Net-_U11-Pad5_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U12-Pad1_ d_dff +U19 Net-_U10-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U13-Pad1_ d_dff +U22 Net-_U12-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U13-Pad2_ Net-_U2-Pad1_ d_dff +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad1_ d_and +U3 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U1-Pad2_ d_and +U4 Net-_U11-Pad5_ Net-_U12-Pad1_ Net-_U1-Pad3_ d_and +U5 Net-_U10-Pad2_ Net-_U13-Pad1_ Net-_U1-Pad4_ d_and +U6 Net-_U12-Pad2_ Net-_U2-Pad1_ Net-_U1-Pad5_ d_and +U8 Net-_U13-Pad2_ Net-_U11-Pad1_ Net-_U1-Pad6_ d_and +U9 Net-_U2-Pad2_ Net-_U11-Pad5_ Net-_U1-Pad7_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad8_ d_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U1-Pad9_ d_and +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad10_ d_and + +.end diff --git a/library/SubcircuitLibrary/4017/4017.cir.out b/library/SubcircuitLibrary/4017/4017.cir.out new file mode 100644 index 00000000..e3a384c5 --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017.cir.out @@ -0,0 +1,72 @@ +* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir + +* u7 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff +* u11 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff +* u15 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff +* u19 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff +* u22 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and +* u3 net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and +* u4 net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and +* u5 net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and +* u6 net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and +* u8 net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and +* u9 net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and +a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7 +a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11 +a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15 +a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19 +a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22 +a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2 +a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3 +a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4 +a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5 +a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6 +a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8 +a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10 +a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 5e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4017/4017.pro b/library/SubcircuitLibrary/4017/4017.pro new file mode 100644 index 00000000..8cdecd6c --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017.pro @@ -0,0 +1,72 @@ +update=Fri Jun 14 10:14:54 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot + diff --git a/library/SubcircuitLibrary/4017/4017.sch b/library/SubcircuitLibrary/4017/4017.sch new file mode 100644 index 00000000..05549a32 --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017.sch @@ -0,0 +1,580 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:4017-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U7 +U 1 1 5C7B9B95 +P 2300 4100 +F 0 "U7" H 2300 4100 60 0000 C CNN +F 1 "d_dff" H 2300 4250 60 0000 C CNN +F 2 "" H 2300 4100 60 0000 C CNN +F 3 "" H 2300 4100 60 0000 C CNN + 1 2300 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U11 +U 1 1 5C7B9CEE +P 3700 4100 +F 0 "U11" H 3700 4100 60 0000 C CNN +F 1 "d_dff" H 3700 4250 60 0000 C CNN +F 2 "" H 3700 4100 60 0000 C CNN +F 3 "" H 3700 4100 60 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U15 +U 1 1 5C7B9D3E +P 5150 4100 +F 0 "U15" H 5150 4100 60 0000 C CNN +F 1 "d_dff" H 5150 4250 60 0000 C CNN +F 2 "" H 5150 4100 60 0000 C CNN +F 3 "" H 5150 4100 60 0000 C CNN + 1 5150 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U19 +U 1 1 5C7B9D85 +P 6550 4100 +F 0 "U19" H 6550 4100 60 0000 C CNN +F 1 "d_dff" H 6550 4250 60 0000 C CNN +F 2 "" H 6550 4100 60 0000 C CNN +F 3 "" H 6550 4100 60 0000 C CNN + 1 6550 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U22 +U 1 1 5C7B9DD9 +P 8050 4100 +F 0 "U22" H 8050 4100 60 0000 C CNN +F 1 "d_dff" H 8050 4250 60 0000 C CNN +F 2 "" H 8050 4100 60 0000 C CNN +F 3 "" H 8050 4100 60 0000 C CNN + 1 8050 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 4400 1500 4400 +Wire Wire Line + 1500 4400 1500 5350 +Wire Wire Line + 1500 5350 7500 5350 +Wire Wire Line + 7500 5350 7500 4400 +Wire Wire Line + 2300 4700 2300 6700 +Wire Wire Line + 2300 4900 8050 4900 +Wire Wire Line + 8050 4900 8050 4700 +Wire Wire Line + 3700 4700 3700 4900 +Connection ~ 3700 4900 +Wire Wire Line + 5150 4700 5150 4900 +Connection ~ 5150 4900 +Wire Wire Line + 6550 4700 6550 4900 +Connection ~ 6550 4900 +Wire Wire Line + 6000 4400 6000 5350 +Connection ~ 6000 5350 +Wire Wire Line + 4600 4400 4600 5350 +Connection ~ 4600 5350 +Wire Wire Line + 3150 4400 3150 5350 +Connection ~ 3150 5350 +Wire Wire Line + 2300 3450 2300 3350 +Wire Wire Line + 1550 3350 8050 3350 +Wire Wire Line + 8050 3350 8050 3450 +Wire Wire Line + 6550 3450 6550 3350 +Connection ~ 6550 3350 +Wire Wire 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950 +F 0 "U1" H 3450 1050 30 0000 C CNN +F 1 "PORT" H 3400 950 30 0000 C CNN +F 2 "" H 3400 950 60 0000 C CNN +F 3 "" H 3400 950 60 0000 C CNN + 3 3400 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C7BCAA7 +P 5850 950 +F 0 "U1" H 5900 1050 30 0000 C CNN +F 1 "PORT" H 5850 950 30 0000 C CNN +F 2 "" H 5850 950 60 0000 C CNN +F 3 "" H 5850 950 60 0000 C CNN + 7 5850 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C7BCB20 +P 6400 1000 +F 0 "U1" H 6450 1100 30 0000 C CNN +F 1 "PORT" H 6400 1000 30 0000 C CNN +F 2 "" H 6400 1000 60 0000 C CNN +F 3 "" H 6400 1000 60 0000 C CNN + 8 6400 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7BCBB1 +P 3950 950 +F 0 "U1" H 4000 1050 30 0000 C CNN +F 1 "PORT" H 3950 950 30 0000 C CNN +F 2 "" H 3950 950 60 0000 C CNN +F 3 "" H 3950 950 60 0000 C CNN + 4 3950 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 5C7BCF23 +P 7050 1000 +F 0 "U1" H 7100 1100 30 0000 C CNN +F 1 "PORT" H 7050 1000 30 0000 C CNN +F 2 "" H 7050 1000 60 0000 C CNN +F 3 "" H 7050 1000 60 0000 C CNN + 9 7050 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 5C7BCFC0 +P 4600 950 +F 0 "U1" H 4650 1050 30 0000 C CNN +F 1 "PORT" H 4600 950 30 0000 C CNN +F 2 "" H 4600 950 60 0000 C CNN +F 3 "" H 4600 950 60 0000 C CNN + 5 4600 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5C7BD0A5 +P 7750 1000 +F 0 "U1" H 7800 1100 30 0000 C CNN +F 1 "PORT" H 7750 1000 30 0000 C CNN +F 2 "" H 7750 1000 60 0000 C CNN +F 3 "" H 7750 1000 60 0000 C CNN + 10 7750 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 5C7BD5BB +P 850 6700 +F 0 "U1" H 900 6800 30 0000 C CNN +F 1 "PORT" H 850 6700 30 0000 C CNN +F 2 "" H 850 6700 60 0000 C CNN +F 3 "" H 850 6700 60 0000 C CNN + 11 850 6700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 1200 2050 1400 +Wire Wire Line + 2700 1250 2700 1400 +Wire Wire Line + 3400 1200 3400 1400 +Wire Wire Line + 3950 1200 3950 1400 +Wire Wire Line + 4600 1200 4600 1400 +Wire Wire Line + 5850 1200 5850 1400 +Wire Wire Line + 6400 1250 6400 1400 +Wire Wire Line + 7050 1250 7050 1400 +Wire Wire Line + 7750 1250 7750 1400 +$Comp +L PORT U1 +U 12 1 5C8A0119 +P 2450 7200 +F 0 "U1" H 2500 7300 30 0000 C CNN +F 1 "PORT" H 2450 7200 30 0000 C CNN +F 2 "" H 2450 7200 60 0000 C CNN +F 3 "" H 2450 7200 60 0000 C CNN + 12 2450 7200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C89F7BC +P 2100 1850 +F 0 "U2" H 2100 1850 60 0000 C CNN +F 1 "d_and" H 2150 1950 60 0000 C CNN +F 2 "" H 2100 1850 60 0000 C CNN +F 3 "" H 2100 1850 60 0000 C CNN + 1 2100 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5C89FA46 +P 2750 1850 +F 0 "U3" H 2750 1850 60 0000 C CNN +F 1 "d_and" H 2800 1950 60 0000 C CNN +F 2 "" H 2750 1850 60 0000 C CNN +F 3 "" H 2750 1850 60 0000 C CNN + 1 2750 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U4 +U 1 1 5C89FAD5 +P 3450 1850 +F 0 "U4" H 3450 1850 60 0000 C CNN +F 1 "d_and" H 3500 1950 60 0000 C CNN +F 2 "" H 3450 1850 60 0000 C CNN +F 3 "" H 3450 1850 60 0000 C CNN + 1 3450 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U5 +U 1 1 5C89FB62 +P 4000 1850 +F 0 "U5" H 4000 1850 60 0000 C CNN +F 1 "d_and" H 4050 1950 60 0000 C CNN +F 2 "" H 4000 1850 60 0000 C CNN +F 3 "" H 4000 1850 60 0000 C CNN + 1 4000 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U6 +U 1 1 5C89FEBF +P 4650 1850 +F 0 "U6" H 4650 1850 60 0000 C CNN +F 1 "d_and" H 4700 1950 60 0000 C CNN +F 2 "" H 4650 1850 60 0000 C CNN +F 3 "" H 4650 1850 60 0000 C CNN + 1 4650 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U8 +U 1 1 5C89FF2C +P 5350 1850 +F 0 "U8" H 5350 1850 60 0000 C CNN +F 1 "d_and" H 5400 1950 60 0000 C CNN +F 2 "" H 5350 1850 60 0000 C CNN +F 3 "" H 5350 1850 60 0000 C CNN + 1 5350 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U9 +U 1 1 5C89FF96 +P 5900 1850 +F 0 "U9" H 5900 1850 60 0000 C CNN +F 1 "d_and" H 5950 1950 60 0000 C CNN +F 2 "" H 5900 1850 60 0000 C CNN +F 3 "" H 5900 1850 60 0000 C CNN + 1 5900 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U10 +U 1 1 5C8A066D +P 6450 1850 +F 0 "U10" H 6450 1850 60 0000 C CNN +F 1 "d_and" H 6500 1950 60 0000 C CNN +F 2 "" H 6450 1850 60 0000 C CNN +F 3 "" H 6450 1850 60 0000 C CNN + 1 6450 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U12 +U 1 1 5C8A06D8 +P 7100 1850 +F 0 "U12" H 7100 1850 60 0000 C CNN +F 1 "d_and" H 7150 1950 60 0000 C CNN +F 2 "" H 7100 1850 60 0000 C CNN +F 3 "" H 7100 1850 60 0000 C CNN + 1 7100 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U13 +U 1 1 5C8A12F5 +P 7800 1850 +F 0 "U13" H 7800 1850 60 0000 C CNN +F 1 "d_and" H 7850 1950 60 0000 C CNN +F 2 "" H 7800 1850 60 0000 C CNN +F 3 "" H 7800 1850 60 0000 C CNN + 1 7800 1850 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4017/4017.sub b/library/SubcircuitLibrary/4017/4017.sub new file mode 100644 index 00000000..2e27ab61 --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017.sub @@ -0,0 +1,66 @@ +* Subcircuit 4017 +.subckt 4017 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ +* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir +* u7 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff +* u11 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff +* u15 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff +* u19 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff +* u22 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and +* u3 net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and +* u4 net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and +* u5 net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and +* u6 net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and +* u8 net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and +* u9 net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and +a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7 +a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11 +a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15 +a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19 +a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22 +a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2 +a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3 +a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4 +a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5 +a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6 +a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8 +a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10 +a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4017
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4017/4017_Previous_Values.xml b/library/SubcircuitLibrary/4017/4017_Previous_Values.xml new file mode 100644 index 00000000..9dfd97a3 --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u7 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u7><u11 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u11><u15 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u19 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u22><u9 name="type">d_nand<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u9><u13 name="type">d_nor<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u13><u5 name="type">d_nand<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u5><u8 name="type">d_nand<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_nand<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_nand<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u12><u14 name="type">d_nand<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_nand<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_nand<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_nand<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u18><u20 name="type">d_nand<field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_nand<field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /></u21><u4 name="type">d_inverter<field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_inverter<field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /></u6><u23 name="type">d_inverter<field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /></u23><u24 name="type">d_buffer<field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /></u24><u2 name="type">d_and<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_and<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_and<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4017/D.lib b/library/SubcircuitLibrary/4017/D.lib new file mode 100644 index 00000000..adbdfb35 --- /dev/null +++ b/library/SubcircuitLibrary/4017/D.lib @@ -0,0 +1,11 @@ +.MODEL 1N4148 D( ++ Vj=1 ++ Cjo=1.700E-12 ++ Rs=4.755E-01 ++ Is=2.495E-09 ++ M=1.959E-01 ++ N=1.679E+00 ++ Bv=1.000E+02 ++ tt=3.030E-09 ++ Ibv=1.000E-04 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4017/analysis b/library/SubcircuitLibrary/4017/analysis new file mode 100644 index 00000000..40bd9d97 --- /dev/null +++ b/library/SubcircuitLibrary/4017/analysis @@ -0,0 +1 @@ +.tran 5e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4023/3_and-cache.lib b/library/SubcircuitLibrary/4023/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4023/3_and.cir b/library/SubcircuitLibrary/4023/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/4023/3_and.cir.out b/library/SubcircuitLibrary/4023/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4023/3_and.pro b/library/SubcircuitLibrary/4023/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/4023/3_and.sch b/library/SubcircuitLibrary/4023/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4023/3_and.sub b/library/SubcircuitLibrary/4023/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4023/3_and_Previous_Values.xml b/library/SubcircuitLibrary/4023/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4023/4023-cache.lib b/library/SubcircuitLibrary/4023/4023-cache.lib new file mode 100644 index 00000000..c989d8c7 --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4023/4023.cir b/library/SubcircuitLibrary/4023/4023.cir new file mode 100644 index 00000000..6aad9b84 --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023.cir @@ -0,0 +1,17 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4023\4023.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 15:33:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X3 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and +U4 Net-_U4-Pad1_ Net-_U1-Pad10_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U3 Net-_U3-Pad1_ Net-_U1-Pad6_ d_inverter +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad9_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/4023/4023.cir.out b/library/SubcircuitLibrary/4023/4023.cir.out new file mode 100644 index 00000000..7f48d16f --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023.cir.out @@ -0,0 +1,28 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir + +.include 3_and.sub +x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and +* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter +a1 net-_u4-pad1_ net-_u1-pad10_ u4 +a2 net-_u3-pad1_ net-_u1-pad6_ u3 +a3 net-_u2-pad1_ net-_u1-pad9_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4023/4023.pro b/library/SubcircuitLibrary/4023/4023.pro new file mode 100644 index 00000000..5a5ce355 --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:32:35 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/4023/4023.sch b/library/SubcircuitLibrary/4023/4023.sch new file mode 100644 index 00000000..57dd7868 --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023.sch @@ -0,0 +1,309 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X3 +U 1 1 5CF0FA82 +P 4800 2500 +F 0 "X3" H 4900 2450 60 0000 C CNN +F 1 "3_and" H 4950 2650 60 0000 C CNN +F 2 "" H 4800 2500 60 0000 C CNN +F 3 "" H 4800 2500 60 0000 C CNN + 1 4800 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF0FB13 +P 6150 2450 +F 0 "U4" H 6150 2350 60 0000 C CNN +F 1 "d_inverter" H 6150 2600 60 0000 C CNN +F 2 "" H 6200 2400 60 0000 C CNN +F 3 "" H 6200 2400 60 0000 C CNN + 1 6150 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF0FB34 +P 3100 1950 +F 0 "U1" H 3150 2050 30 0000 C CNN +F 1 "PORT" H 3100 1950 30 0000 C CNN +F 2 "" H 3100 1950 60 0000 C CNN +F 3 "" H 3100 1950 60 0000 C CNN + 11 3100 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF0FB90 +P 3100 2350 +F 0 "U1" H 3150 2450 30 0000 C CNN +F 1 "PORT" H 3100 2350 30 0000 C CNN +F 2 "" H 3100 2350 60 0000 C CNN +F 3 "" H 3100 2350 60 0000 C CNN + 12 3100 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF0FBB8 +P 3100 2750 +F 0 "U1" H 3150 2850 30 0000 C CNN +F 1 "PORT" H 3100 2750 30 0000 C CNN +F 2 "" H 3100 2750 60 0000 C CNN +F 3 "" H 3100 2750 60 0000 C CNN + 13 3100 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF0FBED +P 7800 2450 +F 0 "U1" H 7850 2550 30 0000 C CNN +F 1 "PORT" H 7800 2450 30 0000 C CNN +F 2 "" H 7800 2450 60 0000 C CNN +F 3 "" H 7800 2450 60 0000 C CNN + 10 7800 2450 + -1 0 0 1 +$EndComp +Wire Wire Line + 7550 2450 6450 2450 +Wire Wire Line + 5850 2450 5300 2450 +Wire Wire Line + 4450 2350 4450 1950 +Wire Wire Line + 4450 1950 3350 1950 +Wire Wire Line + 4450 2450 4100 2450 +Wire Wire Line + 4100 2450 4100 2350 +Wire Wire Line + 4100 2350 3350 2350 +Wire Wire Line + 3350 2750 3950 2750 +Wire Wire Line + 3950 2750 3950 2550 +Wire Wire Line + 3950 2550 4450 2550 +$Comp +L 3_and X2 +U 1 1 5CF0FF35 +P 4700 3800 +F 0 "X2" H 4800 3750 60 0000 C CNN +F 1 "3_and" H 4850 3950 60 0000 C CNN +F 2 "" H 4700 3800 60 0000 C CNN +F 3 "" H 4700 3800 60 0000 C CNN + 1 4700 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5CF0FF3B +P 6050 3750 +F 0 "U3" H 6050 3650 60 0000 C CNN +F 1 "d_inverter" H 6050 3900 60 0000 C CNN +F 2 "" H 6100 3700 60 0000 C CNN +F 3 "" H 6100 3700 60 0000 C CNN + 1 6050 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF0FF41 +P 3000 3250 +F 0 "U1" H 3050 3350 30 0000 C CNN +F 1 "PORT" H 3000 3250 30 0000 C CNN +F 2 "" H 3000 3250 60 0000 C CNN +F 3 "" H 3000 3250 60 0000 C CNN + 4 3000 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF0FF47 +P 3000 3650 +F 0 "U1" H 3050 3750 30 0000 C CNN +F 1 "PORT" H 3000 3650 30 0000 C CNN +F 2 "" H 3000 3650 60 0000 C CNN +F 3 "" H 3000 3650 60 0000 C CNN + 5 3000 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF0FF4D +P 3000 4050 +F 0 "U1" H 3050 4150 30 0000 C CNN +F 1 "PORT" H 3000 4050 30 0000 C CNN +F 2 "" H 3000 4050 60 0000 C CNN +F 3 "" H 3000 4050 60 0000 C CNN + 3 3000 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF0FF53 +P 7700 3750 +F 0 "U1" H 7750 3850 30 0000 C CNN +F 1 "PORT" H 7700 3750 30 0000 C CNN +F 2 "" H 7700 3750 60 0000 C CNN +F 3 "" H 7700 3750 60 0000 C CNN + 6 7700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 7450 3750 6350 3750 +Wire Wire Line + 5750 3750 5200 3750 +Wire Wire Line + 4350 3650 4350 3250 +Wire Wire Line + 4350 3250 3250 3250 +Wire Wire Line + 4350 3750 4000 3750 +Wire Wire Line + 4000 3750 4000 3650 +Wire Wire Line + 4000 3650 3250 3650 +Wire Wire Line + 3250 4050 3850 4050 +Wire Wire Line + 3850 4050 3850 3850 +Wire Wire Line + 3850 3850 4350 3850 +$Comp +L 3_and X1 +U 1 1 5CF100B9 +P 4650 5100 +F 0 "X1" H 4750 5050 60 0000 C CNN +F 1 "3_and" H 4800 5250 60 0000 C CNN +F 2 "" H 4650 5100 60 0000 C CNN +F 3 "" H 4650 5100 60 0000 C CNN + 1 4650 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5CF100BF +P 6000 5050 +F 0 "U2" H 6000 4950 60 0000 C CNN +F 1 "d_inverter" H 6000 5200 60 0000 C CNN +F 2 "" H 6050 5000 60 0000 C CNN +F 3 "" H 6050 5000 60 0000 C CNN + 1 6000 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF100C5 +P 2950 4550 +F 0 "U1" H 3000 4650 30 0000 C CNN +F 1 "PORT" H 2950 4550 30 0000 C CNN +F 2 "" H 2950 4550 60 0000 C CNN +F 3 "" H 2950 4550 60 0000 C CNN + 1 2950 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF100CB +P 2950 4950 +F 0 "U1" H 3000 5050 30 0000 C CNN +F 1 "PORT" H 2950 4950 30 0000 C CNN +F 2 "" H 2950 4950 60 0000 C CNN +F 3 "" H 2950 4950 60 0000 C CNN + 2 2950 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF100D1 +P 2950 5350 +F 0 "U1" H 3000 5450 30 0000 C CNN +F 1 "PORT" H 2950 5350 30 0000 C CNN +F 2 "" H 2950 5350 60 0000 C CNN +F 3 "" H 2950 5350 60 0000 C CNN + 8 2950 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF100D7 +P 7650 5050 +F 0 "U1" H 7700 5150 30 0000 C CNN +F 1 "PORT" H 7650 5050 30 0000 C CNN +F 2 "" H 7650 5050 60 0000 C CNN +F 3 "" H 7650 5050 60 0000 C CNN + 9 7650 5050 + -1 0 0 1 +$EndComp +Wire Wire Line + 7400 5050 6300 5050 +Wire Wire Line + 5700 5050 5150 5050 +Wire Wire Line + 4300 4950 4300 4550 +Wire Wire Line + 4300 4550 3200 4550 +Wire Wire Line + 4300 5050 3950 5050 +Wire Wire Line + 3950 5050 3950 4950 +Wire Wire Line + 3950 4950 3200 4950 +Wire Wire Line + 3200 5350 3800 5350 +Wire Wire Line + 3800 5350 3800 5150 +Wire Wire Line + 3800 5150 4300 5150 +$Comp +L PORT U1 +U 7 1 5CF101BF +P 9950 3350 +F 0 "U1" H 10000 3450 30 0000 C CNN +F 1 "PORT" H 9950 3350 30 0000 C CNN +F 2 "" H 9950 3350 60 0000 C CNN +F 3 "" H 9950 3350 60 0000 C CNN + 7 9950 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF1025C +P 9950 3900 +F 0 "U1" H 10000 4000 30 0000 C CNN +F 1 "PORT" H 9950 3900 30 0000 C CNN +F 2 "" H 9950 3900 60 0000 C CNN +F 3 "" H 9950 3900 60 0000 C CNN + 14 9950 3900 + -1 0 0 1 +$EndComp +NoConn ~ 9700 3350 +NoConn ~ 9700 3900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4023/4023.sub b/library/SubcircuitLibrary/4023/4023.sub new file mode 100644 index 00000000..b953da2e --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023.sub @@ -0,0 +1,22 @@ +* Subcircuit 4023 +.subckt 4023 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir +.include 3_and.sub +x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and +* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter +a1 net-_u4-pad1_ net-_u1-pad10_ u4 +a2 net-_u3-pad1_ net-_u1-pad6_ u3 +a3 net-_u2-pad1_ net-_u1-pad9_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4023
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4023/4023_Previous_Values.xml b/library/SubcircuitLibrary/4023/4023_Previous_Values.xml new file mode 100644 index 00000000..ad900de2 --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u4 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4023/analysis b/library/SubcircuitLibrary/4023/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4023/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4028/4028-cache.lib b/library/SubcircuitLibrary/4028/4028-cache.lib new file mode 100644 index 00000000..5b7e8ebd --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4028/4028.cir b/library/SubcircuitLibrary/4028/4028.cir new file mode 100644 index 00000000..ff25eb55 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U9 Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor +U10 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor +U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor +U6 Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor +U7 Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor +U8 Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor +U2 Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter +U3 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter +U4 Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter +U15 Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and +U16 Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and +U17 Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and +U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and +U19 Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and +U20 Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and +U21 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and +U13 Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U22 Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and + +.end diff --git a/library/SubcircuitLibrary/4028/4028.cir.out b/library/SubcircuitLibrary/4028/4028.cir.out new file mode 100644 index 00000000..882115b7 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028.cir.out @@ -0,0 +1,96 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir + +* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor +* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor +* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor +* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor +* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor +* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor +* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter +* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter +* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and +* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and +* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and +* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and +* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and +* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and +a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9 +a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12 +a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6 +a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7 +a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8 +a8 net-_u1-pad10_ net-_u11-pad1_ u2 +a9 net-_u1-pad13_ net-_u10-pad2_ u3 +a10 net-_u1-pad12_ net-_u4-pad2_ u4 +a11 net-_u1-pad11_ net-_u5-pad2_ u5 +a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15 +a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16 +a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17 +a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18 +a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19 +a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20 +a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21 +a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13 +a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14 +a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4028/4028.pro b/library/SubcircuitLibrary/4028/4028.pro new file mode 100644 index 00000000..a63207b3 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:43:40 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/4028/4028.sch b/library/SubcircuitLibrary/4028/4028.sch new file mode 100644 index 00000000..373a95e6 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028.sch @@ -0,0 +1,628 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nor U9 +U 1 1 5CF0FE64 +P 3750 2500 +F 0 "U9" H 3750 2500 60 0000 C CNN +F 1 "d_nor" H 3800 2600 60 0000 C CNN +F 2 "" H 3750 2500 60 0000 C CNN +F 3 "" H 3750 2500 60 0000 C CNN + 1 3750 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U10 +U 1 1 5CF0FEA4 +P 3750 3050 +F 0 "U10" H 3750 3050 60 0000 C CNN +F 1 "d_nor" H 3800 3150 60 0000 C CNN +F 2 "" H 3750 3050 60 0000 C CNN +F 3 "" H 3750 3050 60 0000 C CNN + 1 3750 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U11 +U 1 1 5CF0FECC +P 3750 3550 +F 0 "U11" H 3750 3550 60 0000 C CNN +F 1 "d_nor" H 3800 3650 60 0000 C CNN +F 2 "" H 3750 3550 60 0000 C CNN +F 3 "" H 3750 3550 60 0000 C CNN + 1 3750 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U12 +U 1 1 5CF0FEF5 +P 3750 4150 +F 0 "U12" H 3750 4150 60 0000 C CNN +F 1 "d_nor" H 3800 4250 60 0000 C CNN +F 2 "" H 3750 4150 60 0000 C CNN +F 3 "" H 3750 4150 60 0000 C CNN + 1 3750 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 5CF0FF23 +P 3700 4750 +F 0 "U6" H 3700 4750 60 0000 C CNN +F 1 "d_nor" H 3750 4850 60 0000 C CNN +F 2 "" H 3700 4750 60 0000 C CNN +F 3 "" H 3700 4750 60 0000 C CNN + 1 3700 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 5CF0FF59 +P 3700 5250 +F 0 "U7" H 3700 5250 60 0000 C CNN +F 1 "d_nor" H 3750 5350 60 0000 C CNN +F 2 "" H 3700 5250 60 0000 C CNN +F 3 "" H 3700 5250 60 0000 C CNN + 1 3700 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U8 +U 1 1 5CF0FFA9 +P 3750 2000 +F 0 "U8" H 3750 2000 60 0000 C CNN +F 1 "d_nor" H 3800 2100 60 0000 C CNN +F 2 "" H 3750 2000 60 0000 C CNN +F 3 "" H 3750 2000 60 0000 C CNN + 1 3750 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5CF1003A +P 2150 2400 +F 0 "U2" H 2150 2300 60 0000 C CNN +F 1 "d_inverter" H 2150 2550 60 0000 C CNN +F 2 "" H 2200 2350 60 0000 C CNN +F 3 "" H 2200 2350 60 0000 C CNN + 1 2150 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5CF1007F +P 2150 3300 +F 0 "U3" H 2150 3200 60 0000 C CNN +F 1 "d_inverter" H 2150 3450 60 0000 C CNN +F 2 "" H 2200 3250 60 0000 C CNN +F 3 "" H 2200 3250 60 0000 C CNN + 1 2150 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF100CC +P 2150 4150 +F 0 "U4" H 2150 4050 60 0000 C CNN +F 1 "d_inverter" H 2150 4300 60 0000 C CNN +F 2 "" H 2200 4100 60 0000 C CNN +F 3 "" H 2200 4100 60 0000 C CNN + 1 2150 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5CF10114 +P 2150 4900 +F 0 "U5" H 2150 4800 60 0000 C CNN +F 1 "d_inverter" H 2150 5050 60 0000 C CNN +F 2 "" H 2200 4850 60 0000 C CNN +F 3 "" H 2200 4850 60 0000 C CNN + 1 2150 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2400 1850 2400 +Wire Wire Line + 1400 3300 1850 3300 +Wire Wire Line + 1450 4150 1850 4150 +Wire Wire Line + 1450 4900 1850 4900 +Wire Wire Line + 2450 4900 2500 4900 +Wire Wire Line + 2500 4900 2500 5250 +Wire Wire Line + 2500 5250 3250 5250 +Wire Wire Line + 2450 4150 2550 4150 +Wire Wire Line + 2550 4150 2550 4650 +Wire Wire Line + 2550 4650 3250 4650 +Wire Wire Line + 2450 3300 2550 3300 +Wire Wire Line + 2550 3300 2550 3550 +Wire Wire Line + 2550 3550 3300 3550 +Wire Wire Line + 2450 2400 2450 2500 +Wire Wire Line + 2450 2500 3300 2500 +Wire Wire Line + 2800 2500 2800 3450 +Wire Wire Line + 2800 3450 3300 3450 +Connection ~ 2800 2500 +Wire Wire Line + 1650 2400 1650 1900 +Wire Wire Line + 1650 1900 3300 1900 +Connection ~ 1650 2400 +Wire Wire Line + 3300 2000 2850 2000 +Wire Wire Line + 2850 2000 2850 3000 +Wire Wire Line + 2850 3000 1650 3000 +Wire Wire Line + 1650 3000 1650 3300 +Connection ~ 1650 3300 +Wire Wire Line + 2850 2400 3300 2400 +Connection ~ 2850 2400 +Wire Wire Line + 2950 1900 2950 2950 +Wire Wire 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60 0000 C CNN +F 3 "" H 6600 2350 60 0000 C CNN + 1 6600 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 5CF107A1 +P 6600 2800 +F 0 "U17" H 6600 2800 60 0000 C CNN +F 1 "d_and" H 6650 2900 60 0000 C CNN +F 2 "" H 6600 2800 60 0000 C CNN +F 3 "" H 6600 2800 60 0000 C CNN + 1 6600 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5CF107E9 +P 6600 3200 +F 0 "U18" H 6600 3200 60 0000 C CNN +F 1 "d_and" H 6650 3300 60 0000 C CNN +F 2 "" H 6600 3200 60 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5CF10834 +P 6600 3650 +F 0 "U19" H 6600 3650 60 0000 C CNN +F 1 "d_and" H 6650 3750 60 0000 C CNN +F 2 "" H 6600 3650 60 0000 C CNN +F 3 "" H 6600 3650 60 0000 C CNN + 1 6600 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 5CF1087E +P 6600 4050 +F 0 "U20" H 6600 4050 60 0000 C CNN +F 1 "d_and" H 6650 4150 60 0000 C CNN +F 2 "" H 6600 4050 60 0000 C CNN +F 3 "" H 6600 4050 60 0000 C CNN + 1 6600 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 5CF108F9 +P 6600 4450 +F 0 "U21" H 6600 4450 60 0000 C CNN +F 1 "d_and" H 6650 4550 60 0000 C CNN +F 2 "" H 6600 4450 60 0000 C CNN +F 3 "" H 6600 4450 60 0000 C CNN + 1 6600 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 5CF1094D +P 6550 4900 +F 0 "U13" H 6550 4900 60 0000 C CNN +F 1 "d_and" H 6600 5000 60 0000 C CNN +F 2 "" H 6550 4900 60 0000 C CNN +F 3 "" H 6550 4900 60 0000 C CNN + 1 6550 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 5CF109A6 +P 6550 5350 +F 0 "U14" H 6550 5350 60 0000 C CNN +F 1 "d_and" H 6600 5450 60 0000 C CNN +F 2 "" H 6550 5350 60 0000 C CNN +F 3 "" H 6550 5350 60 0000 C CNN + 1 6550 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF11966 +P 1150 2400 +F 0 "U1" H 1200 2500 30 0000 C CNN +F 1 "PORT" H 1150 2400 30 0000 C CNN +F 2 "" H 1150 2400 60 0000 C CNN +F 3 "" H 1150 2400 60 0000 C CNN + 10 1150 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF119D4 +P 1150 3300 +F 0 "U1" H 1200 3400 30 0000 C CNN +F 1 "PORT" H 1150 3300 30 0000 C CNN +F 2 "" H 1150 3300 60 0000 C CNN +F 3 "" H 1150 3300 60 0000 C CNN + 13 1150 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF11AFC +P 1200 4150 +F 0 "U1" H 1250 4250 30 0000 C CNN +F 1 "PORT" H 1200 4150 30 0000 C CNN +F 2 "" H 1200 4150 60 0000 C CNN +F 3 "" H 1200 4150 60 0000 C CNN + 12 1200 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF11B6B +P 1200 4900 +F 0 "U1" H 1250 5000 30 0000 C CNN +F 1 "PORT" H 1200 4900 30 0000 C CNN +F 2 "" H 1200 4900 60 0000 C CNN +F 3 "" H 1200 4900 60 0000 C CNN + 11 1200 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF11BDB +P 8000 1800 +F 0 "U1" H 8050 1900 30 0000 C CNN +F 1 "PORT" H 8000 1800 30 0000 C CNN +F 2 "" H 8000 1800 60 0000 C CNN +F 3 "" H 8000 1800 60 0000 C CNN + 3 8000 1800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF11F59 +P 8000 2300 +F 0 "U1" H 8050 2400 30 0000 C CNN +F 1 "PORT" H 8000 2300 30 0000 C CNN +F 2 "" H 8000 2300 60 0000 C CNN +F 3 "" H 8000 2300 60 0000 C CNN + 14 8000 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF11FC5 +P 8000 2750 +F 0 "U1" H 8050 2850 30 0000 C CNN +F 1 "PORT" H 8000 2750 30 0000 C CNN +F 2 "" H 8000 2750 60 0000 C CNN +F 3 "" H 8000 2750 60 0000 C CNN + 2 8000 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 5CF1204F +P 8000 3150 +F 0 "U1" H 8050 3250 30 0000 C CNN +F 1 "PORT" H 8000 3150 30 0000 C CNN +F 2 "" H 8000 3150 60 0000 C CNN +F 3 "" H 8000 3150 60 0000 C CNN + 15 8000 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF120C5 +P 7950 3600 +F 0 "U1" H 8000 3700 30 0000 C CNN +F 1 "PORT" H 7950 3600 30 0000 C CNN +F 2 "" H 7950 3600 60 0000 C CNN +F 3 "" H 7950 3600 60 0000 C CNN + 1 7950 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF1213C +P 7950 4000 +F 0 "U1" H 8000 4100 30 0000 C CNN +F 1 "PORT" H 7950 4000 30 0000 C CNN +F 2 "" H 7950 4000 60 0000 C CNN +F 3 "" H 7950 4000 60 0000 C CNN + 6 7950 4000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CF121B2 +P 7900 4400 +F 0 "U1" H 7950 4500 30 0000 C CNN +F 1 "PORT" H 7900 4400 30 0000 C CNN +F 2 "" H 7900 4400 60 0000 C CNN +F 3 "" H 7900 4400 60 0000 C CNN + 7 7900 4400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF1223D +P 7900 4850 +F 0 "U1" H 7950 4950 30 0000 C CNN +F 1 "PORT" H 7900 4850 30 0000 C CNN +F 2 "" H 7900 4850 60 0000 C CNN +F 3 "" H 7900 4850 60 0000 C CNN + 4 7900 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF1237B +P 7900 5300 +F 0 "U1" H 7950 5400 30 0000 C CNN +F 1 "PORT" H 7900 5300 30 0000 C CNN +F 2 "" H 7900 5300 60 0000 C CNN +F 3 "" H 7900 5300 60 0000 C CNN + 9 7900 5300 + -1 0 0 1 +$EndComp +Wire Wire Line + 7750 1800 7050 1800 +Wire Wire Line + 7050 2300 7750 2300 +Wire Wire Line + 7750 2750 7050 2750 +Wire Wire Line + 7050 3150 7750 3150 +Wire Wire Line + 7700 3600 7050 3600 +Wire Wire Line + 7050 4000 7700 4000 +Wire Wire Line + 7650 4400 7050 4400 +Wire Wire Line + 7000 4850 7650 4850 +Wire Wire Line + 7650 5300 7000 5300 +$Comp +L d_and U22 +U 1 1 5CF14904 +P 6550 5800 +F 0 "U22" H 6550 5800 60 0000 C CNN +F 1 "d_and" H 6600 5900 60 0000 C CNN +F 2 "" H 6550 5800 60 0000 C CNN +F 3 "" H 6550 5800 60 0000 C CNN + 1 6550 5800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 1950 4600 1950 +Wire Wire Line + 4600 1750 4600 5250 +Wire Wire Line + 4600 1750 6150 1750 +Wire Wire Line + 4600 5250 6100 5250 +Connection ~ 4600 1950 +Wire Wire Line + 6100 5800 5900 5800 +Wire Wire Line + 5900 5800 5900 5350 +Wire Wire Line + 5900 5350 6100 5350 +Wire Wire Line + 5850 4900 6100 4900 +Wire Wire Line + 5850 3650 5850 4900 +Wire Wire Line + 5850 4450 6150 4450 +Wire Wire Line + 5850 4050 6150 4050 +Connection ~ 5850 4450 +Wire Wire Line + 5850 3650 6150 3650 +Connection ~ 5850 4050 +Wire Wire Line + 5050 3200 6150 3200 +Wire Wire Line + 5850 1850 5850 3200 +Wire Wire Line + 5850 2800 6150 2800 +Wire Wire Line + 5850 2350 6150 2350 +Connection ~ 5850 2800 +Wire Wire Line + 5850 1850 6150 1850 +Connection ~ 5850 2350 +Wire Wire Line + 4200 2450 4700 2450 +Wire Wire Line + 4700 2250 4700 5700 +Wire Wire Line + 4700 2250 6150 2250 +Wire Wire Line + 4200 3000 4800 3000 +Wire Wire Line + 4800 2700 4800 4350 +Wire Wire Line + 4800 2700 6150 2700 +Wire Wire Line + 4700 5700 6100 5700 +Connection ~ 4700 2450 +Wire Wire Line + 6150 3550 4600 3550 +Connection ~ 4600 3550 +Wire Wire Line + 6150 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4800 4350 6150 4350 +Connection ~ 4800 3000 +Wire Wire Line + 4200 3500 4900 3500 +Wire Wire Line + 4900 3100 4900 4800 +Wire Wire Line + 4900 3100 6150 3100 +Wire Wire Line + 4900 4800 6100 4800 +Connection ~ 4900 3500 +Wire Wire Line + 4200 4100 5050 4100 +Wire Wire Line + 5050 4100 5050 3200 +Connection ~ 5850 3200 +Wire Wire Line + 4150 4700 5850 4700 +Connection ~ 5850 4700 +Wire Wire Line + 4150 5200 4500 5200 +Wire Wire Line + 4500 5200 4500 5550 +Wire Wire Line + 4500 5550 5900 5550 +Connection ~ 5900 5550 +$Comp +L PORT U1 +U 5 1 5CF1563E +P 7950 5750 +F 0 "U1" H 8000 5850 30 0000 C CNN +F 1 "PORT" H 7950 5750 30 0000 C CNN +F 2 "" H 7950 5750 60 0000 C CNN +F 3 "" H 7950 5750 60 0000 C CNN + 5 7950 5750 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 5750 7000 5750 +$Comp +L PORT U1 +U 8 1 5CF15953 +P 9550 4800 +F 0 "U1" H 9600 4900 30 0000 C CNN +F 1 "PORT" H 9550 4800 30 0000 C CNN +F 2 "" H 9550 4800 60 0000 C CNN +F 3 "" H 9550 4800 60 0000 C CNN + 8 9550 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 5CF15A07 +P 9550 5250 +F 0 "U1" H 9600 5350 30 0000 C CNN +F 1 "PORT" H 9550 5250 30 0000 C CNN +F 2 "" H 9550 5250 60 0000 C CNN +F 3 "" H 9550 5250 60 0000 C CNN + 16 9550 5250 + -1 0 0 1 +$EndComp +NoConn ~ 9300 4800 +NoConn ~ 9300 5250 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4028/4028.sub b/library/SubcircuitLibrary/4028/4028.sub new file mode 100644 index 00000000..828e0b67 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028.sub @@ -0,0 +1,90 @@ +* Subcircuit 4028 +.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir +* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor +* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor +* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor +* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor +* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor +* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor +* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter +* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter +* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and +* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and +* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and +* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and +* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and +* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and +* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and +a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9 +a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12 +a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6 +a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7 +a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8 +a8 net-_u1-pad10_ net-_u11-pad1_ u2 +a9 net-_u1-pad13_ net-_u10-pad2_ u3 +a10 net-_u1-pad12_ net-_u4-pad2_ u4 +a11 net-_u1-pad11_ net-_u5-pad2_ u5 +a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15 +a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16 +a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17 +a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18 +a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19 +a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20 +a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21 +a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13 +a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14 +a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4028
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4028/4028_Previous_Values.xml b/library/SubcircuitLibrary/4028/4028_Previous_Values.xml new file mode 100644 index 00000000..189fb200 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4028/analysis b/library/SubcircuitLibrary/4028/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4028/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4073/3_and-cache.lib b/library/SubcircuitLibrary/4073/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4073/3_and.cir b/library/SubcircuitLibrary/4073/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/4073/3_and.cir.out b/library/SubcircuitLibrary/4073/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4073/3_and.pro b/library/SubcircuitLibrary/4073/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/4073/3_and.sch b/library/SubcircuitLibrary/4073/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4073/3_and.sub b/library/SubcircuitLibrary/4073/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4073/3_and_Previous_Values.xml b/library/SubcircuitLibrary/4073/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4073/4073-cache.lib b/library/SubcircuitLibrary/4073/4073-cache.lib new file mode 100644 index 00000000..4ee605a2 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4073/4073.cir b/library/SubcircuitLibrary/4073/4073.cir new file mode 100644 index 00000000..e159f055 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and +X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and + +.end diff --git a/library/SubcircuitLibrary/4073/4073.cir.out b/library/SubcircuitLibrary/4073/4073.cir.out new file mode 100644 index 00000000..b25337cd --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073.cir.out @@ -0,0 +1,16 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4073/4073.pro b/library/SubcircuitLibrary/4073/4073.pro new file mode 100644 index 00000000..94cd9bd4 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073.pro @@ -0,0 +1,43 @@ +update=05/31/19 16:37:06 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/4073/4073.sch b/library/SubcircuitLibrary/4073/4073.sch new file mode 100644 index 00000000..045208e6 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073.sch @@ -0,0 +1,263 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5CF10AEA +P 4550 2650 +F 0 "X1" H 4650 2600 60 0000 C CNN +F 1 "3_and" H 4700 2800 60 0000 C CNN +F 2 "" H 4550 2650 60 0000 C CNN +F 3 "" H 4550 2650 60 0000 C CNN + 1 4550 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF10B72 +P 3100 2200 +F 0 "U1" H 3150 2300 30 0000 C CNN +F 1 "PORT" H 3100 2200 30 0000 C CNN +F 2 "" H 3100 2200 60 0000 C CNN +F 3 "" H 3100 2200 60 0000 C CNN + 1 3100 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF10BC9 +P 3100 2500 +F 0 "U1" H 3150 2600 30 0000 C CNN +F 1 "PORT" H 3100 2500 30 0000 C CNN +F 2 "" H 3100 2500 60 0000 C CNN +F 3 "" H 3100 2500 60 0000 C CNN + 2 3100 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF10BEA +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 8 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF10C10 +P 6200 2600 +F 0 "U1" H 6250 2700 30 0000 C CNN +F 1 "PORT" H 6200 2600 30 0000 C CNN +F 2 "" H 6200 2600 60 0000 C CNN +F 3 "" H 6200 2600 60 0000 C CNN + 9 6200 2600 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2600 5050 2600 +Wire Wire Line + 4200 2500 4200 2200 +Wire Wire Line + 4200 2200 3350 2200 +Wire Wire Line + 3350 2500 3850 2500 +Wire Wire Line + 3850 2500 3850 2600 +Wire Wire Line + 3850 2600 4200 2600 +Wire Wire Line + 4200 2700 4200 2850 +Wire Wire Line + 4200 2850 3350 2850 +$Comp +L 3_and X3 +U 1 1 5CF10DE5 +P 4600 4100 +F 0 "X3" H 4700 4050 60 0000 C CNN +F 1 "3_and" H 4750 4250 60 0000 C CNN +F 2 "" H 4600 4100 60 0000 C CNN +F 3 "" H 4600 4100 60 0000 C CNN + 1 4600 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF10DEB +P 3150 3650 +F 0 "U1" H 3200 3750 30 0000 C CNN +F 1 "PORT" H 3150 3650 30 0000 C CNN +F 2 "" H 3150 3650 60 0000 C CNN +F 3 "" H 3150 3650 60 0000 C CNN + 3 3150 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF10DF1 +P 3150 3950 +F 0 "U1" H 3200 4050 30 0000 C CNN +F 1 "PORT" H 3150 3950 30 0000 C CNN +F 2 "" H 3150 3950 60 0000 C CNN +F 3 "" H 3150 3950 60 0000 C CNN + 4 3150 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF10DF7 +P 3150 4300 +F 0 "U1" H 3200 4400 30 0000 C CNN +F 1 "PORT" H 3150 4300 30 0000 C CNN +F 2 "" H 3150 4300 60 0000 C CNN +F 3 "" H 3150 4300 60 0000 C CNN + 5 3150 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF10DFD +P 6250 4050 +F 0 "U1" H 6300 4150 30 0000 C CNN +F 1 "PORT" H 6250 4050 30 0000 C CNN +F 2 "" H 6250 4050 60 0000 C CNN +F 3 "" H 6250 4050 60 0000 C CNN + 6 6250 4050 + -1 0 0 1 +$EndComp +Wire Wire Line + 6000 4050 5100 4050 +Wire Wire Line + 4250 3950 4250 3650 +Wire Wire Line + 4250 3650 3400 3650 +Wire Wire Line + 3400 3950 3900 3950 +Wire Wire Line + 3900 3950 3900 4050 +Wire Wire Line + 3900 4050 4250 4050 +Wire Wire Line + 4250 4150 4250 4300 +Wire Wire Line + 4250 4300 3400 4300 +$Comp +L 3_and X2 +U 1 1 5CF10E9C +P 4550 5450 +F 0 "X2" H 4650 5400 60 0000 C CNN +F 1 "3_and" H 4700 5600 60 0000 C CNN +F 2 "" H 4550 5450 60 0000 C CNN +F 3 "" H 4550 5450 60 0000 C CNN + 1 4550 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF10EA2 +P 3100 5000 +F 0 "U1" H 3150 5100 30 0000 C CNN +F 1 "PORT" H 3100 5000 30 0000 C CNN +F 2 "" H 3100 5000 60 0000 C CNN +F 3 "" H 3100 5000 60 0000 C CNN + 11 3100 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF10EA8 +P 3100 5300 +F 0 "U1" H 3150 5400 30 0000 C CNN +F 1 "PORT" H 3100 5300 30 0000 C CNN +F 2 "" H 3100 5300 60 0000 C CNN +F 3 "" H 3100 5300 60 0000 C CNN + 12 3100 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF10EAE +P 3100 5650 +F 0 "U1" H 3150 5750 30 0000 C CNN +F 1 "PORT" H 3100 5650 30 0000 C CNN +F 2 "" H 3100 5650 60 0000 C CNN +F 3 "" H 3100 5650 60 0000 C CNN + 13 3100 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF10EB4 +P 6200 5400 +F 0 "U1" H 6250 5500 30 0000 C CNN +F 1 "PORT" H 6200 5400 30 0000 C CNN +F 2 "" H 6200 5400 60 0000 C CNN +F 3 "" H 6200 5400 60 0000 C CNN + 10 6200 5400 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 5400 5050 5400 +Wire Wire Line + 4200 5300 4200 5000 +Wire Wire Line + 4200 5000 3350 5000 +Wire Wire Line + 3350 5300 3850 5300 +Wire Wire Line + 3850 5300 3850 5400 +Wire Wire Line + 3850 5400 4200 5400 +Wire Wire Line + 4200 5500 4200 5650 +Wire Wire Line + 4200 5650 3350 5650 +$Comp +L PORT U1 +U 7 1 5CF11A2A +P 7500 4100 +F 0 "U1" H 7550 4200 30 0000 C CNN +F 1 "PORT" H 7500 4100 30 0000 C CNN +F 2 "" H 7500 4100 60 0000 C CNN +F 3 "" H 7500 4100 60 0000 C CNN + 7 7500 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF11A8A +P 7550 4600 +F 0 "U1" H 7600 4700 30 0000 C CNN +F 1 "PORT" H 7550 4600 30 0000 C CNN +F 2 "" H 7550 4600 60 0000 C CNN +F 3 "" H 7550 4600 60 0000 C CNN + 14 7550 4600 + -1 0 0 1 +$EndComp +NoConn ~ 7250 4100 +NoConn ~ 7300 4600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4073/4073.sub b/library/SubcircuitLibrary/4073/4073.sub new file mode 100644 index 00000000..15208169 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073.sub @@ -0,0 +1,10 @@ +* Subcircuit 4073 +.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +* Control Statements + +.ends 4073
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4073/4073_Previous_Values.xml b/library/SubcircuitLibrary/4073/4073_Previous_Values.xml new file mode 100644 index 00000000..5acac768 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4073/analysis b/library/SubcircuitLibrary/4073/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4073/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_OR/4_OR-cache.lib b/library/SubcircuitLibrary/4_OR/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4_OR/4_OR.cir b/library/SubcircuitLibrary/4_OR/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/4_OR/4_OR.cir.out b/library/SubcircuitLibrary/4_OR/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4_OR/4_OR.pro b/library/SubcircuitLibrary/4_OR/4_OR.pro new file mode 100644 index 00000000..9daf26bc --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR.pro @@ -0,0 +1,45 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/library/SubcircuitLibrary/4_OR/4_OR.sch b/library/SubcircuitLibrary/4_OR/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4_OR/4_OR.sub b/library/SubcircuitLibrary/4_OR/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_OR/analysis b/library/SubcircuitLibrary/4_OR/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_and/3_and-cache.lib b/library/SubcircuitLibrary/4_and/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4_and/3_and.cir b/library/SubcircuitLibrary/4_and/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/4_and/3_and.cir.out b/library/SubcircuitLibrary/4_and/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4_and/3_and.pro b/library/SubcircuitLibrary/4_and/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/4_and/3_and.sch b/library/SubcircuitLibrary/4_and/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4_and/3_and.sub b/library/SubcircuitLibrary/4_and/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_and/3_and_Previous_Values.xml b/library/SubcircuitLibrary/4_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_and/4_and-cache.lib b/library/SubcircuitLibrary/4_and/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4_and/4_and-rescue.lib b/library/SubcircuitLibrary/4_and/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4_and/4_and.cir b/library/SubcircuitLibrary/4_and/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/4_and/4_and.cir.out b/library/SubcircuitLibrary/4_and/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4_and/4_and.pro b/library/SubcircuitLibrary/4_and/4_and.pro new file mode 100644 index 00000000..9c0be79e --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and.pro @@ -0,0 +1,58 @@ +update=06/01/19 15:08:42 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/library/SubcircuitLibrary/4_and/4_and.sch b/library/SubcircuitLibrary/4_and/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4_and/4_and.sub b/library/SubcircuitLibrary/4_and/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_and/4_and_Previous_Values.xml b/library/SubcircuitLibrary/4_and/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_and/analysis b/library/SubcircuitLibrary/4_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/3_and-cache.lib b/library/SubcircuitLibrary/4to16_demux/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4to16_demux/3_and.cir b/library/SubcircuitLibrary/4to16_demux/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/4to16_demux/3_and.cir.out b/library/SubcircuitLibrary/4to16_demux/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4to16_demux/3_and.pro b/library/SubcircuitLibrary/4to16_demux/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/4to16_demux/3_and.sch b/library/SubcircuitLibrary/4to16_demux/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4to16_demux/3_and.sub b/library/SubcircuitLibrary/4to16_demux/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml b/library/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib b/library/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib new file mode 100644 index 00000000..898ea926 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_nand +# +DEF 5_nand X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_nand" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir b/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir new file mode 100644 index 00000000..c97c2f8b --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir @@ -0,0 +1,32 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 17:01:07 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad23_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad22_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad21_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad20_ Net-_U6-Pad2_ d_inverter +U2 Net-_U1-Pad19_ Net-_U1-Pad18_ Net-_U2-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ ? Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ ? PORT +X1 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad1_ 5_nand +X2 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad2_ 5_nand +X3 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad3_ 5_nand +X4 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad4_ 5_nand +X5 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad5_ 5_nand +X6 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad6_ 5_nand +X7 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad7_ 5_nand +X8 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad8_ 5_nand +X9 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad9_ 5_nand +X10 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad10_ 5_nand +X11 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad11_ 5_nand +X12 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad13_ 5_nand +X13 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad14_ 5_nand +X14 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad15_ 5_nand +X15 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad16_ 5_nand +X16 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad17_ 5_nand + +.end diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out b/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out new file mode 100644 index 00000000..eecdfb06 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out @@ -0,0 +1,49 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir + +.include 5_nand.sub +* u3 net-_u1-pad23_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad22_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad21_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad20_ net-_u6-pad2_ d_inverter +* u2 net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? port +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand +x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand +x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand +x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand +x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand +x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand +x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand +x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand +x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand +x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand +x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand +x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand +x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand +x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand +x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand +x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand +a1 net-_u1-pad23_ net-_u3-pad2_ u3 +a2 net-_u1-pad22_ net-_u4-pad2_ u4 +a3 net-_u1-pad21_ net-_u5-pad2_ u5 +a4 net-_u1-pad20_ net-_u6-pad2_ u6 +a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux.pro b/library/SubcircuitLibrary/4to16_demux/4to16_demux.pro new file mode 100644 index 00000000..5a167cd9 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux.pro @@ -0,0 +1,43 @@ +update=Fri Jun 21 16:58:10 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_User +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux.sch b/library/SubcircuitLibrary/4to16_demux/4to16_demux.sch new file mode 100644 index 00000000..c9142e27 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux.sch @@ -0,0 +1,889 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4to16_demux-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 5CF2315F +P 4700 1900 +F 0 "U3" H 4700 1800 60 0000 C CNN +F 1 "d_inverter" H 4700 2050 60 0000 C CNN +F 2 "" H 4750 1850 60 0000 C CNN +F 3 "" H 4750 1850 60 0000 C CNN + 1 4700 1900 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF231D7 +P 5600 1850 +F 0 "U4" H 5600 1750 60 0000 C CNN +F 1 "d_inverter" H 5600 2000 60 0000 C CNN +F 2 "" H 5650 1800 60 0000 C CNN +F 3 "" H 5650 1800 60 0000 C CNN + 1 5600 1850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5CF23245 +P 6550 1850 +F 0 "U5" H 6550 1750 60 0000 C CNN +F 1 "d_inverter" H 6550 2000 60 0000 C CNN +F 2 "" H 6600 1800 60 0000 C CNN +F 3 "" H 6600 1800 60 0000 C CNN + 1 6550 1850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5CF232B2 +P 7500 1800 +F 0 "U6" H 7500 1700 60 0000 C CNN +F 1 "d_inverter" H 7500 1950 60 0000 C CNN +F 2 "" H 7550 1750 60 0000 C CNN +F 3 "" H 7550 1750 60 0000 C CNN + 1 7500 1800 + 0 1 1 0 +$EndComp +Text Notes 1300 5450 0 60 ~ 0 +~Y0 +Text Notes 1950 5450 0 60 ~ 0 +~Y1\n +Text Notes 2500 5450 0 60 ~ 0 +~Y2\n +Text Notes 3050 5450 0 60 ~ 0 +~Y3\n +Text Notes 3600 5450 0 60 ~ 0 +~Y4\n +Text Notes 4150 5500 0 60 ~ 0 +~Y5\n +Text Notes 4700 5500 0 60 ~ 0 +~Y6\n +Text Notes 5250 5500 0 60 ~ 0 +~Y7\n +Text Notes 5800 5500 0 60 ~ 0 +~Y8\n +Text Notes 6400 5500 0 60 ~ 0 +~Y9\n +Text Notes 6950 5500 0 60 ~ 0 +~Y10\n +Text Notes 7500 5500 0 60 ~ 0 +~Y11\n +Text Notes 8050 5500 0 60 ~ 0 +~Y12\n +Text Notes 8600 5500 0 60 ~ 0 +~Y13\n +Text Notes 9150 5500 0 60 ~ 0 +~Y14\n +Text Notes 9700 5500 0 60 ~ 0 +~Y15\n +Wire Wire Line + 4700 1250 4700 1600 +Wire Wire Line + 5600 1150 5600 1550 +Wire Wire Line + 6550 1100 6550 1550 +Wire Wire Line + 7500 1050 7500 1500 +Wire Wire Line + 1400 4400 1400 2950 +Wire Wire Line + 1400 2950 9700 2950 +Wire Wire Line + 1950 2950 1950 4400 +Wire Wire Line + 2500 2950 2500 4400 +Connection ~ 1950 2950 +Wire Wire Line + 3050 2950 3050 4400 +Connection ~ 2500 2950 +Wire Wire Line + 3600 2950 3600 4400 +Connection ~ 3050 2950 +Wire Wire Line + 4150 2950 4150 4400 +Connection ~ 3600 2950 +Wire Wire Line + 4700 2950 4700 4400 +Connection ~ 4150 2950 +Wire Wire Line + 5250 2950 5250 4400 +Connection ~ 4700 2950 +Wire Wire Line + 5800 2950 5800 4400 +Connection ~ 5250 2950 +Wire Wire Line + 6400 2950 6400 4400 +Connection ~ 5800 2950 +Wire Wire Line + 6950 2950 6950 4400 +Connection ~ 6400 2950 +Wire Wire Line + 7500 2950 7500 4400 +Connection ~ 6950 2950 +Wire Wire Line + 8050 2950 8050 4400 +Connection ~ 7500 2950 +Wire Wire Line + 8600 2950 8600 4400 +Connection ~ 8050 2950 +Wire Wire Line + 9150 2950 9150 4400 +Connection ~ 8600 2950 +Wire Wire Line + 9700 2950 9700 4400 +Connection ~ 9150 2950 +Wire Wire Line + 7500 2100 7500 2800 +Wire Wire Line + 7500 2800 7400 2800 +Wire Wire Line + 7400 2800 7400 3050 +Wire Wire Line + 7400 3050 1500 3050 +Wire Wire Line + 1500 3050 1500 4400 +Wire Wire Line + 2050 4400 2050 3050 +Connection ~ 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"" H 5450 6200 60 0000 C CNN + 8 5450 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF2E651 +P 6000 6200 +F 0 "U1" H 6050 6300 30 0000 C CNN +F 1 "PORT" H 6000 6200 30 0000 C CNN +F 2 "" H 6000 6200 60 0000 C CNN +F 3 "" H 6000 6200 60 0000 C CNN + 9 6000 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF2E6E3 +P 6600 6150 +F 0 "U1" H 6650 6250 30 0000 C CNN +F 1 "PORT" H 6600 6150 30 0000 C CNN +F 2 "" H 6600 6150 60 0000 C CNN +F 3 "" H 6600 6150 60 0000 C CNN + 10 6600 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF2E770 +P 7150 6150 +F 0 "U1" H 7200 6250 30 0000 C CNN +F 1 "PORT" H 7150 6150 30 0000 C CNN +F 2 "" H 7150 6150 60 0000 C CNN +F 3 "" H 7150 6150 60 0000 C CNN + 11 7150 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF2E7F8 +P 7700 6150 +F 0 "U1" H 7750 6250 30 0000 C CNN +F 1 "PORT" H 7700 6150 30 0000 C CNN +F 2 "" H 7700 6150 60 0000 C CNN +F 3 "" H 7700 6150 60 0000 C CNN + 13 7700 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 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+Wire Wire Line + 8250 5400 8250 5900 +Wire Wire Line + 7700 5400 7700 5900 +Wire Wire Line + 7150 5400 7150 5900 +Wire Wire Line + 6600 5400 6600 5900 +Wire Wire Line + 6000 5400 6000 5950 +Wire Wire Line + 5450 5400 5450 5950 +Wire Wire Line + 4900 5400 4900 5950 +Wire Wire Line + 4350 5400 4350 5950 +Wire Wire Line + 3800 5400 3800 5950 +Wire Wire Line + 3250 5400 3250 5950 +Wire Wire Line + 2700 5400 2700 5950 +Wire Wire Line + 2150 5400 2150 5950 +Wire Wire Line + 1600 5400 1600 5950 +$Comp +L PORT U1 +U 24 1 5CF327C1 +P 6500 6950 +F 0 "U1" H 6550 7050 30 0000 C CNN +F 1 "PORT" H 6500 6950 30 0000 C CNN +F 2 "" H 6500 6950 60 0000 C CNN +F 3 "" H 6500 6950 60 0000 C CNN + 24 6500 6950 + 0 -1 -1 0 +$EndComp +NoConn ~ 6500 6700 +$Comp +L PORT U1 +U 12 1 5CF33A86 +P 3400 900 +F 0 "U1" H 3450 1000 30 0000 C CNN +F 1 "PORT" H 3400 900 30 0000 C CNN +F 2 "" H 3400 900 60 0000 C CNN +F 3 "" H 3400 900 60 0000 C CNN + 12 3400 900 + 0 1 1 0 +$EndComp +NoConn ~ 3400 1150 +$Comp +L 5_nand X1 +U 1 1 5D0CC4BF +P 1600 4850 +F 0 "X1" H 1650 4750 60 0000 C CNN +F 1 "5_nand" H 1700 5000 60 0000 C CNN +F 2 "" H 1600 4850 60 0000 C CNN +F 3 "" H 1600 4850 60 0000 C CNN + 1 1600 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X2 +U 1 1 5D0CC967 +P 2150 4850 +F 0 "X2" H 2200 4750 60 0000 C CNN +F 1 "5_nand" H 2250 5000 60 0000 C CNN +F 2 "" H 2150 4850 60 0000 C CNN +F 3 "" H 2150 4850 60 0000 C CNN + 1 2150 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X3 +U 1 1 5D0CC9F8 +P 2700 4850 +F 0 "X3" H 2750 4750 60 0000 C CNN +F 1 "5_nand" H 2800 5000 60 0000 C CNN +F 2 "" H 2700 4850 60 0000 C CNN +F 3 "" H 2700 4850 60 0000 C CNN + 1 2700 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X4 +U 1 1 5D0CCA7E +P 3250 4850 +F 0 "X4" H 3300 4750 60 0000 C CNN +F 1 "5_nand" H 3350 5000 60 0000 C CNN +F 2 "" H 3250 4850 60 0000 C CNN +F 3 "" H 3250 4850 60 0000 C CNN + 1 3250 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X5 +U 1 1 5D0CCB6A +P 3800 4850 +F 0 "X5" H 3850 4750 60 0000 C CNN +F 1 "5_nand" H 3900 5000 60 0000 C CNN +F 2 "" H 3800 4850 60 0000 C CNN +F 3 "" H 3800 4850 60 0000 C CNN + 1 3800 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X6 +U 1 1 5D0CCBF6 +P 4350 4850 +F 0 "X6" H 4400 4750 60 0000 C CNN +F 1 "5_nand" H 4450 5000 60 0000 C CNN +F 2 "" H 4350 4850 60 0000 C CNN +F 3 "" H 4350 4850 60 0000 C CNN + 1 4350 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X7 +U 1 1 5D0CCC81 +P 4900 4850 +F 0 "X7" H 4950 4750 60 0000 C CNN +F 1 "5_nand" H 5000 5000 60 0000 C CNN +F 2 "" H 4900 4850 60 0000 C CNN +F 3 "" H 4900 4850 60 0000 C CNN + 1 4900 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X8 +U 1 1 5D0CCD0B +P 5450 4850 +F 0 "X8" H 5500 4750 60 0000 C CNN +F 1 "5_nand" H 5550 5000 60 0000 C CNN +F 2 "" H 5450 4850 60 0000 C CNN +F 3 "" H 5450 4850 60 0000 C CNN + 1 5450 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X9 +U 1 1 5D0CCE34 +P 6000 4850 +F 0 "X9" H 6050 4750 60 0000 C CNN +F 1 "5_nand" H 6100 5000 60 0000 C CNN +F 2 "" H 6000 4850 60 0000 C CNN +F 3 "" H 6000 4850 60 0000 C CNN + 1 6000 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X10 +U 1 1 5D0CCECA +P 6600 4850 +F 0 "X10" H 6650 4750 60 0000 C CNN +F 1 "5_nand" H 6700 5000 60 0000 C CNN +F 2 "" H 6600 4850 60 0000 C CNN +F 3 "" H 6600 4850 60 0000 C CNN + 1 6600 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X11 +U 1 1 5D0CCF63 +P 7150 4850 +F 0 "X11" H 7200 4750 60 0000 C CNN +F 1 "5_nand" H 7250 5000 60 0000 C CNN +F 2 "" H 7150 4850 60 0000 C CNN +F 3 "" H 7150 4850 60 0000 C CNN + 1 7150 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X12 +U 1 1 5D0CD07D +P 7700 4850 +F 0 "X12" H 7750 4750 60 0000 C CNN +F 1 "5_nand" H 7800 5000 60 0000 C CNN +F 2 "" H 7700 4850 60 0000 C CNN +F 3 "" H 7700 4850 60 0000 C CNN + 1 7700 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X13 +U 1 1 5D0CD124 +P 8250 4850 +F 0 "X13" H 8300 4750 60 0000 C CNN +F 1 "5_nand" H 8350 5000 60 0000 C CNN +F 2 "" H 8250 4850 60 0000 C CNN +F 3 "" H 8250 4850 60 0000 C CNN + 1 8250 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X14 +U 1 1 5D0CD1C6 +P 8800 4850 +F 0 "X14" H 8850 4750 60 0000 C CNN +F 1 "5_nand" H 8900 5000 60 0000 C CNN +F 2 "" H 8800 4850 60 0000 C CNN +F 3 "" H 8800 4850 60 0000 C CNN + 1 8800 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X15 +U 1 1 5D0CD348 +P 9350 4850 +F 0 "X15" H 9400 4750 60 0000 C CNN +F 1 "5_nand" H 9450 5000 60 0000 C CNN +F 2 "" H 9350 4850 60 0000 C CNN +F 3 "" H 9350 4850 60 0000 C CNN + 1 9350 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X16 +U 1 1 5D0CD3EE +P 9900 4850 +F 0 "X16" H 9950 4750 60 0000 C CNN +F 1 "5_nand" H 10000 5000 60 0000 C CNN +F 2 "" H 9900 4850 60 0000 C CNN +F 3 "" H 9900 4850 60 0000 C CNN + 1 9900 4850 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux.sub b/library/SubcircuitLibrary/4to16_demux/4to16_demux.sub new file mode 100644 index 00000000..4f7595da --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux.sub @@ -0,0 +1,43 @@ +* Subcircuit 4to16_demux +.subckt 4to16_demux net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir +.include 5_nand.sub +* u3 net-_u1-pad23_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad22_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad21_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad20_ net-_u6-pad2_ d_inverter +* u2 net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand +x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand +x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand +x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand +x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand +x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand +x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand +x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand +x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand +x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand +x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand +x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand +x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand +x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand +x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand +x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand +a1 net-_u1-pad23_ net-_u3-pad2_ u3 +a2 net-_u1-pad22_ net-_u4-pad2_ u4 +a3 net-_u1-pad21_ net-_u5-pad2_ u5 +a4 net-_u1-pad20_ net-_u6-pad2_ u6 +a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4to16_demux
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml b/library/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml new file mode 100644 index 00000000..93c6f25a --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x13><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x13><x14><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x14><x15><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x15><x10><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x10><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x9><x16><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x16><x11><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x11><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x3><x12><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x12><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/5_and-cache.lib b/library/SubcircuitLibrary/4to16_demux/5_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4to16_demux/5_and.cir b/library/SubcircuitLibrary/4to16_demux/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/4to16_demux/5_and.cir.out b/library/SubcircuitLibrary/4to16_demux/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4to16_demux/5_and.pro b/library/SubcircuitLibrary/4to16_demux/5_and.pro new file mode 100644 index 00000000..7a2f090e --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/library/SubcircuitLibrary/4to16_demux/5_and.sch b/library/SubcircuitLibrary/4to16_demux/5_and.sch new file mode 100644 index 00000000..e9eb58ee --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4to16_demux/5_and.sub b/library/SubcircuitLibrary/4to16_demux/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml b/library/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand-cache.lib b/library/SubcircuitLibrary/4to16_demux/5_nand-cache.lib new file mode 100644 index 00000000..cb517be1 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand-cache.lib @@ -0,0 +1,78 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.cir b/library/SubcircuitLibrary/4to16_demux/5_nand.cir new file mode 100644 index 00000000..e833d0f4 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand.cir @@ -0,0 +1,13 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and +U2 Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.cir.out b/library/SubcircuitLibrary/4to16_demux/5_nand.cir.out new file mode 100644 index 00000000..164de911 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand.cir.out @@ -0,0 +1,18 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir + +.include 5_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and +* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 net-_u2-pad1_ net-_u1-pad6_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.pro b/library/SubcircuitLibrary/4to16_demux/5_nand.pro new file mode 100644 index 00000000..b7d23f44 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand.pro @@ -0,0 +1,83 @@ +update=Fri Jun 21 16:46:10 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName41=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName42=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName43=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName44=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName45=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName46=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName47=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName48=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User + diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.sch b/library/SubcircuitLibrary/4to16_demux/5_nand.sch new file mode 100644 index 00000000..86379b08 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand.sch @@ -0,0 +1,175 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5D0CBD44 +P 4150 3700 +F 0 "X1" H 4200 3600 60 0000 C CNN +F 1 "5_and" H 4250 3850 60 0000 C CNN +F 2 "" H 4150 3700 60 0000 C CNN +F 3 "" H 4150 3700 60 0000 C CNN + 1 4150 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5D0CBD97 +P 5150 3700 +F 0 "U2" H 5150 3600 60 0000 C CNN +F 1 "d_inverter" H 5150 3850 60 0000 C CNN +F 2 "" H 5200 3650 60 0000 C CNN +F 3 "" H 5200 3650 60 0000 C CNN + 1 5150 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5D0CBDBE +P 2900 2900 +F 0 "U1" H 2950 3000 30 0000 C CNN +F 1 "PORT" H 2900 2900 30 0000 C CNN +F 2 "" H 2900 2900 60 0000 C CNN +F 3 "" H 2900 2900 60 0000 C CNN + 1 2900 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D0CBDF4 +P 2900 3150 +F 0 "U1" H 2950 3250 30 0000 C CNN +F 1 "PORT" H 2900 3150 30 0000 C CNN +F 2 "" H 2900 3150 60 0000 C CNN +F 3 "" H 2900 3150 60 0000 C CNN + 2 2900 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5D0CBE16 +P 2900 3400 +F 0 "U1" H 2950 3500 30 0000 C CNN +F 1 "PORT" H 2900 3400 30 0000 C CNN +F 2 "" H 2900 3400 60 0000 C CNN +F 3 "" H 2900 3400 60 0000 C CNN + 3 2900 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5D0CBE3F +P 2900 3750 +F 0 "U1" H 2950 3850 30 0000 C CNN +F 1 "PORT" H 2900 3750 30 0000 C CNN +F 2 "" H 2900 3750 60 0000 C CNN +F 3 "" H 2900 3750 60 0000 C CNN + 4 2900 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5D0CBE6B +P 2900 4150 +F 0 "U1" H 2950 4250 30 0000 C CNN +F 1 "PORT" H 2900 4150 30 0000 C CNN +F 2 "" H 2900 4150 60 0000 C CNN +F 3 "" H 2900 4150 60 0000 C CNN + 5 2900 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5D0CBE9C +P 6200 3700 +F 0 "U1" H 6250 3800 30 0000 C CNN +F 1 "PORT" H 6200 3700 30 0000 C CNN +F 2 "" H 6200 3700 60 0000 C CNN +F 3 "" H 6200 3700 60 0000 C CNN + 6 6200 3700 + -1 0 0 1 +$EndComp +Wire Wire Line + 3150 2900 3700 2900 +Wire Wire Line + 3700 2900 3700 3500 +Wire Wire Line + 3700 3600 3500 3600 +Wire Wire Line + 3500 3600 3500 3150 +Wire Wire Line + 3500 3150 3150 3150 +Wire Wire Line + 3150 3400 3350 3400 +Wire Wire Line + 3350 3400 3350 3700 +Wire Wire Line + 3350 3700 3700 3700 +Wire Wire Line + 3700 3800 3250 3800 +Wire Wire Line + 3250 3800 3250 3750 +Wire Wire Line + 3250 3750 3150 3750 +Wire Wire Line + 3150 4150 3350 4150 +Wire Wire Line + 3350 4150 3350 3900 +Wire Wire Line + 3350 3900 3700 3900 +Wire Wire Line + 4700 3700 4850 3700 +Wire Wire Line + 5450 3700 5950 3700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.sub b/library/SubcircuitLibrary/4to16_demux/5_nand.sub new file mode 100644 index 00000000..c3e041fa --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand.sub @@ -0,0 +1,12 @@ +* Subcircuit 5_nand +.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir +.include 5_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and +* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter +a1 net-_u2-pad1_ net-_u1-pad6_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_nand
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml b/library/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml new file mode 100644 index 00000000..c4b4cde2 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/analysis b/library/SubcircuitLibrary/4to16_demux/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/556/556-cache.lib b/library/SubcircuitLibrary/556/556-cache.lib new file mode 100644 index 00000000..75d610da --- /dev/null +++ b/library/SubcircuitLibrary/556/556-cache.lib @@ -0,0 +1,64 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/556/556.cir b/library/SubcircuitLibrary/556/556.cir new file mode 100644 index 00000000..48baa73e --- /dev/null +++ b/library/SubcircuitLibrary/556/556.cir @@ -0,0 +1,13 @@ +* C:\esim\eSim\src\SubcircuitLibrary\556\556.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/18/19 18:30:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad14_ LM555N +X2 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ LM555N +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/556/556.cir.out b/library/SubcircuitLibrary/556/556.cir.out new file mode 100644 index 00000000..c74aab7c --- /dev/null +++ b/library/SubcircuitLibrary/556/556.cir.out @@ -0,0 +1,15 @@ +* c:\esim\esim\src\subcircuitlibrary\556\556.cir + +.include lm555n.sub +x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n +x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/556/556.pro b/library/SubcircuitLibrary/556/556.pro new file mode 100644 index 00000000..a165313d --- /dev/null +++ b/library/SubcircuitLibrary/556/556.pro @@ -0,0 +1,72 @@ +update=03/18/19 18:13:51 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=regul +LibName6=74xx +LibName7=cmos4000 +LibName8=adc-dac +LibName9=memory +LibName10=xilinx +LibName11=microcontrollers +LibName12=dsp +LibName13=microchip +LibName14=analog_switches +LibName15=motorola +LibName16=texas +LibName17=intel +LibName18=audio +LibName19=interface +LibName20=digital-audio +LibName21=philips +LibName22=display +LibName23=cypress +LibName24=siliconi +LibName25=opto +LibName26=atmel +LibName27=contrib +LibName28=valves +LibName29=eSim_User +LibName30=eSim_Subckt +LibName31=eSim_Sources +LibName32=eSim_PSpice +LibName33=eSim_Power +LibName34=eSim_Plot +LibName35=eSim_Miscellaneous +LibName36=eSim_Hybrid +LibName37=eSim_Digital +LibName38=eSim_Devices +LibName39=eSim_Analog diff --git a/library/SubcircuitLibrary/556/556.sch b/library/SubcircuitLibrary/556/556.sch new file mode 100644 index 00000000..af4e1bc9 --- /dev/null +++ b/library/SubcircuitLibrary/556/556.sch @@ -0,0 +1,275 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L LM555N X1 +U 1 1 5C8F9298 +P 4150 3850 +F 0 "X1" H 4150 3800 60 0000 C CNN +F 1 "LM555N" H 4150 3950 60 0000 C CNN +F 2 "" H 4100 3850 60 0000 C CNN +F 3 "" H 4100 3850 60 0000 C CNN + 1 4150 3850 + 1 0 0 -1 +$EndComp +$Comp +L LM555N X2 +U 1 1 5C8F92E5 +P 7100 3850 +F 0 "X2" H 7100 3800 60 0000 C CNN +F 1 "LM555N" H 7100 3950 60 0000 C CNN +F 2 "" H 7050 3850 60 0000 C CNN +F 3 "" H 7050 3850 60 0000 C CNN + 1 7100 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4150 3250 4150 3000 +Wire Wire Line + 4150 3000 7100 3000 +Wire Wire Line + 4150 4450 4150 4650 +Wire Wire Line + 4150 4650 7100 4650 +$Comp +L PORT U1 +U 14 1 5C8F93E6 +P 4650 2600 +F 0 "U1" H 4700 2700 30 0000 C CNN +F 1 "PORT" H 4650 2600 30 0000 C CNN +F 2 "" H 4650 2600 60 0000 C CNN +F 3 "" H 4650 2600 60 0000 C CNN + 14 4650 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4900 2600 5000 2600 +Wire Wire Line + 5000 2600 5000 3000 +Connection ~ 5000 3000 +$Comp +L PORT U1 +U 6 1 5C8F94B6 +P 3050 3600 +F 0 "U1" H 3100 3700 30 0000 C CNN +F 1 "PORT" H 3050 3600 30 0000 C CNN +F 2 "" H 3050 3600 60 0000 C CNN +F 3 "" H 3050 3600 60 0000 C CNN + 6 3050 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C8F95C0 +P 3050 3850 +F 0 "U1" H 3100 3950 30 0000 C CNN +F 1 "PORT" H 3050 3850 30 0000 C CNN +F 2 "" H 3050 3850 60 0000 C CNN +F 3 "" H 3050 3850 60 0000 C CNN + 3 3050 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C8F95E7 +P 3050 4100 +F 0 "U1" H 3100 4200 30 0000 C CNN +F 1 "PORT" H 3050 4100 30 0000 C CNN +F 2 "" H 3050 4100 60 0000 C CNN +F 3 "" H 3050 4100 60 0000 C CNN + 4 3050 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7100 3000 7100 3250 +Wire Wire Line + 7100 4650 7100 4450 +$Comp +L PORT U1 +U 8 1 5C8F9C35 +P 6000 3600 +F 0 "U1" H 6050 3700 30 0000 C CNN +F 1 "PORT" H 6000 3600 30 0000 C CNN +F 2 "" H 6000 3600 60 0000 C CNN +F 3 "" H 6000 3600 60 0000 C CNN + 8 6000 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C8F9C3B +P 6000 3850 +F 0 "U1" H 6050 3950 30 0000 C CNN +F 1 "PORT" H 6000 3850 30 0000 C CNN +F 2 "" H 6000 3850 60 0000 C CNN +F 3 "" H 6000 3850 60 0000 C CNN + 11 6000 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C8F9C41 +P 6000 4100 +F 0 "U1" H 6050 4200 30 0000 C CNN +F 1 "PORT" H 6000 4100 30 0000 C CNN +F 2 "" H 6000 4100 60 0000 C CNN +F 3 "" H 6000 4100 60 0000 C CNN + 10 6000 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C8F9D22 +P 5200 4100 +F 0 "U1" H 5250 4200 30 0000 C CNN +F 1 "PORT" H 5200 4100 30 0000 C CNN +F 2 "" H 5200 4100 60 0000 C CNN +F 3 "" H 5200 4100 60 0000 C CNN + 2 5200 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C8F9D28 +P 5200 3850 +F 0 "U1" H 5250 3950 30 0000 C CNN +F 1 "PORT" H 5200 3850 30 0000 C CNN +F 2 "" H 5200 3850 60 0000 C CNN +F 3 "" H 5200 3850 60 0000 C CNN + 1 5200 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C8F9D2E +P 5200 3600 +F 0 "U1" H 5250 3700 30 0000 C CNN +F 1 "PORT" H 5200 3600 30 0000 C CNN +F 2 "" H 5200 3600 60 0000 C CNN +F 3 "" H 5200 3600 60 0000 C CNN + 5 5200 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C8FA0FA +P 8250 4100 +F 0 "U1" H 8300 4200 30 0000 C CNN +F 1 "PORT" H 8250 4100 30 0000 C CNN +F 2 "" H 8250 4100 60 0000 C CNN +F 3 "" H 8250 4100 60 0000 C CNN + 12 8250 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C8FA100 +P 8250 3850 +F 0 "U1" H 8300 3950 30 0000 C CNN +F 1 "PORT" H 8250 3850 30 0000 C CNN +F 2 "" H 8250 3850 60 0000 C CNN +F 3 "" H 8250 3850 60 0000 C CNN + 13 8250 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C8FA106 +P 8250 3600 +F 0 "U1" H 8300 3700 30 0000 C CNN +F 1 "PORT" H 8250 3600 30 0000 C CNN +F 2 "" H 8250 3600 60 0000 C CNN +F 3 "" H 8250 3600 60 0000 C CNN + 9 8250 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C8FA319 +P 4950 5050 +F 0 "U1" H 5000 5150 30 0000 C CNN +F 1 "PORT" H 4950 5050 30 0000 C CNN +F 2 "" H 4950 5050 60 0000 C CNN +F 3 "" H 4950 5050 60 0000 C CNN + 7 4950 5050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 5050 5200 4650 +Connection ~ 5200 4650 +Wire Wire Line + 3300 3600 3600 3600 +Wire Wire Line + 3300 3850 3600 3850 +Wire Wire Line + 3300 4100 3600 4100 +Wire Wire Line + 4700 3600 4950 3600 +Wire Wire Line + 4700 3850 4950 3850 +Wire Wire Line + 4700 4100 4950 4100 +Wire Wire Line + 6250 3600 6550 3600 +Wire Wire Line + 6250 3850 6550 3850 +Wire Wire Line + 6250 4100 6550 4100 +Wire Wire Line + 8000 3600 7650 3600 +Wire Wire Line + 8000 3850 7650 3850 +Wire Wire Line + 8000 4100 7650 4100 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/556/556.sub b/library/SubcircuitLibrary/556/556.sub new file mode 100644 index 00000000..a370b703 --- /dev/null +++ b/library/SubcircuitLibrary/556/556.sub @@ -0,0 +1,9 @@ +* Subcircuit 556 +.subckt 556 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\esim\esim\src\subcircuitlibrary\556\556.cir +.include lm555n.sub +x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n +x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n +* Control Statements + +.ends 556
\ No newline at end of file diff --git a/library/SubcircuitLibrary/556/556_Previous_Values.xml b/library/SubcircuitLibrary/556/556_Previous_Values.xml new file mode 100644 index 00000000..c025c2d1 --- /dev/null +++ b/library/SubcircuitLibrary/556/556_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/5_and/3_and-cache.lib b/library/SubcircuitLibrary/5_and/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/5_and/3_and.cir b/library/SubcircuitLibrary/5_and/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/5_and/3_and.cir.out b/library/SubcircuitLibrary/5_and/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/5_and/3_and.pro b/library/SubcircuitLibrary/5_and/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/5_and/3_and.sch b/library/SubcircuitLibrary/5_and/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/5_and/3_and.sub b/library/SubcircuitLibrary/5_and/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/5_and/3_and_Previous_Values.xml b/library/SubcircuitLibrary/5_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/5_and/5_and-cache.lib b/library/SubcircuitLibrary/5_and/5_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/5_and/5_and.cir b/library/SubcircuitLibrary/5_and/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/5_and/5_and.cir.out b/library/SubcircuitLibrary/5_and/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/5_and/5_and.pro b/library/SubcircuitLibrary/5_and/5_and.pro new file mode 100644 index 00000000..7a2f090e --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/library/SubcircuitLibrary/5_and/5_and.sch b/library/SubcircuitLibrary/5_and/5_and.sch new file mode 100644 index 00000000..e9eb58ee --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/5_and/5_and.sub b/library/SubcircuitLibrary/5_and/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/5_and/5_and_Previous_Values.xml b/library/SubcircuitLibrary/5_and/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/5_and/analysis b/library/SubcircuitLibrary/5_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/3_and-cache.lib b/library/SubcircuitLibrary/74153/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/3_and.cir b/library/SubcircuitLibrary/74153/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74153/3_and.cir.out b/library/SubcircuitLibrary/74153/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/3_and.pro b/library/SubcircuitLibrary/74153/3_and.pro new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/library/SubcircuitLibrary/74153/3_and.sch b/library/SubcircuitLibrary/74153/3_and.sch new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/3_and.sub b/library/SubcircuitLibrary/74153/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74153/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_OR-cache.lib b/library/SubcircuitLibrary/74153/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/4_OR.cir b/library/SubcircuitLibrary/74153/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/74153/4_OR.cir.out b/library/SubcircuitLibrary/74153/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/4_OR.pro b/library/SubcircuitLibrary/74153/4_OR.pro new file mode 100644 index 00000000..2c258cec --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.pro @@ -0,0 +1,45 @@ +update=03/28/19 22:43:48 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/library/SubcircuitLibrary/74153/4_OR.sch b/library/SubcircuitLibrary/74153/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/4_OR.sub b/library/SubcircuitLibrary/74153/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/74153/4_OR_Previous_Values.xml new file mode 100644 index 00000000..23698d37 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_and-cache.lib b/library/SubcircuitLibrary/74153/4_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/4_and.cir b/library/SubcircuitLibrary/74153/4_and.cir new file mode 100644 index 00000000..50d490fa --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/74153/4_and.cir.out b/library/SubcircuitLibrary/74153/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/4_and.pro b/library/SubcircuitLibrary/74153/4_and.pro new file mode 100644 index 00000000..6eb77fff --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.pro @@ -0,0 +1,57 @@ +update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/74153/4_and.sch b/library/SubcircuitLibrary/74153/4_and.sch new file mode 100644 index 00000000..883458e1 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/4_and.sub b/library/SubcircuitLibrary/74153/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_and_Previous_Values.xml b/library/SubcircuitLibrary/74153/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/74153-cache.lib b/library/SubcircuitLibrary/74153/74153-cache.lib new file mode 100644 index 00000000..1e85854e --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 3900 3050 60 H V C CNN +F1 "4_OR" 3900 3250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900 +A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150 +A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150 +P 2 0 1 0 3550 2900 3900 2900 N +P 2 0 1 0 3550 3400 3900 3400 N +X in1 1 3400 3300 200 R 50 50 1 1 I +X in2 2 3400 3200 200 R 50 50 1 1 I +X in3 3 3400 3100 200 R 50 50 1 1 I +X in4 4 3400 3000 200 R 50 50 1 1 I +X out 5 4300 3150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/74153.cir b/library/SubcircuitLibrary/74153/74153.cir new file mode 100644 index 00000000..b20e6858 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.cir @@ -0,0 +1,25 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\74153.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:33:11 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad12_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U35 Net-_U1-Pad5_ Net-_U35-Pad2_ d_inverter +U34 Net-_U1-Pad10_ Net-_U34-Pad2_ d_inverter +X8 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad1_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and +X9 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad2_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and +X4 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and +X10 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and +X5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and +X6 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad7_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and +X3 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad8_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and +X7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad14_ 4_OR +X2 Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad13_ 4_OR + +.end diff --git a/library/SubcircuitLibrary/74153/74153.cir.out b/library/SubcircuitLibrary/74153/74153.cir.out new file mode 100644 index 00000000..c95e5ad9 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.cir.out @@ -0,0 +1,40 @@ +* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir + +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR +a1 net-_u1-pad12_ net-_u2-pad2_ u2 +a2 net-_u1-pad11_ net-_u3-pad2_ u3 +a3 net-_u1-pad5_ net-_u35-pad2_ u35 +a4 net-_u1-pad10_ net-_u34-pad2_ u34 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/74153.pro b/library/SubcircuitLibrary/74153/74153.pro new file mode 100644 index 00000000..ed8b8bf2 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.pro @@ -0,0 +1,59 @@ +update=03/28/19 23:27:36 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=texas +LibName4=intel +LibName5=audio +LibName6=interface +LibName7=digital-audio +LibName8=philips +LibName9=display +LibName10=cypress +LibName11=siliconi +LibName12=opto +LibName13=atmel +LibName14=contrib +LibName15=valves +LibName16=eSim_Analog +LibName17=eSim_Devices +LibName18=eSim_Digital +LibName19=eSim_Hybrid +LibName20=eSim_Miscellaneous +LibName21=eSim_Plot +LibName22=eSim_Power +LibName23=eSim_PSpice +LibName24=eSim_Sources +LibName25=eSim_User +LibName26=eSim_Subckt diff --git a/library/SubcircuitLibrary/74153/74153.sch b/library/SubcircuitLibrary/74153/74153.sch new file mode 100644 index 00000000..e0bcf950 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.sch @@ -0,0 +1,568 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:74153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 5C9378F6 +P 2650 1350 +F 0 "U2" H 2650 1250 60 0000 C CNN +F 1 "d_inverter" H 2650 1500 60 0000 C CNN +F 2 "" H 2700 1300 60 0000 C CNN +F 3 "" H 2700 1300 60 0000 C CNN + 1 2650 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C93798D +P 2700 950 +F 0 "U3" H 2700 850 60 0000 C CNN +F 1 "d_inverter" H 2700 1100 60 0000 C CNN +F 2 "" H 2750 900 60 0000 C CNN +F 3 "" H 2750 900 60 0000 C CNN + 1 2700 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C93A0F9 +P 1350 2050 +F 0 "U1" H 1400 2150 30 0000 C CNN +F 1 "PORT" H 1350 2050 30 0000 C CNN +F 2 "" H 1350 2050 60 0000 C CNN +F 3 "" H 1350 2050 60 0000 C CNN + 1 1350 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C93A174 +P 1350 4700 +F 0 "U1" H 1400 4800 30 0000 C CNN +F 1 "PORT" H 1350 4700 30 0000 C CNN +F 2 "" H 1350 4700 60 0000 C CNN +F 3 "" H 1350 4700 60 0000 C CNN + 6 1350 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C93AA3C +P 1350 2600 +F 0 "U1" H 1400 2700 30 0000 C CNN +F 1 "PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 2 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 3 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 4 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93AD97 +P 1350 5250 +F 0 "U1" H 1400 5350 30 0000 C CNN +F 1 "PORT" H 1350 5250 30 0000 C CNN +F 2 "" H 1350 5250 60 0000 C CNN +F 3 "" H 1350 5250 60 0000 C CNN + 7 1350 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C93ADFC +P 1350 5850 +F 0 "U1" H 1400 5950 30 0000 C CNN +F 1 "PORT" H 1350 5850 30 0000 C CNN +F 2 "" H 1350 5850 60 0000 C CNN +F 3 "" H 1350 5850 60 0000 C CNN + 8 1350 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C93AE63 +P 1350 6350 +F 0 "U1" H 1400 6450 30 0000 C CNN +F 1 "PORT" H 1350 6350 30 0000 C CNN +F 2 "" H 1350 6350 60 0000 C CNN +F 3 "" H 1350 6350 60 0000 C CNN + 9 1350 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C93AECA +P 1350 3950 +F 0 "U1" H 1400 4050 30 0000 C CNN +F 1 "PORT" H 1350 3950 30 0000 C CNN +F 2 "" H 1350 3950 60 0000 C CNN +F 3 "" H 1350 3950 60 0000 C CNN + 5 1350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C93AF79 +P 1350 6600 +F 0 "U1" H 1400 6700 30 0000 C CNN +F 1 "PORT" H 1350 6600 30 0000 C CNN +F 2 "" H 1350 6600 60 0000 C CNN +F 3 "" H 1350 6600 60 0000 C CNN + 10 1350 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C93B10A +P 1550 950 +F 0 "U1" H 1600 1050 30 0000 C CNN +F 1 "PORT" H 1550 950 30 0000 C CNN +F 2 "" H 1550 950 60 0000 C CNN +F 3 "" H 1550 950 60 0000 C CNN + 11 1550 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C93B179 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 5C95CBCC +P 2700 3950 +F 0 "U35" H 2700 3850 60 0000 C CNN +F 1 "d_inverter" H 2700 4100 60 0000 C CNN +F 2 "" H 2750 3900 60 0000 C CNN +F 3 "" H 2750 3900 60 0000 C CNN + 1 2700 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 5C95CC99 +P 2650 6600 +F 0 "U34" H 2650 6500 60 0000 C CNN +F 1 "d_inverter" H 2650 6750 60 0000 C CNN +F 2 "" H 2700 6550 60 0000 C CNN +F 3 "" H 2700 6550 60 0000 C CNN + 1 2650 6600 + 1 0 0 -1 +$EndComp +Text Notes 1750 2050 0 60 ~ 12 +A0 +Text Notes 1800 2600 0 60 ~ 12 +A1 +Text Notes 1800 3200 0 60 ~ 12 +A2 +Text Notes 1750 3700 0 60 ~ 12 +A3\n +Text Notes 1750 3950 0 60 ~ 12 +EnA\n +Text Notes 1800 4700 0 60 ~ 12 +B0\n +Text Notes 1800 5250 0 60 ~ 12 +B1 +Text Notes 1800 5850 0 60 ~ 12 +B2 +Text Notes 1750 6350 0 60 ~ 12 +B3 +Text Notes 1800 6600 0 60 ~ 12 +EnB +Text Notes 2000 950 0 60 ~ 12 +S1\n +Text Notes 2000 1350 0 60 ~ 12 +S0 +Text Notes 7350 2600 0 60 ~ 12 +YA +Text Notes 7400 5250 0 60 ~ 12 +YB +$Comp +L 4_and X8 +U 1 1 5C9D0C22 +P 2750 3050 +F 0 "X8" H 4250 4100 60 0000 C CNN +F 1 "4_and" H 4300 4250 60 0000 C CNN +F 2 "" H 2750 3050 60 0000 C CNN +F 3 "" H 2750 3050 60 0000 C CNN + 1 2750 3050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X9 +U 1 1 5C9D0CA2 +P 2750 3600 +F 0 "X9" H 4250 4650 60 0000 C CNN +F 1 "4_and" H 4300 4800 60 0000 C CNN +F 2 "" H 2750 3600 60 0000 C CNN +F 3 "" H 2750 3600 60 0000 C CNN + 1 2750 3600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 5C9D0D16 +P 2700 4200 +F 0 "X4" H 4200 5250 60 0000 C CNN +F 1 "4_and" H 4250 5400 60 0000 C CNN +F 2 "" H 2700 4200 60 0000 C CNN +F 3 "" H 2700 4200 60 0000 C CNN + 1 2700 4200 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X10 +U 1 1 5C9D0D93 +P 2750 4700 +F 0 "X10" H 4250 5750 60 0000 C CNN +F 1 "4_and" H 4300 5900 60 0000 C CNN +F 2 "" H 2750 4700 60 0000 C CNN +F 3 "" H 2750 4700 60 0000 C CNN + 1 2750 4700 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 5C9D182A +P 2700 5700 +F 0 "X5" H 4200 6750 60 0000 C CNN +F 1 "4_and" H 4250 6900 60 0000 C CNN +F 2 "" H 2700 5700 60 0000 C CNN +F 3 "" H 2700 5700 60 0000 C CNN + 1 2700 5700 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 5C9D1830 +P 2700 6250 +F 0 "X6" H 4200 7300 60 0000 C CNN +F 1 "4_and" H 4250 7450 60 0000 C CNN +F 2 "" H 2700 6250 60 0000 C CNN +F 3 "" H 2700 6250 60 0000 C CNN + 1 2700 6250 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 5C9D1836 +P 2650 6850 +F 0 "X3" H 4150 7900 60 0000 C CNN +F 1 "4_and" H 4200 8050 60 0000 C CNN +F 2 "" H 2650 6850 60 0000 C CNN +F 3 "" H 2650 6850 60 0000 C CNN + 1 2650 6850 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 5C9D183C +P 2700 7350 +F 0 "X7" H 4200 8400 60 0000 C CNN +F 1 "4_and" H 4250 8550 60 0000 C CNN +F 2 "" H 2700 7350 60 0000 C CNN +F 3 "" H 2700 7350 60 0000 C CNN + 1 2700 7350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 1800 3800 1800 +Wire Wire Line + 3100 1350 3100 5600 +Wire Wire Line + 3200 1900 3800 1900 +Wire Wire Line + 3200 950 3200 5100 +Wire Wire Line + 2950 1350 3100 1350 +Connection ~ 3100 1800 +Wire Wire Line + 3000 950 3200 950 +Connection ~ 3200 1900 +Wire Wire Line + 1800 950 2400 950 +Wire Wire Line + 1800 1350 2350 1350 +Wire Wire Line + 2200 950 2200 6200 +Connection ~ 2200 950 +Wire Wire Line + 2300 1350 2300 6100 +Wire Wire Line + 3300 2100 3800 2100 +Wire Wire Line + 3300 2100 3300 3800 +Wire Wire Line + 3300 2700 3800 2700 +Wire Wire Line + 3300 3300 3750 3300 +Connection ~ 3300 2700 +Wire Wire Line + 3000 3800 3800 3800 +Connection ~ 3300 3300 +Wire Wire Line + 1600 3700 3800 3700 +Wire Wire Line + 1600 3200 3750 3200 +Wire Wire Line + 3400 2600 1600 2600 +Wire Wire Line + 1600 2050 3800 2050 +Wire Wire Line + 3000 3800 3000 3950 +Wire Wire Line + 1600 3950 2400 3950 +Connection ~ 3300 3800 +Wire Wire Line + 3100 4450 3750 4450 +Wire Wire Line + 3200 4550 3750 4550 +Wire Wire Line + 3300 4800 3750 4800 +Wire Wire Line + 3300 4800 3300 6450 +Wire Wire Line + 3300 5350 3750 5350 +Wire Wire Line + 3300 5950 3700 5950 +Connection ~ 3300 5350 +Wire Wire Line + 3200 6450 3750 6450 +Connection ~ 3300 5950 +Wire Wire Line + 3350 6350 1600 6350 +Wire Wire Line + 1600 5850 3700 5850 +Wire Wire Line + 1600 5250 3750 5250 +Wire Wire Line + 3350 4700 1600 4700 +Wire Wire Line + 3200 6600 3200 6450 +Wire Wire Line + 2950 6600 3200 6600 +Wire Wire Line + 1600 6600 2350 6600 +Connection ~ 3300 6450 +Connection ~ 2300 1350 +Connection ~ 3100 4450 +Connection ~ 3200 4550 +Wire Wire Line + 6550 2600 7600 2600 +Wire Wire Line + 6450 5250 7650 5250 +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3750 5100 +Wire Wire Line + 2300 5000 3750 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3700 5600 +Wire Wire Line + 2200 5700 3700 5700 +Wire Wire Line + 2200 6200 3750 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3750 6100 +Wire Wire Line + 3200 2450 3800 2450 +Connection ~ 3200 2450 +Wire Wire Line + 2300 2350 3800 2350 +Connection ~ 2300 2350 +Wire Wire Line + 2200 3050 3750 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3100 2950 3750 2950 +Connection ~ 3100 2950 +Wire Wire Line + 2300 3450 3800 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 2200 3550 3800 3550 +Connection ~ 2200 3550 +Wire Wire Line + 3800 2050 3800 2000 +Wire Wire Line + 3400 2600 3400 2550 +Wire Wire Line + 3400 2550 3800 2550 +Wire Wire Line + 3800 2700 3800 2650 +Wire Wire Line + 3750 3200 3750 3150 +Wire Wire Line + 3750 3300 3750 3250 +Wire Wire Line + 3800 3700 3800 3650 +Wire Wire Line + 3800 3800 3800 3750 +Wire Wire Line + 3350 4700 3350 4650 +Wire Wire Line + 3350 4650 3750 4650 +Wire Wire Line + 3750 4800 3750 4750 +Wire Wire Line + 3750 5250 3750 5200 +Wire Wire Line + 3750 5350 3750 5300 +Wire Wire Line + 3700 5850 3700 5800 +Wire Wire Line + 3700 5950 3700 5900 +Wire Wire Line + 3350 6350 3350 6300 +Wire Wire Line + 3350 6300 3750 6300 +Wire Wire Line + 3750 6450 3750 6400 +$Comp +L 4_OR X1 +U 1 1 5C9D22F7 +P 2150 8400 +F 0 "X1" H 6050 11450 60 0000 C CNN +F 1 "4_OR" H 6050 11650 60 0000 C CNN +F 2 "" H 2150 8400 60 0000 C CNN +F 3 "" H 2150 8400 60 0000 C CNN + 1 2150 8400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 5100 5550 4600 +Wire Wire Line + 5550 4600 4650 4600 +Wire Wire Line + 5550 5200 4650 5200 +Wire Wire Line + 4650 5200 4650 5150 +Wire Wire Line + 4600 5750 4600 5300 +Wire Wire Line + 4600 5300 5550 5300 +Wire Wire Line + 4650 6250 4650 5400 +Wire Wire Line + 4650 5400 5550 5400 +$Comp +L 4_OR X2 +U 1 1 5C9D28DE +P 2250 5750 +F 0 "X2" H 6150 8800 60 0000 C CNN +F 1 "4_OR" H 6150 9000 60 0000 C CNN +F 2 "" H 2250 5750 60 0000 C CNN +F 3 "" H 2250 5750 60 0000 C CNN + 1 2250 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 1950 5650 1950 +Wire Wire Line + 5650 1950 5650 2450 +Wire Wire Line + 5650 2550 4700 2550 +Wire Wire Line + 4700 2550 4700 2500 +Wire Wire Line + 4650 3100 4650 2650 +Wire Wire Line + 4650 2650 5650 2650 +Wire Wire Line + 4700 3600 4700 2750 +Wire Wire Line + 4700 2750 5650 2750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/74153.sub b/library/SubcircuitLibrary/74153/74153.sub new file mode 100644 index 00000000..6e00261f --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.sub @@ -0,0 +1,34 @@ +* Subcircuit 74153 +.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR +a1 net-_u1-pad12_ net-_u2-pad2_ u2 +a2 net-_u1-pad11_ net-_u3-pad2_ u3 +a3 net-_u1-pad5_ net-_u35-pad2_ u35 +a4 net-_u1-pad10_ net-_u34-pad2_ u34 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74153
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/74153_Previous_Values.xml b/library/SubcircuitLibrary/74153/74153_Previous_Values.xml new file mode 100644 index 00000000..ea70e6f3 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u14 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u14><u25 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u25><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u20 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u20><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u21 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u21><u18 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u24 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u24><u28 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u29 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u29><u32 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u32><u2 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u15 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u15><u6 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u4><u16 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u27 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u27><u10 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u10><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u12><u23 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u23><u19 name="type">d_and<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u19><u26 name="type">d_and<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u26><u30 name="type">d_or<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u30><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u17 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u17><u11 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u11><u13 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u13><u9 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x9><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x10><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib b/library/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib new file mode 100644 index 00000000..10496d63 --- /dev/null +++ b/library/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/Dual4to1MUX.cir b/library/SubcircuitLibrary/74153/Dual4to1MUX.cir new file mode 100644 index 00000000..583c4a00 --- /dev/null +++ b/library/SubcircuitLibrary/74153/Dual4to1MUX.cir @@ -0,0 +1,45 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U14 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U25 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and +U5 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and +U7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and +U18 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and +U24 Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and +U28 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or +U29 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or +U32 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or +U2 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U3 Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter +U15 Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U6 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and +U8 Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and +U4 Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and +U16 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and +U27 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and +U22 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and +U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and +U23 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and +U19 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and +U26 Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and +U30 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or +U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or +U33 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or +U17 Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and +U11 Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U13 Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and +U9 Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U34 Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter +U35 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/74153/Dual4to1MUX.sch b/library/SubcircuitLibrary/74153/Dual4to1MUX.sch new file mode 100644 index 00000000..340b1a31 --- /dev/null +++ b/library/SubcircuitLibrary/74153/Dual4to1MUX.sch @@ -0,0 +1,814 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:74153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U14 +U 1 1 5C936BFE +P 3850 2450 +F 0 "U14" H 3850 2450 60 0000 C CNN +F 1 "d_and" H 3900 2550 60 0000 C CNN +F 2 "" H 3850 2450 60 0000 C CNN +F 3 "" H 3850 2450 60 0000 C CNN + 1 3850 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 5C936C8A +P 4850 2600 +F 0 "U25" H 4850 2600 60 0000 C CNN +F 1 "d_and" H 4900 2700 60 0000 C CNN +F 2 "" H 4850 2600 60 0000 C CNN +F 3 "" H 4850 2600 60 0000 C CNN + 1 4850 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5C936E84 +P 3800 3050 +F 0 "U5" H 3800 3050 60 0000 C CNN +F 1 "d_and" H 3850 3150 60 0000 C CNN +F 2 "" H 3800 3050 60 0000 C CNN +F 3 "" H 3800 3050 60 0000 C CNN + 1 3800 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 5C936E8A +P 4800 3200 +F 0 "U20" H 4800 3200 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"PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 2 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 3 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 4 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93AD97 +P 1350 5250 +F 0 "U1" H 1400 5350 30 0000 C CNN +F 1 "PORT" H 1350 5250 30 0000 C CNN +F 2 "" H 1350 5250 60 0000 C CNN +F 3 "" H 1350 5250 60 0000 C CNN + 7 1350 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C93ADFC +P 1350 5850 +F 0 "U1" H 1400 5950 30 0000 C CNN +F 1 "PORT" H 1350 5850 30 0000 C CNN +F 2 "" H 1350 5850 60 0000 C CNN +F 3 "" H 1350 5850 60 0000 C CNN + 8 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0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 2600 7600 2600 +Wire Wire Line + 7300 5250 7650 5250 +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3400 5100 +Wire Wire Line + 3400 5000 2300 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3350 5600 +Wire Wire Line + 2200 5700 3350 5700 +Wire Wire Line + 2200 6200 3350 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3350 6100 +Wire Wire Line + 3400 2450 3200 2450 +Connection ~ 3200 2450 +Wire Wire Line + 3400 2350 2300 2350 +Connection ~ 2300 2350 +Wire Wire Line + 3350 3050 2200 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3350 2950 3100 2950 +Connection ~ 3100 2950 +Wire Wire Line + 3350 3450 2300 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 3350 3550 2200 3550 +Connection ~ 2200 3550 +$Comp +L d_inverter U34 +U 1 1 5C95C9D0 +P 2650 3950 +F 0 "U34" H 2650 3850 60 0000 C CNN +F 1 "d_inverter" H 2650 4100 60 0000 C CNN +F 2 "" H 2700 3900 60 0000 C CNN +F 3 "" H 2700 3900 60 0000 C CNN + 1 2650 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 5C95CD17 +P 2700 6600 +F 0 "U35" H 2700 6500 60 0000 C CNN +F 1 "d_inverter" H 2700 6750 60 0000 C CNN +F 2 "" H 2750 6550 60 0000 C CNN +F 3 "" H 2750 6550 60 0000 C CNN + 1 2700 6600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/analysis b/library/SubcircuitLibrary/74153/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74153/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74157/3_and-cache.lib b/library/SubcircuitLibrary/74157/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74157/3_and.cir b/library/SubcircuitLibrary/74157/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74157/3_and.cir.out b/library/SubcircuitLibrary/74157/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74157/3_and.pro b/library/SubcircuitLibrary/74157/3_and.pro new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/library/SubcircuitLibrary/74157/3_and.sch b/library/SubcircuitLibrary/74157/3_and.sch new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74157/3_and.sub b/library/SubcircuitLibrary/74157/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74157/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74157/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74157/74157-cache.lib b/library/SubcircuitLibrary/74157/74157-cache.lib new file mode 100644 index 00000000..de171255 --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74157/74157.cir b/library/SubcircuitLibrary/74157/74157.cir new file mode 100644 index 00000000..6920161c --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157.cir @@ -0,0 +1,25 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74157\74157.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:37:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad12_ d_or +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad13_ d_or +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad14_ d_or +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad11_ d_or +U3 Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter +X2 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U20-Pad1_ 3_and +X3 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U21-Pad1_ 3_and +X4 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U22-Pad1_ 3_and +X5 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U23-Pad1_ 3_and +X6 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad2_ 3_and +X7 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U21-Pad2_ 3_and +X1 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U22-Pad2_ 3_and +X8 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad8_ Net-_U23-Pad2_ 3_and + +.end diff --git a/library/SubcircuitLibrary/74157/74157.cir.out b/library/SubcircuitLibrary/74157/74157.cir.out new file mode 100644 index 00000000..3a11a42d --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157.cir.out @@ -0,0 +1,45 @@ +* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir + +.include 3_and.sub +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or +* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and +x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and +x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and +x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and +x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23 +a5 net-_u1-pad10_ net-_u3-pad2_ u3 +a6 net-_u1-pad9_ net-_u2-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74157/74157.pro b/library/SubcircuitLibrary/74157/74157.pro new file mode 100644 index 00000000..fcbb1fc8 --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157.pro @@ -0,0 +1,57 @@ +update=03/28/19 22:30:06 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_User +LibName24=eSim_Subckt diff --git a/library/SubcircuitLibrary/74157/74157.sch b/library/SubcircuitLibrary/74157/74157.sch new file mode 100644 index 00000000..7fd3609e --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157.sch @@ -0,0 +1,549 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:74157-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 1650 1850 2750 1850 +Wire Wire Line + 2750 3350 1650 3350 +Wire Wire Line + 2750 3050 2750 3350 +Wire Wire Line + 2800 4050 1650 4050 +Wire Wire Line + 2800 3550 2800 4050 +Wire Wire Line + 2200 2150 2200 4350 +Wire Wire Line + 2200 2150 1650 2150 +Wire Wire Line + 2150 2900 2150 4850 +Wire Wire Line + 2150 2900 1650 2900 +Wire Wire Line + 2100 3600 2100 5300 +Wire Wire Line + 2100 3600 1650 3600 +Wire Wire Line + 2050 4300 2050 5800 +Wire Wire Line + 1650 4300 2050 4300 +Wire Wire Line + 2200 5500 2200 6250 +$Comp +L d_or U20 +U 1 1 5C95E06C +P 6650 3300 +F 0 "U20" H 6650 3300 60 0000 C CNN +F 1 "d_or" H 6650 3400 60 0000 C CNN +F 2 "" H 6650 3300 60 0000 C CNN +F 3 "" H 6650 3300 60 0000 C CNN + 1 6650 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U21 +U 1 1 5C95E114 +P 6650 3800 +F 0 "U21" H 6650 3800 60 0000 C CNN +F 1 "d_or" H 6650 3900 60 0000 C CNN +F 2 "" H 6650 3800 60 0000 C CNN +F 3 "" H 6650 3800 60 0000 C CNN + 1 6650 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U22 +U 1 1 5C95E16E +P 6650 4250 +F 0 "U22" H 6650 4250 60 0000 C CNN +F 1 "d_or" H 6650 4350 60 0000 C CNN +F 2 "" H 6650 4250 60 0000 C CNN +F 3 "" H 6650 4250 60 0000 C CNN + 1 6650 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U23 +U 1 1 5C95E1C9 +P 6650 4750 +F 0 "U23" H 6650 4750 60 0000 C CNN +F 1 "d_or" H 6650 4850 60 0000 C CNN +F 2 "" H 6650 4750 60 0000 C CNN +F 3 "" H 6650 4750 60 0000 C CNN + 1 6650 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 3200 5950 3200 +Wire Wire Line + 5950 3200 5950 2000 +Wire Wire Line + 5950 2000 4750 2000 +Wire Wire Line + 6200 3700 5850 3700 +Wire Wire Line + 5850 3700 5850 2500 +Wire Wire Line + 5850 2500 4750 2500 +Wire Wire Line + 6200 4150 5750 4150 +Wire Wire Line + 5750 4150 5750 2950 +Wire Wire Line + 5750 2950 4750 2950 +Wire Wire Line + 6200 4650 5650 4650 +Wire Wire Line + 5650 4650 5650 3450 +Wire Wire Line + 5650 3450 4750 3450 +Wire Wire Line + 4750 4250 5450 4250 +Wire Wire Line + 5450 4250 5450 3300 +Wire Wire Line + 5450 3300 6200 3300 +Wire Wire Line + 4750 4750 5550 4750 +Wire Wire Line + 5550 4750 5550 3800 +Wire Wire Line + 5550 3800 6200 3800 +Wire Wire Line + 4700 5200 5600 5200 +Wire Wire Line + 5600 5200 5600 4250 +Wire Wire Line + 5600 4250 6200 4250 +Wire Wire Line + 4750 5700 5700 5700 +Wire Wire Line + 5700 5700 5700 4750 +Wire Wire Line + 5700 4750 6200 4750 +Wire Wire Line + 7100 3250 8300 3250 +Wire Wire Line + 7100 3750 8300 3750 +Wire Wire Line + 7100 4200 8300 4200 +Wire Wire Line + 7100 4700 8250 4700 +$Comp +L d_inverter U3 +U 1 1 5C95E74D +P 2750 6250 +F 0 "U3" H 2750 6150 60 0000 C CNN +F 1 "d_inverter" H 2750 6400 60 0000 C CNN +F 2 "" H 2800 6200 60 0000 C CNN +F 3 "" H 2800 6200 60 0000 C CNN + 1 2750 6250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1700 6250 2450 6250 +Connection ~ 2200 6250 +$Comp +L PORT U1 +U 1 1 5C95E920 +P 1400 1850 +F 0 "U1" H 1450 1950 30 0000 C CNN +F 1 "PORT" H 1400 1850 30 0000 C CNN +F 2 "" H 1400 1850 60 0000 C CNN +F 3 "" H 1400 1850 60 0000 C CNN + 1 1400 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C95E9CF +P 1400 2150 +F 0 "U1" H 1450 2250 30 0000 C CNN +F 1 "PORT" H 1400 2150 30 0000 C CNN +F 2 "" H 1400 2150 60 0000 C CNN +F 3 "" H 1400 2150 60 0000 C CNN + 2 1400 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C95EA28 +P 1400 2700 +F 0 "U1" H 1450 2800 30 0000 C CNN +F 1 "PORT" H 1400 2700 30 0000 C CNN +F 2 "" H 1400 2700 60 0000 C CNN +F 3 "" H 1400 2700 60 0000 C CNN + 3 1400 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C95EA9C +P 1400 2900 +F 0 "U1" H 1450 3000 30 0000 C CNN +F 1 "PORT" H 1400 2900 30 0000 C CNN +F 2 "" H 1400 2900 60 0000 C CNN +F 3 "" H 1400 2900 60 0000 C CNN + 4 1400 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C95EAFD +P 1400 3350 +F 0 "U1" H 1450 3450 30 0000 C CNN +F 1 "PORT" H 1400 3350 30 0000 C CNN +F 2 "" H 1400 3350 60 0000 C CNN +F 3 "" H 1400 3350 60 0000 C CNN + 5 1400 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C95EB63 +P 1400 3600 +F 0 "U1" H 1450 3700 30 0000 C CNN +F 1 "PORT" H 1400 3600 30 0000 C CNN +F 2 "" H 1400 3600 60 0000 C CNN +F 3 "" H 1400 3600 60 0000 C CNN + 6 1400 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C95EBC8 +P 1400 4050 +F 0 "U1" H 1450 4150 30 0000 C CNN +F 1 "PORT" H 1400 4050 30 0000 C CNN +F 2 "" H 1400 4050 60 0000 C CNN +F 3 "" H 1400 4050 60 0000 C CNN + 7 1400 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C95EC38 +P 1400 4300 +F 0 "U1" H 1450 4400 30 0000 C CNN +F 1 "PORT" H 1400 4300 30 0000 C CNN +F 2 "" H 1400 4300 60 0000 C CNN +F 3 "" H 1400 4300 60 0000 C CNN + 8 1400 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C95ECA1 +P 1450 6250 +F 0 "U1" H 1500 6350 30 0000 C CNN +F 1 "PORT" H 1450 6250 30 0000 C CNN +F 2 "" H 1450 6250 60 0000 C CNN +F 3 "" H 1450 6250 60 0000 C CNN + 10 1450 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C95ED51 +P 1400 6650 +F 0 "U1" H 1450 6750 30 0000 C CNN +F 1 "PORT" H 1400 6650 30 0000 C CNN +F 2 "" H 1400 6650 60 0000 C CNN +F 3 "" H 1400 6650 60 0000 C CNN + 9 1400 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C95EDCC +P 8550 3250 +F 0 "U1" H 8600 3350 30 0000 C CNN +F 1 "PORT" H 8550 3250 30 0000 C CNN +F 2 "" H 8550 3250 60 0000 C CNN +F 3 "" H 8550 3250 60 0000 C CNN + 12 8550 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C95EEA6 +P 8550 3750 +F 0 "U1" H 8600 3850 30 0000 C CNN +F 1 "PORT" H 8550 3750 30 0000 C CNN +F 2 "" H 8550 3750 60 0000 C CNN +F 3 "" H 8550 3750 60 0000 C CNN + 13 8550 3750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C95EF2D +P 8550 4200 +F 0 "U1" H 8600 4300 30 0000 C CNN +F 1 "PORT" H 8550 4200 30 0000 C CNN +F 2 "" H 8550 4200 60 0000 C CNN +F 3 "" H 8550 4200 60 0000 C CNN + 14 8550 4200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C95EFB5 +P 8500 4700 +F 0 "U1" H 8550 4800 30 0000 C CNN +F 1 "PORT" H 8500 4700 30 0000 C CNN +F 2 "" H 8500 4700 60 0000 C CNN +F 3 "" H 8500 4700 60 0000 C CNN + 11 8500 4700 + -1 0 0 1 +$EndComp +Text Notes 1950 1800 0 60 ~ 12 +A0\n +Text Notes 1950 2100 0 60 ~ 12 +A1 +Text Notes 1900 2650 0 60 ~ 12 +B0 +Text Notes 1900 2900 0 60 ~ 12 +B1\n +Text Notes 1900 3350 0 60 ~ 12 +C0\n +Text Notes 1900 3600 0 60 ~ 12 +C1\n +Text Notes 1800 4050 0 60 ~ 12 +D0 +Text Notes 1800 4300 0 60 ~ 12 +D1 +Text Notes 1850 6250 0 60 ~ 12 +SEL\n +Text Notes 1800 6650 0 60 ~ 12 +~EN +$Comp +L d_inverter U2 +U 1 1 5C95FD56 +P 2650 6650 +F 0 "U2" H 2650 6550 60 0000 C CNN +F 1 "d_inverter" H 2650 6800 60 0000 C CNN +F 2 "" H 2700 6600 60 0000 C CNN +F 3 "" H 2700 6600 60 0000 C CNN + 1 2650 6650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 6650 2950 6650 +Wire Wire Line + 1650 6650 2350 6650 +Text Notes 7850 3200 0 60 ~ 12 +YA +Text Notes 7850 3700 0 60 ~ 12 +YB +Text Notes 7850 4200 2 60 ~ 12 +YC +Text Notes 7800 4700 0 60 ~ 12 +YD +Wire Wire Line + 3450 2000 3900 2000 +Wire Wire Line + 3450 2000 3450 5700 +Wire Wire Line + 3450 2500 3900 2500 +Wire Wire Line + 3450 2950 3900 2950 +Connection ~ 3450 2500 +Wire Wire Line + 3450 3450 3900 3450 +Connection ~ 3450 2950 +Wire Wire Line + 3450 4250 3900 4250 +Connection ~ 3450 3450 +Wire Wire Line + 3450 4750 3900 4750 +Connection ~ 3450 4250 +Wire Wire Line + 3450 5200 3850 5200 +Connection ~ 3450 4750 +Wire Wire Line + 3400 5700 3900 5700 +Connection ~ 3450 5200 +Wire Wire Line + 3300 5600 3900 5600 +Wire Wire Line + 3300 4150 3300 5600 +Wire Wire Line + 3300 5100 3850 5100 +Wire Wire Line + 3300 4650 3900 4650 +Connection ~ 3300 5100 +Wire Wire Line + 3300 4150 3900 4150 +Connection ~ 3300 4650 +Wire Wire Line + 3250 3350 3900 3350 +Wire Wire Line + 3250 1900 3250 3350 +Wire Wire Line + 3250 2850 3900 2850 +Wire Wire Line + 3250 2400 3900 2400 +Connection ~ 3250 2850 +Wire Wire Line + 3250 1900 3900 1900 +Connection ~ 3250 2400 +Wire Wire Line + 3250 3000 3100 3000 +Wire Wire Line + 3100 3000 3100 6250 +Wire Wire Line + 3100 6250 3050 6250 +Connection ~ 3250 3000 +Wire Wire Line + 3300 5500 2200 5500 +Connection ~ 3300 5500 +Wire Wire Line + 3400 6650 3400 5700 +Connection ~ 3450 5700 +$Comp +L 3_and X2 +U 1 1 5C9D0110 +P 3450 2400 +F 0 "X2" H 4350 2700 60 0000 C CNN +F 1 "3_and" H 4400 2900 60 0000 C CNN +F 2 "" H 3450 2400 60 0000 C CNN +F 3 "" H 3450 2400 60 0000 C CNN + 1 3450 2400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 5C9D01B8 +P 3450 2900 +F 0 "X3" H 4350 3200 60 0000 C CNN +F 1 "3_and" H 4400 3400 60 0000 C CNN +F 2 "" H 3450 2900 60 0000 C CNN +F 3 "" H 3450 2900 60 0000 C CNN + 1 3450 2900 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 5C9D0222 +P 3450 3350 +F 0 "X4" H 4350 3650 60 0000 C CNN +F 1 "3_and" H 4400 3850 60 0000 C CNN +F 2 "" H 3450 3350 60 0000 C CNN +F 3 "" H 3450 3350 60 0000 C CNN + 1 3450 3350 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 5C9D0289 +P 3450 3850 +F 0 "X5" H 4350 4150 60 0000 C CNN +F 1 "3_and" H 4400 4350 60 0000 C CNN +F 2 "" H 3450 3850 60 0000 C CNN +F 3 "" H 3450 3850 60 0000 C CNN + 1 3450 3850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 5C9D0361 +P 3450 4650 +F 0 "X6" H 4350 4950 60 0000 C CNN +F 1 "3_and" H 4400 5150 60 0000 C CNN +F 2 "" H 3450 4650 60 0000 C CNN +F 3 "" H 3450 4650 60 0000 C CNN + 1 3450 4650 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X7 +U 1 1 5C9D0367 +P 3450 5150 +F 0 "X7" H 4350 5450 60 0000 C CNN +F 1 "3_and" H 4400 5650 60 0000 C CNN +F 2 "" H 3450 5150 60 0000 C CNN +F 3 "" H 3450 5150 60 0000 C CNN + 1 3450 5150 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 5C9D036D +P 3400 5600 +F 0 "X1" H 4300 5900 60 0000 C CNN +F 1 "3_and" H 4350 6100 60 0000 C CNN +F 2 "" H 3400 5600 60 0000 C CNN +F 3 "" H 3400 5600 60 0000 C CNN + 1 3400 5600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X8 +U 1 1 5C9D0373 +P 3450 6100 +F 0 "X8" H 4350 6400 60 0000 C CNN +F 1 "3_and" H 4400 6600 60 0000 C CNN +F 2 "" H 3450 6100 60 0000 C CNN +F 3 "" H 3450 6100 60 0000 C CNN + 1 3450 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 2100 2750 2100 +Wire Wire Line + 2750 2100 2750 1850 +Wire Wire Line + 3900 2600 1650 2600 +Wire Wire Line + 1650 2600 1650 2700 +Wire Wire Line + 3900 3050 2750 3050 +Wire Wire Line + 3900 3550 2800 3550 +Wire Wire Line + 2200 4350 3900 4350 +Wire Wire Line + 2150 4850 3900 4850 +Wire Wire Line + 2100 5300 3850 5300 +Wire Wire Line + 2050 5800 3900 5800 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74157/74157.sub b/library/SubcircuitLibrary/74157/74157.sub new file mode 100644 index 00000000..545741f5 --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157.sub @@ -0,0 +1,39 @@ +* Subcircuit 74157 +.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir +.include 3_and.sub +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or +* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and +x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and +x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and +x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and +x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23 +a5 net-_u1-pad10_ net-_u3-pad2_ u3 +a6 net-_u1-pad9_ net-_u2-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74157
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74157/74157_Previous_Values.xml b/library/SubcircuitLibrary/74157/74157_Previous_Values.xml new file mode 100644 index 00000000..85f14960 --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u4 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u12 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u13><u8 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u8><u16 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u16><u9 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u9><u17 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u17><u6 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u6><u14 name="type">d_and<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u7 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u7><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u10><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u22 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u23><u3 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74157/analysis b/library/SubcircuitLibrary/74157/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74157/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/3_and-cache.lib b/library/SubcircuitLibrary/7485/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/7485/3_and.cir b/library/SubcircuitLibrary/7485/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/7485/3_and.cir.out b/library/SubcircuitLibrary/7485/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/7485/3_and.pro b/library/SubcircuitLibrary/7485/3_and.pro new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/library/SubcircuitLibrary/7485/3_and.sch b/library/SubcircuitLibrary/7485/3_and.sch new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/3_and.sub b/library/SubcircuitLibrary/7485/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/3_and_Previous_Values.xml b/library/SubcircuitLibrary/7485/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/4_and-cache.lib b/library/SubcircuitLibrary/7485/4_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/7485/4_and.cir b/library/SubcircuitLibrary/7485/4_and.cir new file mode 100644 index 00000000..50d490fa --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/7485/4_and.cir.out b/library/SubcircuitLibrary/7485/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/7485/4_and.pro b/library/SubcircuitLibrary/7485/4_and.pro new file mode 100644 index 00000000..6eb77fff --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and.pro @@ -0,0 +1,57 @@ +update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/7485/4_and.sch b/library/SubcircuitLibrary/7485/4_and.sch new file mode 100644 index 00000000..883458e1 --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/4_and.sub b/library/SubcircuitLibrary/7485/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/4_and_Previous_Values.xml b/library/SubcircuitLibrary/7485/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/5_and-cache.lib b/library/SubcircuitLibrary/7485/5_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/7485/5_and.cir b/library/SubcircuitLibrary/7485/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/7485/5_and.cir.out b/library/SubcircuitLibrary/7485/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/7485/5_and.pro b/library/SubcircuitLibrary/7485/5_and.pro new file mode 100644 index 00000000..c82e4e6d --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and.pro @@ -0,0 +1,50 @@ +update=03/26/19 18:50:27 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/library/SubcircuitLibrary/7485/5_and.sch b/library/SubcircuitLibrary/7485/5_and.sch new file mode 100644 index 00000000..da927b09 --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and.sch @@ -0,0 +1,158 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/5_and.sub b/library/SubcircuitLibrary/7485/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/5_and_Previous_Values.xml b/library/SubcircuitLibrary/7485/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/7485-cache.lib b/library/SubcircuitLibrary/7485/7485-cache.lib new file mode 100644 index 00000000..6edb5033 --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485-cache.lib @@ -0,0 +1,175 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# c_gate +# +DEF c_gate X 0 40 Y Y 1 F N +F0 "X" 5900 4450 60 H V C CNN +F1 "c_gate" 5950 4700 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250 +P 2 0 1 0 5550 4850 6100 4850 N +P 4 0 1 0 5550 4850 5550 4250 6050 4250 6100 4250 N +X in1 1 5350 4800 200 R 50 50 1 1 I I +X in2 2 5350 4700 200 R 50 50 1 1 I I +X in3 3 5350 4600 200 R 50 50 1 1 I I +X in4 4 5350 4500 200 R 50 50 1 1 I I +X in5 5 5350 4400 200 R 50 50 1 1 I I +X in6 6 5350 4300 200 R 50 50 1 1 I I +X out 7 6500 4550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/7485/7485.cir b/library/SubcircuitLibrary/7485/7485.cir new file mode 100644 index 00000000..e15a357f --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485.cir @@ -0,0 +1,42 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\7485\7485.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 20:14:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U6 Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U18-Pad2_ d_nand +U7 Net-_U18-Pad2_ Net-_U1-Pad5_ Net-_U14-Pad2_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor +U19 Net-_U1-Pad5_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and +X12 Net-_U1-Pad7_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad4_ 3_and +X7 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X2-Pad3_ 4_and +X9 Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X2-Pad4_ 5_and +X10 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad1_ Net-_X10-Pad6_ 5_and +X11 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X11-Pad6_ 5_and +X13 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad2_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad13_ 5_and +U18 Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +X8 Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad5_ 3_and +X3 Net-_U1-Pad8_ Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U15-Pad3_ Net-_X1-Pad4_ 4_and +X6 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X1-Pad3_ 5_and +X5 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X1-Pad2_ 5_and +X4 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X1-Pad1_ 5_and +U8 Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and +U3 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U3-Pad3_ d_nand +U9 Net-_U3-Pad3_ Net-_U1-Pad7_ Net-_U15-Pad2_ d_and +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor +U12 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U5 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U12-Pad2_ d_nand +U13 Net-_U12-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad3_ d_and +U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nor +U10 Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U4 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad2_ d_nand +U11 Net-_U10-Pad2_ Net-_U1-Pad9_ Net-_U11-Pad3_ d_and +U16 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_nor +X2 Net-_U19-Pad3_ Net-_X12-Pad4_ Net-_X2-Pad3_ Net-_X2-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad12_ c_gate +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad14_ c_gate +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/7485/7485.cir.out b/library/SubcircuitLibrary/7485/7485.cir.out new file mode 100644 index 00000000..afc7b865 --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485.cir.out @@ -0,0 +1,101 @@ +* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir + +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +.include c_gate.sub +* u6 net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u19 net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and +x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and +x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and +x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and +* u18 net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and +x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and +x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and +x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and +x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and +x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and +* u8 net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7 +a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9 +a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/7485/7485.pro b/library/SubcircuitLibrary/7485/7485.pro new file mode 100644 index 00000000..8fb4abb4 --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485.pro @@ -0,0 +1,58 @@ +update=03/26/19 19:27:48 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_User +LibName25=eSim_Subckt diff --git a/library/SubcircuitLibrary/7485/7485.sch b/library/SubcircuitLibrary/7485/7485.sch new file mode 100644 index 00000000..0db5f0d6 --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485.sch @@ -0,0 +1,1127 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:7485-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U6 +U 1 1 5C9A2432 +P 3150 1200 +F 0 "U6" H 3150 1200 60 0000 C CNN +F 1 "d_and" H 3200 1300 60 0000 C CNN +F 2 "" H 3150 1200 60 0000 C CNN +F 3 "" H 3150 1200 60 0000 C CNN + 1 3150 1200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U2 +U 1 1 5C9A246F +P 2100 1450 +F 0 "U2" H 2100 1450 60 0000 C CNN +F 1 "d_nand" H 2150 1550 60 0000 C CNN +F 2 "" H 2100 1450 60 0000 C CNN +F 3 "" H 2100 1450 60 0000 C CNN + 1 2100 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5C9A24BA +P 3150 1600 +F 0 "U7" H 3150 1600 60 0000 C CNN +F 1 "d_and" H 3200 1700 60 0000 C CNN +F 2 "" H 3150 1600 60 0000 C CNN +F 3 "" H 3150 1600 60 0000 C CNN + 1 3150 1600 + 1 0 0 -1 +$EndComp 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6950 5750 +Wire Wire Line + 6850 6250 6850 5850 +Wire Wire Line + 6850 5850 7350 5850 +Wire Wire Line + 7350 5850 7350 5500 +Wire Wire Line + 7350 5500 8200 5500 +Wire Wire Line + 6800 6950 6950 6950 +Wire Wire Line + 6950 6950 6950 6200 +Wire Wire Line + 6950 6200 7950 6200 +Wire Wire Line + 7950 6200 7950 5700 +Wire Wire Line + 7950 5700 8200 5700 +$Comp +L PORT U1 +U 4 1 5C9A8539 +P 850 1350 +F 0 "U1" H 900 1450 30 0000 C CNN +F 1 "PORT" H 850 1350 30 0000 C CNN +F 2 "" H 850 1350 60 0000 C CNN +F 3 "" H 850 1350 60 0000 C CNN + 4 850 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A8668 +P 850 1550 +F 0 "U1" H 900 1650 30 0000 C CNN +F 1 "PORT" H 850 1550 30 0000 C CNN +F 2 "" H 850 1550 60 0000 C CNN +F 3 "" H 850 1550 60 0000 C CNN + 5 850 1550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1100 1550 1100 1450 +$Comp +L PORT U1 +U 6 1 5C9A8815 +P 950 2650 +F 0 "U1" H 1000 2750 30 0000 C CNN +F 1 "PORT" H 950 2650 30 0000 C CNN +F 2 "" H 950 2650 60 0000 C CNN +F 3 "" H 950 2650 60 0000 C CNN + 6 950 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1200 2650 1200 2750 +$Comp +L PORT U1 +U 7 1 5C9A8B82 +P 950 2850 +F 0 "U1" H 1000 2950 30 0000 C CNN +F 1 "PORT" H 950 2850 30 0000 C CNN +F 2 "" H 950 2850 60 0000 C CNN +F 3 "" H 950 2850 60 0000 C CNN + 7 950 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C9A8C46 +P 950 3900 +F 0 "U1" H 1000 4000 30 0000 C CNN +F 1 "PORT" H 950 3900 30 0000 C CNN +F 2 "" H 950 3900 60 0000 C CNN +F 3 "" H 950 3900 60 0000 C CNN + 8 950 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C9A8D2C +P 950 4100 +F 0 "U1" H 1000 4200 30 0000 C CNN +F 1 "PORT" H 950 4100 30 0000 C CNN +F 2 "" H 950 4100 60 0000 C CNN +F 3 "" H 950 4100 60 0000 C CNN + 9 950 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C9A8DBD +P 1000 5100 +F 0 "U1" H 1050 5200 30 0000 C CNN +F 1 "PORT" H 1000 5100 30 0000 C CNN +F 2 "" H 1000 5100 60 0000 C CNN +F 3 "" H 1000 5100 60 0000 C CNN + 10 1000 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C9A8E65 +P 1000 5300 +F 0 "U1" H 1050 5400 30 0000 C CNN +F 1 "PORT" H 1000 5300 30 0000 C CNN +F 2 "" H 1000 5300 60 0000 C CNN +F 3 "" H 1000 5300 60 0000 C CNN + 11 1000 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A8EEE +P 800 3150 +F 0 "U1" H 850 3250 30 0000 C CNN +F 1 "PORT" H 800 3150 30 0000 C CNN +F 2 "" H 800 3150 60 0000 C CNN +F 3 "" H 800 3150 60 0000 C CNN + 1 800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A8F9C +P 800 3400 +F 0 "U1" H 850 3500 30 0000 C CNN +F 1 "PORT" H 800 3400 30 0000 C CNN +F 2 "" H 800 3400 60 0000 C CNN +F 3 "" H 800 3400 60 0000 C CNN + 2 800 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A9031 +P 800 3600 +F 0 "U1" H 850 3700 30 0000 C CNN +F 1 "PORT" H 800 3600 30 0000 C CNN +F 2 "" H 800 3600 60 0000 C CNN +F 3 "" H 800 3600 60 0000 C CNN + 3 800 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 3250 1050 3150 +Wire Wire Line + 1050 3550 1050 3600 +Wire Wire Line + 1350 4000 1350 4100 +Wire Wire Line + 1350 4100 1200 4100 +Wire Wire Line + 9550 2050 9850 2050 +Wire Wire Line + 9400 3950 9850 3950 +Wire Wire Line + 9350 5450 9900 5450 +$Comp +L PORT U1 +U 12 1 5C9A9B26 +P 10100 2050 +F 0 "U1" H 10150 2150 30 0000 C CNN +F 1 "PORT" H 10100 2050 30 0000 C CNN +F 2 "" H 10100 2050 60 0000 C CNN +F 3 "" H 10100 2050 60 0000 C CNN + 12 10100 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C9A9BCA +P 10100 3950 +F 0 "U1" H 10150 4050 30 0000 C CNN +F 1 "PORT" H 10100 3950 30 0000 C CNN +F 2 "" H 10100 3950 60 0000 C CNN +F 3 "" H 10100 3950 60 0000 C CNN + 13 10100 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C9A9CA0 +P 10150 5450 +F 0 "U1" H 10200 5550 30 0000 C CNN +F 1 "PORT" H 10150 5450 30 0000 C CNN +F 2 "" H 10150 5450 60 0000 C CNN +F 3 "" H 10150 5450 60 0000 C CNN + 14 10150 5450 + -1 0 0 1 +$EndComp +Text Notes 9650 2000 0 60 ~ 12 +A>B +Text Notes 9600 3900 0 60 ~ 12 +A=B\n +Text Notes 9600 5400 0 60 ~ 12 +A<B\n +Text Notes 1250 5100 0 60 ~ 12 +A0 +Text Notes 1200 5400 0 60 ~ 12 +B0 +Text Notes 1300 3900 2 60 ~ 12 +A1 +Text Notes 1300 4200 2 60 ~ 12 +B1 +Text Notes 1250 3250 2 60 ~ 12 +A<B +Text Notes 1250 3400 2 60 ~ 12 +A=B +Text Notes 1250 3550 2 60 ~ 12 +A>B +Text Notes 1350 2750 2 60 ~ 12 +A2 +Text Notes 1350 2950 2 60 ~ 12 +B2 +Text Notes 1300 1350 2 60 ~ 12 +A3 +Text Notes 1300 1550 2 60 ~ 12 +B3 +Wire Wire Line + 8200 5600 7450 5600 +Wire Wire Line + 7450 5600 7450 6050 +Wire Wire Line + 7450 6050 6900 6050 +Wire Wire Line + 6800 6650 6800 6300 +Wire Wire Line + 6800 6300 6900 6300 +Wire Wire Line + 6900 6300 6900 6050 +Wire Notes Line + 500 3000 1350 3000 +Wire Notes Line + 1350 3000 1350 3750 +Wire Notes Line + 1350 3750 500 3750 +Wire Notes Line + 500 3750 500 3000 +Text Notes 600 3000 3 60 ~ 12 +Cascading Inputs +Wire Notes Line + 9500 1550 9500 6050 +Wire Notes Line + 9500 6050 10550 6050 +Wire Notes Line + 10550 6050 10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +Wire Wire Line + 2600 3400 2050 3400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/7485.sub b/library/SubcircuitLibrary/7485/7485.sub new file mode 100644 index 00000000..5a45c57c --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485.sub @@ -0,0 +1,95 @@ +* Subcircuit 7485 +.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +.include c_gate.sub +* u6 net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u19 net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and +x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and +x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and +x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and +* u18 net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and +x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and +x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and +x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and +x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and +x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and +* u8 net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate +a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7 +a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9 +a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 7485
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/7485_Previous_Values.xml b/library/SubcircuitLibrary/7485/7485_Previous_Values.xml new file mode 100644 index 00000000..6d8f93b6 --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u6 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nand<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u7 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u7><u14 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u14><u19 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u19><u18 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u3 name="type">d_nand<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u3><u9 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u9><u15 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u12 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_nand<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u13><u17 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u10 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u10><u4 name="type">d_nand<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u4><u11 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u11><u16 name="type">d_nor<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x1><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x9><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x10><x11><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x11><x12><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x12><x13><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x13><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
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8050 5200 6950 5200 +Wire Wire Line + 8200 5400 7250 5400 +Wire Wire Line + 7250 5400 7250 5750 +Wire Wire Line + 7250 5750 6950 5750 +Wire Wire Line + 6850 6250 6850 5850 +Wire Wire Line + 6850 5850 7350 5850 +Wire Wire Line + 7350 5850 7350 5500 +Wire Wire Line + 7350 5500 8200 5500 +Wire Wire Line + 6800 6950 6950 6950 +Wire Wire Line + 6950 6950 6950 6200 +Wire Wire Line + 6950 6200 7950 6200 +Wire Wire Line + 7950 6200 7950 5700 +Wire Wire Line + 7950 5700 8200 5700 +$Comp +L PORT U1 +U 4 1 5C9A8539 +P 850 1350 +F 0 "U1" H 900 1450 30 0000 C CNN +F 1 "PORT" H 850 1350 30 0000 C CNN +F 2 "" H 850 1350 60 0000 C CNN +F 3 "" H 850 1350 60 0000 C CNN + 4 850 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A8668 +P 850 1550 +F 0 "U1" H 900 1650 30 0000 C CNN +F 1 "PORT" H 850 1550 30 0000 C CNN +F 2 "" H 850 1550 60 0000 C CNN +F 3 "" H 850 1550 60 0000 C CNN + 5 850 1550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1100 1550 1100 1450 +$Comp +L PORT U1 +U 6 1 5C9A8815 +P 950 2650 +F 0 "U1" H 1000 2750 30 0000 C CNN +F 1 "PORT" H 950 2650 30 0000 C CNN +F 2 "" H 950 2650 60 0000 C CNN +F 3 "" H 950 2650 60 0000 C CNN + 6 950 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1200 2650 1200 2750 +$Comp +L PORT U1 +U 7 1 5C9A8B82 +P 950 2850 +F 0 "U1" H 1000 2950 30 0000 C CNN +F 1 "PORT" H 950 2850 30 0000 C CNN +F 2 "" H 950 2850 60 0000 C CNN +F 3 "" H 950 2850 60 0000 C CNN + 7 950 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C9A8C46 +P 950 3900 +F 0 "U1" H 1000 4000 30 0000 C CNN +F 1 "PORT" H 950 3900 30 0000 C CNN +F 2 "" H 950 3900 60 0000 C CNN +F 3 "" H 950 3900 60 0000 C CNN + 8 950 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C9A8D2C +P 950 4100 +F 0 "U1" H 1000 4200 30 0000 C CNN +F 1 "PORT" H 950 4100 30 0000 C CNN +F 2 "" H 950 4100 60 0000 C CNN +F 3 "" H 950 4100 60 0000 C CNN + 9 950 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C9A8DBD +P 1000 5100 +F 0 "U1" H 1050 5200 30 0000 C CNN +F 1 "PORT" H 1000 5100 30 0000 C CNN +F 2 "" H 1000 5100 60 0000 C CNN +F 3 "" H 1000 5100 60 0000 C CNN + 10 1000 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C9A8E65 +P 1000 5300 +F 0 "U1" H 1050 5400 30 0000 C CNN +F 1 "PORT" H 1000 5300 30 0000 C CNN +F 2 "" H 1000 5300 60 0000 C CNN +F 3 "" H 1000 5300 60 0000 C CNN + 11 1000 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A8EEE +P 800 3150 +F 0 "U1" H 850 3250 30 0000 C CNN +F 1 "PORT" H 800 3150 30 0000 C CNN +F 2 "" H 800 3150 60 0000 C CNN +F 3 "" H 800 3150 60 0000 C CNN + 1 800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A8F9C +P 800 3400 +F 0 "U1" H 850 3500 30 0000 C CNN +F 1 "PORT" H 800 3400 30 0000 C CNN +F 2 "" H 800 3400 60 0000 C CNN +F 3 "" H 800 3400 60 0000 C CNN + 2 800 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A9031 +P 800 3600 +F 0 "U1" H 850 3700 30 0000 C CNN +F 1 "PORT" H 800 3600 30 0000 C CNN +F 2 "" H 800 3600 60 0000 C CNN +F 3 "" H 800 3600 60 0000 C CNN + 3 800 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 3250 1050 3150 +Wire Wire Line + 1050 3550 1050 3600 +Wire Wire Line + 1350 4000 1350 4100 +Wire Wire Line + 1350 4100 1200 4100 +Wire Wire Line + 9550 2050 9850 2050 +Wire Wire Line + 9400 3950 9850 3950 +Wire Wire Line + 9350 5450 9900 5450 +$Comp +L PORT U1 +U 12 1 5C9A9B26 +P 10100 2050 +F 0 "U1" H 10150 2150 30 0000 C CNN +F 1 "PORT" H 10100 2050 30 0000 C CNN +F 2 "" H 10100 2050 60 0000 C CNN +F 3 "" H 10100 2050 60 0000 C CNN + 12 10100 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C9A9BCA +P 10100 3950 +F 0 "U1" H 10150 4050 30 0000 C CNN +F 1 "PORT" H 10100 3950 30 0000 C CNN +F 2 "" H 10100 3950 60 0000 C CNN +F 3 "" H 10100 3950 60 0000 C CNN + 13 10100 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C9A9CA0 +P 10150 5450 +F 0 "U1" H 10200 5550 30 0000 C CNN +F 1 "PORT" H 10150 5450 30 0000 C CNN +F 2 "" H 10150 5450 60 0000 C CNN +F 3 "" H 10150 5450 60 0000 C CNN + 14 10150 5450 + -1 0 0 1 +$EndComp +Text Notes 9650 2000 0 60 ~ 12 +A>B +Text Notes 9600 3900 0 60 ~ 12 +A=B\n +Text Notes 9600 5400 0 60 ~ 12 +A<B\n +Text Notes 1250 5100 0 60 ~ 12 +A0 +Text Notes 1200 5400 0 60 ~ 12 +B0 +Text Notes 1300 3900 2 60 ~ 12 +A1 +Text Notes 1300 4200 2 60 ~ 12 +B1 +Text Notes 1250 3250 2 60 ~ 12 +A<B +Text Notes 1250 3400 2 60 ~ 12 +A=B +Text Notes 1250 3550 2 60 ~ 12 +A>B +Text Notes 1350 2750 2 60 ~ 12 +A2 +Text Notes 1350 2950 2 60 ~ 12 +B2 +Text Notes 1300 1350 2 60 ~ 12 +A3 +Text Notes 1300 1550 2 60 ~ 12 +B3 +Wire Wire Line + 8200 5600 7450 5600 +Wire Wire Line + 7450 5600 7450 6050 +Wire Wire Line + 7450 6050 6900 6050 +Wire Wire Line + 6800 6650 6800 6300 +Wire Wire Line + 6800 6300 6900 6300 +Wire Wire Line + 6900 6300 6900 6050 +Wire Notes Line + 500 3000 1350 3000 +Wire Notes Line + 1350 3000 1350 3750 +Wire Notes Line + 1350 3750 500 3750 +Wire Notes Line + 500 3750 500 3000 +Text Notes 600 3000 3 60 ~ 12 +Cascading Inputs +Wire Notes Line + 9500 1550 9500 6050 +Wire Notes Line + 9500 6050 10550 6050 +Wire Notes Line + 10550 6050 10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/analysis b/library/SubcircuitLibrary/7485/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/7485/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/c_gate-cache.lib b/library/SubcircuitLibrary/7485/c_gate-cache.lib new file mode 100644 index 00000000..05fb44d7 --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/7485/c_gate.cir b/library/SubcircuitLibrary/7485/c_gate.cir new file mode 100644 index 00000000..1ac12515 --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and +U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT + +.end diff --git a/library/SubcircuitLibrary/7485/c_gate.cir.out b/library/SubcircuitLibrary/7485/c_gate.cir.out new file mode 100644 index 00000000..db7bb2f8 --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate.cir.out @@ -0,0 +1,42 @@ +* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir + +.include 5_and.sub +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/7485/c_gate.pro b/library/SubcircuitLibrary/7485/c_gate.pro new file mode 100644 index 00000000..f0743529 --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate.pro @@ -0,0 +1,57 @@ +update=03/26/19 19:06:59 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/7485/c_gate.sch b/library/SubcircuitLibrary/7485/c_gate.sch new file mode 100644 index 00000000..5d960c8d --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate.sch @@ -0,0 +1,246 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:c_gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5C9A2B0B +P 3300 3750 +F 0 "X1" H 4650 4550 60 0000 C CNN +F 1 "5_and" H 4700 4800 60 0000 C CNN +F 2 "" H 3300 3750 60 0000 C CNN +F 3 "" H 3300 3750 60 0000 C CNN + 1 3300 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C9A2B3E +P 5600 3300 +F 0 "U8" H 5600 3300 60 0000 C CNN +F 1 "d_and" H 5650 3400 60 0000 C CNN +F 2 "" H 5600 3300 60 0000 C CNN +F 3 "" H 5600 3300 60 0000 C CNN + 1 5600 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3200 5150 2850 +Wire Wire Line + 4150 2650 4150 2350 +Wire Wire Line + 4150 2350 3600 2350 +Wire Wire Line + 4150 2750 4050 2750 +Wire Wire Line + 4050 2750 4050 2550 +Wire Wire Line + 4050 2550 3600 2550 +Wire Wire Line + 4150 2850 3700 2850 +Wire Wire Line + 3700 2850 3700 2750 +Wire Wire Line + 3700 2750 3600 2750 +Wire Wire Line + 4150 2950 3600 2950 +Wire Wire Line + 4150 3050 4150 3150 +Wire Wire Line + 4150 3150 3600 3150 +Wire Wire Line + 5150 3300 3600 3300 +$Comp +L d_inverter U2 +U 1 1 5C9A2CDC +P 3300 2350 +F 0 "U2" H 3300 2250 60 0000 C CNN +F 1 "d_inverter" H 3300 2500 60 0000 C CNN +F 2 "" H 3350 2300 60 0000 C CNN +F 3 "" H 3350 2300 60 0000 C CNN + 1 3300 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C9A2D06 +P 3300 2550 +F 0 "U3" H 3300 2450 60 0000 C CNN +F 1 "d_inverter" H 3300 2700 60 0000 C CNN +F 2 "" H 3350 2500 60 0000 C CNN +F 3 "" H 3350 2500 60 0000 C CNN + 1 3300 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5C9A2D26 +P 3300 2750 +F 0 "U4" H 3300 2650 60 0000 C CNN +F 1 "d_inverter" H 3300 2900 60 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3300 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5C9A2D49 +P 3300 2950 +F 0 "U5" H 3300 2850 60 0000 C CNN +F 1 "d_inverter" H 3300 3100 60 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 1 3300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5C9A2D73 +P 3300 3150 +F 0 "U6" H 3300 3050 60 0000 C CNN +F 1 "d_inverter" H 3300 3300 60 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 1 3300 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5C9A2D9E +P 3300 3300 +F 0 "U7" H 3300 3200 60 0000 C CNN +F 1 "d_inverter" H 3300 3450 60 0000 C CNN +F 2 "" H 3350 3250 60 0000 C CNN +F 3 "" H 3350 3250 60 0000 C CNN + 1 3300 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2350 2000 2350 +Wire Wire Line + 3000 2550 2000 2550 +Wire Wire Line + 3000 2750 2050 2750 +Wire Wire Line + 3000 2950 2050 2950 +Wire Wire Line + 3000 3150 2050 3150 +Wire Wire Line + 3000 3300 2050 3300 +Wire Wire Line + 6050 3250 6950 3250 +$Comp +L PORT U1 +U 1 1 5C9A2F6F +P 1750 2350 +F 0 "U1" H 1800 2450 30 0000 C CNN +F 1 "PORT" H 1750 2350 30 0000 C CNN +F 2 "" H 1750 2350 60 0000 C CNN +F 3 "" H 1750 2350 60 0000 C CNN + 1 1750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A2FAB +P 1750 2550 +F 0 "U1" H 1800 2650 30 0000 C CNN +F 1 "PORT" H 1750 2550 30 0000 C CNN +F 2 "" H 1750 2550 60 0000 C CNN +F 3 "" H 1750 2550 60 0000 C CNN + 2 1750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2FDD +P 1800 2750 +F 0 "U1" H 1850 2850 30 0000 C CNN +F 1 "PORT" H 1800 2750 30 0000 C CNN +F 2 "" H 1800 2750 60 0000 C CNN +F 3 "" H 1800 2750 60 0000 C CNN + 3 1800 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A301A +P 1800 2950 +F 0 "U1" H 1850 3050 30 0000 C CNN +F 1 "PORT" H 1800 2950 30 0000 C CNN +F 2 "" H 1800 2950 60 0000 C CNN +F 3 "" H 1800 2950 60 0000 C CNN + 4 1800 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A3052 +P 1800 3150 +F 0 "U1" H 1850 3250 30 0000 C CNN +F 1 "PORT" H 1800 3150 30 0000 C CNN +F 2 "" H 1800 3150 60 0000 C CNN +F 3 "" H 1800 3150 60 0000 C CNN + 5 1800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A308D +P 1800 3300 +F 0 "U1" H 1850 3400 30 0000 C CNN +F 1 "PORT" H 1800 3300 30 0000 C CNN +F 2 "" H 1800 3300 60 0000 C CNN +F 3 "" H 1800 3300 60 0000 C CNN + 6 1800 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C9A30DD +P 7200 3250 +F 0 "U1" H 7250 3350 30 0000 C CNN +F 1 "PORT" H 7200 3250 30 0000 C CNN +F 2 "" H 7200 3250 60 0000 C CNN +F 3 "" H 7200 3250 60 0000 C CNN + 7 7200 3250 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/c_gate.sub b/library/SubcircuitLibrary/7485/c_gate.sub new file mode 100644 index 00000000..c6eaa478 --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate.sub @@ -0,0 +1,36 @@ +* Subcircuit c_gate +.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ +* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir +.include 5_and.sub +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends c_gate
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/c_gate_Previous_Values.xml b/library/SubcircuitLibrary/7485/c_gate_Previous_Values.xml new file mode 100644 index 00000000..e51d62de --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib b/library/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib new file mode 100644 index 00000000..cc25b0c9 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir b/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out b/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out new file mode 100644 index 00000000..cb2b6641 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out @@ -0,0 +1,18 @@ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u1 net-_m1-pad2_ net-_c1-pad1_ port +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +.tran 0e-03 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS.pro b/library/SubcircuitLibrary/INVCMOS/INVCMOS.pro new file mode 100644 index 00000000..b3f410b6 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS.pro @@ -0,0 +1,73 @@ +update=Sun Aug 25 15:54:56 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User +LibName37=eSim_Plot +LibName38=eSim_PSpice +LibName39=/home/saurabh/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS.sch b/library/SubcircuitLibrary/INVCMOS/INVCMOS.sch new file mode 100644 index 00000000..13a7fc09 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:INVCMOS-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 4000 5900 4150 +Connection ~ 5800 2450 +Connection ~ 5800 4150 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5050 3350 +Wire Wire Line + 4000 3350 5050 3350 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 4200 3350 +$Comp +L PORT U1 +U 1 1 5D6263BC +P 3750 3350 +F 0 "U1" H 3800 3450 30 0000 C CNN +F 1 "PORT" H 3750 3350 30 0000 C CNN +F 2 "" H 3750 3350 60 0000 C CNN +F 3 "" H 3750 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3250 5800 3250 +Connection ~ 5800 3250 +Wire Wire Line + 5800 4050 5800 4550 +$Comp +L eSim_MOS_N M1 +U 1 1 5D6265DB +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 5D626659 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2850 6050 2850 +Wire Wire Line + 6050 2850 6050 2450 +Wire Wire Line + 6050 2450 5800 2450 +Connection ~ 6000 3250 +Connection ~ 5800 4300 +$Comp +L GND #PWR1 +U 1 1 5D626C59 +P 5800 4550 +F 0 "#PWR1" H 5800 4300 50 0001 C CNN +F 1 "GND" H 5800 4400 50 0000 C CNN +F 2 "" H 5800 4550 50 0001 C CNN +F 3 "" H 5800 4550 50 0001 C CNN + 1 5800 4550 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5D626C7F +P 6250 2300 +F 0 "v1" H 6050 2400 60 0000 C CNN +F 1 "5" H 6050 2250 60 0000 C CNN +F 2 "R1" H 5950 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 1 6250 2300 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR2 +U 1 1 5D626CF6 +P 6850 2300 +F 0 "#PWR2" H 6850 2050 50 0001 C CNN +F 1 "GND" H 6850 2150 50 0000 C CNN +F 2 "" H 6850 2300 50 0001 C CNN +F 3 "" H 6850 2300 50 0001 C CNN + 1 6850 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 2300 6700 2300 +$Comp +L PORT U1 +U 2 1 5D626DCB +P 6300 3250 +F 0 "U1" H 6350 3350 30 0000 C CNN +F 1 "PORT" H 6300 3250 30 0000 C CNN +F 2 "" H 6300 3250 60 0000 C CNN +F 3 "" H 6300 3250 60 0000 C CNN + 2 6300 3250 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D62796C +P 6050 3850 +F 0 "C1" H 6075 3950 50 0000 L CNN +F 1 "1u" H 6075 3750 50 0000 L CNN +F 2 "" H 6088 3700 30 0000 C CNN +F 3 "" H 6050 3850 60 0000 C CNN + 1 6050 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3700 6050 3400 +Wire Wire Line + 6050 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 3250 +Wire Wire Line + 6050 4000 6050 4300 +Wire Wire Line + 6050 4300 5800 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS.sub b/library/SubcircuitLibrary/INVCMOS/INVCMOS.sub new file mode 100644 index 00000000..2319995c --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS.sub @@ -0,0 +1,12 @@ +* Subcircuit INVCMOS +.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +* Control Statements + +.ends INVCMOS
\ No newline at end of file diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml b/library/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml new file mode 100644 index 00000000..e5bb98c7 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib b/library/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib b/library/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/INVCMOS/analysis b/library/SubcircuitLibrary/INVCMOS/analysis new file mode 100644 index 00000000..334c5333 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM7812/LM7812-cache.lib b/library/SubcircuitLibrary/LM7812/LM7812-cache.lib new file mode 100644 index 00000000..c02b3211 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812-cache.lib @@ -0,0 +1,135 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN-RESCUE-LM7812 +# +DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-LM7812 +# +DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM7812/LM7812-rescue.lib b/library/SubcircuitLibrary/LM7812/LM7812-rescue.lib new file mode 100644 index 00000000..e6cfa7d6 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812-rescue.lib @@ -0,0 +1,42 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# eSim_NPN-RESCUE-LM7812 +# +DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-LM7812 +# +DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM7812/LM7812.cir b/library/SubcircuitLibrary/LM7812/LM7812.cir new file mode 100644 index 00000000..3f0d3adf --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812.cir @@ -0,0 +1,51 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM7812/LM7812.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 10 16:26:28 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k +R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 +R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k +R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k +U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R5 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500 +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN +R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R7 Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k +Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R10 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k +Q7 Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R12 Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k +R9 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k +Q5 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP +R8 Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100 +R11 Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50 +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN +R13 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +R14 Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k +Q14 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN +R17 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k +R16 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 10.38k +R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k +U2 Net-_Q15-Pad2_ Net-_R15-Pad2_ zener +Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN +R18 Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200 +R20 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3 +R19 Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240 +U3 Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM7812/LM7812.cir.out b/library/SubcircuitLibrary/LM7812/LM7812.cir.out new file mode 100644 index 00000000..73404965 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812.cir.out @@ -0,0 +1,60 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir + +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 10.38k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +* u3 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM7812/LM7812.pro b/library/SubcircuitLibrary/LM7812/LM7812.pro new file mode 100644 index 00000000..12d08139 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812.pro @@ -0,0 +1,46 @@ +update=Mon Aug 26 14:09:03 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=LM7812-rescue +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User + diff --git a/library/SubcircuitLibrary/LM7812/LM7812.sch b/library/SubcircuitLibrary/LM7812/LM7812.sch new file mode 100644 index 00000000..ca95c2ca --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812.sch @@ -0,0 +1,758 @@ +EESchema Schematic File Version 2 +LIBS:LM7812-rescue +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:LM7812-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 5CE41429 +P 1250 1600 +F 0 "R1" V 1330 1600 50 0000 C CNN +F 1 "100k" V 1250 1600 50 0000 C CNN +F 2 "" V 1180 1600 50 0001 C CNN +F 3 "" H 1250 1600 50 0001 C CNN + 1 1250 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5CE4148B +P 1950 1600 +F 0 "R2" V 2030 1600 50 0000 C CNN +F 1 "500" V 1950 1600 50 0000 C CNN +F 2 "" V 1880 1600 50 0001 C CNN +F 3 "" H 1950 1600 50 0001 C CNN + 1 1950 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5CE414A5 +P 1950 3050 +F 0 "R3" V 2030 3050 50 0000 C CNN +F 1 "3.3k" V 1950 3050 50 0000 C CNN +F 2 "" V 1880 3050 50 0001 C CNN +F 3 "" H 1950 3050 50 0001 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5CE414CA +P 1950 3750 +F 0 "R4" V 2030 3750 50 0000 C CNN +F 1 "2.7k" V 1950 3750 50 0000 C CNN +F 2 "" V 1880 3750 50 0001 C CNN +F 3 "" H 1950 3750 50 0001 C CNN + 1 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 5CE414FA +P 1250 3350 +F 0 "U1" H 1200 3250 60 0000 C CNN +F 1 "zener" H 1250 3450 60 0000 C CNN +F 2 "" H 1300 3350 60 0000 C CNN +F 3 "" H 1300 3350 60 0000 C CNN + 1 1250 3350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q1 +U 1 1 5CE41586 +P 1850 2350 +F 0 "Q1" H 1750 2400 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN +F 2 "" H 2050 2450 29 0000 C CNN +F 3 "" H 1850 2350 60 0000 C CNN + 1 1850 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5CE418C5 +P 1950 4600 +F 0 "R5" V 2030 4600 50 0000 C CNN +F 1 "500" V 1950 4600 50 0000 C CNN +F 2 "" V 1880 4600 50 0001 C CNN +F 3 "" H 1950 4600 50 0001 C CNN + 1 1950 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 1750 1250 3050 +Wire Wire Line + 1250 1450 1250 1300 +Wire Wire Line + 1250 1300 1950 1300 +Wire Wire Line + 1950 1300 1950 1450 +Wire Wire Line + 1950 2150 1950 1750 +Wire Wire Line + 1950 2550 1950 2900 +Wire Wire Line + 1950 3200 1950 3600 +Wire Wire Line + 1950 3900 1950 4450 +Wire Wire Line + 1250 3550 1250 5200 +Wire Wire Line + 1250 5200 3200 5200 +Wire Wire Line + 1950 5200 1950 4750 +Wire Wire Line + 1650 2350 1250 2350 +Connection ~ 1250 2350 +$Comp +L eSim_NPN-RESCUE-LM7812 Q2 +U 1 1 5CE41D6C +P 2650 3350 +F 0 "Q2" H 2550 3400 50 0000 R CNN +F 1 "eSim_NPN" H 2600 3500 50 0000 R CNN +F 2 "" H 2850 3450 29 0000 C CNN +F 3 "" H 2650 3350 60 0000 C CNN + 1 2650 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q4 +U 1 1 5CE41E26 +P 3100 4100 +F 0 "Q4" H 3000 4150 50 0000 R CNN +F 1 "eSim_NPN" H 3050 4250 50 0000 R CNN +F 2 "" H 3300 4200 29 0000 C CNN +F 3 "" H 3100 4100 60 0000 C CNN + 1 3100 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 5CE41EA8 +P 2750 3850 +F 0 "R6" V 2830 3850 50 0000 C CNN +F 1 "1k" V 2750 3850 50 0000 C CNN +F 2 "" V 2680 3850 50 0001 C CNN +F 3 "" H 2750 3850 50 0001 C CNN + 1 2750 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q3 +U 1 1 5CE41EFE +P 2850 4650 +F 0 "Q3" H 2750 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN +F 2 "" H 3050 4750 29 0000 C CNN +F 3 "" H 2850 4650 60 0000 C CNN + 1 2850 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3550 2750 3700 +Wire Wire Line + 2750 4000 2750 4450 +Wire Wire Line + 2900 4100 2750 4100 +Connection ~ 2750 4100 +Wire Wire Line + 3200 4300 3200 4750 +Wire Wire Line + 3050 4650 3450 4650 +Wire Wire Line + 2450 3350 1950 3350 +Connection ~ 1950 3350 +Wire Wire Line + 2750 3600 3600 3600 +Wire Wire Line + 3200 3600 3200 3900 +Connection ~ 2750 3600 +$Comp +L R R7 +U 1 1 5CE42281 +P 3200 4900 +F 0 "R7" V 3280 4900 50 0000 C CNN +F 1 "6k" V 3200 4900 50 0000 C CNN +F 2 "" V 3130 4900 50 0001 C CNN +F 3 "" H 3200 4900 50 0001 C CNN + 1 3200 4900 + 1 0 0 -1 +$EndComp +Connection ~ 3200 4650 +Wire Wire Line + 3200 5050 3200 5250 +Connection ~ 1950 5200 +Wire Wire Line + 2750 4850 2750 5200 +Connection ~ 2750 5200 +$Comp +L eSim_NPN-RESCUE-LM7812 Q6 +U 1 1 5CE424FB +P 3650 4650 +F 0 "Q6" H 3550 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3600 4800 50 0000 R CNN +F 2 "" H 3850 4750 29 0000 C CNN +F 3 "" H 3650 4650 60 0000 C CNN + 1 3650 4650 + 1 0 0 -1 +$EndComp +$Comp +L R R10 +U 1 1 5CE42584 +P 3750 5100 +F 0 "R10" V 3830 5100 50 0000 C CNN +F 1 "1k" V 3750 5100 50 0000 C CNN +F 2 "" V 3680 5100 50 0001 C CNN +F 3 "" H 3750 5100 50 0001 C CNN + 1 3750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4850 3750 4950 +Wire Wire Line + 3200 5250 3750 5250 +Connection ~ 3200 5200 +$Comp +L eSim_NPN-RESCUE-LM7812 Q7 +U 1 1 5CE427DA +P 3700 2750 +F 0 "Q7" H 3600 2800 50 0000 R CNN +F 1 "eSim_NPN" H 3650 2900 50 0000 R CNN +F 2 "" H 3900 2850 29 0000 C CNN +F 3 "" H 3700 2750 60 0000 C CNN + 1 3700 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q8 +U 1 1 5CE428D0 +P 3700 3400 +F 0 "Q8" H 3600 3450 50 0000 R CNN +F 1 "eSim_NPN" H 3650 3550 50 0000 R CNN +F 2 "" H 3900 3500 29 0000 C CNN +F 3 "" H 3700 3400 60 0000 C CNN + 1 3700 3400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q12 +U 1 1 5CE4293A +P 4350 3000 +F 0 "Q12" H 4250 3050 50 0000 R CNN +F 1 "eSim_NPN" H 4300 3150 50 0000 R CNN +F 2 "" H 4550 3100 29 0000 C CNN +F 3 "" H 4350 3000 60 0000 C CNN + 1 4350 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2950 3600 3200 +Wire Wire Line + 4250 3200 4250 3400 +Wire Wire Line + 4250 3400 3900 3400 +Wire Wire Line + 4250 2750 4250 2800 +Wire Wire Line + 3900 2750 4250 2750 +Connection ~ 3200 3600 +$Comp +L R R12 +U 1 1 5CE42C4F +P 4350 3450 +F 0 "R12" V 4430 3450 50 0000 C CNN +F 1 "6k" V 4350 3450 50 0000 C CNN +F 2 "" V 4280 3450 50 0001 C CNN +F 3 "" H 4350 3450 50 0001 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 3300 4250 3300 +Connection ~ 4250 3300 +Wire Wire Line + 3700 3600 4350 3600 +Wire Wire Line + 3700 3600 3700 3650 +Wire Wire Line + 3700 3650 3550 3650 +Wire Wire Line + 3550 3650 3550 3600 +Connection ~ 3550 3600 +$Comp +L R R9 +U 1 1 5CE42EA3 +P 3750 3950 +F 0 "R9" V 3830 3950 50 0000 C CNN +F 1 "20k" V 3750 3950 50 0000 C CNN +F 2 "" V 3680 3950 50 0001 C CNN +F 3 "" H 3750 3950 50 0001 C CNN + 1 3750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4100 3750 4450 +Wire Wire Line + 3750 3800 3750 3600 +Connection ~ 3750 3600 +Wire Wire Line + 2750 3150 2750 2450 +Wire Wire Line + 2750 2450 3600 2450 +Wire Wire Line + 3600 2450 3600 2550 +$Comp +L eSim_PNP-RESCUE-LM7812 Q5 +U 1 1 5CE43397 +P 3450 1700 +F 0 "Q5" H 3350 1750 50 0000 R CNN +F 1 "eSim_PNP" H 3400 1850 50 0000 R CNN +F 2 "" H 3650 1800 29 0000 C CNN +F 3 "" H 3450 1700 60 0000 C CNN + 1 3450 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP-RESCUE-LM7812 Q9 +U 1 1 5CE4353C +P 4100 1700 +F 0 "Q9" H 4000 1750 50 0000 R CNN +F 1 "eSim_PNP" H 4050 1850 50 0000 R CNN +F 2 "" H 4300 1800 29 0000 C CNN +F 3 "" H 4100 1700 60 0000 C CNN + 1 4100 1700 + 1 0 0 1 +$EndComp +$Comp +L R R8 +U 1 1 5CE435B8 +P 3350 1250 +F 0 "R8" V 3430 1250 50 0000 C CNN +F 1 "100" V 3350 1250 50 0000 C CNN +F 2 "" V 3280 1250 50 0001 C CNN +F 3 "" H 3350 1250 50 0001 C CNN + 1 3350 1250 + 1 0 0 -1 +$EndComp +$Comp +L R R11 +U 1 1 5CE4368E +P 4200 1250 +F 0 "R11" V 4280 1250 50 0000 C CNN +F 1 "50" V 4200 1250 50 0000 C CNN +F 2 "" V 4130 1250 50 0001 C CNN +F 3 "" H 4200 1250 50 0001 C CNN + 1 4200 1250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q10 +U 1 1 5CE43705 +P 4100 2200 +F 0 "Q10" H 4000 2250 50 0000 R CNN +F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN +F 2 "" H 4300 2300 29 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 1400 3350 1500 +Wire Wire Line + 3650 1700 3900 1700 +Wire Wire Line + 4200 1400 4200 1500 +Wire Wire Line + 3350 1100 3350 1050 +Wire Wire Line + 1650 1050 7800 1050 +Wire Wire Line + 4200 1050 4200 1100 +Wire Wire Line + 4200 1900 4200 2000 +Wire Wire Line + 3750 1700 3750 2000 +Wire Wire Line + 3750 2000 3350 2000 +Wire Wire Line + 3350 1900 3350 2450 +Connection ~ 3750 1700 +Connection ~ 3350 2450 +Connection ~ 3350 2000 +Wire Wire Line + 2300 2200 3900 2200 +Wire Wire Line + 2300 2200 2300 4200 +Wire Wire Line + 2300 4200 1950 4200 +Connection ~ 1950 4200 +Wire Wire Line + 2200 2400 4200 2400 +Wire Wire Line + 2200 2400 2200 5200 +Connection ~ 2200 5200 +$Comp +L eSim_NPN-RESCUE-LM7812 Q11 +U 1 1 5CE4439E +P 4300 4400 +F 0 "Q11" H 4200 4450 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4550 50 0000 R CNN +F 2 "" H 4500 4500 29 0000 C CNN +F 3 "" H 4300 4400 60 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q13 +U 1 1 5CE44419 +P 4600 4800 +F 0 "Q13" H 4500 4850 50 0000 R CNN +F 1 "eSim_NPN" H 4550 4950 50 0000 R CNN +F 2 "" H 4800 4900 29 0000 C CNN +F 3 "" H 4600 4800 60 0000 C CNN + 1 4600 4800 + 1 0 0 -1 +$EndComp +$Comp +L R R13 +U 1 1 5CE444B9 +P 4400 5050 +F 0 "R13" V 4480 5050 50 0000 C CNN +F 1 "6k" V 4400 5050 50 0000 C CNN +F 2 "" V 4330 5050 50 0001 C CNN +F 3 "" H 4400 5050 50 0001 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE4451D +P 4050 4150 +F 0 "C1" H 4075 4250 50 0000 L CNN +F 1 "30p" H 4075 4050 50 0000 L CNN +F 2 "" H 4088 4000 30 0000 C CNN +F 3 "" H 4050 4150 60 0000 C CNN + 1 4050 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4100 4400 3750 4400 +Connection ~ 3750 4400 +Wire Wire Line + 3900 4150 3750 4150 +Connection ~ 3750 4150 +Wire Wire Line + 4700 4150 4200 4150 +Wire Wire Line + 4400 4150 4400 4200 +Wire Wire Line + 4400 4600 4400 4900 +Connection ~ 4400 4800 +Wire Wire Line + 4400 5200 4400 5300 +Wire Wire Line + 3650 5300 6400 5300 +Wire Wire Line + 3650 5300 3650 5250 +Connection ~ 3650 5250 +Wire Wire Line + 4700 5300 4700 5000 +Connection ~ 4400 5300 +Wire Wire Line + 4700 3800 4700 4600 +Connection ~ 4400 4150 +$Comp +L R R14 +U 1 1 5CE44FFF +P 4700 3650 +F 0 "R14" V 4780 3650 50 0000 C CNN +F 1 "6k" V 4700 3650 50 0000 C CNN +F 2 "" V 4630 3650 50 0001 C CNN +F 3 "" H 4700 3650 50 0001 C CNN + 1 4700 3650 + 1 0 0 -1 +$EndComp +Connection ~ 4700 4150 +$Comp +L eSim_PNP-RESCUE-LM7812 Q14 +U 1 1 5CE45652 +P 5050 3950 +F 0 "Q14" H 4950 4000 50 0000 R CNN +F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN +F 2 "" H 5250 4050 29 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5050 3950 + 1 0 0 1 +$EndComp +Wire Wire Line + 4850 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4700 3500 4700 3450 +Wire Wire Line + 4700 3450 5150 3450 +Wire Wire Line + 5150 3450 5150 3750 +Wire Wire Line + 5150 5300 5150 4150 +Connection ~ 4700 5300 +Wire Wire Line + 4750 3450 4750 1950 +Wire Wire Line + 4200 1950 5300 1950 +Connection ~ 4200 1950 +Connection ~ 4750 3450 +$Comp +L eSim_NPN-RESCUE-LM7812 Q15 +U 1 1 5CE463AD +P 5400 2150 +F 0 "Q15" H 5300 2200 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN +F 2 "" H 5600 2250 29 0000 C CNN +F 3 "" H 5400 2150 60 0000 C CNN + 1 5400 2150 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1950 +Wire Wire Line + 4150 2750 4150 2600 +Wire Wire Line + 4150 2600 6100 2600 +Wire Wire Line + 5300 2600 5300 2350 +Connection ~ 4150 2750 +$Comp +L R R17 +U 1 1 5CE46DDE +P 6050 4250 +F 0 "R17" V 6130 4250 50 0000 C CNN +F 1 "5k" V 6050 4250 50 0000 C CNN +F 2 "" V 5980 4250 50 0001 C CNN +F 3 "" H 6050 4250 50 0001 C CNN + 1 6050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R16 +U 1 1 5CE46F8E +P 6050 3050 +F 0 "R16" V 6130 3050 50 0000 C CNN +F 1 "10.38k" V 6050 3050 50 0000 C CNN +F 2 "" V 5980 3050 50 0001 C CNN +F 3 "" H 6050 3050 50 0001 C CNN + 1 6050 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3200 6050 4100 +Wire Wire Line + 6050 5300 6050 4400 +Connection ~ 5150 5300 +Wire Wire Line + 6050 2600 6050 2900 +Connection ~ 5300 2600 +Wire Wire Line + 4550 3000 5100 3000 +Wire Wire Line + 5100 3000 5100 3250 +Wire Wire Line + 5100 3250 5350 3250 +Wire Wire Line + 5350 3250 5350 3600 +Wire Wire Line + 5350 3600 6050 3600 +Connection ~ 6050 3600 +Wire Wire Line + 1650 1050 1650 1300 +Connection ~ 1650 1300 +Connection ~ 3350 1050 +$Comp +L R R15 +U 1 1 5CE47F7A +P 5850 1300 +F 0 "R15" V 5930 1300 50 0000 C CNN +F 1 "10k" V 5850 1300 50 0000 C CNN +F 2 "" V 5780 1300 50 0001 C CNN +F 3 "" H 5850 1300 50 0001 C CNN + 1 5850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1050 5850 1150 +Connection ~ 4200 1050 +$Comp +L zener U2 +U 1 1 5CE48686 +P 5850 1900 +F 0 "U2" H 5800 1800 60 0000 C CNN +F 1 "zener" H 5850 2000 60 0000 C CNN +F 2 "" H 5900 1900 60 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 1450 5850 1600 +Wire Wire Line + 5850 2100 5850 2250 +Wire Wire Line + 5850 2150 5600 2150 +$Comp +L eSim_NPN-RESCUE-LM7812 Q16 +U 1 1 5CE4907A +P 6550 1600 +F 0 "Q16" H 6450 1650 50 0000 R CNN +F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN +F 2 "" H 6750 1700 29 0000 C CNN +F 3 "" H 6550 1600 60 0000 C CNN + 1 6550 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q17 +U 1 1 5CE4942E +P 7300 1950 +F 0 "Q17" H 7200 2000 50 0000 R CNN +F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN +F 2 "" H 7500 2050 29 0000 C CNN +F 3 "" H 7300 1950 60 0000 C CNN + 1 7300 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 1800 6650 2300 +Wire Wire Line + 6650 1950 7100 1950 +Wire Wire Line + 7400 1050 7400 1750 +Connection ~ 5850 1050 +Wire Wire Line + 6650 1400 6650 1050 +Connection ~ 6650 1050 +$Comp +L R R18 +U 1 1 5CE498BA +P 6650 2450 +F 0 "R18" V 6730 2450 50 0000 C CNN +F 1 "200" V 6650 2450 50 0000 C CNN +F 2 "" V 6580 2450 50 0001 C CNN +F 3 "" H 6650 2450 50 0001 C CNN + 1 6650 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R20 +U 1 1 5CE4999A +P 7400 2450 +F 0 "R20" V 7480 2450 50 0000 C CNN +F 1 "0.3" V 7400 2450 50 0000 C CNN +F 2 "" V 7330 2450 50 0001 C CNN +F 3 "" H 7400 2450 50 0001 C CNN + 1 7400 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R19 +U 1 1 5CE49AF5 +P 7000 2250 +F 0 "R19" V 7080 2250 50 0000 C CNN +F 1 "240" V 7000 2250 50 0000 C CNN +F 2 "" V 6930 2250 50 0001 C CNN +F 3 "" H 7000 2250 50 0001 C CNN + 1 7000 2250 + 0 1 1 0 +$EndComp +Connection ~ 6650 1950 +Wire Wire Line + 5850 2250 6850 2250 +Connection ~ 5850 2150 +Wire Wire Line + 7400 2150 7400 2300 +Wire Wire Line + 7150 2250 7400 2250 +Connection ~ 7400 2250 +Wire Wire Line + 6100 2600 6100 2650 +Wire Wire Line + 6100 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 2600 +Connection ~ 6050 2600 +Wire Wire Line + 6650 2600 6650 2650 +Connection ~ 6650 2650 +$Comp +L PORT U3 +U 1 1 5CE4AAF6 +P 8050 1050 +F 0 "U3" H 8100 1150 30 0000 C CNN +F 1 "PORT" H 8050 1050 30 0000 C CNN +F 2 "" H 8050 1050 60 0000 C CNN +F 3 "" H 8050 1050 60 0000 C CNN + 1 8050 1050 + -1 0 0 1 +$EndComp +Connection ~ 7400 1050 +$Comp +L PORT U3 +U 3 1 5CE4B13E +P 7700 3000 +F 0 "U3" H 7750 3100 30 0000 C CNN +F 1 "PORT" H 7700 3000 30 0000 C CNN +F 2 "" H 7700 3000 60 0000 C CNN +F 3 "" H 7700 3000 60 0000 C CNN + 3 7700 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 2 1 5CE4B701 +P 6650 5300 +F 0 "U3" H 6700 5400 30 0000 C CNN +F 1 "PORT" H 6650 5300 30 0000 C CNN +F 2 "" H 6650 5300 60 0000 C CNN +F 3 "" H 6650 5300 60 0000 C CNN + 2 6650 5300 + -1 0 0 1 +$EndComp +Connection ~ 6050 5300 +Wire Wire Line + 6350 1600 5950 1600 +Wire Wire Line + 5950 1600 5950 1550 +Wire Wire Line + 5950 1550 5000 1550 +Wire Wire Line + 5000 1550 5000 1950 +Connection ~ 5000 1950 +Wire Wire Line + 7300 2650 7300 3000 +Wire Wire Line + 7300 3000 7450 3000 +Connection ~ 7300 2650 +Connection ~ 2500 5200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM7812/LM7812.sub b/library/SubcircuitLibrary/LM7812/LM7812.sub new file mode 100644 index 00000000..0dd95154 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812.sub @@ -0,0 +1,54 @@ +* Subcircuit LM7812 +.subckt LM7812 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 10.38k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Control Statements + +.ends LM7812
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml b/library/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml new file mode 100644 index 00000000..263f360c --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM7812/NPN.lib b/library/SubcircuitLibrary/LM7812/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM7812/PNP.lib b/library/SubcircuitLibrary/LM7812/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM7812/Q_PNP.lib b/library/SubcircuitLibrary/LM7812/Q_PNP.lib new file mode 100644 index 00000000..154ed2d8 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/Q_PNP.lib @@ -0,0 +1 @@ +.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM7812/analysis b/library/SubcircuitLibrary/LM7812/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_adder/analysis b/library/SubcircuitLibrary/full_adder/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_adder/full_adder-cache.lib b/library/SubcircuitLibrary/full_adder/full_adder-cache.lib new file mode 100644 index 00000000..623a7f41 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/full_adder/full_adder.cir b/library/SubcircuitLibrary/full_adder/full_adder.cir new file mode 100644 index 00000000..6461b5b6 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 8 7 6 2 half_adder +X2 5 6 4 3 half_adder +U1 8 7 5 4 1 PORT +U2 3 2 1 d_or + +.end diff --git a/library/SubcircuitLibrary/full_adder/full_adder.cir.out b/library/SubcircuitLibrary/full_adder/full_adder.cir.out new file mode 100644 index 00000000..b90ce70d --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 + +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u1 8 7 5 4 1 port +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/full_adder/full_adder.pro b/library/SubcircuitLibrary/full_adder/full_adder.pro new file mode 100644 index 00000000..c0db0775 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 12:19:16 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/library/SubcircuitLibrary/full_adder/full_adder.sch b/library/SubcircuitLibrary/full_adder/full_adder.sch new file mode 100644 index 00000000..8bd400f2 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.sch @@ -0,0 +1,180 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L half_adder X1 +U 1 1 558AA064 +P 3800 3350 +F 0 "X1" H 4700 3850 60 0000 C CNN +F 1 "half_adder" H 4700 3750 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L half_adder X2 +U 1 1 558AA0C1 +P 5700 3350 +F 0 "X2" H 6600 3850 60 0000 C CNN +F 1 "half_adder" H 6600 3750 60 0000 C CNN +F 2 "" H 5700 3350 60 0000 C CNN +F 3 "" H 5700 3350 60 0000 C CNN + 1 5700 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558AA277 +P 3450 2650 +F 0 "U1" H 3500 2750 30 0000 C CNN +F 1 "PORT" H 3450 2650 30 0000 C CNN +F 2 "" H 3450 2650 60 0000 C CNN +F 3 "" H 3450 2650 60 0000 C CNN + 1 3450 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558AA29E +P 3450 3250 +F 0 "U1" H 3500 3350 30 0000 C CNN +F 1 "PORT" H 3450 3250 30 0000 C CNN +F 2 "" H 3450 3250 60 0000 C CNN +F 3 "" H 3450 3250 60 0000 C CNN + 2 3450 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558AA2D8 +P 5650 2300 +F 0 "U1" H 5700 2400 30 0000 C CNN +F 1 "PORT" H 5650 2300 30 0000 C CNN +F 2 "" H 5650 2300 60 0000 C CNN +F 3 "" H 5650 2300 60 0000 C CNN + 3 5650 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 558AA378 +P 7900 2650 +F 0 "U1" H 7950 2750 30 0000 C CNN +F 1 "PORT" H 7900 2650 30 0000 C CNN +F 2 "" H 7900 2650 60 0000 C CNN +F 3 "" H 7900 2650 60 0000 C CNN + 4 7900 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 558AA3E0 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 5 8700 3400 + -1 0 0 1 +$EndComp +$Comp +L d_or U2 +U 1 1 558AA43B +P 7900 3450 +F 0 "U2" H 7900 3450 60 0000 C CNN +F 1 "d_or" H 7900 3550 60 0000 C CNN +F 2 "" H 7900 3450 60 0000 C CNN +F 3 "" H 7900 3450 60 0000 C CNN + 1 7900 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 2650 4100 2650 +Wire Wire Line + 3700 3250 4100 3250 +Wire Wire Line + 5250 2650 5650 2650 +Wire Wire Line + 5650 2650 5650 3250 +Wire Wire Line + 5650 3250 6000 3250 +Wire Wire Line + 5900 2300 5900 2650 +Wire Wire Line + 5900 2650 6000 2650 +Wire Wire Line + 7150 2650 7650 2650 +Wire Wire Line + 7150 3250 7350 3250 +Wire Wire Line + 7350 3250 7350 3350 +Wire Wire Line + 7350 3350 7450 3350 +Wire Wire Line + 5250 3250 5400 3250 +Wire Wire Line + 5400 3250 5400 3450 +Wire Wire Line + 5400 3450 7450 3450 +Wire Wire Line + 8350 3400 8450 3400 +Text Notes 3850 2500 0 60 ~ 0 +IN1 +Text Notes 3850 3150 0 60 ~ 0 +IN2 +Text Notes 6000 2350 0 60 ~ 0 +CIN +Text Notes 7350 2550 0 60 ~ 0 +SUM +Text Notes 8300 3200 0 60 ~ 0 +COUT +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/full_adder/full_adder.sub b/library/SubcircuitLibrary/full_adder/full_adder.sub new file mode 100644 index 00000000..5f261f78 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.sub @@ -0,0 +1,13 @@ +* Subcircuit full_adder +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml b/library/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml new file mode 100644 index 00000000..b63184d6 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_adder/half_adder-cache.lib b/library/SubcircuitLibrary/full_adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/full_adder/half_adder.cir b/library/SubcircuitLibrary/full_adder/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/library/SubcircuitLibrary/full_adder/half_adder.cir.out b/library/SubcircuitLibrary/full_adder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/full_adder/half_adder.pro b/library/SubcircuitLibrary/full_adder/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/library/SubcircuitLibrary/full_adder/half_adder.sch b/library/SubcircuitLibrary/full_adder/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/full_adder/half_adder.sub b/library/SubcircuitLibrary/full_adder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml b/library/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_sub/analysis b/library/SubcircuitLibrary/full_sub/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_sub/full_sub-cache.lib b/library/SubcircuitLibrary/full_sub/full_sub-cache.lib new file mode 100644 index 00000000..6949ac1a --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/full_sub/full_sub-rescue.lib b/library/SubcircuitLibrary/full_sub/full_sub-rescue.lib new file mode 100644 index 00000000..803b5ece --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub-rescue.lib @@ -0,0 +1,20 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# half_sub-RESCUE-full_sub +# +DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1450 850 1550 -1050 0 1 0 N +X A 1 -1100 850 200 R 50 50 1 1 I +X B 2 -350 850 200 R 50 50 1 1 I +X D 3 -800 -1050 200 L 50 50 1 1 O +X BORROW 4 0 -1050 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/full_sub/full_sub.cir b/library/SubcircuitLibrary/full_sub/full_sub.cir new file mode 100644 index 00000000..67359421 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.cir @@ -0,0 +1,14 @@ +* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or +U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT +X1 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub +X2 Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub + +.end diff --git a/library/SubcircuitLibrary/full_sub/full_sub.cir.out b/library/SubcircuitLibrary/full_sub/full_sub.cir.out new file mode 100644 index 00000000..5e58cc0a --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.cir.out @@ -0,0 +1,19 @@ +* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir + +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/full_sub/full_sub.pro b/library/SubcircuitLibrary/full_sub/full_sub.pro new file mode 100644 index 00000000..1a0c3543 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.pro @@ -0,0 +1,74 @@ +update=03/07/19 10:55:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=full_sub-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=device +LibName24=transistors +LibName25=conn +LibName26=linear +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_User +LibName39=eSim_Plot +LibName40=eSim_PSpice + diff --git a/library/SubcircuitLibrary/full_sub/full_sub.sch b/library/SubcircuitLibrary/full_sub/full_sub.sch new file mode 100644 index 00000000..99ca85e5 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.sch @@ -0,0 +1,211 @@ +EESchema Schematic File Version 2 +LIBS:full_sub-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:full_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U3 +U 1 1 5C80734A +P 9350 4050 +F 0 "U3" H 9350 4050 60 0000 C CNN +F 1 "d_or" H 9350 4150 60 0000 C CNN +F 2 "" H 9350 4050 60 0000 C CNN +F 3 "" H 9350 4050 60 0000 C CNN + 1 9350 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 3600 5800 3600 +Wire Wire Line + 4650 2800 8600 2800 +Wire Wire Line + 8600 2800 8600 3950 +Wire Wire Line + 8600 3950 8900 3950 +Wire Wire Line + 8100 4450 8650 4450 +Wire Wire Line + 8650 4450 8650 4050 +Wire Wire Line + 8650 4050 8900 4050 +Wire Wire Line + 2800 3450 2800 3250 +Wire Wire Line + 2800 3250 3300 3250 +Wire Wire Line + 1450 3550 3300 3550 +Wire Wire Line + 4050 5100 5200 5100 +Wire Wire Line + 5800 3600 5800 5250 +Wire Wire Line + 8250 5250 9350 5250 +Wire Wire Line + 9350 5250 9350 4900 +Wire Wire Line + 9350 4900 10750 4900 +Wire Wire Line + 9800 4000 9800 4600 +Wire Wire Line + 9800 4600 9550 4600 +Wire Wire Line + 9550 4600 9550 4800 +Wire Wire Line + 9550 4800 10750 4800 +$Comp +L PORT U5 +U 1 1 5C80A4E8 +P 1200 3450 +F 0 "U5" H 1250 3550 30 0000 C CNN +F 1 "PORT" H 1200 3450 30 0000 C CNN +F 2 "" H 1200 3450 60 0000 C CNN +F 3 "" H 1200 3450 60 0000 C CNN + 1 1200 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 2 1 5C80A51E +P 1200 3650 +F 0 "U5" H 1250 3750 30 0000 C CNN +F 1 "PORT" H 1200 3650 30 0000 C CNN +F 2 "" H 1200 3650 60 0000 C CNN +F 3 "" H 1200 3650 60 0000 C CNN + 2 1200 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 3 1 5C80A54E +P 3800 5100 +F 0 "U5" H 3850 5200 30 0000 C CNN +F 1 "PORT" H 3800 5100 30 0000 C CNN +F 2 "" H 3800 5100 60 0000 C CNN +F 3 "" H 3800 5100 60 0000 C CNN + 3 3800 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 5 1 5C80A828 +P 11000 4800 +F 0 "U5" H 11050 4900 30 0000 C CNN +F 1 "PORT" H 11000 4800 30 0000 C CNN +F 2 "" H 11000 4800 60 0000 C CNN +F 3 "" H 11000 4800 60 0000 C CNN + 5 11000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 4 1 5C80AB2A +P 11000 4950 +F 0 "U5" H 11050 5050 30 0000 C CNN +F 1 "PORT" H 11000 4950 30 0000 C CNN +F 2 "" H 11000 4950 60 0000 C CNN +F 3 "" H 11000 4950 60 0000 C CNN + 4 11000 4950 + -1 0 0 1 +$EndComp +Wire Wire Line + 1450 3450 2800 3450 +Wire Wire Line + 1450 3650 1450 3550 +Wire Wire Line + 10750 4900 10750 4950 +$Comp +L half_sub X1 +U 1 1 5C80AC4D +P 3800 3450 +F 0 "X1" H 3800 3450 60 0000 C CNN +F 1 "half_sub" H 3800 3450 60 0000 C CNN +F 2 "" H 3800 3450 60 0001 C CNN +F 3 "" H 3800 3450 60 0001 C CNN + 1 3800 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 3550 4650 3550 +Wire Wire Line + 4650 3550 4650 2800 +Wire Wire Line + 4300 3300 4850 3300 +Wire Wire Line + 4850 3300 4850 3600 +$Comp +L half_sub X2 +U 1 1 5C80AD72 +P 7300 5150 +F 0 "X2" H 7300 5150 60 0000 C CNN +F 1 "half_sub" H 7300 5150 60 0000 C CNN +F 2 "" H 7300 5150 60 0001 C CNN +F 3 "" H 7300 5150 60 0001 C CNN + 1 7300 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5800 5250 6800 5250 +Wire Wire Line + 5200 5100 5200 4950 +Wire Wire Line + 5200 4950 6800 4950 +Wire Wire Line + 7800 5000 8250 5000 +Wire Wire Line + 8250 5000 8250 5250 +Wire Wire Line + 7800 5250 8100 5250 +Wire Wire Line + 8100 5250 8100 4450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/full_sub/full_sub.sub b/library/SubcircuitLibrary/full_sub/full_sub.sub new file mode 100644 index 00000000..9c9dcc5a --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.sub @@ -0,0 +1,13 @@ +* Subcircuit full_sub +.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ +* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml b/library/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml new file mode 100644 index 00000000..fcdb63e0 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_sub/half_sub-cache.lib b/library/SubcircuitLibrary/full_sub/half_sub-cache.lib new file mode 100644 index 00000000..bd15e664 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/full_sub/half_sub.cir b/library/SubcircuitLibrary/full_sub/half_sub.cir new file mode 100644 index 00000000..f20f0368 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.cir @@ -0,0 +1,14 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/full_sub/half_sub.cir.out b/library/SubcircuitLibrary/full_sub/half_sub.cir.out new file mode 100644 index 00000000..91816956 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.cir.out @@ -0,0 +1,24 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/full_sub/half_sub.pro b/library/SubcircuitLibrary/full_sub/half_sub.pro new file mode 100644 index 00000000..90e3ded9 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.pro @@ -0,0 +1,74 @@ +update=Wed 06 Mar 2019 11:10:38 PM IST +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/library/SubcircuitLibrary/full_sub/half_sub.sch b/library/SubcircuitLibrary/full_sub/half_sub.sch new file mode 100644 index 00000000..e70b1675 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U3 +U 1 1 5C7FDDA3 +P 4400 3150 +F 0 "U3" H 4400 3150 60 0000 C CNN +F 1 "d_xor" H 4450 3250 47 0000 C CNN +F 2 "" H 4400 3150 60 0000 C CNN +F 3 "" H 4400 3150 60 0000 C CNN + 1 4400 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5C7FDDD8 +P 3400 3750 +F 0 "U2" H 3400 3650 60 0000 C CNN +F 1 "d_inverter" H 3400 3900 60 0000 C CNN +F 2 "" H 3450 3700 60 0000 C CNN +F 3 "" H 3450 3700 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FDE57 +P 4450 3750 +F 0 "U4" H 4450 3750 60 0000 C CNN +F 1 "d_and" H 4500 3850 60 0000 C CNN +F 2 "" H 4450 3750 60 0000 C CNN +F 3 "" H 4450 3750 60 0000 C CNN + 1 4450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 3150 3950 3650 +Wire Wire Line + 3950 3650 4000 3650 +Wire Wire Line + 3700 3750 4000 3750 +Wire Wire Line + 3100 3750 3100 3050 +Wire Wire Line + 2950 3050 3950 3050 +$Comp +L PORT U1 +U 1 1 5C7FDF5A +P 2700 3050 +F 0 "U1" H 2750 3150 30 0000 C CNN +F 1 "PORT" H 2700 3050 30 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FDF97 +P 3500 3350 +F 0 "U1" H 3550 3450 30 0000 C CNN +F 1 "PORT" H 3500 3350 30 0000 C CNN +F 2 "" H 3500 3350 60 0000 C CNN +F 3 "" H 3500 3350 60 0000 C CNN + 2 3500 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FE00A +P 5300 3100 +F 0 "U1" H 5350 3200 30 0000 C CNN +F 1 "PORT" H 5300 3100 30 0000 C CNN +F 2 "" H 5300 3100 60 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 3 5300 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7FE064 +P 5350 3700 +F 0 "U1" H 5400 3800 30 0000 C CNN +F 1 "PORT" H 5350 3700 30 0000 C CNN +F 2 "" H 5350 3700 60 0000 C CNN +F 3 "" H 5350 3700 60 0000 C CNN + 4 5350 3700 + -1 0 0 1 +$EndComp +Connection ~ 3100 3050 +Wire Wire Line + 3750 3350 3950 3350 +Connection ~ 3950 3350 +Wire Wire Line + 4850 3100 5050 3100 +Wire Wire Line + 4900 3700 5100 3700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/full_sub/half_sub.sub b/library/SubcircuitLibrary/full_sub/half_sub.sub new file mode 100644 index 00000000..a61a3409 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.sub @@ -0,0 +1,18 @@ +* Subcircuit half_sub +.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml b/library/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml new file mode 100644 index 00000000..115ba703 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_adder/analysis b/library/SubcircuitLibrary/half_adder/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_adder/half_adder-cache.lib b/library/SubcircuitLibrary/half_adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/half_adder/half_adder.cir b/library/SubcircuitLibrary/half_adder/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/library/SubcircuitLibrary/half_adder/half_adder.cir.out b/library/SubcircuitLibrary/half_adder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/half_adder/half_adder.pro b/library/SubcircuitLibrary/half_adder/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/library/SubcircuitLibrary/half_adder/half_adder.sch b/library/SubcircuitLibrary/half_adder/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/half_adder/half_adder.sub b/library/SubcircuitLibrary/half_adder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml b/library/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_sub/analysis b/library/SubcircuitLibrary/half_sub/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_sub/half_sub-cache.lib b/library/SubcircuitLibrary/half_sub/half_sub-cache.lib new file mode 100644 index 00000000..bd15e664 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/half_sub/half_sub.cir b/library/SubcircuitLibrary/half_sub/half_sub.cir new file mode 100644 index 00000000..f20f0368 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub.cir @@ -0,0 +1,14 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/half_sub/half_sub.cir.out b/library/SubcircuitLibrary/half_sub/half_sub.cir.out new file mode 100644 index 00000000..91816956 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub.cir.out @@ -0,0 +1,24 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/half_sub/half_sub.pro b/library/SubcircuitLibrary/half_sub/half_sub.pro new file mode 100644 index 00000000..90e3ded9 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub.pro @@ -0,0 +1,74 @@ +update=Wed 06 Mar 2019 11:10:38 PM IST +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/library/SubcircuitLibrary/half_sub/half_sub.sch b/library/SubcircuitLibrary/half_sub/half_sub.sch new file mode 100644 index 00000000..e70b1675 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U3 +U 1 1 5C7FDDA3 +P 4400 3150 +F 0 "U3" H 4400 3150 60 0000 C CNN +F 1 "d_xor" H 4450 3250 47 0000 C CNN +F 2 "" H 4400 3150 60 0000 C CNN +F 3 "" H 4400 3150 60 0000 C CNN + 1 4400 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5C7FDDD8 +P 3400 3750 +F 0 "U2" H 3400 3650 60 0000 C CNN +F 1 "d_inverter" H 3400 3900 60 0000 C CNN +F 2 "" H 3450 3700 60 0000 C CNN +F 3 "" H 3450 3700 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FDE57 +P 4450 3750 +F 0 "U4" H 4450 3750 60 0000 C CNN +F 1 "d_and" H 4500 3850 60 0000 C CNN +F 2 "" H 4450 3750 60 0000 C CNN +F 3 "" H 4450 3750 60 0000 C CNN + 1 4450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 3150 3950 3650 +Wire Wire Line + 3950 3650 4000 3650 +Wire Wire Line + 3700 3750 4000 3750 +Wire Wire Line + 3100 3750 3100 3050 +Wire Wire Line + 2950 3050 3950 3050 +$Comp +L PORT U1 +U 1 1 5C7FDF5A +P 2700 3050 +F 0 "U1" H 2750 3150 30 0000 C CNN +F 1 "PORT" H 2700 3050 30 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FDF97 +P 3500 3350 +F 0 "U1" H 3550 3450 30 0000 C CNN +F 1 "PORT" H 3500 3350 30 0000 C CNN +F 2 "" H 3500 3350 60 0000 C CNN +F 3 "" H 3500 3350 60 0000 C CNN + 2 3500 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FE00A +P 5300 3100 +F 0 "U1" H 5350 3200 30 0000 C CNN +F 1 "PORT" H 5300 3100 30 0000 C CNN +F 2 "" H 5300 3100 60 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 3 5300 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7FE064 +P 5350 3700 +F 0 "U1" H 5400 3800 30 0000 C CNN +F 1 "PORT" H 5350 3700 30 0000 C CNN +F 2 "" H 5350 3700 60 0000 C CNN +F 3 "" H 5350 3700 60 0000 C CNN + 4 5350 3700 + -1 0 0 1 +$EndComp +Connection ~ 3100 3050 +Wire Wire Line + 3750 3350 3950 3350 +Connection ~ 3950 3350 +Wire Wire Line + 4850 3100 5050 3100 +Wire Wire Line + 4900 3700 5100 3700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/half_sub/half_sub.sub b/library/SubcircuitLibrary/half_sub/half_sub.sub new file mode 100644 index 00000000..a61a3409 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub.sub @@ -0,0 +1,18 @@ +* Subcircuit half_sub +.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml b/library/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml new file mode 100644 index 00000000..115ba703 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm555n/NPN.lib b/library/SubcircuitLibrary/lm555n/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/lm555n/analysis b/library/SubcircuitLibrary/lm555n/analysis new file mode 100644 index 00000000..a0953567 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm555n/lm555n-cache.lib b/library/SubcircuitLibrary/lm555n/lm555n-cache.lib new file mode 100644 index 00000000..824af11e --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n-cache.lib @@ -0,0 +1,205 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND-RESCUE-lm555n +# +DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# R-RESCUE-lm555n +# +DEF R-RESCUE-lm555n R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" 0 150 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_srlatch +# +DEF d_srlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srlatch" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X EN 3 -800 0 200 R 50 50 1 1 I +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# limit +# +DEF limit U 0 40 Y Y 1 F N +F0 "U" 50 -50 60 H V C CNN +F1 "limit" 50 50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +C 300 0 0 0 1 0 N +P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N +X IN 1 -400 0 200 R 50 50 1 1 I +X OUT 2 600 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/lm555n/lm555n-rescue.lib b/library/SubcircuitLibrary/lm555n/lm555n-rescue.lib new file mode 100644 index 00000000..fffeca36 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n-rescue.lib @@ -0,0 +1,18 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# d_inverter-RESCUE-lm555n +# +DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/lm555n/lm555n.cir b/library/SubcircuitLibrary/lm555n/lm555n.cir new file mode 100644 index 00000000..682d4945 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n.cir @@ -0,0 +1,31 @@ +* /home/ash98/Downloads/lm555n/lm555n.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 24 15:58:04 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +E2 Net-_E2-Pad1_ GND /c /d 10000 +U1 Net-_Q1-Pad3_ /d Net-_U1-Pad3_ Net-_U1-Pad4_ /a /b Net-_Q1-Pad1_ Net-_R1-Pad1_ PORT +R8 Net-_R8-Pad1_ Net-_Q1-Pad2_ 1500 +R7 Net-_E2-Pad1_ Net-_R7-Pad2_ 25 +R6 Net-_E1-Pad1_ Net-_R6-Pad2_ 25 +E1 Net-_E1-Pad1_ GND /b /a 10000 +R4 /b /a 2E6 +R5 /c /d 2E6 +R3 /c Net-_Q1-Pad3_ 5000 +R2 /a /c 5000 +R1 Net-_R1-Pad1_ /a 5000 +U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U7-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad6_ Net-_U10-Pad1_ d_srlatch +U7 Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ adc_bridge_1 +U4 Net-_U3-Pad2_ Net-_U4-Pad2_ adc_bridge_1 +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ adc_bridge_1 +U3 Net-_R7-Pad2_ Net-_U3-Pad2_ limit +U2 Net-_R6-Pad2_ Net-_U2-Pad2_ limit +U9 Net-_U8-Pad6_ Net-_U1-Pad3_ dac_bridge_1 +U10 Net-_U10-Pad1_ Net-_R8-Pad1_ dac_bridge_1 +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN + +.end diff --git a/library/SubcircuitLibrary/lm555n/lm555n.cir.out b/library/SubcircuitLibrary/lm555n/lm555n.cir.out new file mode 100644 index 00000000..a81070a1 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n.cir.out @@ -0,0 +1,42 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +.include npn_1.lib +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 npn_1 +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/lm555n/lm555n.pro b/library/SubcircuitLibrary/lm555n/lm555n.pro new file mode 100644 index 00000000..0a5408b6 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n.pro @@ -0,0 +1,57 @@ +update=Tue Apr 2 17:35:59 2019 +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +[eeschema/libraries] +LibName1=lm555n-rescue +LibName2=power +LibName3=device +LibName4=transistors +LibName5=conn +LibName6=linear +LibName7=regul +LibName8=74xx +LibName9=cmos4000 +LibName10=adc-dac +LibName11=memory +LibName12=xilinx +LibName13=special +LibName14=microcontrollers +LibName15=dsp +LibName16=microchip +LibName17=analog_switches +LibName18=motorola +LibName19=texas +LibName20=intel +LibName21=audio +LibName22=interface +LibName23=digital-audio +LibName24=philips +LibName25=display +LibName26=cypress +LibName27=siliconi +LibName28=opto +LibName29=atmel +LibName30=contrib +LibName31=valves +LibName32=analogSpice +LibName33=analogXSpice +LibName34=converterSpice +LibName35=digitalSpice +LibName36=linearSpice +LibName37=measurementSpice +LibName38=portSpice +LibName39=sourcesSpice +LibName40=digitalXSpice +LibName41=eSim_User +LibName42=eSim_Subckt +LibName43=eSim_Sources +LibName44=eSim_PSpice +LibName45=eSim_Power +LibName46=eSim_Plot +LibName47=eSim_Miscellaneous +LibName48=eSim_Hybrid +LibName49=eSim_Digital +LibName50=eSim_Devices +LibName51=eSim_Analog diff --git a/library/SubcircuitLibrary/lm555n/lm555n.sch b/library/SubcircuitLibrary/lm555n/lm555n.sch new file mode 100644 index 00000000..28110b13 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n.sch @@ -0,0 +1,518 @@ +EESchema Schematic File Version 2 +LIBS:lm555n-rescue +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3700 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 2650 3000 2850 3000 +Wire Wire Line + 2650 4750 2650 4650 +Connection ~ 2350 3550 +Connection ~ 2350 4900 +Wire Wire Line + 2350 4100 2350 4200 +Wire Wire Line + 9100 4900 9100 4800 +Wire Wire Line + 8500 4600 8500 4250 +Wire Wire Line + 3350 3250 3050 3250 +Wire Wire Line + 3050 3250 3050 3750 +Wire Wire Line + 3500 4350 3500 4500 +Wire Wire Line + 3650 3550 4200 3550 +Wire Wire Line + 3850 3250 4200 3250 +Wire Wire Line + 3150 3550 3150 3700 +Wire Wire Line + 3150 3700 3500 3700 +Wire Wire Line + 3500 3700 3500 3750 +Connection ~ 3500 4450 +Wire Wire Line + 3700 4450 3700 4400 +Wire Wire Line + 3050 4350 3050 4450 +Wire Wire Line + 3050 4450 3700 4450 +Wire Wire Line + 9100 4250 9000 4250 +Wire Wire Line + 9100 4400 9100 4350 +Wire Wire Line + 9100 4350 9200 4350 +Wire Wire Line + 10100 2950 10350 2950 +Wire Wire Line + 2350 4900 2350 4700 +Wire Wire Line + 2350 3500 2350 3600 +Wire Wire Line + 2250 3000 2350 3000 +Wire Wire Line + 2350 4150 2650 4150 +Connection ~ 2350 4150 +Wire Wire Line + 2250 3550 2650 3550 +Wire Wire Line + 2650 3550 2650 3500 +Wire Wire Line + 4300 4750 4300 4650 +Text Label 2800 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 3000 4050 +F 0 "E2" H 2800 4150 50 0000 C CNN +F 1 "10000" H 2800 4000 50 0000 C CNN +F 2 "" H 3000 4050 60 0001 C CNN +F 3 "" H 3000 4050 60 0001 C CNN + 1 3000 4050 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 3700 4400 +F 0 "#FLG01" H 3700 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 3700 4630 30 0000 C CNN +F 2 "" H 3700 4400 60 0001 C CNN +F 3 "" H 3700 4400 60 0001 C CNN + 1 3700 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 2000 3550 +F 0 "U1" H 2000 3500 30 0000 C CNN +F 1 "PORT" H 2000 3550 30 0000 C CNN +F 2 "" H 2000 3550 60 0001 C CNN +F 3 "" H 2000 3550 60 0001 C CNN + 5 2000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 2000 4900 +F 0 "U1" H 2000 4850 30 0000 C CNN +F 1 "PORT" H 2000 4900 30 0000 C CNN +F 2 "" H 2000 4900 60 0001 C CNN +F 3 "" H 2000 4900 60 0001 C CNN + 1 2000 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 2650 5000 +F 0 "U1" H 2650 4950 30 0000 C CNN +F 1 "PORT" H 2650 5000 30 0000 C CNN +F 2 "" H 2650 5000 60 0001 C CNN +F 3 "" H 2650 5000 60 0001 C CNN + 2 2650 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 4300 5000 +F 0 "U1" H 4300 4950 30 0000 C CNN +F 1 "PORT" H 4300 5000 30 0000 C CNN +F 2 "" H 4300 5000 60 0001 C CNN +F 3 "" H 4300 5000 60 0001 C CNN + 4 4300 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 9450 4350 +F 0 "U1" H 9450 4300 30 0000 C CNN +F 1 "PORT" H 9450 4350 30 0000 C CNN +F 2 "" H 9450 4350 60 0001 C CNN +F 3 "" H 9450 4350 60 0001 C CNN + 7 9450 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 10600 2950 +F 0 "U1" H 10600 2900 30 0000 C CNN +F 1 "PORT" H 10600 2950 30 0000 C CNN +F 2 "" H 10600 2950 60 0001 C CNN +F 3 "" H 10600 2950 60 0001 C CNN + 3 10600 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 3100 3000 +F 0 "U1" H 3100 2950 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0001 C CNN +F 3 "" H 3100 3000 60 0001 C CNN + 6 3100 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 2000 3000 +F 0 "U1" H 2000 2950 30 0000 C CNN +F 1 "PORT" H 2000 3000 30 0000 C CNN +F 2 "" H 2000 3000 60 0001 C CNN +F 3 "" H 2000 3000 60 0001 C CNN + 8 2000 3000 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R8 +U 1 1 50AA20DA +P 8750 4250 +F 0 "R8" V 8830 4250 50 0000 C CNN +F 1 "1500" V 8750 4250 50 0000 C CNN +F 2 "" H 8750 4250 60 0001 C CNN +F 3 "" H 8750 4250 60 0001 C CNN + 1 8750 4250 + 0 1 1 0 +$EndComp +$Comp +L GND-RESCUE-lm555n #PWR02 +U 1 1 50AA140C +P 3500 4500 +F 0 "#PWR02" H 3500 4500 30 0001 C CNN +F 1 "GND" H 3500 4430 30 0001 C CNN +F 2 "" H 3500 4500 60 0001 C CNN +F 3 "" H 3500 4500 60 0001 C CNN + 1 3500 4500 + 1 0 0 -1 +$EndComp +Text Label 2800 4000 0 60 ~ 0 +c +Text Label 2650 4650 0 60 ~ 0 +d +Text Label 2650 4150 0 60 ~ 0 +c +$Comp +L R-RESCUE-lm555n R7 +U 1 1 50AA12F7 +P 3600 3250 +F 0 "R7" V 3680 3250 50 0000 C CNN +F 1 "25" V 3600 3250 50 0000 C CNN +F 2 "" H 3600 3250 60 0001 C CNN +F 3 "" H 3600 3250 60 0001 C CNN + 1 3600 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R6 +U 1 1 50AA12B0 +P 3400 3550 +F 0 "R6" V 3480 3550 50 0000 C CNN +F 1 "25" V 3400 3550 50 0000 C CNN +F 2 "" H 3400 3550 60 0001 C CNN +F 3 "" H 3400 3550 60 0001 C CNN + 1 3400 3550 + 0 -1 -1 0 +$EndComp +Text Label 3250 4000 0 60 ~ 0 +b +Text Label 3250 4100 0 60 ~ 0 +a +Text Label 2650 3000 0 60 ~ 0 +b +Text Label 2650 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 3450 4050 +F 0 "E1" H 3250 4150 50 0000 C CNN +F 1 "10000" H 3250 4000 50 0000 C CNN +F 2 "" H 3450 4050 60 0001 C CNN +F 3 "" H 3450 4050 60 0001 C CNN + 1 3450 4050 + 0 1 1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R4 +U 1 1 50A9E00B +P 2650 3250 +F 0 "R4" V 2730 3250 50 0000 C CNN +F 1 "2E6" V 2650 3250 50 0000 C CNN +F 2 "" H 2650 3250 60 0001 C CNN +F 3 "" H 2650 3250 60 0001 C CNN + 1 2650 3250 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R5 +U 1 1 50A9E001 +P 2650 4400 +F 0 "R5" V 2730 4400 50 0000 C CNN +F 1 "2E6" V 2650 4400 50 0000 C CNN +F 2 "" H 2650 4400 60 0001 C CNN +F 3 "" H 2650 4400 60 0001 C CNN + 1 2650 4400 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R3 +U 1 1 50A9DF09 +P 2350 4450 +F 0 "R3" V 2430 4450 50 0000 C CNN +F 1 "5000" V 2350 4450 50 0000 C CNN +F 2 "" H 2350 4450 60 0001 C CNN +F 3 "" H 2350 4450 60 0001 C CNN + 1 2350 4450 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R2 +U 1 1 50A9DF03 +P 2350 3850 +F 0 "R2" V 2430 3850 50 0000 C CNN +F 1 "5000" V 2350 3850 50 0000 C CNN +F 2 "" H 2350 3850 60 0001 C CNN +F 3 "" H 2350 3850 60 0001 C CNN + 1 2350 3850 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R1 +U 1 1 50A9DEFE +P 2350 3250 +F 0 "R1" V 2430 3250 50 0000 C CNN +F 1 "5000" V 2350 3250 50 0000 C CNN +F 2 "" H 2350 3250 60 0001 C CNN +F 3 "" H 2350 3250 60 0001 C CNN + 1 2350 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_srlatch U8 +U 1 1 5E01E563 +P 8000 3350 +F 0 "U8" H 8000 3350 60 0000 C CNN +F 1 "d_srlatch" H 8050 3500 60 0000 C CNN +F 2 "" H 8000 3350 60 0000 C CNN +F 3 "" H 8000 3350 60 0000 C CNN + 1 8000 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5E01F10F +P 7450 4400 +F 0 "U7" H 7450 4300 60 0000 C CNN +F 1 "d_inverter" H 7450 4550 60 0000 C CNN +F 2 "" H 7500 4350 60 0000 C CNN +F 3 "" H 7500 4350 60 0000 C CNN + 1 7450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 4400 8150 4400 +Wire Wire Line + 8000 4400 8000 4150 +$Comp +L adc_bridge_1 U5 +U 1 1 5E01F2C7 +P 6350 3400 +F 0 "U5" H 6350 3400 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3550 60 0000 C CNN +F 2 "" H 6350 3400 60 0000 C CNN +F 3 "" H 6350 3400 60 0000 C CNN + 1 6350 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3350 7200 3350 +Wire Wire Line + 4300 4650 5600 4650 +Wire Wire Line + 5600 4650 5600 3350 +Wire Wire Line + 5600 3350 5750 3350 +$Comp +L adc_bridge_1 U4 +U 1 1 5E01F3F2 +P 6350 3000 +F 0 "U4" H 6350 3000 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3150 60 0000 C CNN +F 2 "" H 6350 3000 60 0000 C CNN +F 3 "" H 6350 3000 60 0000 C CNN + 1 6350 3000 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U6 +U 1 1 5E01F469 +P 6350 3850 +F 0 "U6" H 6350 3850 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 4000 60 0000 C CNN +F 2 "" H 6350 3850 60 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3800 7200 3800 +Wire Wire Line + 7200 2950 6900 2950 +$Comp +L limit U3 +U 1 1 5E01F5DC +P 4900 2950 +F 0 "U3" H 4950 2900 60 0000 C CNN +F 1 "limit" H 4950 3000 60 0000 C CNN +F 2 "" H 4900 3000 60 0000 C CNN +F 3 "" H 4900 3000 60 0000 C CNN + 1 4900 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 2950 5750 2950 +Wire Wire Line + 4200 3250 4200 2950 +Wire Wire Line + 4200 2950 4500 2950 +$Comp +L limit U2 +U 1 1 5E01F79D +P 4800 3800 +F 0 "U2" H 4850 3750 60 0000 C CNN +F 1 "limit" H 4850 3850 60 0000 C CNN +F 2 "" H 4800 3850 60 0000 C CNN +F 3 "" H 4800 3850 60 0000 C CNN + 1 4800 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 3800 5750 3800 +Wire Wire Line + 4200 3550 4200 3800 +Wire Wire Line + 4200 3800 4400 3800 +Wire Wire Line + 7050 3350 7050 4400 +Wire Wire Line + 7050 4400 7150 4400 +Connection ~ 7050 3350 +Wire Wire Line + 8000 2600 8150 2600 +Wire Wire Line + 8150 2600 8150 4400 +Connection ~ 8000 4400 +$Comp +L dac_bridge_1 U9 +U 1 1 5E01FCD2 +P 9550 3000 +F 0 "U9" H 9550 3000 60 0000 C CNN +F 1 "dac_bridge_1" H 9550 3150 60 0000 C CNN +F 2 "" H 9550 3000 60 0000 C CNN +F 3 "" H 9550 3000 60 0000 C CNN + 1 9550 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 2950 8950 2950 +$Comp +L dac_bridge_1 U10 +U 1 1 5E01FE8E +P 9600 3850 +F 0 "U10" H 9600 3850 60 0000 C CNN +F 1 "dac_bridge_1" H 9600 4000 60 0000 C CNN +F 2 "" H 9600 3850 60 0000 C CNN +F 3 "" H 9600 3850 60 0000 C CNN + 1 9600 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 3800 8800 3800 +Wire Wire Line + 9100 4000 9100 4250 +Wire Wire Line + 9100 4000 10300 4000 +Wire Wire Line + 10300 4000 10300 3800 +Wire Wire Line + 10300 3800 10150 3800 +$Comp +L eSim_NPN Q1 +U 1 1 5E01E782 +P 9000 4600 +F 0 "Q1" H 8900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 8950 4750 50 0000 R CNN +F 2 "" H 9200 4700 29 0000 C CNN +F 3 "" H 9000 4600 60 0000 C CNN + 1 9000 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 4600 8500 4600 +Wire Wire Line + 2250 4900 9100 4900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/lm555n/lm555n.sub b/library/SubcircuitLibrary/lm555n/lm555n.sub new file mode 100644 index 00000000..b524f5c6 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n.sub @@ -0,0 +1,39 @@ +* Subcircuit lm555n +.subckt lm555n 22 14 7 6 15 16 3 13 +.include npn_1.lib +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +r8 9 2 1500 +q1 3 2 22 npn_1 +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) +*control statements + +.ends lm555n diff --git a/library/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml b/library/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml new file mode 100644 index 00000000..58d33ec5 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">false</field2><field3 name="Oct">true</field3><field4 name="Start Frequency">kjadsfh</field4><field5 name="Stop Frequency">jhdsakj</field5><field6 name="No. of points">897897</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm555n/npn_1.lib b/library/SubcircuitLibrary/lm555n/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm7805/NPN.lib b/library/SubcircuitLibrary/lm7805/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/lm7805/PNP.lib b/library/SubcircuitLibrary/lm7805/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/lm7805/Q_PNP.lib b/library/SubcircuitLibrary/lm7805/Q_PNP.lib new file mode 100644 index 00000000..154ed2d8 --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/Q_PNP.lib @@ -0,0 +1 @@ +.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm7805/analysis b/library/SubcircuitLibrary/lm7805/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm7805/lm7805-cache.lib b/library/SubcircuitLibrary/lm7805/lm7805-cache.lib new file mode 100644 index 00000000..aaf8454e --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805-cache.lib @@ -0,0 +1,136 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/lm7805/lm7805.cir b/library/SubcircuitLibrary/lm7805/lm7805.cir new file mode 100644 index 00000000..081b4920 --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805.cir @@ -0,0 +1,51 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm7805\lm7805.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/26/19 17:24:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k +R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 +R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k +R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k +U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R5 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500 +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN +R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R7 Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k +Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R10 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k +Q7 Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R12 Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k +R9 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k +Q5 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP +R8 Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100 +R11 Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50 +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN +R13 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +R14 Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k +Q14 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN +R17 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k +R16 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 1.385k +R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k +U2 Net-_Q15-Pad2_ Net-_R15-Pad2_ zener +Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN +R18 Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200 +R20 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3 +R19 Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240 +U3 Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/lm7805/lm7805.cir.out b/library/SubcircuitLibrary/lm7805/lm7805.cir.out new file mode 100644 index 00000000..f122fba6 --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805.cir.out @@ -0,0 +1,60 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir + +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 1.385k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +* u3 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/lm7805/lm7805.pro b/library/SubcircuitLibrary/lm7805/lm7805.pro new file mode 100644 index 00000000..d410e2fa --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805.pro @@ -0,0 +1,45 @@ +update=Mon Aug 26 14:34:23 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User + diff --git a/library/SubcircuitLibrary/lm7805/lm7805.sch b/library/SubcircuitLibrary/lm7805/lm7805.sch new file mode 100644 index 00000000..701d163d --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805.sch @@ -0,0 +1,757 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm7805-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 5CE41429 +P 1250 1600 +F 0 "R1" V 1330 1600 50 0000 C CNN +F 1 "100k" V 1250 1600 50 0000 C CNN +F 2 "" V 1180 1600 50 0001 C CNN +F 3 "" H 1250 1600 50 0001 C CNN + 1 1250 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5CE4148B +P 1950 1600 +F 0 "R2" V 2030 1600 50 0000 C CNN +F 1 "500" V 1950 1600 50 0000 C CNN +F 2 "" V 1880 1600 50 0001 C CNN +F 3 "" H 1950 1600 50 0001 C CNN + 1 1950 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5CE414A5 +P 1950 3050 +F 0 "R3" V 2030 3050 50 0000 C CNN +F 1 "3.3k" V 1950 3050 50 0000 C CNN +F 2 "" V 1880 3050 50 0001 C CNN +F 3 "" H 1950 3050 50 0001 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5CE414CA +P 1950 3750 +F 0 "R4" V 2030 3750 50 0000 C CNN +F 1 "2.7k" V 1950 3750 50 0000 C CNN +F 2 "" V 1880 3750 50 0001 C CNN +F 3 "" H 1950 3750 50 0001 C CNN + 1 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 5CE414FA +P 1250 3350 +F 0 "U1" H 1200 3250 60 0000 C CNN +F 1 "zener" H 1250 3450 60 0000 C CNN +F 2 "" H 1300 3350 60 0000 C CNN +F 3 "" H 1300 3350 60 0000 C CNN + 1 1250 3350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 5CE41586 +P 1850 2350 +F 0 "Q1" H 1750 2400 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN +F 2 "" H 2050 2450 29 0000 C CNN +F 3 "" H 1850 2350 60 0000 C CNN + 1 1850 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5CE418C5 +P 1950 4600 +F 0 "R5" V 2030 4600 50 0000 C CNN +F 1 "500" V 1950 4600 50 0000 C CNN +F 2 "" V 1880 4600 50 0001 C CNN +F 3 "" H 1950 4600 50 0001 C CNN + 1 1950 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 1750 1250 3050 +Wire Wire Line + 1250 1450 1250 1300 +Wire Wire Line + 1250 1300 1950 1300 +Wire Wire Line + 1950 1300 1950 1450 +Wire Wire Line + 1950 2150 1950 1750 +Wire Wire Line + 1950 2550 1950 2900 +Wire Wire Line + 1950 3200 1950 3600 +Wire Wire Line + 1950 3900 1950 4450 +Wire Wire Line + 1250 3550 1250 5200 +Wire Wire Line + 1250 5200 3200 5200 +Wire Wire Line + 1950 5200 1950 4750 +Wire Wire Line + 1650 2350 1250 2350 +Connection ~ 1250 2350 +$Comp +L eSim_NPN Q2 +U 1 1 5CE41D6C +P 2650 3350 +F 0 "Q2" H 2550 3400 50 0000 R CNN +F 1 "eSim_NPN" H 2600 3500 50 0000 R CNN +F 2 "" H 2850 3450 29 0000 C CNN +F 3 "" H 2650 3350 60 0000 C CNN + 1 2650 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 5CE41E26 +P 3100 4100 +F 0 "Q4" H 3000 4150 50 0000 R CNN +F 1 "eSim_NPN" H 3050 4250 50 0000 R CNN +F 2 "" H 3300 4200 29 0000 C CNN +F 3 "" H 3100 4100 60 0000 C CNN + 1 3100 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 5CE41EA8 +P 2750 3850 +F 0 "R6" V 2830 3850 50 0000 C CNN +F 1 "1k" V 2750 3850 50 0000 C CNN +F 2 "" V 2680 3850 50 0001 C CNN +F 3 "" H 2750 3850 50 0001 C CNN + 1 2750 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE41EFE +P 2850 4650 +F 0 "Q3" H 2750 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN +F 2 "" H 3050 4750 29 0000 C CNN +F 3 "" H 2850 4650 60 0000 C CNN + 1 2850 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3550 2750 3700 +Wire Wire Line + 2750 4000 2750 4450 +Wire Wire Line + 2900 4100 2750 4100 +Connection ~ 2750 4100 +Wire Wire Line + 3200 4300 3200 4750 +Wire Wire Line + 3050 4650 3450 4650 +Wire Wire Line + 2450 3350 1950 3350 +Connection ~ 1950 3350 +Wire Wire Line + 2750 3600 3600 3600 +Wire Wire Line + 3200 3600 3200 3900 +Connection ~ 2750 3600 +$Comp +L R R7 +U 1 1 5CE42281 +P 3200 4900 +F 0 "R7" V 3280 4900 50 0000 C CNN +F 1 "6k" V 3200 4900 50 0000 C CNN +F 2 "" V 3130 4900 50 0001 C CNN +F 3 "" H 3200 4900 50 0001 C CNN + 1 3200 4900 + 1 0 0 -1 +$EndComp +Connection ~ 3200 4650 +Wire Wire Line + 3200 5050 3200 5250 +Connection ~ 1950 5200 +Wire Wire Line + 2750 4850 2750 5200 +Connection ~ 2750 5200 +$Comp +L eSim_NPN Q6 +U 1 1 5CE424FB +P 3650 4650 +F 0 "Q6" H 3550 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3600 4800 50 0000 R CNN +F 2 "" H 3850 4750 29 0000 C CNN +F 3 "" H 3650 4650 60 0000 C CNN + 1 3650 4650 + 1 0 0 -1 +$EndComp +$Comp +L R R10 +U 1 1 5CE42584 +P 3750 5100 +F 0 "R10" V 3830 5100 50 0000 C CNN +F 1 "1k" V 3750 5100 50 0000 C CNN +F 2 "" V 3680 5100 50 0001 C CNN +F 3 "" H 3750 5100 50 0001 C CNN + 1 3750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4850 3750 4950 +Wire Wire Line + 3200 5250 3750 5250 +Connection ~ 3200 5200 +$Comp +L eSim_NPN Q7 +U 1 1 5CE427DA +P 3700 2750 +F 0 "Q7" H 3600 2800 50 0000 R CNN +F 1 "eSim_NPN" H 3650 2900 50 0000 R CNN +F 2 "" H 3900 2850 29 0000 C CNN +F 3 "" H 3700 2750 60 0000 C CNN + 1 3700 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE428D0 +P 3700 3400 +F 0 "Q8" H 3600 3450 50 0000 R CNN +F 1 "eSim_NPN" H 3650 3550 50 0000 R CNN +F 2 "" H 3900 3500 29 0000 C CNN +F 3 "" H 3700 3400 60 0000 C CNN + 1 3700 3400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE4293A +P 4350 3000 +F 0 "Q12" H 4250 3050 50 0000 R CNN +F 1 "eSim_NPN" H 4300 3150 50 0000 R CNN +F 2 "" H 4550 3100 29 0000 C CNN +F 3 "" H 4350 3000 60 0000 C CNN + 1 4350 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2950 3600 3200 +Wire Wire Line + 4250 3200 4250 3400 +Wire Wire Line + 4250 3400 3900 3400 +Wire Wire Line + 4250 2750 4250 2800 +Wire Wire Line + 3900 2750 4250 2750 +Connection ~ 3200 3600 +$Comp +L R R12 +U 1 1 5CE42C4F +P 4350 3450 +F 0 "R12" V 4430 3450 50 0000 C CNN +F 1 "6k" V 4350 3450 50 0000 C CNN +F 2 "" V 4280 3450 50 0001 C CNN +F 3 "" H 4350 3450 50 0001 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 3300 4250 3300 +Connection ~ 4250 3300 +Wire Wire Line + 3700 3600 4350 3600 +Wire Wire Line + 3700 3600 3700 3650 +Wire Wire Line + 3700 3650 3550 3650 +Wire Wire Line + 3550 3650 3550 3600 +Connection ~ 3550 3600 +$Comp +L R R9 +U 1 1 5CE42EA3 +P 3750 3950 +F 0 "R9" V 3830 3950 50 0000 C CNN +F 1 "20k" V 3750 3950 50 0000 C CNN +F 2 "" V 3680 3950 50 0001 C CNN +F 3 "" H 3750 3950 50 0001 C CNN + 1 3750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4100 3750 4450 +Wire Wire Line + 3750 3800 3750 3600 +Connection ~ 3750 3600 +Wire Wire Line + 2750 3150 2750 2450 +Wire Wire Line + 2750 2450 3600 2450 +Wire Wire Line + 3600 2450 3600 2550 +$Comp +L eSim_PNP Q5 +U 1 1 5CE43397 +P 3450 1700 +F 0 "Q5" H 3350 1750 50 0000 R CNN +F 1 "eSim_PNP" H 3400 1850 50 0000 R CNN +F 2 "" H 3650 1800 29 0000 C CNN +F 3 "" H 3450 1700 60 0000 C CNN + 1 3450 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE4353C +P 4100 1700 +F 0 "Q9" H 4000 1750 50 0000 R CNN +F 1 "eSim_PNP" H 4050 1850 50 0000 R CNN +F 2 "" H 4300 1800 29 0000 C CNN +F 3 "" H 4100 1700 60 0000 C CNN + 1 4100 1700 + 1 0 0 1 +$EndComp +$Comp +L R R8 +U 1 1 5CE435B8 +P 3350 1250 +F 0 "R8" V 3430 1250 50 0000 C CNN +F 1 "100" V 3350 1250 50 0000 C CNN +F 2 "" V 3280 1250 50 0001 C CNN +F 3 "" H 3350 1250 50 0001 C CNN + 1 3350 1250 + 1 0 0 -1 +$EndComp +$Comp +L R R11 +U 1 1 5CE4368E +P 4200 1250 +F 0 "R11" V 4280 1250 50 0000 C CNN +F 1 "50" V 4200 1250 50 0000 C CNN +F 2 "" V 4130 1250 50 0001 C CNN +F 3 "" H 4200 1250 50 0001 C CNN + 1 4200 1250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 5CE43705 +P 4100 2200 +F 0 "Q10" H 4000 2250 50 0000 R CNN +F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN +F 2 "" H 4300 2300 29 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 1400 3350 1500 +Wire Wire Line + 3650 1700 3900 1700 +Wire Wire Line + 4200 1400 4200 1500 +Wire Wire Line + 3350 1100 3350 1050 +Wire Wire Line + 1650 1050 7800 1050 +Wire Wire Line + 4200 1050 4200 1100 +Wire Wire Line + 4200 1900 4200 2000 +Wire Wire Line + 3750 1700 3750 2000 +Wire Wire Line + 3750 2000 3350 2000 +Wire Wire Line + 3350 1900 3350 2450 +Connection ~ 3750 1700 +Connection ~ 3350 2450 +Connection ~ 3350 2000 +Wire Wire Line + 2300 2200 3900 2200 +Wire Wire Line + 2300 2200 2300 4200 +Wire Wire Line + 2300 4200 1950 4200 +Connection ~ 1950 4200 +Wire Wire Line + 2200 2400 4200 2400 +Wire Wire Line + 2200 2400 2200 5200 +Connection ~ 2200 5200 +$Comp +L eSim_NPN Q11 +U 1 1 5CE4439E +P 4300 4400 +F 0 "Q11" H 4200 4450 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4550 50 0000 R CNN +F 2 "" H 4500 4500 29 0000 C CNN +F 3 "" H 4300 4400 60 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE44419 +P 4600 4800 +F 0 "Q13" H 4500 4850 50 0000 R CNN +F 1 "eSim_NPN" H 4550 4950 50 0000 R CNN +F 2 "" H 4800 4900 29 0000 C CNN +F 3 "" H 4600 4800 60 0000 C CNN + 1 4600 4800 + 1 0 0 -1 +$EndComp +$Comp +L R R13 +U 1 1 5CE444B9 +P 4400 5050 +F 0 "R13" V 4480 5050 50 0000 C CNN +F 1 "6k" V 4400 5050 50 0000 C CNN +F 2 "" V 4330 5050 50 0001 C CNN +F 3 "" H 4400 5050 50 0001 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE4451D +P 4050 4150 +F 0 "C1" H 4075 4250 50 0000 L CNN +F 1 "30p" H 4075 4050 50 0000 L CNN +F 2 "" H 4088 4000 30 0000 C CNN +F 3 "" H 4050 4150 60 0000 C CNN + 1 4050 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4100 4400 3750 4400 +Connection ~ 3750 4400 +Wire Wire Line + 3900 4150 3750 4150 +Connection ~ 3750 4150 +Wire Wire Line + 4700 4150 4200 4150 +Wire Wire Line + 4400 4150 4400 4200 +Wire Wire Line + 4400 4600 4400 4900 +Connection ~ 4400 4800 +Wire Wire Line + 4400 5200 4400 5300 +Wire Wire Line + 3650 5300 6400 5300 +Wire Wire Line + 3650 5300 3650 5250 +Connection ~ 3650 5250 +Wire Wire Line + 4700 5300 4700 5000 +Connection ~ 4400 5300 +Wire Wire Line + 4700 3800 4700 4600 +Connection ~ 4400 4150 +$Comp +L R R14 +U 1 1 5CE44FFF +P 4700 3650 +F 0 "R14" V 4780 3650 50 0000 C CNN +F 1 "6k" V 4700 3650 50 0000 C CNN +F 2 "" V 4630 3650 50 0001 C CNN +F 3 "" H 4700 3650 50 0001 C CNN + 1 4700 3650 + 1 0 0 -1 +$EndComp +Connection ~ 4700 4150 +$Comp +L eSim_PNP Q14 +U 1 1 5CE45652 +P 5050 3950 +F 0 "Q14" H 4950 4000 50 0000 R CNN +F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN +F 2 "" H 5250 4050 29 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5050 3950 + 1 0 0 1 +$EndComp +Wire Wire Line + 4850 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4700 3500 4700 3450 +Wire Wire Line + 4700 3450 5150 3450 +Wire Wire Line + 5150 3450 5150 3750 +Wire Wire Line + 5150 5300 5150 4150 +Connection ~ 4700 5300 +Wire Wire Line + 4750 3450 4750 1950 +Wire Wire Line + 4200 1950 5300 1950 +Connection ~ 4200 1950 +Connection ~ 4750 3450 +$Comp +L eSim_NPN Q15 +U 1 1 5CE463AD +P 5400 2150 +F 0 "Q15" H 5300 2200 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN +F 2 "" H 5600 2250 29 0000 C CNN +F 3 "" H 5400 2150 60 0000 C CNN + 1 5400 2150 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1950 +Wire Wire Line + 4150 2750 4150 2600 +Wire Wire Line + 4150 2600 6100 2600 +Wire Wire Line + 5300 2600 5300 2350 +Connection ~ 4150 2750 +$Comp +L R R17 +U 1 1 5CE46DDE +P 6050 4250 +F 0 "R17" V 6130 4250 50 0000 C CNN +F 1 "5k" V 6050 4250 50 0000 C CNN +F 2 "" V 5980 4250 50 0001 C CNN +F 3 "" H 6050 4250 50 0001 C CNN + 1 6050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R16 +U 1 1 5CE46F8E +P 6050 3050 +F 0 "R16" V 6130 3050 50 0000 C CNN +F 1 "1.385k" V 6050 3050 50 0000 C CNN +F 2 "" V 5980 3050 50 0001 C CNN +F 3 "" H 6050 3050 50 0001 C CNN + 1 6050 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3200 6050 4100 +Wire Wire Line + 6050 5300 6050 4400 +Connection ~ 5150 5300 +Wire Wire Line + 6050 2600 6050 2900 +Connection ~ 5300 2600 +Wire Wire Line + 4550 3000 5100 3000 +Wire Wire Line + 5100 3000 5100 3250 +Wire Wire Line + 5100 3250 5350 3250 +Wire Wire Line + 5350 3250 5350 3600 +Wire Wire Line + 5350 3600 6050 3600 +Connection ~ 6050 3600 +Wire Wire Line + 1650 1050 1650 1300 +Connection ~ 1650 1300 +Connection ~ 3350 1050 +$Comp +L R R15 +U 1 1 5CE47F7A +P 5850 1300 +F 0 "R15" V 5930 1300 50 0000 C CNN +F 1 "10k" V 5850 1300 50 0000 C CNN +F 2 "" V 5780 1300 50 0001 C CNN +F 3 "" H 5850 1300 50 0001 C CNN + 1 5850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1050 5850 1150 +Connection ~ 4200 1050 +$Comp +L zener U2 +U 1 1 5CE48686 +P 5850 1900 +F 0 "U2" H 5800 1800 60 0000 C CNN +F 1 "zener" H 5850 2000 60 0000 C CNN +F 2 "" H 5900 1900 60 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 1450 5850 1600 +Wire Wire Line + 5850 2100 5850 2250 +Wire Wire Line + 5850 2150 5600 2150 +$Comp +L eSim_NPN Q16 +U 1 1 5CE4907A +P 6550 1600 +F 0 "Q16" H 6450 1650 50 0000 R CNN +F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN +F 2 "" H 6750 1700 29 0000 C CNN +F 3 "" H 6550 1600 60 0000 C CNN + 1 6550 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE4942E +P 7300 1950 +F 0 "Q17" H 7200 2000 50 0000 R CNN +F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN +F 2 "" H 7500 2050 29 0000 C CNN +F 3 "" H 7300 1950 60 0000 C CNN + 1 7300 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 1800 6650 2300 +Wire Wire Line + 6650 1950 7100 1950 +Wire Wire Line + 7400 1050 7400 1750 +Connection ~ 5850 1050 +Wire Wire Line + 6650 1400 6650 1050 +Connection ~ 6650 1050 +$Comp +L R R18 +U 1 1 5CE498BA +P 6650 2450 +F 0 "R18" V 6730 2450 50 0000 C CNN +F 1 "200" V 6650 2450 50 0000 C CNN +F 2 "" V 6580 2450 50 0001 C CNN +F 3 "" H 6650 2450 50 0001 C CNN + 1 6650 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R20 +U 1 1 5CE4999A +P 7400 2450 +F 0 "R20" V 7480 2450 50 0000 C CNN +F 1 "0.3" V 7400 2450 50 0000 C CNN +F 2 "" V 7330 2450 50 0001 C CNN +F 3 "" H 7400 2450 50 0001 C CNN + 1 7400 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R19 +U 1 1 5CE49AF5 +P 7000 2250 +F 0 "R19" V 7080 2250 50 0000 C CNN +F 1 "240" V 7000 2250 50 0000 C CNN +F 2 "" V 6930 2250 50 0001 C CNN +F 3 "" H 7000 2250 50 0001 C CNN + 1 7000 2250 + 0 1 1 0 +$EndComp +Connection ~ 6650 1950 +Wire Wire Line + 5850 2250 6850 2250 +Connection ~ 5850 2150 +Wire Wire Line + 7400 2150 7400 2300 +Wire Wire Line + 7150 2250 7400 2250 +Connection ~ 7400 2250 +Wire Wire Line + 6100 2600 6100 2650 +Wire Wire Line + 6100 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 2600 +Connection ~ 6050 2600 +Wire Wire Line + 6650 2600 6650 2650 +Connection ~ 6650 2650 +$Comp +L PORT U3 +U 1 1 5CE4AAF6 +P 8050 1050 +F 0 "U3" H 8100 1150 30 0000 C CNN +F 1 "PORT" H 8050 1050 30 0000 C CNN +F 2 "" H 8050 1050 60 0000 C CNN +F 3 "" H 8050 1050 60 0000 C CNN + 1 8050 1050 + -1 0 0 1 +$EndComp +Connection ~ 7400 1050 +$Comp +L PORT U3 +U 3 1 5CE4B13E +P 7700 3000 +F 0 "U3" H 7750 3100 30 0000 C CNN +F 1 "PORT" H 7700 3000 30 0000 C CNN +F 2 "" H 7700 3000 60 0000 C CNN +F 3 "" H 7700 3000 60 0000 C CNN + 3 7700 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 2 1 5CE4B701 +P 6650 5300 +F 0 "U3" H 6700 5400 30 0000 C CNN +F 1 "PORT" H 6650 5300 30 0000 C CNN +F 2 "" H 6650 5300 60 0000 C CNN +F 3 "" H 6650 5300 60 0000 C CNN + 2 6650 5300 + -1 0 0 1 +$EndComp +Connection ~ 6050 5300 +Wire Wire Line + 6350 1600 5950 1600 +Wire Wire Line + 5950 1600 5950 1550 +Wire Wire Line + 5950 1550 5000 1550 +Wire Wire Line + 5000 1550 5000 1950 +Connection ~ 5000 1950 +Wire Wire Line + 7300 2650 7300 3000 +Wire Wire Line + 7300 3000 7450 3000 +Connection ~ 7300 2650 +Connection ~ 2500 5200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/lm7805/lm7805.sub b/library/SubcircuitLibrary/lm7805/lm7805.sub new file mode 100644 index 00000000..7ee1489c --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805.sub @@ -0,0 +1,54 @@ +* Subcircuit lm7805 +.subckt lm7805 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ +* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 1.385k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Control Statements + +.ends lm7805
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml b/library/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml new file mode 100644 index 00000000..7395bd7c --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm_741/NPN.lib b/library/SubcircuitLibrary/lm_741/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/lm_741/PNP.lib b/library/SubcircuitLibrary/lm_741/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/lm_741/analysis b/library/SubcircuitLibrary/lm_741/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm_741/lm_741-cache.lib b/library/SubcircuitLibrary/lm_741/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/lm_741/lm_741.cir b/library/SubcircuitLibrary/lm_741/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/lm_741/lm_741.cir.out b/library/SubcircuitLibrary/lm_741/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/lm_741/lm_741.pro b/library/SubcircuitLibrary/lm_741/lm_741.pro new file mode 100644 index 00000000..cbe83f35 --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741.pro @@ -0,0 +1,45 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/library/SubcircuitLibrary/lm_741/lm_741.sch b/library/SubcircuitLibrary/lm_741/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 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+$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/lm_741/lm_741.sub b/library/SubcircuitLibrary/lm_741/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm_741/npn_1.lib b/library/SubcircuitLibrary/lm_741/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm_741/pnp_1.lib b/library/SubcircuitLibrary/lm_741/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/scr/D.lib b/library/SubcircuitLibrary/scr/D.lib new file mode 100644 index 00000000..ef18bb50 --- /dev/null +++ b/library/SubcircuitLibrary/scr/D.lib @@ -0,0 +1,20 @@ +.MODEL D1N750 D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ Bv=8.1 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=880.5E-18 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/scr/PowerDiode.lib b/library/SubcircuitLibrary/scr/PowerDiode.lib new file mode 100644 index 00000000..a2f61dce --- /dev/null +++ b/library/SubcircuitLibrary/scr/PowerDiode.lib @@ -0,0 +1,20 @@ +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/scr/analysis b/library/SubcircuitLibrary/scr/analysis new file mode 100644 index 00000000..687c71ec --- /dev/null +++ b/library/SubcircuitLibrary/scr/analysis @@ -0,0 +1 @@ +.tran 0e-12 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/scr/scr-cache.lib b/library/SubcircuitLibrary/scr/scr-cache.lib new file mode 100644 index 00000000..0a685b80 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr-cache.lib @@ -0,0 +1,150 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# CCCS +# +DEF CCCS F 0 40 Y Y 1 F N +F0 "F" 0 150 50 H V C CNN +F1 "CCCS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R-RESCUE-scr +# +DEF R-RESCUE-scr R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R-RESCUE-scr" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# aswitch +# +DEF aswitch U 0 40 Y Y 1 F N +F0 "U" 450 300 60 H V C CNN +F1 "aswitch" 450 200 60 H V C CNN +F2 "" 450 100 60 H V C CNN +F3 "" 450 100 60 H V C CNN +DRAW +S 200 250 650 100 0 1 0 N +X ~ 2 0 150 200 R 50 50 1 1 O +X ~ 3 850 150 200 L 50 50 1 1 O +X ~ 1_IN 450 -100 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +# dc-RESCUE-scr +# +DEF dc-RESCUE-scr v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/scr/scr-rescue.lib b/library/SubcircuitLibrary/scr/scr-rescue.lib new file mode 100644 index 00000000..64237b7d --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr-rescue.lib @@ -0,0 +1,39 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# R-RESCUE-scr +# +DEF R-RESCUE-scr R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R-RESCUE-scr" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# dc-RESCUE-scr +# +DEF dc-RESCUE-scr v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/scr/scr.cir b/library/SubcircuitLibrary/scr/scr.cir new file mode 100644 index 00000000..4b279764 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr.cir @@ -0,0 +1,20 @@ +* /opt/eSim/src/SubcircuitLibrary/scr/scr.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:47:20 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 3 7 1 PORT +F2 3 9 2 3 100 +D1 5 2 D +C1 3 9 10u +F1 3 9 4 3 10 +v1 8 4 dc +v2 6 5 dc +U1 9 1 6 aswitch +R1 7 8 50 +R2 3 9 1 + +.end diff --git a/library/SubcircuitLibrary/scr/scr.cir.out b/library/SubcircuitLibrary/scr/scr.cir.out new file mode 100644 index 00000000..d600f25d --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr.cir.out @@ -0,0 +1,29 @@ +* /opt/esim/src/subcircuitlibrary/scr/scr.cir + +.include PowerDiode.lib +* u2 3 7 1 port +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +.tran 0e-12 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/scr/scr.pro b/library/SubcircuitLibrary/scr/scr.pro new file mode 100644 index 00000000..ca0df803 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr.pro @@ -0,0 +1,45 @@ +update=Wed Jul 31 19:51:09 2019 +last_client=kicad +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=scr-rescue +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Sources +LibName8=eSim_Subckt +LibName9=eSim_User +LibName10=power +LibName11=device +LibName12=transistors +LibName13=conn +LibName14=linear +LibName15=regul +LibName16=74xx +LibName17=cmos4000 +LibName18=adc-dac +LibName19=memory +LibName20=xilinx +LibName21=special +LibName22=microcontrollers +LibName23=dsp +LibName24=microchip +LibName25=analog_switches +LibName26=motorola +LibName27=texas +LibName28=intel +LibName29=audio +LibName30=interface +LibName31=digital-audio +LibName32=philips +LibName33=display +LibName34=cypress +LibName35=siliconi +LibName36=opto +LibName37=atmel +LibName38=contrib +LibName39=valves diff --git a/library/SubcircuitLibrary/scr/scr.sch b/library/SubcircuitLibrary/scr/scr.sch new file mode 100644 index 00000000..69244f56 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr.sch @@ -0,0 +1,242 @@ +EESchema Schematic File Version 2 +LIBS:scr-rescue +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:scr-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "21 aug 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3600 3250 3600 3150 +Connection ~ 5550 4950 +Wire Wire Line + 5800 3900 5800 3850 +Wire Wire Line + 5800 3850 6150 3850 +Wire Wire Line + 6150 3850 6150 4950 +Wire Wire Line + 6150 4950 3600 4950 +Connection ~ 4300 4950 +Wire Wire Line + 4300 4950 4300 4050 +Wire Wire Line + 4300 4050 3850 4050 +Wire Wire Line + 4700 5400 4700 5950 +Wire Wire Line + 4250 5950 4250 5500 +Connection ~ 4250 4950 +Wire Wire Line + 4250 4950 4250 5200 +Wire Wire Line + 5550 3600 5550 3450 +Wire Wire Line + 5550 4950 5550 4250 +Wire Wire Line + 3600 4950 3600 4400 +Wire Wire Line + 3600 2300 3600 2850 +Wire Wire Line + 3600 2300 3150 2300 +Wire Wire Line + 3600 4150 3600 4300 +Wire Wire Line + 5550 4150 5550 4000 +Wire Wire Line + 5550 2550 5550 2250 +Wire Wire Line + 4700 4950 4700 5100 +Connection ~ 4700 4950 +Wire Wire Line + 6650 2000 6650 5950 +Connection ~ 4700 5950 +Wire Wire Line + 3850 4650 3850 5950 +Wire Wire Line + 3850 5950 6650 5950 +Connection ~ 4250 5950 +Wire Wire Line + 5800 4500 5800 5950 +Connection ~ 5800 5950 +$Comp +L PORT U2 +U 3 1 53F4C93D +P 6650 2250 +F 0 "U2" H 6650 2200 30 0000 C CNN +F 1 "PORT" H 6650 2250 30 0000 C CNN +F 2 "" H 6650 2250 60 0001 C CNN +F 3 "" H 6650 2250 60 0001 C CNN + 3 6650 2250 + -1 0 0 1 +$EndComp +$Comp +L PORT U2 +U 2 1 53F4C934 +P 2900 2300 +F 0 "U2" H 2900 2250 30 0000 C CNN +F 1 "PORT" H 2900 2300 30 0000 C CNN +F 2 "" H 2900 2300 60 0001 C CNN +F 3 "" H 2900 2300 60 0001 C CNN + 2 2900 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 1 1 53F4C92A +P 6400 4950 +F 0 "U2" H 6400 4900 30 0000 C CNN +F 1 "PORT" H 6400 4950 30 0000 C CNN +F 2 "" H 6400 4950 60 0001 C CNN +F 3 "" H 6400 4950 60 0001 C CNN + 1 6400 4950 + -1 0 0 1 +$EndComp +$Comp +L CCCS F2 +U 1 1 53F4C735 +P 5750 4200 +F 0 "F2" H 5550 4300 50 0000 C CNN +F 1 "100" H 5550 4150 50 0000 C CNN +F 2 "" H 5750 4200 60 0001 C CNN +F 3 "" H 5750 4200 60 0001 C CNN + 1 5750 4200 + 0 1 1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 53F4C6D9 +P 5550 3800 +F 0 "D1" H 5550 3900 40 0000 C CNN +F 1 "D" H 5550 3700 40 0000 C CNN +F 2 "" H 5550 3800 60 0001 C CNN +F 3 "" H 5550 3800 60 0001 C CNN + 1 5550 3800 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 53F4C6C2 +P 4700 5250 +F 0 "C1" H 4750 5350 50 0000 L CNN +F 1 "10u" H 4750 5150 50 0000 L CNN +F 2 "" H 4700 5250 60 0001 C CNN +F 3 "" H 4700 5250 60 0001 C CNN + 1 4700 5250 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F1 +U 1 1 53F4C67F +P 3800 4350 +F 0 "F1" H 3600 4450 50 0000 C CNN +F 1 "10" H 3600 4300 50 0000 C CNN +F 2 "" H 3800 4350 60 0001 C CNN +F 3 "" H 3800 4350 60 0001 C CNN + 1 3800 4350 + 0 1 1 0 +$EndComp +$Comp +L dc-RESCUE-scr v1 +U 1 1 565DBF58 +P 3600 3700 +F 0 "v1" H 3400 3800 60 0000 C CNN +F 1 "dc" H 3400 3650 60 0000 C CNN +F 2 "R1" H 3300 3700 60 0000 C CNN +F 3 "" H 3600 3700 60 0000 C CNN + 1 3600 3700 + 1 0 0 -1 +$EndComp +$Comp +L dc-RESCUE-scr v2 +U 1 1 565DC066 +P 5550 3000 +F 0 "v2" H 5350 3100 60 0000 C CNN +F 1 "dc" H 5350 2950 60 0000 C CNN +F 2 "R1" H 5250 3000 60 0000 C CNN +F 3 "" H 5550 3000 60 0000 C CNN + 1 5550 3000 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U1 +U 1 1 565DC87E +P 6400 2100 +F 0 "U1" H 6850 2400 60 0000 C CNN +F 1 "aswitch" H 6850 2300 60 0000 C CNN +F 2 "" H 6850 2200 60 0000 C CNN +F 3 "" H 6850 2200 60 0000 C CNN + 1 6400 2100 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2000 6650 2000 +$Comp +L R-RESCUE-scr R1 +U 1 1 5666B019 +P 3550 2950 +F 0 "R1" H 3600 3080 50 0000 C CNN +F 1 "50" H 3600 3000 50 0000 C CNN +F 2 "" H 3600 2930 30 0000 C CNN +F 3 "" V 3600 3000 30 0000 C CNN + 1 3550 2950 + 0 1 1 0 +$EndComp +$Comp +L R-RESCUE-scr R2 +U 1 1 5666B17A +P 4200 5300 +F 0 "R2" H 4250 5430 50 0000 C CNN +F 1 "1" H 4250 5350 50 0000 C CNN +F 2 "" H 4250 5280 30 0000 C CNN +F 3 "" V 4250 5350 30 0000 C CNN + 1 4200 5300 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/scr/scr.sub b/library/SubcircuitLibrary/scr/scr.sub new file mode 100644 index 00000000..398c8921 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr.sub @@ -0,0 +1,23 @@ +* Subcircuit scr +.subckt scr 3 7 1 +* /opt/esim/src/subcircuitlibrary/scr/scr.cir +.include PowerDiode.lib +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +* Control Statements + +.ends scr diff --git a/library/SubcircuitLibrary/scr/scr_Previous_Values.xml b/library/SubcircuitLibrary/scr/scr_Previous_Values.xml new file mode 100644 index 00000000..8ff6e8d3 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)" /><field3 name="Enter OFF Resistance (default=1.0e12)" /><field4 name="Enter ON Resistance (default=1.0)" /><field5 name="Enter Control ON value(default=1.0)" /></u1></model><devicemodel><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ps</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ua741/analysis b/library/SubcircuitLibrary/ua741/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/library/SubcircuitLibrary/ua741/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ua741/ua741.cir b/library/SubcircuitLibrary/ua741/ua741.cir new file mode 100644 index 00000000..de797429 --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/library/SubcircuitLibrary/ua741/ua741.cir.out b/library/SubcircuitLibrary/ua741/ua741.cir.out new file mode 100644 index 00000000..72e68514 --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +* u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ua741/ua741.pro b/library/SubcircuitLibrary/ua741/ua741.pro new file mode 100644 index 00000000..5dbb81a5 --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/library/SubcircuitLibrary/ua741/ua741.sch b/library/SubcircuitLibrary/ua741/ua741.sch new file mode 100644 index 00000000..7dfc5e1a --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ua741/ua741.sub b/library/SubcircuitLibrary/ua741/ua741.sub new file mode 100644 index 00000000..ad26c001 --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741.sub @@ -0,0 +1,12 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +* Control Statements + +.ends ua741
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ujt/D.lib b/library/SubcircuitLibrary/ujt/D.lib new file mode 100644 index 00000000..8a7fb4da --- /dev/null +++ b/library/SubcircuitLibrary/ujt/D.lib @@ -0,0 +1,2 @@ +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/ujt/analysis b/library/SubcircuitLibrary/ujt/analysis new file mode 100644 index 00000000..ffc57a6b --- /dev/null +++ b/library/SubcircuitLibrary/ujt/analysis @@ -0,0 +1 @@ +.tran 5e-03 100e-03 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ujt/emitter.lib b/library/SubcircuitLibrary/ujt/emitter.lib new file mode 100644 index 00000000..3e78b1ee --- /dev/null +++ b/library/SubcircuitLibrary/ujt/emitter.lib @@ -0,0 +1,11 @@ +.model emitter D( ++ Vj=1 ++ Cjo=1.700E-12 ++ Rs=4.755E-01 ++ Is=21.3P ++ M=1.959E-01 ++ N=1.8 ++ Bv=1.000E+02 ++ tt=3.030E-09 ++ Ibv=1.000E-04 +) diff --git a/library/SubcircuitLibrary/ujt/plot_data_i.txt b/library/SubcircuitLibrary/ujt/plot_data_i.txt new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/library/SubcircuitLibrary/ujt/plot_data_i.txt diff --git a/library/SubcircuitLibrary/ujt/plot_data_v.txt b/library/SubcircuitLibrary/ujt/plot_data_v.txt new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/library/SubcircuitLibrary/ujt/plot_data_v.txt diff --git a/library/SubcircuitLibrary/ujt/ujt-cache.lib b/library/SubcircuitLibrary/ujt/ujt-cache.lib new file mode 100644 index 00000000..ff75f664 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt-cache.lib @@ -0,0 +1,137 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# CCVS +# +DEF CCVS H 0 40 Y Y 1 F N +F0 "H" 0 150 50 H V C CNN +F1 "CCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# NLDS +# +DEF NLDS BB 0 40 Y Y 1 F N +F0 "BB" 0 0 60 H V C CNN +F1 "NLDS" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 0 141 0 1 0 N +X 1 1 0 350 200 D 50 50 1 1 B +X 2 2 0 -350 200 U 50 50 1 1 B +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ujt/ujt.cir b/library/SubcircuitLibrary/ujt/ujt.cir new file mode 100644 index 00000000..e0e911d7 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt.cir @@ -0,0 +1,18 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/ujt/ujt.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 15 12:43:54 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R3 /0 /6 1000k +H1 /6 /0 /4 /5 1k +C1 /5 /7 35p +R1 /7 /2 38.15k +R2 /3 /5 2.518k +U1 /1 /2 /3 PORT +B1 /5 /7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6) +D1 /1 /4 eSim_Diode + +.end diff --git a/library/SubcircuitLibrary/ujt/ujt.cir.out b/library/SubcircuitLibrary/ujt/ujt.cir.out new file mode 100644 index 00000000..2045c539 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt.cir.out @@ -0,0 +1,22 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir + +.include emitter.lib +r3 /0 /6 1000k +* h1 +c1 /5 /7 35p +r1 /7 /2 38.15k +r2 /3 /5 2.518k +* u1 /1 /2 /3 port +b1 /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) +d1 /1 /4 emitter +Vh1 /4 /5 0 +h1 /6 /0 Vh1 1k +.tran 5e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ujt/ujt.pro b/library/SubcircuitLibrary/ujt/ujt.pro new file mode 100644 index 00000000..24c5e186 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt.pro @@ -0,0 +1,44 @@ +update=Tue Jun 11 16:36:40 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User +LibName3=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName4=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName5=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName6=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName7=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName8=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName9=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName10=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName11=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog diff --git a/library/SubcircuitLibrary/ujt/ujt.sch b/library/SubcircuitLibrary/ujt/ujt.sch new file mode 100644 index 00000000..a82bddf7 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt.sch @@ -0,0 +1,199 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:ujt-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R3 +U 1 1 5CF5F733 +P 6650 3400 +F 0 "R3" H 6700 3530 50 0000 C CNN +F 1 "1000k" H 6700 3450 50 0000 C CNN +F 2 "" H 6700 3380 30 0000 C CNN +F 3 "" V 6700 3450 30 0000 C CNN + 1 6650 3400 + 0 1 -1 0 +$EndComp +$Comp +L CCVS H1 +U 1 1 5CF5F77B +P 6150 3350 +F 0 "H1" H 6150 3500 50 0000 C CNN +F 1 "1k" H 5950 3300 50 0000 C CNN +F 2 "" H 6150 3350 60 0000 C CNN +F 3 "" H 6150 3350 60 0000 C CNN + 1 6150 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CF61B3A +P 5150 4700 +F 0 "C1" H 5175 4800 50 0000 L CNN +F 1 "35p" H 5175 4600 50 0000 L CNN +F 2 "" H 5188 4550 30 0000 C CNN +F 3 "" H 5150 4700 60 0000 C CNN + 1 5150 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CF6211F +P 4300 4850 +F 0 "R1" H 4350 4980 50 0000 C CNN +F 1 "38.15k" H 4350 4900 50 0000 C CNN +F 2 "" H 4350 4830 30 0000 C CNN +F 3 "" V 4350 4900 30 0000 C CNN + 1 4300 4850 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CF6218A +P 4550 3650 +F 0 "R2" H 4600 3780 50 0000 C CNN +F 1 "2.518k" H 4600 3700 50 0000 C CNN +F 2 "" H 4600 3630 30 0000 C CNN +F 3 "" V 4600 3700 30 0000 C CNN + 1 4550 3650 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF6830A +P 4250 4150 +F 0 "U1" H 4300 4250 30 0000 C CNN +F 1 "PORT" H 4250 4150 30 0000 C CNN +F 2 "" H 4250 4150 60 0000 C CNN +F 3 "" H 4250 4150 60 0000 C CNN + 2 4250 4150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF689AD +P 5950 2200 +F 0 "U1" H 6000 2300 30 0000 C CNN +F 1 "PORT" H 5950 2200 30 0000 C CNN +F 2 "" H 5950 2200 60 0000 C CNN +F 3 "" H 5950 2200 60 0000 C CNN + 1 5950 2200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF69586 +P 4600 3000 +F 0 "U1" H 4650 3100 30 0000 C CNN +F 1 "PORT" H 4600 3000 30 0000 C CNN +F 2 "" H 4600 3000 60 0000 C CNN +F 3 "" H 4600 3000 60 0000 C CNN + 3 4600 3000 + 0 1 1 0 +$EndComp +Text Label 5600 4100 0 60 ~ 0 +5 +Text Label 5950 3150 0 60 ~ 0 +4 +Text Label 5950 2600 0 60 ~ 0 +1 +Text Label 6450 3050 0 60 ~ 0 +6 +Text Label 6450 3650 0 60 ~ 0 +0 +$Comp +L NLDS B1 +U 1 1 5CFD2C88 +P 5950 4800 +F 0 "B1" H 5950 4800 60 0000 C CNN +F 1 "I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)" H 7050 4900 60 0000 C CNN +F 2 "" H 5950 4800 60 0000 C CNN +F 3 "" H 5950 4800 60 0000 C CNN + 1 5950 4800 + 1 0 0 -1 +$EndComp +Text Label 5350 5250 0 60 ~ 0 +7 +Text Label 4600 3450 0 60 ~ 0 +3 +Text Label 4250 4500 0 60 ~ 0 +2 +$Comp +L eSim_Diode D1 +U 1 1 5CFF8BB7 +P 5950 2850 +F 0 "D1" H 5950 2950 50 0000 C CNN +F 1 "eSim_Diode" H 5950 2750 50 0000 C CNN +F 2 "" H 5950 2850 60 0000 C CNN +F 3 "" H 5950 2850 60 0000 C CNN + 1 5950 2850 + 0 1 1 0 +$EndComp +Wire Wire Line + 6200 3050 6700 3050 +Wire Wire Line + 6700 3050 6700 3200 +Wire Wire Line + 6200 3650 6300 3650 +Wire Wire Line + 6300 3650 6700 3650 +Wire Wire Line + 5950 2450 5950 2700 +Wire Wire Line + 5950 3000 5950 3300 +Wire Wire Line + 5950 3400 5950 3850 +Wire Wire Line + 5950 3850 5950 4100 +Wire Wire Line + 5950 4100 5950 4450 +Wire Wire Line + 5150 4100 5150 4550 +Wire Wire Line + 4600 4100 5150 4100 +Wire Wire Line + 5150 4100 5950 4100 +Connection ~ 5950 4100 +Wire Wire Line + 5150 4850 5150 5250 +Wire Wire Line + 4250 5250 5150 5250 +Wire Wire Line + 5150 5250 5950 5250 +Wire Wire Line + 4250 5250 4250 4950 +Wire Wire Line + 4600 4100 4600 3850 +Connection ~ 5150 4100 +Wire Wire Line + 4250 4650 4250 4400 +Wire Wire Line + 4600 3550 4600 3250 +Wire Wire Line + 5950 5250 5950 5150 +Connection ~ 5150 5250 +Wire Wire Line + 6700 3650 6700 3500 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ujt/ujt.sub b/library/SubcircuitLibrary/ujt/ujt.sub new file mode 100644 index 00000000..2fb1db35 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt.sub @@ -0,0 +1,16 @@ +* Subcircuit ujt +.subckt ujt /1 /2 /3 +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir +.include emitter.lib +r3 /0 /6 1000k +* h1 +c1 /5 /7 35p +r1 /7 /2 38.15k +r2 /3 /5 2.518k +b1 /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) +d1 /1 /4 emitter +Vh1 /4 /5 0 +h1 /6 /0 Vh1 1k +* Control Statements + +.ends ujt
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ujt/ujt_Previous_Values.xml b/library/SubcircuitLibrary/ujt/ujt_Previous_Values.xml new file mode 100644 index 00000000..4468b395 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">0</v1><ve1 name="Source type">0</ve1><i1 name="Source type">dc<field1 name="Value">0.000001m</field1></i1><v2 name="Source type">0</v2></source><model /><devicemodel><d1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Diode/emitter.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/browser/User-Manual/eSim.html b/library/browser/User-Manual/eSim.html new file mode 100644 index 00000000..79afa31e --- /dev/null +++ b/library/browser/User-Manual/eSim.html @@ -0,0 +1,3672 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" + "http://www.w3.org/TR/html4/loose.dtd"> +<html > +<head><title>eSim Manual</title> +<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> +<meta name="generator" content="TeX4ht (http://www.cse.ohio-state.edu/~gurari/TeX4ht/)"> +<meta name="originator" content="TeX4ht (http://www.cse.ohio-state.edu/~gurari/TeX4ht/)"> +<!-- html --> +<meta name="src" content="esim.tex"> +<meta name="date" content="2015-09-15 14:59:00"> +<link rel="stylesheet" type="text/css" href="esim.css"> +</head><body +> + +<div class="center" +> +<!--l. 1--><p class="noindent" > +<!--l. 2--><p class="noindent" ><span +class="cmbx-12x-x-207">eSim</span><br /><br /> +<span +class="cmbx-12x-x-144">An open source EDA tool for circuit design,</span> +<span +class="cmbx-12x-x-144">simulation, analysis and PCB design</span><br /> + +<img +src="figures/logo-trimmed.png" alt="PIC" +> +<span +class="cmbx-12x-x-144">eSim User Manual</span><br /> +<span +class="cmr-10">version 1.0.0</span><br /> +<span +class="cmbx-10">Prepared By:</span><br /> +<span +class="cmr-10">eSim Team</span><br /> +<span +class="cmr-10">FOSSEE at IIT,Bombay</span> + +<!--l. 17--><p class="noindent" ><img +src="figures/iitblogo.png" alt="PIC" +><br /> +<span +class="cmr-10">Indian Institute of Technology Bombay</span><br /> +<img +src="esim0x.png" alt="○BY:" class="oalign" > <img +src="esim1x.png" alt="○$\" class="oalign" > <img +src="esim2x.png" alt="○=" class="oalign" > <br /> +<span +class="cmr-10">August 2015</span></div> + + + <h2 class="likechapterHead"><a + id="x1-1000"></a>Contents</h2> <div class="tableofcontents"> + <span class="chapterToc" >1 <a +href="#x1-20001" id="QQ2-1-2">Introduction</a></span> +<br /> <span class="chapterToc" >2 <a +href="#x1-30002" id="QQ2-1-3">Installing eSim</a></span> +<br /> <span class="chapterToc" >3 <a +href="#x1-40003" id="QQ2-1-4">Architecture of eSim</a></span> +<br />  <span class="sectionToc" >3.1 <a +href="#x1-50003.1" id="QQ2-1-5">Modules used in eSim</a></span> +<br />   <span class="subsectionToc" >3.1.1 <a +href="#x1-60003.1.1" id="QQ2-1-6">Eeschema</a></span> +<br />   <span class="subsectionToc" >3.1.2 <a +href="#x1-70003.1.2" id="QQ2-1-7">CvPcb</a></span> +<br />   <span class="subsectionToc" >3.1.3 <a +href="#x1-80003.1.3" id="QQ2-1-8">Pcbnew</a></span> +<br />   <span class="subsectionToc" >3.1.4 <a +href="#x1-90003.1.4" id="QQ2-1-9">KiCad to Ngspice converter</a></span> +<br />   <span class="subsectionToc" >3.1.5 <a +href="#x1-100003.1.5" id="QQ2-1-10">Model Builder</a></span> +<br />   <span class="subsectionToc" >3.1.6 <a +href="#x1-110003.1.6" id="QQ2-1-11">Subcircuit Builder</a></span> +<br />   <span class="subsectionToc" >3.1.7 <a +href="#x1-120003.1.7" id="QQ2-1-12">Ngspice</a></span> +<br />  <span class="sectionToc" >3.2 <a +href="#x1-130003.2" id="QQ2-1-13">Work flow of eSim</a></span> +<br /> <span class="chapterToc" >4 <a +href="#x1-140004" id="QQ2-1-15">Getting Started</a></span> +<br />  <span class="sectionToc" >4.1 <a +href="#x1-150004.1" id="QQ2-1-16">eSim Main Window</a></span> +<br />   <span class="subsectionToc" >4.1.1 <a +href="#x1-160004.1.1" id="QQ2-1-17">How to launch eSim in Ubuntu?</a></span> +<br />   <span class="subsectionToc" >4.1.2 <a +href="#x1-170004.1.2" id="QQ2-1-19">Main-GUI</a></span> +<br /> <span class="chapterToc" >5 <a +href="#x1-280005" id="QQ2-1-33">Schematic Creation</a></span> +<br />  <span class="sectionToc" >5.1 <a +href="#x1-290005.1" id="QQ2-1-34">Familiarizing the Schematic Editor interface</a></span> +<br />   <span class="subsectionToc" >5.1.1 <a +href="#x1-300005.1.1" id="QQ2-1-36">Top menu bar</a></span> +<br />   <span class="subsectionToc" >5.1.2 <a +href="#x1-310005.1.2" id="QQ2-1-38">Top toolbar</a></span> +<br />   <span class="subsectionToc" >5.1.3 <a +href="#x1-320005.1.3" id="QQ2-1-40">Toolbar on the right</a></span> +<br />   <span class="subsectionToc" >5.1.4 <a +href="#x1-330005.1.4" id="QQ2-1-42">Toolbar on the left</a></span> +<br />   <span class="subsectionToc" >5.1.5 <a +href="#x1-340005.1.5" id="QQ2-1-44">Hotkeys</a></span> +<br />  <span class="sectionToc" >5.2 <a +href="#x1-350005.2" id="QQ2-1-45">Schematic creation for simulation</a></span> +<br />   <span class="subsectionToc" >5.2.1 <a +href="#x1-360005.2.1" id="QQ2-1-47">Selection and placement of components</a></span> +<br />   <span class="subsectionToc" >5.2.2 <a +href="#x1-370005.2.2" id="QQ2-1-51">Wiring the circuit</a></span> +<br />   <span class="subsectionToc" >5.2.3 <a +href="#x1-380005.2.3" id="QQ2-1-53">Assigning values to components</a></span> +<br />   <span class="subsectionToc" >5.2.4 <a +href="#x1-390005.2.4" id="QQ2-1-55">Annotation and ERC</a></span> +<br />   <span class="subsectionToc" >5.2.5 <a +href="#x1-400005.2.5" id="QQ2-1-59">Netlist generation</a></span> +<br /> <span class="chapterToc" >6 <a +href="#x1-410006" id="QQ2-1-61">PCB Design</a></span> +<br />  <span class="sectionToc" >6.1 <a +href="#x1-420006.1" id="QQ2-1-62">Schematic creation for PCB design</a></span> +<br />   <span class="subsectionToc" >6.1.1 <a +href="#x1-430006.1.1" id="QQ2-1-64">Netlist generation for PCB</a></span> + +<br />   <span class="subsectionToc" >6.1.2 <a +href="#x1-440006.1.2" id="QQ2-1-66">Mapping of components using Footprint Editor</a></span> +<br />   <span class="subsectionToc" >6.1.3 <a +href="#x1-450006.1.3" id="QQ2-1-67">Familiarising the Footprint Editor tool</a></span> +<br />   <span class="subsectionToc" >6.1.4 <a +href="#x1-470006.1.4" id="QQ2-1-71">Viewing footprints in 2D and 3D</a></span> +<br />   <span class="subsectionToc" >6.1.5 <a +href="#x1-480006.1.5" id="QQ2-1-75">Mapping of components in the RC circuit</a></span> +<br />  <span class="sectionToc" >6.2 <a +href="#x1-490006.2" id="QQ2-1-77">Creation of PCB layout</a></span> +<br />   <span class="subsectionToc" >6.2.1 <a +href="#x1-500006.2.1" id="QQ2-1-78">Familiarizing the Layout Editor tool</a></span> +<br />   <span class="subsectionToc" >6.2.2 <a +href="#x1-520006.2.2" id="QQ2-1-82">Hotkeys</a></span> +<br />   <span class="subsectionToc" >6.2.3 <a +href="#x1-530006.2.3" id="QQ2-1-83">PCB design example using RC circuit</a></span> +<br /> <span class="chapterToc" >7 <a +href="#x1-540007" id="QQ2-1-98">Model Editor</a></span> +<br />  <span class="sectionToc" >7.1 <a +href="#x1-550007.1" id="QQ2-1-100">Creating New Model Library </a></span> +<br />  <span class="sectionToc" >7.2 <a +href="#x1-560007.2" id="QQ2-1-105">Editing Current Model Library</a></span> +<br />  <span class="sectionToc" >7.3 <a +href="#x1-570007.3" id="QQ2-1-107">Uploading external .lib file to eSim repository</a></span> +<br /> <span class="chapterToc" >8 <a +href="#x1-580008" id="QQ2-1-108">SubCircuit Builder</a></span> +<br />  <span class="sectionToc" >8.1 <a +href="#x1-590008.1" id="QQ2-1-110">Creating a SubCircuit</a></span> +<br />  <span class="sectionToc" >8.2 <a +href="#x1-600008.2" id="QQ2-1-118">Edit a Subcircuit</a></span> +<br /> <span class="chapterToc" >9 <a +href="#x1-610009" id="QQ2-1-119">Solved Examples</a></span> +<br />  <span class="sectionToc" >9.1 <a +href="#x1-620009.1" id="QQ2-1-120">Solved Examples</a></span> +<br />   <span class="subsectionToc" >9.1.1 <a +href="#x1-630009.1.1" id="QQ2-1-121">Basic RC Circuit</a></span> +<br />   <span class="subsectionToc" >9.1.2 <a +href="#x1-660009.1.2" id="QQ2-1-136">Half Wave Rectifier</a></span> +<br />   <span class="subsectionToc" >9.1.3 <a +href="#x1-690009.1.3" id="QQ2-1-143">Precision Rectifier</a></span> +<br />   <span class="subsectionToc" >9.1.4 <a +href="#x1-720009.1.4" id="QQ2-1-150">Inverting Amplifier</a></span> +<br />   <span class="subsectionToc" >9.1.5 <a +href="#x1-750009.1.5" id="QQ2-1-157">Half Adder Example</a></span> +<br /> <span class="chapterToc" > <a +href="#Q1-1-166">References </a></span> + </div> + + + <h2 class="chapterHead"><span class="titlemark">Chapter 1</span><br /><a + id="x1-20001"></a>Introduction</h2> Electronic systems are an integral part of human life. They have +simplified our lives to a great extent. Starting from small systems made of a few +discrete components to the present day integrated circuits (ICs) with millions of +logic gates, electronic systems have undergone a sea change. As a result, design of +electronic systems too have become extremely difficult and time consuming. Thanks to +a host of computer aided design tools, we have been able to come up with quick +and efficient designs. These are called <span +class="cmtt-10x-x-109">Electronic Design Automation </span>or <span +class="cmtt-10x-x-109">EDA</span> +<a + id="dx1-2001"></a>tools. +<!--l. 20--><p class="noindent" >Let us see the steps involved in EDA.<a + id="dx1-2002"></a> In the first stage, the specifications of the system are +laid out. These specifications are then converted to a design. The design could be in +the form of a circuit schematic, logical description using an HDL language, etc. +The design is then simulated and re-designed, if needed, to achieve the desired +results. Once simulation achieves the specifications, the design is either converted to +a PCB, a chip layout, or ported to an FPGA. The final product is again tested +for specifications. The whole cycle is repeated until desired results are obtained +<span class="cite"> [<a +href="#Xeda">9</a>]</span>. +<!--l. 31--><p class="indent" > A person who builds an electronic system has to first design the circuit, produce a virtual +representation of it through a schematic for easy comprehension, simulate it and finally +convert it into a Printed Circuit Board (PCB). <a + id="dx1-2003"></a>There are various tools available that will help +us do this. Some of the popular EDA tools are those of <span +class="cmtt-10x-x-109">Cadence</span>, <span +class="cmtt-10x-x-109">Synopys</span>, <span +class="cmtt-10x-x-109">Mentor Graphics</span> +and <span +class="cmtt-10x-x-109">Xilinx</span>. Although these are fairly comprehensive and high end, their licenses are +expensive, being proprietary. +<!--l. 40--><p class="indent" > There are some free and open source EDA tools like <span +class="cmtt-10x-x-109">gEDA</span>, <span +class="cmtt-10x-x-109">KiCad </span>and <span +class="cmtt-10x-x-109">Ngspice</span>. The main +drawback of these open source tools is that they are not comprehensive. Some of them are +capable of PCB design (e.g. <span +class="cmtt-10x-x-109">KiCad</span>) while some of them are capable of performing simulations +(e.g. <span +class="cmtt-10x-x-109">gEDA</span>). To the best of our knowledge, there is no open source software that can perform +circuit design, simulation and layout design together. eSim is capable of doing all of the +above. +<!--l. 49--><p class="indent" > eSim is a free and open source EDA tool. It is an acronym for <span +class="cmbx-10x-x-109">E</span>lectronics <span +class="cmbx-10x-x-109">Sim</span>ulation. +eSim is created using open source software packages, such as KiCad, Ngspice and Python. <a + id="dx1-2004"></a><a + id="dx1-2005"></a> +<a + id="dx1-2006"></a>Using eSim, one can create circuit schematics, perform simulations and design PCB +layouts. It can create or edit new device models, and create or edit subcircuits for +simulation. +<!--l. 57--><p class="indent" > Because of these reasons, eSim is expected to be useful for students, teachers and other +professionals who would want to study and/or design electronic systems. eSim is also useful +for entrepreneurs and small scale enterprises who do not have the capability to invest in +heavily priced proprietary tools. +<!--l. 63--><p class="indent" > This book introduces eSim to the reader and illustrates all the features of eSim with +examples. Chapter <a +href="#x1-30002">2<!--tex4ht:ref: chap2 --></a> gives step by step instructions to install eSim on a typical computer +system and to validate the installation. The software architecture of eSim is presented in +Chapter <a +href="#x1-40003">3<!--tex4ht:ref: chap3 --></a>. Chapter <a +href="#x1-140004">4<!--tex4ht:ref: chap4 --></a> gets the user started with eSim. It takes them through a tour + +of eSim with the help of a simple RC circuit example. Chapter 5 illustrates how +to simulate circuits. Chapter 6 explains PCB design using eSim, in detail. The +advanced features of eSim such as Model Builder covered in Chapter 7 and Sub +circuiting is covered in Chapter 8. Chapter <a +href="#x1-610009">9<!--tex4ht:ref: chap5 --></a> illustrates how to use eSim for solving +problems. +<!--l. 73--><p class="indent" > The following convention has been adopted throughout this manual.All the +menu names, options under each menu item, tool names, certain points to be noted, +etc., are given in <span +class="cmti-10x-x-109">italics</span>. Some keywords, names of certain windows/dialog boxes, +names of some files/projects/folders, messages displayed during an activity, names +of websites, component references, etc., are given in <span +class="cmtt-10x-x-109">typewriter </span>font. Some key +presses, e.g. <span +class="cmtt-10x-x-109">Enter </span>key, <span +class="cmtt-10x-x-109">F1 </span>key, <span +class="cmtt-10x-x-109">y </span>for yes, etc., are also mentioned in <span +class="cmtt-10x-x-109">typewriter</span> +font. + + <h2 class="chapterHead"><span class="titlemark">Chapter 2</span><br /><a + id="x1-30002"></a>Installing eSim</h2> + <dl class="enumerate"><dt class="enumerate"> + 1. </dt><dd +class="enumerate"><span +class="cmbx-10x-x-109">eSim installation in Ubuntu:</span><br +class="newline" />After downloading the zip file from https://github.com/FOSSEE/eSim to a local + directory unpack it using:<br +class="newline" />      <span +class="cmbx-10x-x-109">$ unzip eSim.zip </span><br +class="newline" />Now change directories in to the top-level source directory (where this INSTALL + file can be found). + <!--l. 13--><p class="noindent" >To install eSim and other dependecies run the following command. <br +class="newline" />      <span +class="cmbx-10x-x-109">$ ../install-linux.sh –install </span><br +class="newline" />Above script will install eSim along with dependencies. + <!--l. 19--><p class="noindent" >eSim will be installed to /opt/eSim + <!--l. 21--><p class="noindent" >To run eSim you can directly run it from terminal as <br +class="newline" />      <span +class="cmbx-10x-x-109">$ esim </span><br +class="newline" />or you can double click on eSim icon created on desktop after installation.</dd></dl> + + <h2 class="chapterHead"><span class="titlemark">Chapter 3</span><br /><a + id="x1-40003"></a>Architecture of eSim</h2> +<!--l. 6--><p class="noindent" >eSim is a CAD <a + id="dx1-4001"></a>tool that helps electronic system designers to design, test and analyse their +circuits. But the important feature of this tool is that it is open source and hence the user can +modify the source as per his/her need. The software provides a generic, modular and +extensible platform for experiment with electronic circuits. This software runs on all +Ubuntu Linux distributions and some flavours of Windows. It uses <span +class="cmtt-10x-x-109">Python</span>, <span +class="cmtt-10x-x-109">KiCad </span>and +<span +class="cmtt-10x-x-109">Ngspice</span>. +<!--l. 13--><p class="indent" > The objective behind the development of eSim is to provide an open source EDA solution +for electronics and electrical engineers. The software should be capable of performing +schematic creation, PCB design and circuit simulation (analog, digital and mixed signal). It +should provide facilities to create new models and components. The architecture of eSim has +been designed by keeping these objectives in mind. + <h3 class="sectionHead"><span class="titlemark">3.1 </span> <a + id="x1-50003.1"></a>Modules used in eSim</h3> +<!--l. 21--><p class="noindent" >Various open-source tools have been used for the underlying build-up of eSim. In this section +we will give a brief idea about all the modules used in eSim. +<!--l. 23--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">3.1.1 </span> <a + id="x1-60003.1.1"></a>Eeschema</h4> +<a + id="dx1-6001"></a> +<a + id="dx1-6002"></a> +<!--l. 24--><p class="noindent" >Eeschema is an integrated software where all functions of circuit drawing, control, layout, +library management and access to the PCB design software are carried out. It is the +schematic editor tool used in KiCad <span class="cite"> [<a +href="#Xeeschema">11</a>]</span>. Eeschema is intended to work with PCB layout +software such as Pcbnew. It provides netlist that describes the electrical connections of the +PCB. Eeschema also integrates a component editor which allows the creation, editing and +visualization of components. It also allows the user to effectively handle the symbol +libraries i.e; import, export, addition and deletion of library components. Eeschema +also integrates the following additional but essential functions needed for a modern +schematic capture software: <a + id="x1-6003r1"></a>1. Design rules check <a + id="dx1-6004"></a>(<span +class="cmtt-10x-x-109">DRC</span>) for the automatic control of +incorrect connections and inputs of components left unconnected. <a + id="x1-6005r2"></a>2. Generation of +layout files in <span +class="cmtt-10x-x-109">POSTSCRIPT</span> <a + id="dx1-6006"></a>or <span +class="cmtt-10x-x-109">HPGL</span> <a + id="dx1-6007"></a>format. <a + id="x1-6008r3"></a>3. Generation of layout files printable via +printer. <a + id="x1-6009r4"></a>4. Bill of material generation. <a + id="x1-6010r5"></a>5. Netlist generation for PCB layout or for +simulation. +This module is indicated by the label 1 in Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 45--><p class="indent" > As Eeschema is originally intended for PCB Design, there are no fictitious + +components<span class="footnote-mark"><a +href="esim2.html#fn1x3"><sup class="textsuperscript">1</sup></a></span><a + id="x1-6011f1"></a> +such as voltage or current sources. Thus, we have added a new library for different types of +voltage and current sources such as sine, pulse and square wave. We have also built a library +which gives printing and plotting solutions. This extension, developed by us for eSim, is +indicated by the label 2 in Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. + <h4 class="subsectionHead"><span class="titlemark">3.1.2 </span> <a + id="x1-70003.1.2"></a>CvPcb</h4> +<a + id="dx1-7001"></a> +<!--l. 58--><p class="noindent" >CvPcb is a tool that allows the user to associate components in the schematic to component +footprints when designing the printed circuit board. CvPcb is the footprint editor tool in +KiCad <span class="cite"> [<a +href="#Xeeschema">11</a>]</span>. Typically the netlist file generated by Eeschema does not specify which printed +circuit board footprint is associated with each component in the schematic. However, this is +not always the case as component footprints can be associated during schematic capture by +setting the component’s footprint field. CvPcb provides a convenient method of associating +footprints to components. It provides footprint list filtering, footprint viewing, and 3D +component model viewing to help ensure that the correct footprint is associated with each +component. Components can be assigned to their corresponding footprints manually or +automatically by creating equivalence files. Equivalence files are look up tables +associating each component with its footprint. This interactive approach is simpler +and less error prone than directly associating footprints in the schematic editor. +This is because CvPcb not only allows automatic association, but also allows to +see the list of available footprints and displays them on the screen to ensure the +correct footprint is being associated. This module is indicated by the label 3 in +Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 80--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">3.1.3 </span> <a + id="x1-80003.1.3"></a>Pcbnew</h4> +<a + id="dx1-8001"></a> +<!--l. 81--><p class="noindent" >Pcbnew is a powerful printed circuit board software tool. It is the layout editor tool +used in KiCad <span class="cite"> [<a +href="#Xeeschema">11</a>]</span>. It is used in association with the schematic capture software +Eeschema, which provides the netlist. Netlist describes the electrical connections of +the circuit. CvPcb is used to assign each component, in the netlist produced by +Eeschema, to a module that is used by Pcbnew. The features of Pcbnew are given +below: + + <ul class="itemize1"> + <li class="itemize">It manages libraries of modules. Each module is a drawing of the physical + component including its footprint<a + id="dx1-8002"></a> - the layout of pads providing connections to the + component. The required modules are automatically loaded during the reading of + the netlist produced by CvPcb. + </li> + <li class="itemize">Pcbnew integrates automatically and immediately any circuit modification by + removal of any erroneous tracks, addition of new components, or by modifying + any value (and under certain conditions any reference) of old or new modules, + according to the electrical connections appearing in the schematic. + </li> + <li class="itemize">This tool provides a rats nest display, a hairline connecting the pads of modules + connected on the schematic. These connections move dynamically as track and + module movements are made. + </li> + <li class="itemize">It has an active Design Rules Check (<span +class="cmtt-10x-x-109">DRC</span>) which automatically indicates any error + of track layout in real time. + </li> + <li class="itemize">It automatically generates a copper plane, with or without thermal breaks on the + pads. + </li> + <li class="itemize">It has a simple but effective auto router to assist in the production of the + circuit. An export/import in <span +class="cmtt-10x-x-109">SPECCTRA </span>dsn format allows to use more advanced + auto-routers. + </li> + <li class="itemize">It provides options specifically for the production of ultra high frequency circuits + (such as pads of trapezoidal and complex form, automatic layout of coils on the + printed circuit). + </li> + <li class="itemize">Pcbnew displays the elements (tracks, pads, texts, drawings and more) as actual size + and according to personal preferences such as: + <ul class="itemize2"> + <li class="itemize">display in full or outline. + </li> + <li class="itemize">display the track/pad clearance.</li></ul> + + </li></ul> +<!--l. 121--><p class="noindent" >This module is indicated by the label 4 in Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. + <h4 class="subsectionHead"><span class="titlemark">3.1.4 </span> <a + id="x1-90003.1.4"></a>KiCad to Ngspice converter</h4> +<!--l. 124--><p class="noindent" >We can provide analysis parameters, and the source details through this module. It also +allows us to add and edit the device models and subcircuits, included in the circuit +schematic. Finally, this module facilitates the conversion of KiCad netlist to Ngspice +compatible ones. It is developed by us for eSim and it is indicated by the label 7 in +Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 149--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">3.1.5 </span> <a + id="x1-100003.1.5"></a>Model Builder</h4> +<a + id="dx1-10001"></a> +<!--l. 150--><p class="noindent" >This tool provides the facility to define a new model for devices such as, <a + id="x1-10002r1"></a>1. Diode <a + id="x1-10003r2"></a>2. Bipolar +Junction Transistor (BJT) <a + id="x1-10004r3"></a>3. Metal Oxide Semiconductor Field Effect Transistor +(MOSFET) <a + id="x1-10005r4"></a>4. Junction Field Effect Transistor (JFET) <a + id="x1-10006r5"></a>5. IGBT and <a + id="x1-10007r6"></a>6. Magnetic +core. +This module also helps edit existing models. It is developed by us for eSim and it is indicated +by the label 5 in Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 164--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">3.1.6 </span> <a + id="x1-110003.1.6"></a>Subcircuit Builder</h4> +<a + id="dx1-11001"></a> +<!--l. 164--><p class="noindent" >This module allows the user to create a subcircuit for a component. Once the subcircuit for a +component is created, the user can use it in other circuits. It has the facility to define new +components such as, Op-amps and IC-555. This component also helps edit existing +subcircuits. This module is developed by us for eSim and it is indicated by the label 6 in +Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 172--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">3.1.7 </span> <a + id="x1-120003.1.7"></a>Ngspice</h4> +<a + id="dx1-12001"></a> +<!--l. 173--><p class="noindent" >Ngspice is a general purpose circuit simulation program for nonlinear dc, nonlinear transient, +and linear ac analysis <span class="cite"> [<a +href="#Xngspice-web">12</a>]</span>. Circuits may contain resistors, capacitors, inductors, mutual +inductors, independent voltage and current sources, four types of dependent sources, lossless +and lossy transmission lines (two separate implementations), switches, uniform + +distributed RC lines, and the five most common semiconductor devices: diodes, +<a + id="dx1-12002"></a>BJTs, <a + id="dx1-12003"></a>JFETs, MESFETs, and MOSFET. <a + id="dx1-12004"></a>This module is indicated by the label 9 in +Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 184--><p class="noindent" > + <h3 class="sectionHead"><span class="titlemark">3.2 </span> <a + id="x1-130003.2"></a>Work flow of eSim</h3> +<!--l. 185--><p class="noindent" >Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a> shows the work flow in eSim. The block diagram consists of mainly three +parts: + <ul class="itemize1"> + <li class="itemize">Schematic Editor + </li> + <li class="itemize">PCB Layout Editor + </li> + <li class="itemize">Circuit Simulators</li></ul> +<!--l. 193--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-130011"></a> + + +<!--l. 196--><p class="noindent" ><img +src="figures/blockdiagram.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 3.1: </span><span +class="content">Work flow in eSim. (Boxes with dotted lines denote the modules developed +in this work).</span></div><!--tex4ht:label?: x1-130011 --> + +<!--l. 201--><p class="indent" > </div><hr class="endfigure"> +<!--l. 203--><p class="indent" > Here we explain the role of each block in designing electronic systems. Circuit design is the +first step in the design of an electronic circuit. Generally a circuit diagram is drawn on a +paper, and then entered into a computer using a schematic editor. Eeschema is the schematic +editor for eSim. Thus all the functionalities of Eeschema are naturally available in eSim. +<a + id="dx1-13002"></a> +<!--l. 210--><p class="indent" > Libraries for components, explicitly or implicitly supported by Ngspice, have been created +using the features of Eeschema. As Eeschema is originally intended for PCB design, there are +no fictitious components such as voltage or current sources. Thus, a new library for different +types of voltage and current sources such as sine, pulse and square wave, has been added in +eSim. A library which gives the functionality of printing and plotting has also been +created. +<!--l. 219--><p class="indent" > The schematic editor provides a netlist file, which describes the electrical connections of +the design. In order to create a PCB layout, physical components are required to be mapped +into their footprints. To perform component to footprint mapping, CvPcb is used. Footprints +have been created for the components in the newly created libraries. Pcbnew is used to draw +a PCB layout. +<!--l. 227--><p class="indent" > After designing a circuit, it is essential to check the integrity of the circuit design. In the +case of large electronic circuits, breadboard testing is impractical. In such cases, electronic +system designers rely heavily on simulation. The accuracy of the simulation results can be +increased by accurate modeling of the circuit elements. Model Builder provides the facility to +define a new model for devices and edit existing models. Complex circuit elements can be +created by hierarchical modeling. Subcircuit Builder provides an easy way to create a +subcircuit. +<!--l. 238--><p class="indent" > The netlist generated by Schematic Editor cannot be directly used for simulation due to +compatibility issues. Netlist Converter converts it into Ngspice compatible format. The +type of simulation to be performed and the corresponding options are provided +through a graphical user interface (GUI). This is called KiCad to Ngspice Converter in +eSim. +<!--l. 245--><p class="indent" > eSim uses Ngspice for analog, digital, mixed-level/mixed-signal circuit simulation. Ngspice +is based on three open source software packages<span class="cite"> [<a +href="#Xspice">14</a>]</span>: + <ul class="itemize1"> + <li class="itemize">Spice3f5 (analog circuit simulator) + </li> + <li class="itemize">Cider1b1 (couples Spice3f5 circuit simulator to DSIM device simulator) + </li> + <li class="itemize">Xspice (code modeling support and simulation of digital components through an + event driven algorithm)</li></ul> +<!--l. 253--><p class="noindent" >It is a part of gEDA <a + id="dx1-13003"></a>project. Ngspice is capable of simulating devices with BSIM, <a + id="dx1-13004"></a>EKV, HICUM, <a + id="dx1-13005"></a><a + id="dx1-13006"></a> + +HiSim, <a + id="dx1-13007"></a>PSP, <a + id="dx1-13008"></a>and PTM <a + id="dx1-13009"></a>models. It is widely used due to its accuracy even for the latest +technology devices. + + <h2 class="chapterHead"><span class="titlemark">Chapter 4</span><br /><a + id="x1-140004"></a>Getting Started</h2> +<!--l. 5--><p class="noindent" >In this chapter we will get started with eSim. We will run through the various options +available with an example circuit. Referring to this chapter will make one familiar with +eSim and will help plan the project before actually designing a circuit. Lets get +started. + <h3 class="sectionHead"><span class="titlemark">4.1 </span> <a + id="x1-150004.1"></a>eSim Main Window</h3> +<!--l. 12--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">4.1.1 </span> <a + id="x1-160004.1.1"></a>How to launch eSim in Ubuntu?</h4> +<!--l. 13--><p class="noindent" >After installation is completed, to launch eSim 1. Go to terminal.<br +class="newline" />2. Type <span +class="cmbx-10x-x-109">esim </span>and hit enter.<br +class="newline" />The first window that appears is workspace dialog as shown in Fig. <a +href="#x1-160011">4.1<!--tex4ht:ref: workspace --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-160011"></a> + + +<!--l. 19--><p class="noindent" ><img +src="figures/workspace.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 4.1: </span><span +class="content">eSim-Workspace</span></div><!--tex4ht:label?: x1-160011 --> + +<!--l. 22--><p class="indent" > </div><hr class="endfigure"> +<!--l. 24--><p class="indent" > The default workspace is eSim-Workspace under home directory. To create new workspace +use <span +class="cmti-10x-x-109">browse </span>option. + <h4 class="subsectionHead"><span class="titlemark">4.1.2 </span> <a + id="x1-170004.1.2"></a>Main-GUI</h4> +<!--l. 27--><p class="noindent" >The main GUI window of eSim is as shown in Fig. <a +href="#x1-170012">4.2<!--tex4ht:ref: maingui --></a> <hr class="figure"><div class="figure" +> + +<a + id="x1-170012"></a> + + +<!--l. 30--><p class="noindent" ><img +src="figures/maingui.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 4.2: </span><span +class="content">eSim Main GUI</span></div><!--tex4ht:label?: x1-170012 --> + +<!--l. 33--><p class="indent" > </div><hr class="endfigure"> +<!--l. 34--><p class="indent" > The eSim main window consists of the following symbols. + <dl class="enumerate"><dt class="enumerate"> + 1. </dt><dd +class="enumerate">Toolbar + </dd><dt class="enumerate"> + 2. </dt><dd +class="enumerate">Menubar + </dd><dt class="enumerate"> + 3. </dt><dd +class="enumerate">Project explorer + </dd><dt class="enumerate"> + 4. </dt><dd +class="enumerate">Dockarea + </dd><dt class="enumerate"> + 5. </dt><dd +class="enumerate">Console area</dd></dl> + <h5 class="subsubsectionHead"><a + id="x1-180004.1.2"></a>Toolbar</h5> +<!--l. 44--><p class="noindent" ><hr class="figure"><div class="figure" +> + +<a + id="x1-180013"></a> + + +<!--l. 46--><p class="noindent" ><img +src="figures/guitoolbar.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 4.3: </span><span +class="content">Toolbar</span></div><!--tex4ht:label?: x1-180013 --> + +<!--l. 49--><p class="noindent" ></div><hr class="endfigure"> + <ul class="itemize1"> + <li class="itemize">Open Schematic: The first tool on the toolbar i.e. <span +class="cmti-10x-x-109">Schematic Editor</span><a + id="dx1-18002"></a>. Clicking on + this button will open Eeschema, the KiCad schematic editor. + </li> + <li class="itemize">Convert KiCad to Ngspice: This converter converts KiCad spice netlist into + Ngspice compatible netlist. The KiCad to Ngspice window consists of total five + tabs as namely <span +class="cmti-10x-x-109">Analysis, Device Model, Source Details, Model Library, Subcircuits</span>. + Once the values have been entered, press the <span +class="cmtt-10x-x-109">Convert </span>key. It will generate + <span +class="cmtt-10x-x-109">.cir.out </span>file in the same project directory.<br +class="newline" />Note that <span +class="cmti-10x-x-109">KiCad to Ngspice Converter </span>can only be used if current project has + created the KiCad spice netlist file <span +class="cmtt-10x-x-109">.cir</span>.<br +class="newline" /> + <!--l. 62--><p class="noindent" >The details of tabs under KiCad to Ngspice converter are as follows:<br +class="newline" /> + <h5 class="subsubsectionHead"><a + id="x1-190004.1.2"></a>Analysis</h5> + <!--l. 65--><p class="noindent" >This feature helps the user to perform different types of analysis such as Operating + point analysis, <a + id="dx1-19001"></a>DC analysis, <a + id="dx1-19002"></a>AC analysis, <a + id="dx1-19003"></a>transient analysis. <a + id="dx1-19004"></a>It has the facility + to + <ul class="itemize2"> + <li class="itemize">Insert type of analysis such as AC or DC or Transient + </li> + <li class="itemize">Insert values for analysis</li></ul> + <!--l. 73--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-200004.1.2"></a>Source Details</h5> + <!--l. 74--><p class="noindent" >eSim sources are added from <span +class="cmtt-10x-x-109">eSim</span><span +class="cmtt-10x-x-109">_Sources </span>library. Source such as <span +class="cmti-10x-x-109">SINE, AC, DC,</span> + <span +class="cmti-10x-x-109">PULSE </span>are in this library. The parameter values to all the sources added in the + shcematic can be given through ’Source Details’. + + <!--l. 76--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-210004.1.2"></a>Ngspice Model</h5> + <!--l. 77--><p class="noindent" >Ngspice has in built model such as <span +class="cmti-10x-x-109">flipflop(D,SR,JK,T),gain,summer </span>etc. which can be + utilised while building a circuit. eSim allows to add and modify Ngspice model + parameter through Ngspice Model tab. + <!--l. 80--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-220004.1.2"></a>Device Modeling</h5> + <!--l. 81--><p class="noindent" >Devices like <span +class="cmti-10x-x-109">Diode, JFET, MOSFET, IGBT, MOS </span>etc used in the circuit can be + modeled using device model libraries. eSim also provides editing and adding new model + libraries. While converting KiCad to Ngspice, these library files are added to the + corresponding devices used in the circuit. + <!--l. 83--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-230004.1.2"></a>Subcircuits</h5> + <!--l. 84--><p class="noindent" >Subcircuits are circuits within circuit. Subcircuiting helps to reuse the parts of the + circuits. The subcircuits in the main circuits are added using this facility. Also, eSim + provides us with the facility to edit already existing subcircuits. + </li> + <li class="itemize">Simulation: The netlist generated using the <span +class="cmti-10x-x-109">KiCad to Ngspice </span>converter is + simulated using simulation button. Clicking on the <span +class="cmti-10x-x-109">Simulation </span>button will run + the Ngspice simulation for current project. Python plotting window will open, as + shown in Fig. <a +href="#x1-230014">4.4<!--tex4ht:ref: simulation-op --></a>. It shows the output waveform of current project. In the + Ngspice tab we can view the output plotted by Ngspice. <hr class="figure"><div class="figure" +><a + id="x1-230014"></a> <img +src="figures/simulation-op.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 4.4: </span><span +class="content">Simulation Output in Python Plotting Window</span></div><!--tex4ht:label?: x1-230014 --> + <!--l. 94--><p class="noindent" ></div><hr class="endfigure"> + </li> + <li class="itemize">Foot Print Editor: Clicking on the <span +class="cmti-10x-x-109">Footprint Editor </span>tool will open the <span +class="cmtt-10x-x-109">CvPcb</span> + <a + id="dx1-23002"></a>window. This window will ideally open the .net file for the current project. So, + before using this tool, one should have the netlist for PCB design (a .net + file). + </li> + <li class="itemize">PCB Layout: Clicking on the <span +class="cmti-10x-x-109">Layout Editor </span>tool will open <span +class="cmtt-10x-x-109">Pcbnew</span><a + id="dx1-23003"></a>, the layout editor + + used in eSim. In this window, one will create the PCB. It involves laying + tracks and vias, performing optimum routing of tracks, creating one or more + copper layers for PCB, etc. It will be saved as a <span +class="cmtt-10x-x-109">.brd </span>file in the current project + directory. + </li> + <li class="itemize">Model Editor: eSim also gives an option to re-configure the model library of a device. It + facilitates the user to change model library of devices such as diode, transistor, + MOSFET, etc. + </li> + <li class="itemize">Subcircuit: eSim has an option to build subcircuits. The subcircuits can again have + components having subcircuits and so on. This enables users to build commonly used + circuits as subcircuits and then use it across circuits. For example, one can build a 12 + Volt power supply as a subcircuit and then use it as just a single component across + circuits without having to recreate it. Clicking on <span +class="cmti-10x-x-109">Subcircuit Builder </span>tool will allow one + to edit or create a subcircuit. + <!--l. 126--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-240004.1.2"></a>Menubar</h5> + <ul class="itemize2"> + <li class="itemize">New Project: New projects are created in the eSim-workspace. When this + menu is selected, a new window opens up with <span +class="cmtt-10x-x-109">Enter Project name </span>field. + Type the name of the new project and click on OK. A project directory will + be created in eSim-Workspace. The name of this folder will be the same as + that of the project created. Make sure project name does not have any spaces. + </li> + <li class="itemize">Open Project: This opens the file dialog of defalut workspace where the + projects are stored. The project can be selected which is then added in the + project explorer. + </li> + <li class="itemize">Exit: This button closes the project window and exits. + </li> + <li class="itemize">Help: It opens user manual in the dockarea.</li></ul> + + <!--l. 141--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-250004.1.2"></a>Project Explorer</h5> + <!--l. 142--><p class="noindent" >Project explorer has tree of all the project previously added in it. On right clicking the + project we can simply remove or refresh the project in the explorer. Also on + double/right clicking, the project file can be opened in the text editor which can then be + edited. + <!--l. 145--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-260004.1.2"></a>Dockarea</h5> + <!--l. 146--><p class="noindent" >This area is used to open the following windows. + <dl class="enumerate"><dt class="enumerate"> + 1. </dt><dd +class="enumerate">KiCad to Ngspice converter + </dd><dt class="enumerate"> + 2. </dt><dd +class="enumerate">Ngspice plotting + </dd><dt class="enumerate"> + 3. </dt><dd +class="enumerate">Python plotting + </dd><dt class="enumerate"> + 4. </dt><dd +class="enumerate">Model builder + </dd><dt class="enumerate"> + 5. </dt><dd +class="enumerate">Subcircuit builder</dd></dl> + <!--l. 155--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-270004.1.2"></a>Console Area</h5> + <!--l. 156--><p class="noindent" >Console area provides information about the activity done in current project. + </li></ul> + + <h2 class="chapterHead"><span class="titlemark">Chapter 5</span><br /><a + id="x1-280005"></a>Schematic Creation</h2> The first step in the design of an electronic system is the +design of its circuit. This circuit is usually created using a <span +class="cmtt-10x-x-109">Schematic Editor</span><a + id="dx1-28001"></a> and is called a +<span +class="cmtt-10x-x-109">Schematic</span>. <a + id="dx1-28002"></a>eSim uses <span +class="cmtt-10x-x-109">Eeschema</span> <a + id="dx1-28003"></a>as its schematic editor. Eeschema is the schematic editor of +KiCad. <a + id="dx1-28004"></a>It is a powerful schematic editor software. It allows the creation and modification of +components and symbol libraries and supports multiple hierarchical layers of printed circuit +design. + <h3 class="sectionHead"><span class="titlemark">5.1 </span> <a + id="x1-290005.1"></a>Familiarizing the Schematic Editor interface</h3> +<!--l. 22--><p class="noindent" >Fig. <a +href="#x1-290011">5.1<!--tex4ht:ref: eesch1 --></a> shows the schematic editor and the various menu and toolbars. We will explain them +briefly in this section. <hr class="figure"><div class="figure" +> + +<a + id="x1-290011"></a> + +<div class="center" +> +<!--l. 25--><p class="noindent" > + +<!--l. 26--><p class="noindent" ><img +src="figures/schematic1.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.1: </span><span +class="content">Schematic editor with the menu bar and toolbars marked</span></div><!--tex4ht:label?: x1-290011 --> +</div> + +<!--l. 30--><p class="indent" > </div><hr class="endfigure"> + <h4 class="subsectionHead"><span class="titlemark">5.1.1 </span> <a + id="x1-300005.1.1"></a>Top menu bar</h4> +<!--l. 35--><p class="noindent" >The top menu bar will be available at the top left corner. Some of the important menu +options in the top menu bar are: + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">File - The file menu items are given below: + <dl class="compactenum"><dt class="compactenum"> + (a) </dt><dd +class="compactenum">New - Clear current schematic and start a new one + </dd><dt class="compactenum"> + (b) </dt><dd +class="compactenum">Open - Open a schematic + </dd><dt class="compactenum"> + (c) </dt><dd +class="compactenum">Open Recent - A list of recently opened files for loading + </dd><dt class="compactenum"> + (d) </dt><dd +class="compactenum">Save Whole Schematic project - Save current sheet and all its hierarchy. + </dd><dt class="compactenum"> + (e) </dt><dd +class="compactenum">Save Current Sheet Only - Save current sheet, but not others in a hierarchy. + </dd><dt class="compactenum"> + (f) </dt><dd +class="compactenum">Save Current sheet as - Save current sheet with a new name. + </dd><dt class="compactenum"> + (g) </dt><dd +class="compactenum">Print - Access to print menu (See Fig. <a +href="#x1-300112">5.2<!--tex4ht:ref: print --></a>). + </dd><dt class="compactenum"> + (h) </dt><dd +class="compactenum">Plot - Plot the schematic in Postscript, HPGL, SVF or DXF format + </dd><dt class="compactenum"> + (i) </dt><dd +class="compactenum">Quit - Quit the schematic editor.</dd></dl> + <!--l. 53--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-300112"></a> +<div class="center" +> +<!--l. 54--><p class="noindent" > + +<!--l. 55--><p class="noindent" ><img +src="figures/print.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.2: </span><span +class="content">Print options</span></div><!--tex4ht:label?: x1-300112 --> +</div> + <!--l. 59--><p class="noindent" ></div><hr class="endfigure"> + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">Place - The place menu has shortcuts for placing various items like components, wire + and junction, on to the schematic editor window. See Sec. <a +href="#x1-340005.1.5">5.1.5<!--tex4ht:ref: short --></a> to know more about + various shortcut keys (hotkeys). + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Preferences - The preferences menu has the following options: + <dl class="compactenum"><dt class="compactenum"> + + (a) </dt><dd +class="compactenum">Library - Select libraries and library paths + </dd><dt class="compactenum"> + (b) </dt><dd +class="compactenum">Colors - Select colors for various items. + </dd><dt class="compactenum"> + (c) </dt><dd +class="compactenum">Options - Display schematic editor options (Units, Grid size). + </dd><dt class="compactenum"> + (d) </dt><dd +class="compactenum">Language - Shows the current list of translations. Use default. + </dd><dt class="compactenum"> + (e) </dt><dd +class="compactenum">Hotkeys - Access to the hot keys menu. See Sec. <a +href="#x1-340005.1.5">5.1.5<!--tex4ht:ref: short --></a> about hotkeys. + </dd><dt class="compactenum"> + (f) </dt><dd +class="compactenum">Read preferences - Read configuration file. + </dd><dt class="compactenum"> + (g) </dt><dd +class="compactenum">Save preferences - Save configuration file.</dd></dl> + </dd></dl> +<!--l. 79--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">5.1.2 </span> <a + id="x1-310005.1.2"></a>Top toolbar</h4> +<a + id="dx1-31001"></a> +<a + id="dx1-31002"></a> +<!--l. 80--><p class="noindent" >Some of the important tools in the top toolbar are discussed below. They are marked in +Fig. <a +href="#x1-310033">5.3<!--tex4ht:ref: eeschem2 --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-310033"></a> + + +<!--l. 84--><p class="noindent" ><img +src="figures/toptoolbar.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.3: </span><span +class="content">Toolbar on top with important tools marked</span></div><!--tex4ht:label?: x1-310033 --> + +<!--l. 87--><p class="indent" > </div><hr class="endfigure"> + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">Save - Save the current schematic + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">Library Editor - Create or edit components. + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Library Browser - Browse through the various component libraries available + </dd><dt class="compactenum"> + 4. </dt><dd +class="compactenum">Navigate schematic hierarchy - Navigate among the root and sub-sheets in the + hierarchy + </dd><dt class="compactenum"> + 5. </dt><dd +class="compactenum">Print - Print the schematic + </dd><dt class="compactenum"> + 6. </dt><dd +class="compactenum">Generate netlist - Generate a netlist for PCB design or for simulation. + </dd><dt class="compactenum"> + 7. </dt><dd +class="compactenum">Annotate - Annotate the schematic + </dd><dt class="compactenum"> + 8. </dt><dd +class="compactenum">Check ERC - Do Electric Rules Check for the schematic + </dd><dt class="compactenum"> + 9. </dt><dd +class="compactenum">Create BOM - Create a Bill of Materials of the schematic</dd></dl> + <h4 class="subsectionHead"><span class="titlemark">5.1.3 </span> <a + id="x1-320005.1.3"></a>Toolbar on the right</h4> +<a + id="dx1-32001"></a> +<a + id="dx1-32002"></a> +<!--l. 104--><p class="noindent" >The toolbar on the right side of the schematic editor window has many important tools. Some +of them are marked in Fig. <a +href="#x1-320034">5.4<!--tex4ht:ref: eeschem3 --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-320034"></a> + + +<!--l. 108--><p class="noindent" ><img +src="figures/rightoolbar.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.4: </span><span +class="content">Toolbar on right with important tools marked</span></div><!--tex4ht:label?: x1-320034 --> + +<!--l. 111--><p class="indent" > </div><hr class="endfigure"> +<!--l. 112--><p class="indent" > Let us now look at each of these tools and their uses. + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">Place a component - Load a component to the schematic. See Sec. <a +href="#x1-360005.2.1">5.2.1<!--tex4ht:ref: selplace --></a> for more + details. + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">Place a power port - Load a power port (Vcc, ground) to the schematic + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Place wire - Draw wires to connect components in schematic + </dd><dt class="compactenum"> + 4. </dt><dd +class="compactenum">Place bus - Place a bus on the schematic + </dd><dt class="compactenum"> + 5. </dt><dd +class="compactenum">Place a no connect - Place a no connect flag, particularly useful in ICs + </dd><dt class="compactenum"> + 6. </dt><dd +class="compactenum">Place a local label - Place a label or node name which is local to the schematic + </dd><dt class="compactenum"> + 7. </dt><dd +class="compactenum">Place a global label - Place a global label (these are connected across all schematic + diagrams in the hierarchy) + </dd><dt class="compactenum"> + 8. </dt><dd +class="compactenum">Place a text or comment - Place a text or comment in the schematic</dd></dl> + <h4 class="subsectionHead"><span class="titlemark">5.1.4 </span> <a + id="x1-330005.1.4"></a>Toolbar on the left</h4> +<a + id="dx1-33001"></a> +<a + id="dx1-33002"></a> +<!--l. 126--><p class="noindent" >Some of the important tools in the toolbar on the left are discussed below. They are marked +in Fig. <a +href="#x1-330035">5.5<!--tex4ht:ref: eeschem4 --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-330035"></a> + + +<!--l. 130--><p class="noindent" ><img +src="figures/lefttoolbar.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.5: </span><span +class="content">Toolbar on left with important tools marked</span></div><!--tex4ht:label?: x1-330035 --> + +<!--l. 133--><p class="indent" > </div><hr class="endfigure"> + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">Show/Hide grid - Show or Hide the grid in the schematic editor. Pressing the tool + again hides (shows) the grid if it was shown (hidden) earlier. + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">Show hidden pins - Show hidden pins of certain components, for example, power + pins of certain ICs.</dd></dl> + <h4 class="subsectionHead"><span class="titlemark">5.1.5 </span> <a + id="x1-340005.1.5"></a>Hotkeys</h4> +<!--l. 142--><p class="noindent" >A set of keyboard keys are associated with various operations in the schematic editor. These +keys save time and make it easy to switch from one operation to another. The list of hotkeys +can be viewed by going to Preferences in the top menu bar. Choose <span +class="cmti-10x-x-109">Hotkeys </span>and +select <span +class="cmti-10x-x-109">List current keys</span>. The hotkeys can also be edited by selecting the option +<span +class="cmti-10x-x-109">Edit Hotkeys</span>. Some frequently used hotkeys, along with their functions, are given +below: + <ul> + <li class="compactitem">F1 - Zoom in + </li> + <li class="compactitem">F2 - Zoom out + </li> + <li class="compactitem">Ctrl + Z - Undo + </li> + <li class="compactitem">Delete - Delete item + </li> + <li class="compactitem">M - Move item + </li> + <li class="compactitem">C - Copy item + </li> + <li class="compactitem">A - Add/place component + </li> + <li class="compactitem">P - Place power component + </li> + <li class="compactitem">R - Rotate item + </li> + <li class="compactitem">X - Mirror component about X axis + </li> + <li class="compactitem">Y - Mirror component about Y axis + </li> + <li class="compactitem">E - Edit schematic component + </li> + + <li class="compactitem">W - Place wire + </li> + <li class="compactitem">T - Add text + </li> + <li class="compactitem">S - Add sheet</li></ul> +<!--l. 166--><p class="noindent" ><span +class="cmti-10x-x-109">Note: Both lower and upper-case keys will work as hotkeys</span>. +<!--l. 168--><p class="noindent" > + <h3 class="sectionHead"><span class="titlemark">5.2 </span> <a + id="x1-350005.2"></a>Schematic creation for simulation</h3> +<a + id="dx1-35001"></a> +<!--l. 170--><p class="noindent" >There are certain differences between the schematic created for simulation and that created +for PCB design. We need certain components like plots and current sources. For simulation +whereas these are not needed for PCB design. For PCB design, we would require connectors +(e.g. DB15 and 2 pin connector) for taking signals in and out of the PCB whereas +these have no meaning in simulation. This section covers schematic creation for +simulation. +<!--l. 177--><p class="indent" > The first step in the creation of circuit schematic is the selection and placement of +required components. The components are grouped under eSim-libraries as shown in Fig. <a +href="#x1-350026">5.6<!--tex4ht:ref: libraries --></a>. +<hr class="figure"><div class="figure" +> + +<a + id="x1-350026"></a> + + +<!--l. 181--><p class="noindent" ><img +src="figures/libraries.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.6: </span><span +class="content">eSim-Components Libraries</span></div><!--tex4ht:label?: x1-350026 --> + +<!--l. 184--><p class="indent" > </div><hr class="endfigure"> + <h4 class="subsectionHead"><span class="titlemark">5.2.1 </span> <a + id="x1-360005.2.1"></a>Selection and placement of components</h4> +<a + id="dx1-36001"></a> +<!--l. 189--><p class="noindent" >We would need a resistor, a capacitor, a voltage source, ground terminal. To place a resistor +on the schematic editor window, select the <span +class="cmti-10x-x-109">Place a component </span>tool from the toolbar +on the right side and click anywhere on the schematic editor. This opens up the +component selection window. Resistor component can be found under <span +class="cmti-10x-x-109">eSim</span><span +class="cmti-10x-x-109">_Devices</span> +library. Fig. <a +href="#x1-360027">5.7<!--tex4ht:ref: resistor --></a> shows the selection of resistor component. Click on OK. A resistor +will be tied to the cursor. Place the resistor on the schematic editor by a single +click. +<!--l. 196--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-360027"></a> + + +<!--l. 198--><p class="noindent" ><img +src="figures/resistor.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.7: </span><span +class="content">Placing a resistor using the Place a Component tool</span></div><!--tex4ht:label?: x1-360027 --> + +<!--l. 201--><p class="indent" > </div><hr class="endfigure"> +<!--l. 202--><p class="indent" > To place the next component, i.e., capacitor, click again on the schematic editor.Similarly, +Capacitor component is found under <span +class="cmti-10x-x-109">eSim</span><span +class="cmti-10x-x-109">_Devices </span>library. Click on OK. Place the capacitor +on the schematic editor by a single click. Let us now place a sinusoidal voltage source. This is +required for performing transient analysis. To place it, click again on the schematic editor. On +the component selection window, choose the library <span +class="cmti-10x-x-109">eSim</span><span +class="cmti-10x-x-109">_source </span>by double clicking on it. +Select the component <span +class="cmtt-10x-x-109">SINE </span>and click on OK. Place the sine source on the schematic editor by +a single click. +<!--l. 211--><p class="indent" > Place the component by clicking on the schematic editor. Similarly place <span +class="cmtt-10x-x-109">gnd</span>, a ground +terminal and <span +class="cmtt-10x-x-109">power</span><span +class="cmtt-10x-x-109">_flag </span>under <span +class="cmtt-10x-x-109">power </span>library. Once all the components are placed, the +schematic editor would look like the Fig. <a +href="#x1-360038">5.8<!--tex4ht:ref: afterplace --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-360038"></a> + + +<!--l. 216--><p class="noindent" ><img +src="figures/afterplace.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.8: </span><span +class="content">All RC circuit components placed</span></div><!--tex4ht:label?: x1-360038 --> + +<!--l. 219--><p class="indent" > </div><hr class="endfigure"> +<!--l. 220--><p class="indent" > Let us rotate the resistor to complete the circuit. To rotate the resistor, place the cursor +on the resistor and press the key <span +class="cmtt-10x-x-109">R</span>. Note that if the cursor is placed above the letter <span +class="cmtt-10x-x-109">R </span>(not +<span +class="cmtt-10x-x-109">R?</span>) on the resistor, it asks to clarify selection. Choose the option <span +class="cmti-10x-x-109">Component R</span>. This can be +avoided by placing the cursor slightly away from the letter R as shown in Fig. <a +href="#x1-360059">5.9<!--tex4ht:ref: rotate --></a>. This +applies to all components.<a + id="dx1-36004"></a> <hr class="figure"><div class="figure" +> + +<a + id="x1-360059"></a> + + +<!--l. 228--><p class="noindent" ><img +src="figures/rotate.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.9: </span><span +class="content">Placing the cursor (cross mark) slightly away from the letter R</span></div><!--tex4ht:label?: x1-360059 --> + +<!--l. 231--><p class="indent" > </div><hr class="endfigure"> +<!--l. 232--><p class="indent" > If one wants to move a component, place the cursor on top of the component and press the +key <span +class="cmtt-10x-x-109">M</span>. The component will be tied to the cursor and can be moved in any direction. +<a + id="dx1-36006"></a> + <h4 class="subsectionHead"><span class="titlemark">5.2.2 </span> <a + id="x1-370005.2.2"></a>Wiring the circuit</h4> +<a + id="dx1-37001"></a> +<!--l. 238--><p class="noindent" >The next step is to wire the connections. Let us connect the resistor to the capacitor. +To do so, point the cursor to the terminal of resistor to be connected and press +the key <span +class="cmtt-10x-x-109">W</span>. It has now changed to the wiring mode. Move the cursor towards the +terminal of the capacitor and click on it. A wire is formed as shown in Fig. <a +href="#x1-37002r1">5.10a<!--tex4ht:ref: wire1 --></a>. +<hr class="figure"><div class="figure" +> + +<a + id="x1-3700510"></a> + +<a + id="x1-37002r1"></a> +<!--l. 248--><p class="noindent" > <img +src="figures/wire1.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Initial</span> +<span +class="cmr-9">stages</span> <a + id="x1-37003r2"></a> <img +src="figures/wirefin.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Wiring</span> + <span +class="cmr-9">done</span> <a + id="x1-37004r3"></a> <img +src="figures/schemfin.png" alt="PIC" +> + <span +class="cmr-9">(c)</span> + <span +class="cmr-9">Final</span> + <span +class="cmr-9">schematic</span> + <span +class="cmr-9">with</span> + <span +class="cmr-9">PWR</span><span +class="cmr-9">_FLAG</span> +<br /> <div class="caption" +><span class="id">Figure 5.10: </span><span +class="content">Various stages of wiring</span></div><!--tex4ht:label?: x1-3700510 --> + +<!--l. 256--><p class="indent" > </div><hr class="endfigure"> +<!--l. 257--><p class="indent" > Similarly connect the wires between all terminals and the final schematic would look like +Fig. <a +href="#x1-37003r2">5.10b<!--tex4ht:ref: wirefin --></a>. + <h4 class="subsectionHead"><span class="titlemark">5.2.3 </span> <a + id="x1-380005.2.3"></a>Assigning values to components</h4> +<a + id="dx1-38001"></a> +<!--l. 261--><p class="noindent" >We need to assign values to the components in our circuit i.e., resistor and capacitor. Note +that the sine voltage source has been placed for simulation. The specifications of sine source +will be given during simulation. To assign value to the resistor, place the cursor above the +letter <span +class="cmtt-10x-x-109">R </span>(not <span +class="cmtt-10x-x-109">R?</span>) and press the key <span +class="cmtt-10x-x-109">E</span>. Choose <span +class="cmti-10x-x-109">Field value</span>. Type <span +class="cmtt-10x-x-109">1k </span>in the <span +class="cmti-10x-x-109">Edit value field </span>box +as shown in Fig. <a +href="#x1-3800211">5.11<!--tex4ht:ref: field --></a>. 1k means 1<span +class="cmmi-10x-x-109">k</span>Ω. Similarly give the value <span +class="cmtt-10x-x-109">1u </span>for the capacitor. 1u means +1<span +class="cmmi-10x-x-109">μF</span>. +<!--l. 271--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-3800211"></a> + + +<!--l. 273--><p class="noindent" ><img +src="figures/field.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.11: </span><span +class="content">Editing value of resistor</span></div><!--tex4ht:label?: x1-3800211 --> + +<!--l. 276--><p class="indent" > </div><hr class="endfigure"> + <h4 class="subsectionHead"><span class="titlemark">5.2.4 </span> <a + id="x1-390005.2.4"></a>Annotation and ERC</h4> +<a + id="dx1-39001"></a> +<a + id="dx1-39002"></a> +<a + id="dx1-39003"></a> +<a + id="dx1-39004"></a> +<!--l. 280--><p class="noindent" >The next step is to annotate the schematic. Annotation gives unique references to the +components. To annotate the schematic, click on <span +class="cmti-10x-x-109">Annotate schematic </span>tool from the +top toolbar. Click on <span +class="cmtt-10x-x-109">annotation</span>, then click on <span +class="cmtt-10x-x-109">OK </span>and finally click on close as +shown in Fig. <a +href="#x1-3900813">5.13<!--tex4ht:ref: anno --></a>. The schematic is now annotated. The question marks next to +component references have been replaced by unique numbers. If there are more than +one instance of a component (say resistor), the annotation will be done as R1, R2, +etc. +<!--l. 289--><p class="indent" > Let us now do <span +class="cmtt-10x-x-109">ERC </span>or <span +class="cmtt-10x-x-109">Electric Rules Check</span>. To do so, click on <span +class="cmti-10x-x-109">Perform electric rules</span> +<span +class="cmti-10x-x-109">check </span>tool from the top toolbar. Click on <span +class="cmti-10x-x-109">Test Erc </span>button. The error as shown in Fig. <a +href="#x1-3900712">5.12<!--tex4ht:ref: erc --></a> +may be displayed. Click on close in the test erc<a + id="dx1-39005"></a> window. <a + id="dx1-39006"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-3900712"></a> + + +<!--l. 296--><p class="noindent" ><img +src="figures/erc2.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.12: </span><span +class="content">ERC error</span></div><!--tex4ht:label?: x1-3900712 --> + +<!--l. 299--><p class="indent" > </div><hr class="endfigure"> +<!--l. 300--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-3900813"></a> + + +<!--l. 302--><p class="noindent" ><img +src="figures/anno.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.13: </span><span +class="content">Steps in annotating a schematic: 1. First click on Annotation then 2. Click +on Ok then 3. Click on close</span></div><!--tex4ht:label?: x1-3900813 --> + +<!--l. 305--><p class="indent" > </div><hr class="endfigure"> +<!--l. 306--><p class="indent" > There will be a green arrow pointing to the source of error in the schematic. Here it points +to the ground terminal. This is shown in Fig. <a +href="#x1-3900914">5.14<!--tex4ht:ref: ercgnd --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-3900914"></a> + + +<!--l. 311--><p class="noindent" ><img +src="figures/ercgnd.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.14: </span><span +class="content">Green arrow pointing to Ground terminal indicating an ERC error</span></div><!--tex4ht:label?: x1-3900914 --> + +<!--l. 314--><p class="indent" > </div><hr class="endfigure"> +<!--l. 315--><p class="indent" > To correct this error, place a <span +class="cmtt-10x-x-109">PWR</span><span +class="cmtt-10x-x-109">_FLAG </span>from the Eeschema library <span +class="cmti-10x-x-109">power</span>. <a + id="dx1-39010"></a>Connect the +power flag to the ground terminal as shown in Fig. <a +href="#x1-37004r3">5.10c<!--tex4ht:ref: schemfin --></a>. One needs to place <span +class="cmtt-10x-x-109">PWR</span><span +class="cmtt-10x-x-109">_FLAG</span> +wherever the error shown in Fig. <a +href="#x1-3900712">5.12<!--tex4ht:ref: erc --></a> is obtained. Repeat the ERC. Now there are no errors. +With this we have created the schematic for simulation. + <h4 class="subsectionHead"><span class="titlemark">5.2.5 </span> <a + id="x1-400005.2.5"></a>Netlist generation</h4> +<a + id="dx1-40001"></a> +<!--l. 326--><p class="noindent" >To simulate the circuit that has been created in the previous section, we need to generate its +netlist. <span +class="cmtt-10x-x-109">Netlist </span>is a list of components in the schematic along with their connection +information. <a + id="dx1-40002"></a>To do so, click on the <span +class="cmti-10x-x-109">Generate netlist </span>tool from the top toolbar. Click on spice +from the window that opens up. Check the option <span +class="cmtt-10x-x-109">Default Format</span>. Then click on <span +class="cmti-10x-x-109">Generate</span>. +This is shown in Fig. <a +href="#x1-4000315">5.15<!--tex4ht:ref: chap5net --></a>. Save the netlist. This will be a <span +class="cmtt-10x-x-109">.cir </span>file. Do not change the +directory while saving. <hr class="figure"><div class="figure" +> + +<a + id="x1-4000315"></a> + + +<!--l. 337--><p class="noindent" ><img +src="figures/netlist.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.15: </span><span +class="content">Steps in generating a Netlist for simulation: 1. Click on Spice then 2. +Check the option <span +class="cmtt-10x-x-109">Default Format </span>then 3. Click on Generate </span></div><!--tex4ht:label?: x1-4000315 --> + +<!--l. 340--><p class="indent" > </div><hr class="endfigure"> +<!--l. 341--><p class="indent" > Now the netlist is ready to be simulated. Refer to <span class="cite"> [<a +href="#Xkicad">15</a>]</span> or <span class="cite"> [<a +href="#Xkicad2">16</a>]</span> to know more about +Eeschema. + + <h2 class="chapterHead"><span class="titlemark">Chapter 6</span><br /><a + id="x1-410006"></a>PCB Design</h2> Printed Circuit Board (PCB) <a + id="dx1-41001"></a>design is an important step in +electronic system design. Every component of the circuit needs to be placed and connections +routed to minimise delay and area. Each component has an associated footprint. Footprint +refers to the physical layout of a component that is required to mount it on the PCB.<a + id="dx1-41002"></a> <a + id="dx1-41003"></a>PCB +design involves associating footprints to all components, placing them appropriately to +minimise wire length and area, connecting the footprints using tracks/vias and finally +extracting the required files needed for printing the PCB. Let us see the steps to design PCB +using eSim. + <h3 class="sectionHead"><span class="titlemark">6.1 </span> <a + id="x1-420006.1"></a>Schematic creation for PCB design</h3> +<!--l. 16--><p class="noindent" >In Chapter <a +href="#x1-610009">9<!--tex4ht:ref: chap5 --></a>, we will see the differences between schematic for simulation and schematic for +PCB design. Let us design the PCB for a RC circuit. A resistor, capacitor, ground, power flag +and a connector are required. Connectors are used to take signals in and out of the +PCB. +<!--l. 22--><p class="indent" > Create the circuit schematic as shown in Fig. <a +href="#x1-420011">6.1<!--tex4ht:ref: pcbschfin --></a>. The two pin connector (<span +class="cmti-10x-x-109">CONN</span><span +class="cmti-10x-x-109">_2</span>) can +be placed from the Eeschema library <span +class="cmti-10x-x-109">conn</span>. Do the annotation and test for ERC. Refer to +Chapter <a +href="#x1-610009">9<!--tex4ht:ref: chap5 --></a> to know more about basic steps in schematic creation. +<!--l. 28--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-420011"></a> + + +<!--l. 30--><p class="noindent" ><img +src="figures/pcbschfin.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.1: </span><span +class="content">Final circuit schematic for RC low pass circuit</span></div><!--tex4ht:label?: x1-420011 --> + +<!--l. 33--><p class="indent" > </div><hr class="endfigure"> + <h4 class="subsectionHead"><span class="titlemark">6.1.1 </span> <a + id="x1-430006.1.1"></a>Netlist generation for PCB</h4> +<a + id="dx1-43001"></a> +<a + id="dx1-43002"></a> +<!--l. 38--><p class="noindent" >The netlist for PCB is different from that for simulation. To generate netlist for PCB, click on +the <span +class="cmti-10x-x-109">Generate netlist </span>tool from the top toolbar in Schematic editor. In the Netlist window, +under the tab <span +class="cmti-10x-x-109">Pcbnew</span>, <a + id="dx1-43003"></a>click on the button <span +class="cmti-10x-x-109">Netlist</span>. This is shown in Fig. <a +href="#x1-430042">6.2<!--tex4ht:ref: netlistpcb --></a>. Click on +<span +class="cmti-10x-x-109">Save </span>in the Save netlist file dialog box that opens up. Do not change the directory +or the name of the netlist file. Save the schematic and close the schematic editor. +<hr class="figure"><div class="figure" +> + +<a + id="x1-430042"></a> + + +<!--l. 48--><p class="noindent" ><img +src="figures/netlistpcb.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.2: </span><span +class="content">Netlist generation for PCB</span></div><!--tex4ht:label?: x1-430042 --> + +<!--l. 51--><p class="indent" > </div><hr class="endfigure"> +<!--l. 52--><p class="indent" > <span +class="cmti-10x-x-109">Note that the netlist for PCB has an extension </span><span +class="cmtt-10x-x-109">.net</span><span +class="cmti-10x-x-109">. The netlist created for simulation</span> +<span +class="cmti-10x-x-109">has an extension </span><span +class="cmtt-10x-x-109">.cir</span>. + <h4 class="subsectionHead"><span class="titlemark">6.1.2 </span> <a + id="x1-440006.1.2"></a>Mapping of components using Footprint Editor</h4> +<a + id="dx1-44001"></a> +<a + id="dx1-44002"></a> +<a + id="dx1-44003"></a> +<!--l. 59--><p class="noindent" >Once the netlist for PCB is created, one needs to map each component in the netlist to a +footprint. The tool <span +class="cmti-10x-x-109">Footprint Editor </span>is used for this. eSim uses <span +class="cmtt-10x-x-109">CvPcb </span>as its footprint editor. +<span +class="cmtt-10x-x-109">CvPcb </span>is the footprint editor tool in KiCad. <a + id="dx1-44004"></a> +<!--l. 64--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">6.1.3 </span> <a + id="x1-450006.1.3"></a>Familiarising the Footprint Editor tool</h4> +<a + id="dx1-45001"></a> +<!--l. 67--><p class="noindent" >If one opens the <span +class="cmti-10x-x-109">Footprint Editor </span>after creating the <span +class="cmtt-10x-x-109">.net </span>netlist file, the Footprint editor as +shown in Fig. <a +href="#x1-450023">6.3<!--tex4ht:ref: fe --></a> will be obtained. The menu bar and toolbars and the panes are marked in +this figure. The menu bar will be available in the top left corner. The left pane has a list of +components in the netlist file and the right pane has a list of available footprints for each +component. <hr class="figure"><div class="figure" +> + +<a + id="x1-450023"></a> + + +<!--l. 75--><p class="noindent" ><img +src="figures/fe.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.3: </span><span +class="content">Footprint editor with the menu bar, toolbar, left pane and right pane +marked</span></div><!--tex4ht:label?: x1-450023 --> + +<!--l. 78--><p class="indent" > </div><hr class="endfigure"> +<!--l. 79--><p class="indent" > <span +class="cmti-10x-x-109">Note that if the Footprint Editor is opened before creating a ‘.net’ file, then the left and</span> +<span +class="cmti-10x-x-109">right panes will be empty</span>. + <h5 class="subsubsectionHead"><a + id="x1-460006.1.3"></a>Toolbar</h5> +<!--l. 82--><p class="noindent" >Some of the important tools in the toolbar are shown in Fig. <a +href="#x1-460014">6.4<!--tex4ht:ref: tb_fe --></a>. They are explained below: +<hr class="figure"><div class="figure" +> + +<a + id="x1-460014"></a> + + +<!--l. 86--><p class="noindent" ><img +src="figures/tb_fe.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.4: </span><span +class="content">Some important tools in the toolbar</span></div><!--tex4ht:label?: x1-460014 --> + +<!--l. 89--><p class="indent" > </div><hr class="endfigure"> + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">Save netlist and footprint files - Save the netlist and the footprints that are + associated with it. + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">View selected footprint - View the selected footprint in 2D. See Sec. <a +href="#x1-470006.1.4">6.1.4<!--tex4ht:ref: viewfp --></a> for more + details. + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Automatic footprint association - Perform footprint association for each + component automatically. Footprints will be selected from the list of footprints + available. + </dd><dt class="compactenum"> + 4. </dt><dd +class="compactenum">Delete all associations - Delete all the footprint associations made + </dd><dt class="compactenum"> + 5. </dt><dd +class="compactenum">Display filtered footprint list - Display a filtered list of footprints suitable to the + selected component + </dd><dt class="compactenum"> + 6. </dt><dd +class="compactenum">Display full footprint list - Display the list of all footprints available (without + filtering)</dd></dl> + <h4 class="subsectionHead"><span class="titlemark">6.1.4 </span> <a + id="x1-470006.1.4"></a>Viewing footprints in 2D and 3D</h4> +<a + id="dx1-47001"></a> +<a + id="dx1-47002"></a> +<!--l. 110--><p class="noindent" >To view a footprint in 2D, select it from the right pane and click on <span +class="cmti-10x-x-109">View selected footprint</span> +from the menu bar. Let us view the footprint for <span +class="cmtt-10x-x-109">SM1210</span>. Choose SM1210 from +the right pane as shown in Fig. <a +href="#x1-470035">6.5<!--tex4ht:ref: sm --></a>. On clicking the <span +class="cmti-10x-x-109">View selected footprint </span>tool, +the <span +class="cmtt-10x-x-109">Footprint </span>window with the view in 2D will be displayed. Click on the <span +class="cmti-10x-x-109">3D</span> +tool in the <span +class="cmtt-10x-x-109">Footprint </span>window, as shown in Fig. <a +href="#x1-470046">6.6<!--tex4ht:ref: 3d --></a>. A top view of the selected +footprint in 3D is obtained. Click on the footprint and rotate it using mouse to get 3D +views from various angles. One such side view of the footprint in 3D is shown in +Fig. <a +href="#x1-470057">6.7<!--tex4ht:ref: 3dv --></a>. +<!--l. 121--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-470035"></a> + + +<!--l. 123--><p class="noindent" ><img +src="figures/sm.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.5: </span><span +class="content">Viewing footprint for SM1210: 1. Choose the footprint SM1210 from the +right pane, 2. Click on <span +class="cmti-10x-x-109">View selected footprint</span></span></div><!--tex4ht:label?: x1-470035 --> + +<!--l. 127--><p class="indent" > </div><hr class="endfigure"> +<!--l. 128--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-470046"></a> + + +<!--l. 130--><p class="noindent" ><img +src="figures/3d.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.6: </span><span +class="content">Footprint view in 2D. Click on <span +class="cmti-10x-x-109">3D </span>to get 3D view</span></div><!--tex4ht:label?: x1-470046 --> + +<!--l. 133--><p class="indent" > </div><hr class="endfigure"> +<!--l. 134--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-470057"></a> + + +<!--l. 136--><p class="noindent" ><img +src="figures/3dv.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.7: </span><span +class="content">Side view of the footprint in 3D</span></div><!--tex4ht:label?: x1-470057 --> + +<!--l. 139--><p class="indent" > </div><hr class="endfigure"> + <h4 class="subsectionHead"><span class="titlemark">6.1.5 </span> <a + id="x1-480006.1.5"></a>Mapping of components in the RC circuit</h4> +<!--l. 142--><p class="noindent" >Click on <span +class="cmtt-10x-x-109">C1 </span>from the left pane. Choose the footprint <span +class="cmti-10x-x-109">C1 </span>from the right pane by double +clicking on it. Click on connector <span +class="cmtt-10x-x-109">P1 </span>from the left pane. Choose the footprint <span +class="cmti-10x-x-109">SIL-2 </span>from the +right pane by double clicking on it. Similarly choose the footprint <span +class="cmti-10x-x-109">R3 </span>for the resistor <span +class="cmtt-10x-x-109">R1</span>. The +footprint mapping is shown in Fig. <a +href="#x1-480018">6.8<!--tex4ht:ref: map --></a>. Save the footprint association by clicking on the <span +class="cmti-10x-x-109">Save</span> +<span +class="cmti-10x-x-109">netlist and footprint files </span>tool from the <span +class="cmtt-10x-x-109">CvPcb </span>toolbar. The <span +class="cmtt-10x-x-109">Save Net and component List</span> +window appears. Browse to the directory where the schematic file for this project is saved and +click on <span +class="cmti-10x-x-109">Save</span>. The netlist gets saved and the <span +class="cmti-10x-x-109">Footprint Editor </span>window closes automatically. +<hr class="figure"><div class="figure" +> + +<a + id="x1-480018"></a> + + +<!--l. 155--><p class="noindent" ><img +src="figures/map.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.8: </span><span +class="content">Footprint mapping done</span></div><!--tex4ht:label?: x1-480018 --> + +<!--l. 158--><p class="indent" > </div><hr class="endfigure"> +<!--l. 159--><p class="indent" > <span +class="cmti-10x-x-109">Note that one needs to browse to the directory where the schematic file is saved and save</span> +<span +class="cmti-10x-x-109">the ‘.net’ file in the same directory</span>. + <h3 class="sectionHead"><span class="titlemark">6.2 </span> <a + id="x1-490006.2"></a>Creation of PCB layout</h3> +<a + id="dx1-49001"></a> +<a + id="dx1-49002"></a> +<!--l. 164--><p class="noindent" >The next step is to place the footprints and lay tracks between them to get the layout. This is +done using the <span +class="cmti-10x-x-109">Layout Editor </span>tool. eSim uses <span +class="cmtt-10x-x-109">Pcbnew</span>, the layout creation tool in KiCad, as its +layout editor. +<!--l. 169--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">6.2.1 </span> <a + id="x1-500006.2.1"></a>Familiarizing the Layout Editor tool</h4> +<a + id="dx1-50001"></a> +<!--l. 172--><p class="noindent" >The layout editor with the various menu bar and toolbars is shown in Fig. <a +href="#x1-500029">6.9<!--tex4ht:ref: pcbnew --></a>. +<hr class="figure"><div class="figure" +> + +<a + id="x1-500029"></a> + + +<!--l. 176--><p class="noindent" ><img +src="figures/pcbnew.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.9: </span><span +class="content">Layout editor with menu bar, toolbars and layer options marked</span></div><!--tex4ht:label?: x1-500029 --> + +<!--l. 179--><p class="indent" > </div><hr class="endfigure"> +<!--l. 180--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-5000310"></a> + + +<!--l. 182--><p class="noindent" ><img +src="figures/toptble.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.10: </span><span +class="content">Top toolbar with important tools marked</span></div><!--tex4ht:label?: x1-5000310 --> + +<!--l. 185--><p class="indent" > </div><hr class="endfigure"> + <h5 class="subsubsectionHead"><a + id="x1-510006.2.1"></a>Top toolbar</h5> +<!--l. 188--><p class="noindent" >Some of the important menu options in the top menu bar are shown in Fig. <a +href="#x1-5000310">6.10<!--tex4ht:ref: toptble --></a>. They are +explained below: + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">Save board - Save the printed circuit board + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">Module editor - Open module editor to edit footprint modules or libraries + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Read netlist - Import the netlist whose layout needs to be created. + </dd><dt class="compactenum"> + 4. </dt><dd +class="compactenum">Perform design rules check - Check for design rules, unconnected nets, etc., in the + layout. + </dd><dt class="compactenum"> + 5. </dt><dd +class="compactenum">Select working layer - Selection of working layer + </dd><dt class="compactenum"> + 6. </dt><dd +class="compactenum">Show active layer selections and select layer pair for route and place - Select layer + in top and bottom layers. It also shows the currently active layer selections. + </dd><dt class="compactenum"> + 7. </dt><dd +class="compactenum">Mode footprint: Manual/automatic move and place - Move and place modules</dd></dl> +<!--l. 206--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">6.2.2 </span> <a + id="x1-520006.2.2"></a>Hotkeys</h4> +<a + id="dx1-52001"></a> +<!--l. 208--><p class="noindent" >A list of hotkeys are given below: + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">F1 - Zoom in + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">F2 - Zoom out + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Delete - Delete Track or Footprint + </dd><dt class="compactenum"> + 4. </dt><dd +class="compactenum">X - Add new track + </dd><dt class="compactenum"> + 5. </dt><dd +class="compactenum">V - Add Via + </dd><dt class="compactenum"> + 6. </dt><dd +class="compactenum">M - Move Item + + </dd><dt class="compactenum"> + 7. </dt><dd +class="compactenum">F - Flip Footprint + </dd><dt class="compactenum"> + 8. </dt><dd +class="compactenum">R - Rotate Item + </dd><dt class="compactenum"> + 9. </dt><dd +class="compactenum">G - Drag Footprint + </dd><dt class="compactenum"> + 10. </dt><dd +class="compactenum">Ctrl+Z - Undo + </dd><dt class="compactenum"> + 11. </dt><dd +class="compactenum">E - Edit Item</dd></dl> +<!--l. 222--><p class="noindent" >The list can be viewed by selecting <span +class="cmti-10x-x-109">Preferences </span>from the top menu bar and choosing <span +class="cmti-10x-x-109">List Current</span> +<span +class="cmti-10x-x-109">Keys </span>from the option <span +class="cmti-10x-x-109">Hotkeys</span>. +<!--l. 226--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">6.2.3 </span> <a + id="x1-530006.2.3"></a>PCB design example using RC circuit</h4> +<a + id="dx1-53001"></a> +<!--l. 227--><p class="noindent" >Click on <span +class="cmti-10x-x-109">Layout Editor </span>from the eSim toolbar. Click on <span +class="cmti-10x-x-109">Read Netlist </span>tool from the top +toolbar. Click on <span +class="cmti-10x-x-109">Browse Netlist files </span>on the Netlist window that opens up. Select the <span +class="cmtt-10x-x-109">.net </span>file +that was modified after assigning footprints. Click on <span +class="cmti-10x-x-109">Open</span>. Now Click on <span +class="cmti-10x-x-109">Read Current</span> +<span +class="cmti-10x-x-109">Netlist </span>on the Netlist window. The message area in the Netlist window says that +the RC_pcb.net has been read. The sequence of operations is shown in Fig. <a +href="#x1-5300411">6.11<!--tex4ht:ref: brnet --></a>. +<a + id="dx1-53002"></a><a + id="dx1-53003"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-5300411"></a> + + +<!--l. 238--><p class="noindent" ><img +src="figures/rcpcb.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.11: </span><span +class="content">Importing netlist file to layout editor: 1. Browse netlist Files, 2. Choose +the RC_pcb.net file, 3. Read Netlist file, 4. Close</span></div><!--tex4ht:label?: x1-5300411 --> + +<!--l. 242--><p class="indent" > </div><hr class="endfigure"> +<!--l. 243--><p class="indent" > The footprint modules will now be imported to the top left hand corner of the layout +editor window. This is shown in Fig. <a +href="#x1-5300512">6.12<!--tex4ht:ref: netlisttop --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-5300512"></a> + + +<!--l. 247--><p class="noindent" ><img +src="figures/netlisttop.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.12: </span><span +class="content">Footprint modules imported to top left corner of layout editor window</span></div><!--tex4ht:label?: x1-5300512 --> + +<!--l. 250--><p class="indent" > </div><hr class="endfigure"> +<!--l. 251--><p class="indent" > Zoom in to the top left corner by pressing the key <span +class="cmtt-10x-x-109">F1 </span>or using the scroll button of the +mouse. The zoomed in version of the imported netlist is shown in Fig. <a +href="#x1-5300613">6.13<!--tex4ht:ref: zoom --></a>. +<!--l. 255--><p class="indent" > Let us now place this in the center of the layout editor window. <hr class="figure"><div class="figure" +> + +<a + id="x1-5300613"></a> + + +<!--l. 259--><p class="noindent" ><img +src="figures/zoom.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.13: </span><span +class="content">Zoomed in version of the imported netlist</span></div><!--tex4ht:label?: x1-5300613 --> + +<!--l. 262--><p class="indent" > </div><hr class="endfigure"> +<!--l. 263--><p class="indent" > Click on <span +class="cmti-10x-x-109">Mode footprint: Manual/automatic move and place </span>tool from the top toolbar. +Place the cursor near the center of the layout editor window. Right click and choose <span +class="cmti-10x-x-109">Glob</span> +<span +class="cmti-10x-x-109">move and place</span>. Choose <span +class="cmti-10x-x-109">move all modules</span>. The sequence of operations is shown in Fig. <a +href="#x1-5300714">6.14<!--tex4ht:ref: movep --></a>. +Click on <span +class="cmti-10x-x-109">Yes </span>on the confirmation window to move the modules. Zoom in using the F1 key. +The current placement of components after zooming in is shown in Fig. <a +href="#x1-53008r1">6.15a<!--tex4ht:ref: curplace --></a>. +<hr class="figure"><div class="figure" +> + +<a + id="x1-5300714"></a> + + +<!--l. 272--><p class="noindent" ><img +src="figures/movep.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.14: </span><span +class="content">Moving and placing modules to the center of layout editor. 1. Click on +<span +class="cmti-10x-x-109">Mode footprint: Manual/automatic move and place</span>, 2. Place cursor at center of layout +editor and right click on it 3. Choose <span +class="cmti-10x-x-109">Glob Move and Place </span>and then choose <span +class="cmti-10x-x-109">Move All</span> +<span +class="cmti-10x-x-109">Modules.</span></span></div><!--tex4ht:label?: x1-5300714 --> + +<!--l. 279--><p class="indent" > </div><hr class="endfigure"> +<!--l. 286--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-5301015"></a> + +<a + id="x1-53008r1"></a> +<!--l. 290--><p class="noindent" > <img +src="figures/curplace.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Zoomed</span> +<span +class="cmr-9">in</span> +<span +class="cmr-9">version</span> +<span +class="cmr-9">of the</span> +<span +class="cmr-9">current</span> +<span +class="cmr-9">placement</span> +<span +class="cmr-9">after</span> +<span +class="cmr-9">moving</span> +<span +class="cmr-9">modules</span> +<span +class="cmr-9">to the</span> +<span +class="cmr-9">center</span> +<span +class="cmr-9">of the</span> +<span +class="cmr-9">layout</span> +<span +class="cmr-9">editor</span> <a + id="x1-53009r2"></a> <img +src="figures/fplace.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Final</span> + <span +class="cmr-9">placement</span> + <span +class="cmr-9">of</span> + <span +class="cmr-9">footprints</span> + <span +class="cmr-9">after</span> + <span +class="cmr-9">rotating</span> + <span +class="cmr-9">and</span> + <span +class="cmr-9">moving</span> + <span +class="cmr-9">P1</span> +<br /> <div class="caption" +><span class="id">Figure 6.15: </span><span +class="content">Different stages of placement of modules on PCB</span></div><!--tex4ht:label?: x1-5301015 --> + +<!--l. 295--><p class="indent" > </div><hr class="endfigure"> +<!--l. 296--><p class="indent" > We need to arrange the modules properly to lay tracks. Rotate the connector P1 by +placing the cursor on top of P1 and pressing R. Move it by placing the cursor on top of it and +pressing M. The final placement is shown in Fig. <a +href="#x1-53009r2">6.15b<!--tex4ht:ref: fplace --></a>. <a + id="dx1-53011"></a> +<!--l. 302--><p class="indent" > Let us now lay the tracks. Let us first change the track width. Click on <span +class="cmti-10x-x-109">Design rules </span>from +the top menu bar. Click on <span +class="cmti-10x-x-109">Design rules</span>. This is shown in Fig. <a +href="#x1-5301416">6.16<!--tex4ht:ref: drules --></a>. The <span +class="cmti-10x-x-109">Design Rules Editor</span> +window opens up. Here one can edit the various design rules. Double click on the track width +field to edit it. Type 0.8 and press <span +class="cmtt-10x-x-109">Enter</span>. Click on OK. Fig. <a +href="#x1-5301517">6.17<!--tex4ht:ref: druleedit --></a> shows the sequence of +operations. <a + id="dx1-53012"></a><a + id="dx1-53013"></a> <hr class="figure"><div class="figure" +> + +<a + id="x1-5301416"></a> + + +<!--l. 312--><p class="noindent" ><img +src="figures/drules.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.16: </span><span +class="content">Choose <span +class="cmti-10x-x-109">Design Rules </span>from the top menu bar and <span +class="cmti-10x-x-109">Design Rules </span>again</span></div><!--tex4ht:label?: x1-5301416 --> + +<!--l. 316--><p class="indent" > </div><hr class="endfigure"> +<!--l. 317--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-5301517"></a> + + +<!--l. 319--><p class="noindent" ><img +src="figures/druleedit.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.17: </span><span +class="content">Changing the track width: 1. Double click on <span +class="cmti-10x-x-109">Track Width </span>field and type +0.8, 2. Click on <span +class="cmti-10x-x-109">OK</span></span></div><!--tex4ht:label?: x1-5301517 --> + +<!--l. 323--><p class="indent" > </div><hr class="endfigure"> +<!--l. 325--><p class="indent" > Click on <span +class="cmti-10x-x-109">Back </span>from the <span +class="cmti-10x-x-109">Layer </span>options as shown in Fig. <a +href="#x1-5301718">6.18<!--tex4ht:ref: layer --></a>. <a + id="dx1-53016"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-5301718"></a> + + +<!--l. 329--><p class="noindent" ><img +src="figures/layer.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.18: </span><span +class="content">Choosing the copper layer <span +class="cmti-10x-x-109">Back</span></span></div><!--tex4ht:label?: x1-5301718 --> + +<!--l. 332--><p class="indent" > </div><hr class="endfigure"> +<!--l. 333--><p class="indent" > Let us now start laying the tracks. Place the cursor above the left terminal of R1 +in the layout editor window. Press the key <span +class="cmtt-10x-x-109">x</span>. Move the cursor down and double +click on the left terminal of C1. A track is formed. This is shown in Fig. <a +href="#x1-53018r1">6.19a<!--tex4ht:ref: track1 --></a>. +<hr class="figure"><div class="figure" +> + +<a + id="x1-5302119"></a> + +<a + id="x1-53018r1"></a> +<!--l. 341--><p class="noindent" > <img +src="figures/track1.png" alt="PIC" +> +<span +class="cmr-9">(a) A</span> +<span +class="cmr-9">track</span> +<span +class="cmr-9">formed</span> +<span +class="cmr-9">between</span> +<span +class="cmr-9">resistor</span> +<span +class="cmr-9">and</span> +<span +class="cmr-9">capacitor</span> <a + id="x1-53019r2"></a> <img +src="figures/track2.png" alt="PIC" +> + <span +class="cmr-9">(b) A</span> + <span +class="cmr-9">track</span> + <span +class="cmr-9">formed</span> + <span +class="cmr-9">between</span> + <span +class="cmr-9">capacitor</span> + <span +class="cmr-9">and</span> + <span +class="cmr-9">connector</span> <a + id="x1-53020r3"></a> <img +src="figures/track3.png" alt="PIC" +> + <span +class="cmr-9">(c) A</span> + <span +class="cmr-9">track</span> + <span +class="cmr-9">formed</span> + <span +class="cmr-9">between</span> + <span +class="cmr-9">connector</span> + <span +class="cmr-9">and</span> + <span +class="cmr-9">resistor</span> +<br /> <div class="caption" +><span class="id">Figure 6.19: </span><span +class="content">Different stages of laying tracks during PCB design</span></div><!--tex4ht:label?: x1-5302119 --> + +<!--l. 349--><p class="indent" > </div><hr class="endfigure"> +<!--l. 350--><p class="indent" > Similarly lay the track between capacitor C1 and connector P1 as shown in +Fig. <a +href="#x1-53019r2">6.19b<!--tex4ht:ref: track2 --></a>. The last track needs to be laid at an angle. To do so, place the cursor +above the second terminal of R1. Press the key x and move the cursor diagonally +down. Double click on the other terminal of the connector. The track will be laid +as shown in Fig. <a +href="#x1-53020r3">6.19c<!--tex4ht:ref: track3 --></a>. All tracks are now laid. The next step is to create PCB +edges. +<!--l. 358--><p class="indent" > Choose <span +class="cmti-10x-x-109">PCB</span><span +class="cmti-10x-x-109">_edges </span>from the <span +class="cmti-10x-x-109">Layer </span>options to add edges. Click on <span +class="cmti-10x-x-109">Add graphic line or</span> +<span +class="cmti-10x-x-109">polygon </span>from the toolbar on the left. Fig. <a +href="#x1-5302320">6.20<!--tex4ht:ref: pcbedges --></a> shows the sequence of operations. Let us now +start drawing edges for PCB. <a + id="dx1-53022"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-5302320"></a> + + +<!--l. 365--><p class="noindent" ><img +src="figures/pcbedges.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.20: </span><span +class="content">Creating PCB edges: 1. Choose <span +class="cmti-10x-x-109">PCB</span><span +class="cmti-10x-x-109">_Edges </span>from <span +class="cmti-10x-x-109">Layer </span>options 2. Choose +<span +class="cmti-10x-x-109">Add graphic line or polygon </span>from left toolbar</span></div><!--tex4ht:label?: x1-5302320 --> + +<!--l. 370--><p class="indent" > </div><hr class="endfigure"> +<!--l. 371--><p class="indent" > Click to the left of the layout. Move cursor horizontally to the right. Click once to change +orientation. Move cursor vertically down. Draw the edges as shown in Fig. <a +href="#x1-5302421">6.21<!--tex4ht:ref: pcbed --></a>. Double click +to finish drawing the edges. <hr class="figure"><div class="figure" +> + +<a + id="x1-5302421"></a> + + +<!--l. 377--><p class="noindent" ><img +src="figures/pcbed.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.21: </span><span +class="content">PCB edges drawn</span></div><!--tex4ht:label?: x1-5302421 --> + +<!--l. 380--><p class="indent" > </div><hr class="endfigure"> +<!--l. 382--><p class="indent" > Click on <span +class="cmti-10x-x-109">Perform design rules check </span>from the top toolbar to check for design rules. The +<span +class="cmti-10x-x-109">DRC Control </span>window opens up. Click on <span +class="cmti-10x-x-109">Start DRC</span>. There are no errors under the <span +class="cmtt-10x-x-109">Error</span> +<span +class="cmtt-10x-x-109">messages </span>tab. Click on <span +class="cmti-10x-x-109">OK </span>to close DRC control window. Fig. <a +href="#x1-5302622">6.22<!--tex4ht:ref: drc --></a> shows the sequence of +operations. <a + id="dx1-53025"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-5302622"></a> + + +<!--l. 390--><p class="noindent" ><img +src="figures/drc.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.22: </span><span +class="content">Performing design rules check: 1. Click on <span +class="cmti-10x-x-109">Start DRC</span>, 2. Click on <span +class="cmti-10x-x-109">Ok</span></span></div><!--tex4ht:label?: x1-5302622 --> + +<!--l. 394--><p class="indent" > </div><hr class="endfigure"> +<!--l. 395--><p class="indent" > Click on <span +class="cmti-10x-x-109">Save board </span>on the top toolbar. +<!--l. 397--><p class="indent" > To generate Gerber files, click on <span +class="cmti-10x-x-109">File </span>from the top menu bar. Click on <span +class="cmti-10x-x-109">Plot</span>. This is shown +in Fig. <a +href="#x1-5302823">6.23<!--tex4ht:ref: plot --></a>. The plot window opens up. One can choose which layers to plot by +selecting/deselecting them from the <span +class="cmtt-10x-x-109">Layers </span>pane on the left side. One can also choose the +format used to plot them. Choose <span +class="cmti-10x-x-109">Gerber</span>. The output directory of the plots created +can also be chosen. By default, it is the project directory. Some more options can +be chosen in this window. Click on <span +class="cmti-10x-x-109">Plot</span>. The message window shows the location +in which the Gerber files are created. Click on <span +class="cmti-10x-x-109">Close</span>. This is shown in Fig. <a +href="#x1-5302924">6.24<!--tex4ht:ref: plot2 --></a>. +<a + id="dx1-53027"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-5302823"></a> + + +<!--l. 410--><p class="noindent" ><img +src="figures/plot.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.23: </span><span +class="content">Choosing <span +class="cmti-10x-x-109">Plot </span>from the <span +class="cmti-10x-x-109">File </span>menu</span></div><!--tex4ht:label?: x1-5302823 --> + +<!--l. 413--><p class="indent" > </div><hr class="endfigure"> +<!--l. 414--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-5302924"></a> + + +<!--l. 416--><p class="noindent" ><img +src="figures/plot2.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.24: </span><span +class="content">Creating Gerber files: 1. Choose <span +class="cmti-10x-x-109">Gerber </span>as the plot format, 2. Click on +<span +class="cmti-10x-x-109">Plot</span>. Message window shows location in which Gerber files are created, 3. Click on <span +class="cmti-10x-x-109">Close</span></span></div><!--tex4ht:label?: x1-5302924 --> + +<!--l. 421--><p class="indent" > </div><hr class="endfigure"> +<!--l. 422--><p class="indent" > The PCB design of RC circuit is now complete. To know more about Pcbnew, refer to +<span class="cite"> [<a +href="#Xkicad">15</a>]</span> or <span class="cite"> [<a +href="#Xkicad2">16</a>]</span>. + + <h2 class="chapterHead"><span class="titlemark">Chapter 7</span><br /><a + id="x1-540007"></a>Model Editor</h2> +<!--l. 4--><p class="noindent" >Spice based simulators include a feature which allows accurate modeling of semiconductor +devices such as diodes, transistors etc. eSim Model Editor provides a facility to define a new +model for devices such as <span +class="cmti-10x-x-109">diodes, MOSFET, BJT, JFET, IGBT, Magnetic core </span>etc. Model +Editor in eSim lets the user enter the values of parameters depending on the type of +device for which a model is required. The parameter values can be obtained from the +data-sheet of the device. A newly created model can be exported to the model library +and one can import it for different projects, whenever required. Model Editor also +provides a facility to edit existing models. The GUI of the model editor is as shown in +Fig. <a +href="#x1-540011">7.1<!--tex4ht:ref: modeleditor --></a> +<!--l. 15--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-540011"></a> + + +<!--l. 17--><p class="noindent" ><img +src="figures/modeleditor_new.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.1: </span><span +class="content">Model Editor</span></div><!--tex4ht:label?: x1-540011 --> + +<!--l. 20--><p class="indent" > </div><hr class="endfigure"> + <h3 class="sectionHead"><span class="titlemark">7.1 </span> <a + id="x1-550007.1"></a>Creating New Model Library </h3> +<!--l. 24--><p class="noindent" >eSim lets us create new model libraries based on the template model libraries. On selecting +<span +class="cmtt-10x-x-109">New </span>button the window is popped as shown in Fig. <a +href="#x1-550012">7.2<!--tex4ht:ref: modeleditor_new --></a>. The name has to be unique otherwise +the error message appears on the window. +<!--l. 27--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-550012"></a> + + +<!--l. 29--><p class="noindent" ><img +src="figures/modeleditor.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.2: </span><span +class="content">Creating New Model Library</span></div><!--tex4ht:label?: x1-550012 --> + +<!--l. 32--><p class="indent" > </div><hr class="endfigure"> +<!--l. 33--><p class="indent" > After the OK button is pressed the type of model library to be created is chosen by +selecting one of the types on the left hand side i.e. <span +class="cmtt-10x-x-109">Diode, BJT, MOS, JFET, IGBT,</span> +<span +class="cmtt-10x-x-109">Magnetic Core</span>. The template model library opens up in a tabular form as shown in Fig. <a +href="#x1-550023">7.3<!--tex4ht:ref: modelnew --></a> +<hr class="figure"><div class="figure" +> + +<a + id="x1-550023"></a> + + +<!--l. 36--><p class="noindent" ><img +src="figures/modelnew.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.3: </span><span +class="content">Choosing the Template Model Library </span></div><!--tex4ht:label?: x1-550023 --> + +<!--l. 39--><p class="indent" > </div><hr class="endfigure"> + +<!--l. 43--><p class="indent" > New parameters can be added or current parameters can be removed using <span +class="cmtt-10x-x-109">ADD</span> +and <span +class="cmtt-10x-x-109">REMOVE </span>buttons. Also the values of parameters can be changed in the table. +Adding and removing the parameters in library files is shown in the Fig. <a +href="#x1-550034">7.4<!--tex4ht:ref: modeladd --></a> and +Fig. <a +href="#x1-550045">7.5<!--tex4ht:ref: modelremove --></a> +<!--l. 45--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-550034"></a> + + +<!--l. 47--><p class="noindent" ><img +src="figures/modeladd.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.4: </span><span +class="content">Adding the Parameter in a Library</span></div><!--tex4ht:label?: x1-550034 --> + +<!--l. 50--><p class="indent" > </div><hr class="endfigure"> +<!--l. 52--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-550045"></a> + + +<!--l. 54--><p class="noindent" ><img +src="figures/modelremove.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.5: </span><span +class="content">Removing a Parameter from a Library </span></div><!--tex4ht:label?: x1-550045 --> + +<!--l. 57--><p class="indent" > </div><hr class="endfigure"> +<!--l. 59--><p class="indent" > After the editing of the model library is done, the file can be saved by selecting the <span +class="cmtt-10x-x-109">SAVE</span> +button. These libraries are saved in the <span +class="cmti-10x-x-109">User Libraries </span>folder under <span +class="cmti-10x-x-109">deviceModelLibrary</span> +repository. + <h3 class="sectionHead"><span class="titlemark">7.2 </span> <a + id="x1-560007.2"></a>Editing Current Model Library</h3> +<!--l. 62--><p class="noindent" >The existing model library can be modified using <span +class="cmtt-10x-x-109">EDIT </span>option. On clicking the <span +class="cmtt-10x-x-109">EDIT </span>button +the file dialog opens where all the library files are saved as shown in Fig. <a +href="#x1-560016">7.6<!--tex4ht:ref: modeledit --></a>. You can select +the library you want to edit. Once you are done with the editing, click on <span +class="cmtt-10x-x-109">SAVE</span> +button. +<!--l. 65--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-560016"></a> + + +<!--l. 67--><p class="noindent" ><img +src="figures/modeledit.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.6: </span><span +class="content">Editing Existing Model Library</span></div><!--tex4ht:label?: x1-560016 --> + +<!--l. 70--><p class="indent" > </div><hr class="endfigure"> + <h3 class="sectionHead"><span class="titlemark">7.3 </span> <a + id="x1-570007.3"></a>Uploading external .lib file to eSim repository</h3> +<!--l. 73--><p class="noindent" >eSim directly cannot use the external .lib file. It has to be uploaded to eSim repository before +using it in a circuit. eSim provides the facility to upload library files. They are then converted +into xml format, which can be easily modified from the eSim interface. On clicking <span +class="cmtt-10x-x-109">UPLOAD</span> +button the library can be uploaded from any location. The model library will be +saved with the name you have provided, in the <span +class="cmti-10x-x-109">User Libraries </span>folder of repository +<span +class="cmti-10x-x-109">deviceModelLibrary</span>. + + <h2 class="chapterHead"><span class="titlemark">Chapter 8</span><br /><a + id="x1-580008"></a>SubCircuit Builder</h2> Subcircuit is a way to implement hierarchical modeling. +Once a subcircuit for a compo- nent is created, it can be used in other circuits. +eSim provides an easy way to create a subcircuit. The following Fig. <a +href="#x1-580011">8.1<!--tex4ht:ref: subcircuit_mainwin --></a> shows +the window that is opened when the SubCircuit tool is chosen from the toolbar. +<hr class="figure"><div class="figure" +> + +<a + id="x1-580011"></a> + + +<!--l. 8--><p class="noindent" ><img +src="figures/subcirciut_window.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.1: </span><span +class="content">Subcircuit Window</span></div><!--tex4ht:label?: x1-580011 --> + +<!--l. 11--><p class="noindent" ></div><hr class="endfigure"> + + <h3 class="sectionHead"><span class="titlemark">8.1 </span> <a + id="x1-590008.1"></a>Creating a SubCircuit</h3> +<!--l. 32--><p class="noindent" >The steps to create subcircuit are as follows. + <ul class="itemize1"> + <li class="itemize">After opening the Subcircuit tool, click on <span +class="cmtt-10x-x-109">New Subcircuit Schematic </span>button. + It will ask the name of the subcircuit. Enter the name of subcircuit (without any + spaces) and click <span +class="cmtt-10x-x-109">OK </span>as shown in Fig. <a +href="#x1-590012">8.2<!--tex4ht:ref: newsubcktschematic --></a>. + <!--l. 39--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-590012"></a> <img +src="figures/newsubcktschematic.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.2: </span><span +class="content">New Sub circuit Window</span></div><!--tex4ht:label?: x1-590012 --> + <!--l. 44--><p class="noindent" ></div><hr class="endfigure"> + </li> + <li class="itemize">After clicking <span +class="cmtt-10x-x-109">OK </span>button it will open KiCad schematic. Draw your circuit + which will be later used as a subcircuit. e.g the Fig. <a +href="#x1-590023">8.3<!--tex4ht:ref: createsubcktsch --></a> shows the half adder + circuit. + <!--l. 49--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-590023"></a> <img +src="figures/createsubcktsch.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.3: </span><span +class="content">New Sub circuit Window</span></div><!--tex4ht:label?: x1-590023 --> + <!--l. 54--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Once you complete the circuit, assign port to the node of your circuit which will be + used to connect with the main circuit. The circuit will look like Fig. <a +href="#x1-590034">8.4<!--tex4ht:ref: halfadder --></a> after + adding PORT to it. The PORT symbol can be found in Eeschema as shown in + Fig. <a +href="#x1-590045">8.5<!--tex4ht:ref: port --></a>. + <!--l. 61--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-590034"></a> <img +src="figures/ha_sub.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.4: </span><span +class="content">Half-Adder Subcircuit </span></div><!--tex4ht:label?: x1-590034 --> + <!--l. 66--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 69--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-590045"></a> <img +src="figures/port_lib.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.5: </span><span +class="content">Selection of PORT component</span></div><!--tex4ht:label?: x1-590045 --> + <!--l. 74--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Next step is to save the schematic and generate KiCad netlist as explained in Chapter + 5. + </li> + <li class="itemize">To use this as a subcircuit, create a block in KiCad Eeschema by following steps given + below: + <dl class="enumerate"><dt class="enumerate"> + 1. </dt><dd +class="enumerate">Go to library browser of Eeschema. + </dd><dt class="enumerate"> + 2. </dt><dd +class="enumerate">Select the working library as eSim_Subckt as shown in Fig. <a +href="#x1-590076">8.6<!--tex4ht:ref: esimsubckt --></a> <hr class="figure"><div class="figure" +><a + id="x1-590076"></a> <img +src="figures/esim-subckt.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.6: </span><span +class="content">Selecting Working Library</span></div><!--tex4ht:label?: x1-590076 --> + <!--l. 90--><p class="noindent" ></div><hr class="endfigure"> + + </dd><dt class="enumerate"> + 3. </dt><dd +class="enumerate">Click on create a new component with reference X as shown in Fig. <a +href="#x1-590097">8.7<!--tex4ht:ref: subcktnewcomp --></a> <hr class="figure"><div class="figure" +><a + id="x1-590097"></a> + <img +src="figures/subcktnewcomp.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.7: </span><span +class="content">Creating New Component</span></div><!--tex4ht:label?: x1-590097 --> + <!--l. 99--><p class="noindent" ></div><hr class="endfigure"> + </dd><dt class="enumerate"> + 4. </dt><dd +class="enumerate">Start drawing the subcircuit block. Update and save it as shown in Fig. <a +href="#x1-590118">8.8<!--tex4ht:ref: block --></a>. + <!--l. 104--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-590118"></a> <img +src="figures/halfadderblock.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.8: </span><span +class="content">Half-Adder Subcircuit Block</span></div><!--tex4ht:label?: x1-590118 --> + <!--l. 109--><p class="noindent" ></div><hr class="endfigure"> + </dd></dl> + + </li> + <li class="itemize">Close the Eeschema window and click on Convert KiCad to Ngspice button in subcircuit + builder tool. This will convert the KiCad spice netlist to Ngspice netlist. And it will + save your subcircuit into eSim repository, which you can add in your main + circuit. + </li></ul> +<!--l. 120--><p class="noindent" > + <h3 class="sectionHead"><span class="titlemark">8.2 </span> <a + id="x1-600008.2"></a>Edit a Subcircuit</h3> +<!--l. 121--><p class="noindent" >The steps to edit a subcircuit are as follows. + <ul class="itemize1"> + <li class="itemize">After opening the Subcircuit tool, click on <span +class="cmtt-10x-x-109">Edit Subcircuit Schematic </span>button. + It will open a dialog box where you can select any subcircuit for editing. + </li> + <li class="itemize">After selecting the subcircuit it will open it in KiCad Eeschema, where you can + edit the subcircuit. + </li> + <li class="itemize">Next step is to save the schematic and generate KiCad netlist. + </li> + <li class="itemize">If you have edited the number of ports then you have to change the block in KiCad + Eeschema accordingly. + </li> + <li class="itemize">Close the Eeschema window and click on <span +class="cmtt-10x-x-109">Convert KiCad to Ngspice </span>button in + subcircuit builder tool to convert the edited subcircuit KiCad netlist into Ngspice + netlist. + </li></ul> + + <h2 class="chapterHead"><span class="titlemark">Chapter 9</span><br /><a + id="x1-610009"></a>Solved Examples</h2> + <h3 class="sectionHead"><span class="titlemark">9.1 </span> <a + id="x1-620009.1"></a>Solved Examples</h3> +<!--l. 8--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">9.1.1 </span> <a + id="x1-630009.1.1"></a>Basic RC Circuit</h4> +<!--l. 9--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-640009.1.1"></a>Problem Statement:</h5> +<!--l. 9--><p class="noindent" >Plot the Input and Output Waveform of an RC circuit whose input voltage (Vs) is 50Hz, +3V peak to peak. The values of Resistor (R) and Capacitor(C) are 1<span +class="cmmi-10x-x-109">k </span>and 1<span +class="cmmi-10x-x-109">uf</span> +respectively. + <h5 class="subsubsectionHead"><a + id="x1-650009.1.1"></a>Solution:</h5> + <ul class="itemize1"> + <li class="itemize">Creating a Project: The new project is created by clicking the <span +class="cmtt-10x-x-109">New </span>icon on the + menubar. The name of the project is given in the pop up window as shown in + Fig. <a +href="#x1-650011">9.1<!--tex4ht:ref: rc1 --></a>. <hr class="figure"><div class="figure" +><a + id="x1-650011"></a> <img +src="figures/rc1.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.1: </span><span +class="content">Creating New Project</span></div><!--tex4ht:label?: x1-650011 --> + <!--l. 20--><p class="noindent" ></div><hr class="endfigure"> + </li> + <li class="itemize">Creating the Schematic: To create the schematic, click the very first icon of the left + toolbar as shown in the Fig. <a +href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema. + <!--l. 25--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650022"></a> <img +src="figures/rc2.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.2: </span><span +class="content">Open Schematic Editor</span></div><!--tex4ht:label?: x1-650022 --> + <!--l. 31--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 33--><p class="noindent" >To create a schematic in KiCad, we need to place the required components. Fig. <a +href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> + shows the icon on the right toolbar which opens the component library. + <!--l. 35--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650033"></a> <img +src="figures/rc_component.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.3: </span><span +class="content">Place Component Icon</span></div><!--tex4ht:label?: x1-650033 --> + <!--l. 41--><p class="noindent" ></div><hr class="endfigure"> + + <!--l. 45--><p class="noindent" >After all the required components of the simple RC circuit are placed, wiring is done + using the <span +class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig. <a +href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a> + <!--l. 47--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650044"></a> <img +src="figures/rc_wire.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.4: </span><span +class="content">Place Wire Icon</span></div><!--tex4ht:label?: x1-650044 --> + <!--l. 53--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 55--><p class="noindent" >Next step is <span +class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig. <a +href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span +class="cmtt-10x-x-109">ERC</span>. + <!--l. 57--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650055"></a> <img +src="figures/erc1.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.5: </span><span +class="content">Electric Rules Check Icon</span></div><!--tex4ht:label?: x1-650055 --> + <!--l. 63--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 65--><p class="noindent" >Fig. <a +href="#x1-650066">9.6<!--tex4ht:ref: rc_complete1 --></a> shows the RC circuit after connecting the components by wire. + <!--l. 67--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650066"></a> <img +src="figures/rc_complete1.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.6: </span><span +class="content">RC circuit</span></div><!--tex4ht:label?: x1-650066 --> + <!--l. 72--><p class="noindent" ></div><hr class="endfigure"> + + <!--l. 76--><p class="noindent" >After clicking the <span +class="cmtt-10x-x-109">ERC </span>icon a window opens up. Click the <span +class="cmtt-10x-x-109">Run </span>button to run rules check. + The errors are listed in as shown in Fig. <a +href="#x1-65007r1">9.7a<!--tex4ht:ref: erc2 --></a>. This error is handled by adding <span +class="cmtt-10x-x-109">Power</span> + <span +class="cmtt-10x-x-109">Flag </span>as shown in Fig. <a +href="#x1-65008r2">9.7b<!--tex4ht:ref: rc_pwr --></a>. + <!--l. 78--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650097"></a> <a + id="x1-65007r1"></a> <img +src="figures/erc2.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">ERC</span> + <span +class="cmr-9">Run</span> <a + id="x1-65008r2"></a> <img +src="figures/rc_pwr.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Power</span> + <span +class="cmr-9">Flag</span> +<br /> <div class="caption" +><span class="id">Figure 9.7: </span><span +class="content">ERC check and POWER FLAG</span></div><!--tex4ht:label?: x1-650097 --> + <!--l. 87--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 89--><p class="noindent" >After adding the <span +class="cmtt-10x-x-109">Power Flag </span>the completed RC circuit is shown in Fig. <a +href="#x1-65010r1">9.8a<!--tex4ht:ref: rc_schematic --></a> and the + netlist is generated as shown in Fig. <a +href="#x1-65011r2">9.8b<!--tex4ht:ref: rc_netlist --></a>. + <!--l. 92--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650128"></a> <a + id="x1-65010r1"></a> <img +src="figures/rc_schematic.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">Schematic</span> + <span +class="cmr-9">of RC</span> + <span +class="cmr-9">circuit</span> <a + id="x1-65011r2"></a> <img +src="figures/rc_netlistgeneration.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Generating</span> + <span +class="cmr-9">KiCad</span> + <span +class="cmr-9">Netlist</span> + <span +class="cmr-9">of RC</span> + <span +class="cmr-9">circuit</span> +<br /> <div class="caption" +><span class="id">Figure 9.8: </span><span +class="content">RC Schematic and Netlist Generation</span></div><!--tex4ht:label?: x1-650128 --> + <!--l. 101--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Convert KiCad to Ngspice: To convert KiCad netlist of RC circuit to NgSpice + compatible netlist click on KiCad to Ngspice icon as shown in Fig. <a +href="#x1-650139">9.9<!--tex4ht:ref: rcki2ng --></a>. + <!--l. 107--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650139"></a> <img +src="figures/rc_ki2ng.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.9: </span><span +class="content">Convert KiCad to Ngspice Icon</span></div><!--tex4ht:label?: x1-650139 --> + <!--l. 112--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 114--><p class="noindent" >Now you can enter the type of analysis and source details as shown in Fig. <a +href="#x1-65014r1">9.10a<!--tex4ht:ref: rc_analysistab --></a> and + Fig. <a +href="#x1-65015r2">9.10b<!--tex4ht:ref: rc_sourcedetailstab --></a> respectively. + <!--l. 116--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-6501610"></a> <a + id="x1-65014r1"></a> <img +src="figures/rc_analysistab.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">RC</span> + <span +class="cmr-9">Analysis</span> <a + id="x1-65015r2"></a> <img +src="figures/rc_sourcedetailstab.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">RC</span> + <span +class="cmr-9">Source</span> + <span +class="cmr-9">Details</span> +<br /> <div class="caption" +><span class="id">Figure 9.10: </span><span +class="content">RC Analysis and Source Detail</span></div><!--tex4ht:label?: x1-6501610 --> + <!--l. 125--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 126--><p class="noindent" >The other tab will be empty as RC circuit do not use any Ngspice model, device library + and subcircuit. + <!--l. 128--><p class="noindent" >After entering the value, press the convert button. It will convert the netlist into + Ngspice compatible netlist. + + </li> + <li class="itemize">Simulation: To run Ngspice simulation click the simulation icon in the tool bar + as shown in the Fig. <a +href="#x1-6501711">9.11<!--tex4ht:ref: rcplot --></a>. <hr class="figure"><div class="figure" +><a + id="x1-6501711"></a> <img +src="figures/rc_plot.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.11: </span><span +class="content">Simulation Icon</span></div><!--tex4ht:label?: x1-6501711 --> + <!--l. 139--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 141--><p class="noindent" >In eSim, there are two types of plot. First is normal Ngspice plot and second is + interactive python plot as shown in Fig. <a +href="#x1-65018r1">9.12a<!--tex4ht:ref: rc_ngspiceplot --></a> and Fig. <a +href="#x1-65019r2">9.12b<!--tex4ht:ref: rc_pythonplot --></a> respectively. + <!--l. 143--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-6502012"></a> <a + id="x1-65018r1"></a> <img +src="figures/rc_ngspiceplot.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">Ngspice</span> + <span +class="cmr-9">Plot</span> + <span +class="cmr-9">of RC</span> <a + id="x1-65019r2"></a> <img +src="figures/rc_pythonplot.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Python</span> + <span +class="cmr-9">Plot</span> + <span +class="cmr-9">of RC</span> +<br /> <div class="caption" +><span class="id">Figure 9.12: </span><span +class="content">Ngspice and Interactive Python Plotting</span></div><!--tex4ht:label?: x1-6502012 --> + <!--l. 152--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 154--><p class="noindent" >In the interactive python plot you can select any node or branch to plot voltage or + current across it. Also it has the facility to plot basic functions across the node like + addition, substraction, multiplication, division and v/s. + </li></ul> + +<!--l. 160--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">9.1.2 </span> <a + id="x1-660009.1.2"></a>Half Wave Rectifier</h4> +<!--l. 162--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-670009.1.2"></a>Problem Statement:</h5> +<!--l. 162--><p class="noindent" >Plot the Input and Output Waveform of Half Wave Rectifier circuit where the input voltage +(Vs) is 50Hz, 2V peak to peak. The value for Resistor (R) is 1k. +<!--l. 164--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-680009.1.2"></a>Solution:</h5> +<!--l. 165--><p class="noindent" >The new project is created by clicking the <span +class="cmtt-10x-x-109">New </span>icon on the menubar. The name of the project +is given in the window shown in Fig. <a +href="#x1-650011">9.1<!--tex4ht:ref: rc1 --></a>. + <ul class="itemize1"> + <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left + toolbar as shown in the Fig. <a +href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br +class="newline" /> + <!--l. 171--><p class="noindent" >After the KiCad window is opened, to create a schematic we need to place the + required components. Fig. <a +href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens + the component library.<br +class="newline" /> + <!--l. 174--><p class="noindent" >After all the required components of the simple Half Wave rectifier circuits are + placed, wiring is done using the <span +class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig. <a +href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a><br +class="newline" /> + <!--l. 176--><p class="noindent" >Next step is <span +class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig. <a +href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span +class="cmtt-10x-x-109">ERC</span>. After + completing all the above steps the final Half Wave Rectifier schematic will look + like Fig. <a +href="#x1-6800113">9.13<!--tex4ht:ref: hwr_schematic --></a>.<br +class="newline" /> + <!--l. 178--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-6800113"></a> <img +src="figures/hwr_schematic.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.13: </span><span +class="content">Schematic of Half Wave Rectifier circuit</span></div><!--tex4ht:label?: x1-6800113 --> + <!--l. 183--><p class="noindent" ></div><hr class="endfigure"> + + <!--l. 187--><p class="noindent" >KiCad netlist is generated as shown in the Fig. <a +href="#x1-6800214">9.14<!--tex4ht:ref: hwr_netlistgeneration --></a> <br +class="newline" /> + <!--l. 189--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-6800214"></a> <img +src="figures/hwr_netlistgeneration.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.14: </span><span +class="content">Half Wave Rectifier circuit Netlist Generation</span></div><!--tex4ht:label?: x1-6800214 --> + <!--l. 194--><p class="noindent" ></div><hr class="endfigure"> + </li> + <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist, click on the <span +class="cmtt-10x-x-109">KiCad-Ngspice</span> + <span +class="cmtt-10x-x-109">converter </span>button. This will open converter window where you can enter details of + Analysis, Source values and Device library. + <!--l. 198--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-6800615"></a> <a + id="x1-68003r1"></a> <img +src="figures/hwr_analysistab.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Wave</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Analysis</span> <a + id="x1-68004r2"></a> <img +src="figures/hwr_sourcedetailstab.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Wave</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Source</span> + <span +class="cmr-9">Details</span> <a + id="x1-68005r3"></a> <img +src="figures/hwr_devicemodelingtab.png" alt="PIC" +> + <span +class="cmr-9">(c)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Wave</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Device</span> + <span +class="cmr-9">Modeling</span> +<br /> <div class="caption" +><span class="id">Figure 9.15: </span><span +class="content">Analysis, Source and Device Tab</span></div><!--tex4ht:label?: x1-6800615 --> + <!--l. 210--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 212--><p class="noindent" >Under device library you can add the library for diode used in the circuit. If you do not + add any library it will take default Ngspice model. + </li> + <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run + simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure" +><a + id="x1-6800916"></a> <a + id="x1-68007r1"></a> <img +src="figures/hwr_ngspiceplot.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Ngspice</span> +<span +class="cmr-9">Plot</span> +<span +class="cmr-9">of</span> +<span +class="cmr-9">Half</span> +<span +class="cmr-9">Wave</span> +<span +class="cmr-9">Rectifier</span> <a + id="x1-68008r2"></a> <img +src="figures/hwr_pythonplot.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Python</span> + <span +class="cmr-9">Plot</span> + <span +class="cmr-9">of</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Wave</span> + <span +class="cmr-9">Rectifier</span> +<br /> <div class="caption" +><span class="id">Figure 9.16: </span><span +class="content">Half Wave Rectifier Simulation Output</span></div><!--tex4ht:label?: x1-6800916 --> + <!--l. 225--><p class="noindent" ></div><hr class="endfigure"> + </li></ul> + +<!--l. 232--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">9.1.3 </span> <a + id="x1-690009.1.3"></a>Precision Rectifier</h4> +<!--l. 233--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-700009.1.3"></a>Problem Statement:</h5> +<!--l. 233--><p class="noindent" >Plot the input and output waveform of the Precision Rectifier circuit where input voltage +(Vs) is 50<span +class="cmmi-10x-x-109">Hz </span>, 3<span +class="cmmi-10x-x-109">V </span>peak to peak. +<!--l. 235--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-710009.1.3"></a>Solution:</h5> +<!--l. 236--><p class="noindent" >The new project is created by clicking the <span +class="cmtt-10x-x-109">New </span>icon on the menubar. The name of the project +is given as shown in the Fig. <a +href="#x1-650011">9.1<!--tex4ht:ref: rc1 --></a>. + <ul class="itemize1"> + <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left + toolbar as shown in the Fig. <a +href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br +class="newline" />After the KiCad window is opened, to create a schematic we need to place the + required components. Fig. <a +href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens + the component library.<br +class="newline" />After all the required components of the precision rectifier circuit are placed, + wiring is done using the <span +class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig. <a +href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a>.<br +class="newline" />Next step is <span +class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig. <a +href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span +class="cmtt-10x-x-109">ERC</span>. The + Fig. <a +href="#x1-7100117">9.17<!--tex4ht:ref: pr_schematic --></a> shows the complete Precision Rectifier schematic after removing the + errors. + <!--l. 246--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-7100117"></a> <img +src="figures/pr_schematic.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.17: </span><span +class="content">Schematic of Precision Rectifier circuit</span></div><!--tex4ht:label?: x1-7100117 --> + <!--l. 251--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 253--><p class="noindent" >The KiCad netlist is generated as shown in Fig. <a +href="#x1-7100218">9.18<!--tex4ht:ref: pr_netlistgeneration --></a>.<br +class="newline" /> + <!--l. 255--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-7100218"></a> <img +src="figures/pr_netlistgeneration.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.18: </span><span +class="content">Precision Rectifier circuit Netlist Generation</span></div><!--tex4ht:label?: x1-7100218 --> + <!--l. 260--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist, click on KiCad-Ngspice + converter button.<br +class="newline" /> + <!--l. 266--><p class="noindent" >This will open converter window where you can enter details of Analysis, Source values, + Device library and Subcircuit. + <!--l. 268--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-7100719"></a> <a + id="x1-71003r1"></a> <img +src="figures/pr_analysistab.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">Precision</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Analysis</span> <a + id="x1-71004r2"></a> <img +src="figures/pr_sourcedetailstab.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Precision</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Source</span> + <span +class="cmr-9">Details</span> +<a + id="x1-71005r3"></a> +<!--l. 278--><p class="noindent" > <img +src="figures/pr_devicemodelingtab.png" alt="PIC" +> +<span +class="cmr-9">(c)</span> +<span +class="cmr-9">Precision</span> +<span +class="cmr-9">Rectifier</span> +<span +class="cmr-9">Device</span> +<span +class="cmr-9">Modeling</span> <a + id="x1-71006r4"></a> <img +src="figures/pr_subcircuitstab.png" alt="PIC" +> + <span +class="cmr-9">(d)</span> + <span +class="cmr-9">Precision</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Subcircuit</span> +<br /> <div class="caption" +><span class="id">Figure 9.19: </span><span +class="content">Analysis, Source, Device library and Subcircuit tab</span></div><!--tex4ht:label?: x1-7100719 --> + <!--l. 283--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 285--><p class="noindent" >Under device library you can add the library for the diode used in the circuit. If you do + not add any library it will take default Ngspice model for diode.<br +class="newline" /> + <!--l. 288--><p class="noindent" >Under subcircuit tab you have to add the subciruit used in your circuit. If you forget to + add subcircuit it will throw an error. + + </li> + <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run the + simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure" +><a + id="x1-7101020"></a> <a + id="x1-71008r1"></a> <img +src="figures/pr_ngspiceplot.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Ngspice</span> +<span +class="cmr-9">Plot</span> +<span +class="cmr-9">of</span> +<span +class="cmr-9">Precision</span> +<span +class="cmr-9">Rectifier</span> <a + id="x1-71009r2"></a> <img +src="figures/pr_pythonplot.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Python</span> + <span +class="cmr-9">Plot</span> + <span +class="cmr-9">of</span> + <span +class="cmr-9">Precision</span> + <span +class="cmr-9">Rectifier</span> +<br /> <div class="caption" +><span class="id">Figure 9.20: </span><span +class="content">Precision Rectifier Simulation Output</span></div><!--tex4ht:label?: x1-7101020 --> + <!--l. 302--><p class="noindent" ></div><hr class="endfigure"> + </li></ul> + +<!--l. 309--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">9.1.4 </span> <a + id="x1-720009.1.4"></a>Inverting Amplifier</h4> +<!--l. 310--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-730009.1.4"></a>Problem Statement:</h5> +<!--l. 311--><p class="noindent" >Plot the Input and Output Waveform of Inverting Amplifier circuit where the input voltage +(Vs) is 50<span +class="cmmi-10x-x-109">Hz</span>, 2<span +class="cmmi-10x-x-109">V </span>peak to peak and gain is 2. + <h5 class="subsubsectionHead"><a + id="x1-740009.1.4"></a>Solution:</h5> + <ul class="itemize1"> + <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left + toolbar as shown in the Fig. <a +href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br +class="newline" />After the KiCad window is opened, to create a schematic we need to place the + required components. Fig. <a +href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens + the component library.<br +class="newline" />After all the required components of the inverting amplifier circuit are placed, + wiring is done using the <span +class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig. <a +href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a>.<br +class="newline" />Next step is <span +class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig. <a +href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span +class="cmtt-10x-x-109">ERC</span>. + <!--l. 321--><p class="noindent" >The Fig. <a +href="#x1-7400121">9.21<!--tex4ht:ref: ia_schematic --></a> shows the complete Precision Rectifier schematic after removing + the errors. + <!--l. 323--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-7400121"></a> <img +src="figures/ia_schematic.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.21: </span><span +class="content">Schematic of Inverting Amplifier circuit</span></div><!--tex4ht:label?: x1-7400121 --> + <!--l. 328--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 330--><p class="noindent" >The KiCad netlist is generated as shown in Fig. <a +href="#x1-7400222">9.22<!--tex4ht:ref: ia_netlistgeneration --></a>.<br +class="newline" /><hr class="figure"><div class="figure" +><a + id="x1-7400222"></a> <img +src="figures/ia_netlistgeneration.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.22: </span><span +class="content">Inverting Amplifier circuit Netlist Generation</span></div><!--tex4ht:label?: x1-7400222 --> + <!--l. 336--><p class="noindent" ></div><hr class="endfigure"> + </li> + <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist, click on KiCad-Ngspice + converter button.<br +class="newline" /> + <!--l. 342--><p class="noindent" >This will open converter window where you can enter details of Analysis, Source values, + Device library and Subcircuit. + + <!--l. 344--><p class="noindent" >Subcircuit of Op-Amp is shown in Fig. <a +href="#x1-74006r4">9.23d<!--tex4ht:ref: ia_sub --></a> <hr class="figure"><div class="figure" +><a + id="x1-7400723"></a> <a + id="x1-74003r1"></a> <img +src="figures/ia_analysistab.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Inverting</span> +<span +class="cmr-9">Amplifier</span> +<span +class="cmr-9">Analysis</span> <a + id="x1-74004r2"></a> <img +src="figures/ia_sourcedetailstab.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Inverting</span> + <span +class="cmr-9">Amplifier</span> + <span +class="cmr-9">Source</span> + <span +class="cmr-9">Details</span> +<a + id="x1-74005r3"></a> +<!--l. 355--><p class="noindent" > <img +src="figures/ia_subcircuitstab.png" alt="PIC" +> +<span +class="cmr-9">(c)</span> +<span +class="cmr-9">Inverting</span> +<span +class="cmr-9">Amplifier</span> +<span +class="cmr-9">Subcircuit</span> <a + id="x1-74006r4"></a> <img +src="figures/ia_sub.png" alt="PIC" +> + <span +class="cmr-9">(d)</span> + <span +class="cmr-9">Sub-Circuit</span> + <span +class="cmr-9">of</span> + <span +class="cmr-9">Op-Amp</span> +<br /> <div class="caption" +><span class="id">Figure 9.23: </span><span +class="content">Analysis, Source, and Subcircuit tab</span></div><!--tex4ht:label?: x1-7400723 --> + <!--l. 360--><p class="noindent" ></div><hr class="endfigure"> + + <!--l. 363--><p class="noindent" >Under subcircuit tab you have to add the subciruit used in your circuit. If you forget to + add subcircuit, it will throw an error.<br +class="newline" /> + </li> + <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run + simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure" +><a + id="x1-7401024"></a> <a + id="x1-74008r1"></a> <img +src="figures/ia_ngspiceplot.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Inverting</span> +<span +class="cmr-9">Amplifier</span> +<span +class="cmr-9">Ngspice</span> +<span +class="cmr-9">Plot</span> +<a + id="x1-74009r2"></a> +<!--l. 374--><p class="noindent" > <img +src="figures/ia_pythonplot.png" alt="PIC" +> +<span +class="cmr-9">(b)</span> +<span +class="cmr-9">Inverting</span> +<span +class="cmr-9">Amplifier</span> +<span +class="cmr-9">Python</span> +<span +class="cmr-9">Plot</span> +<br /> <div class="caption" +><span class="id">Figure 9.24: </span><span +class="content">Inverting Amplifier Simulation Output</span></div><!--tex4ht:label?: x1-7401024 --> + <!--l. 376--><p class="noindent" ></div><hr class="endfigure"> + </li></ul> + +<!--l. 386--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">9.1.5 </span> <a + id="x1-750009.1.5"></a>Half Adder Example</h4> +<!--l. 388--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-760009.1.5"></a>Problem Statement:</h5> +<!--l. 388--><p class="noindent" >Plot the Input and Output Waveform of Half Adder circuit. +<!--l. 390--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-770009.1.5"></a>Solution:</h5> + <ul class="itemize1"> + <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left + toolbar as shown in the Fig. <a +href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br +class="newline" />After the KiCad window is opened, to create a schematic we need to place the + required components. Fig. <a +href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens + the component library.<br +class="newline" />After all the required components of the Half Adder circuit are placed, wiring is + done using the <span +class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig. <a +href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a>.<br +class="newline" />Next step is <span +class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig. <a +href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span +class="cmtt-10x-x-109">ERC</span>. + <!--l. 399--><p class="noindent" >The Fig. <a +href="#x1-7700125">9.25<!--tex4ht:ref: ha_schematic --></a> shows the complete Half Adder schematic after removing the + errors. <hr class="figure"><div class="figure" +><a + id="x1-7700125"></a> <img +src="figures/ha_schematic.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.25: </span><span +class="content">Schematic of Half Adder circuit</span></div><!--tex4ht:label?: x1-7700125 --> + <!--l. 405--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 407--><p class="noindent" >The KiCad netlist is generated as shown in Fig. <a +href="#x1-7700226">9.26<!--tex4ht:ref: ha_netlistgeneration --></a>.<br +class="newline" /><hr class="figure"><div class="figure" +><a + id="x1-7700226"></a> <img +src="figures/ha_netlistgeneration.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.26: </span><span +class="content">Half Adder circuit Netlist Generation</span></div><!--tex4ht:label?: x1-7700226 --> + <!--l. 413--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist click on KiCad-Ngspice + converter button.<br +class="newline" /> + <!--l. 420--><p class="noindent" >This will open converter window where you can enter details of Analysis, Source values, + Ngspice model and Subcircuit. + <!--l. 422--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-7700727"></a> <a + id="x1-77003r1"></a> <img +src="figures/ha_analysistab.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Adder</span> + <span +class="cmr-9">Analysis</span> <a + id="x1-77004r2"></a> <img +src="figures/ha_sourcedetailstab.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Adder</span> + <span +class="cmr-9">Source</span> + <span +class="cmr-9">Details</span> +<a + id="x1-77005r3"></a> +<!--l. 432--><p class="noindent" > <img +src="figures/ha_ngspicemodeltab.png" alt="PIC" +> +<span +class="cmr-9">(c)</span> +<span +class="cmr-9">Half</span> +<span +class="cmr-9">Adder</span> +<span +class="cmr-9">Ngspice</span> +<span +class="cmr-9">Model</span> <a + id="x1-77006r4"></a> <img +src="figures/ha_subcircuitstab.png" alt="PIC" +> + <span +class="cmr-9">(d)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Adder</span> + <span +class="cmr-9">Subcircuit</span> + <span +class="cmr-9">Model</span> +<br /> <div class="caption" +><span class="id">Figure 9.27: </span><span +class="content">Analysis, Source, Ngspice Model and Subcircuit tab</span></div><!--tex4ht:label?: x1-7700727 --> + <!--l. 437--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 439--><p class="noindent" >Subcircuit of Half Adder in Fig. <a +href="#x1-7700828">9.28<!--tex4ht:ref: ha_sub --></a> <hr class="figure"><div class="figure" +><a + id="x1-7700828"></a> <img +src="figures/ha_sub.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.28: </span><span +class="content">Half Adder Subcircuit</span></div><!--tex4ht:label?: x1-7700828 --> + <!--l. 445--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run + simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure" +><a + id="x1-7701129"></a> <a + id="x1-77009r1"></a> <img +src="figures/ha_ngspiceplot.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Half</span> +<span +class="cmr-9">Adder</span> +<span +class="cmr-9">Ngspice</span> +<span +class="cmr-9">Plot</span> <a + id="x1-77010r2"></a> <img +src="figures/ha_pythonplot.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Adder</span> + <span +class="cmr-9">Python</span> + <span +class="cmr-9">Plot</span> +<br /> <div class="caption" +><span class="id">Figure 9.29: </span><span +class="content">Half Adder Simulation Output</span></div><!--tex4ht:label?: x1-7701129 --> + <!--l. 459--><p class="noindent" ></div><hr class="endfigure"> + </li></ul> + + <h2 class="likechapterHead"><a + id="x1-780009.1.5"></a>References</h2><a + id="Q1-1-166"></a> + <div class="thebibliography"> + <p class="bibitem" ><span class="biblabel"> + [1]<span class="bibsp">   </span></span><a + id="Xsedra"></a>A. S. Sedra and K. C. Smith, <span +class="cmti-10x-x-109">Microelectronic Circuits - Theory and</span> + <span +class="cmti-10x-x-109">Applications</span>. Oxford University Press, 2009. + </p> + <p class="bibitem" ><span class="biblabel"> + [2]<span class="bibsp">   </span></span><a + id="Xkmm11-csi"></a>K. M. Moudgalya, “Spoken Tutorial: A Collaborative and Scalable Education + Technology,” <span +class="cmti-10x-x-109">CSI Communications</span>, vol. 35, no. 6, pp. 10–12, September 2011, + available at <a +href="http://spoken-tutorial.org/CSI.pdf" class="url" >http://spoken-tutorial.org/CSI.pdf</a>. + </p> + <p class="bibitem" ><span class="biblabel"> + [3]<span class="bibsp">   </span></span><a + id="Xscilab"></a>(2013, May). [Online]. Available: <a +href="http://www.scilab.org/" class="url" >http://www.scilab.org/</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [4]<span class="bibsp">   </span></span><a + id="XGARUDA"></a>(2013, May). [Online]. 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http://scilab-test.garudaindia.in/cloud" class="url" >http://scilab-test.garudaindia.in/scilab_in/,http://scilab-test.garudaindia.in/cloud</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [5]<span class="bibsp">   </span></span><a + id="XT10KT"></a>D. B. Phatak. (2013, May) Teach 10,000 teacher programme. [Online]. + Available: <a +href="http://www.it.iitb.ac.in/nmeict/MegaWorkshop.do" class="url" >http://www.it.iitb.ac.in/nmeict/MegaWorkshop.do</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [6]<span class="bibsp">   </span></span><a + id="XT10KT-kal"></a>K. Kannan and K. Narayanan, “Ict-enabled scalable workshops for engineering + college teachers in india,” in <span +class="cmti-10x-x-109">Post-Secondary Education and Technology: A Global</span> + <span +class="cmti-10x-x-109">Perspective on Opportunities and Obstacles to Development (International and</span> + <span +class="cmti-10x-x-109">Development Education)</span>, R. Clohey, S. Austin-Li, and J. C. Weldman, Eds. + Palgrave Macmillan, 2012. + + </p> + <p class="bibitem" ><span class="biblabel"> + [7]<span class="bibsp">   </span></span><a + id="XT10KT-kgp"></a>(2013, May) Teach 10,000 teacher programme on analog electronics. [Online]. + Available: <a +href="http://www.nmeict.iitkgp.ernet.in/Analogmain.htm" class="url" >http://www.nmeict.iitkgp.ernet.in/Analogmain.htm</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [8]<span class="bibsp">   </span></span><a + id="Xaakash"></a>(2013, May). [Online]. Available: <a +href="http://www.aakashlabs.org/" class="url" >http://www.aakashlabs.org/</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [9]<span class="bibsp">   </span></span><a + id="Xeda"></a>(2013, May). [Online]. Available: + <a +href="http://en.wikipedia.org/wiki/Electronic_design_automation" class="url" >http://en.wikipedia.org/wiki/Electronic_design_automation</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [10]<span class="bibsp">   </span></span><a + id="Xsynaptic"></a>(2013, May) Synaptic Package Manager Spoken Tutorial. [Online]. Available: + <a +href="http://www.spoken-tutorial.org/list_videos?view=1&foss=Linux&language=English" class="url" >http://www.spoken-tutorial.org/list_videos?view=1&foss=Linux&language=English</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [11]<span class="bibsp">   </span></span><a + id="Xeeschema"></a>(2013, May). [Online]. Available: + <a +href="http://www.kicad-pcb.org/display/KICAD/KiCad+EDA+Software+Suite" class="url" >http://www.kicad-pcb.org/display/KICAD/KiCad+EDA+Software+Suite</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [12]<span class="bibsp">   </span></span><a + id="Xngspice-web"></a>(2013, May). [Online]. Available: <a +href="http://ngspice.sourceforge.net/" class="url" >http://ngspice.sourceforge.net/</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [13]<span class="bibsp">   </span></span><a + id="Xscilab-in"></a>(2013, May). [Online]. Available: <a +href="http://scilab.in/" class="url" >http://scilab.in/</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [14]<span class="bibsp">   </span></span><a + id="Xspice"></a>S. M. Sandler and C. Hymowitz, <span +class="cmti-10x-x-109">SPICE Circuit Handbook</span>. New York: + McGraw-Hill Professional, 2006. + </p> + <p class="bibitem" ><span class="biblabel"> + [15]<span class="bibsp">   </span></span><a + id="Xkicad"></a>J.-P. Charras and F. Tappero. (2013, May). [Online]. Available: + <a +href="http://www.kicad-pcb.org/display/KICAD/KiCad+Documentation" class="url" >http://www.kicad-pcb.org/display/KICAD/KiCad+Documentation</a> + + </p> + <p class="bibitem" ><span class="biblabel"> + [16]<span class="bibsp">   </span></span><a + id="Xkicad2"></a>D. Jahshan and P. Hutchinson. (2013, May). [Online]. Available: + <a +href="http://bazaar.launchpad.net/~kicad-developers/kicad/doc/files/head:/doc/tutorials/" class="url" >http://bazaar.launchpad.net/<span +class="cmsy-8">∼</span>kicad-developers/kicad/doc/files/head:/doc/tutorials/</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [17]<span class="bibsp">   </span></span><a + id="Xngspice"></a>P. Nenzi and H. Vogt. (2013) Ngspice users manual version 25plus. [Online]. + Available: <a +href="http://ngspice.sourceforge.net/docs/ngspice-manual.pdf" class="url" >http://ngspice.sourceforge.net/docs/ngspice-manual.pdf</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [18]<span class="bibsp">   </span></span><a + id="Xkmm11-TUGboat"></a>K. M. Moudgalya, “<span class="LATEX">L<span class="A">A</span><span class="TEX">T<span +class="E">E</span>X</span></span> Training through Spoken Tutorials,” <span +class="cmti-10x-x-109">TUGboat</span>, + vol. 32, no. 3, pp. 251–257, 2011. + </p> + <p class="bibitem" ><span class="biblabel"> + [19]<span class="bibsp">   </span></span><a + id="Xst"></a>(2013, May). [Online]. Available: <a +href="http://www.spoken-tutorial.org/" class="url" >http://www.spoken-tutorial.org/</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [20]<span class="bibsp">   </span></span><a + id="Xoscad"></a>(2013, May). [Online]. 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font-family: sans-serif; + margin: 0px; + padding: 0px; + background-color: #efefef; +} + +h1{ + font-weight: bold; + font-size: 22pt; + color: #eeeeee; + padding: 10px; + background-color: #165982; + border: 4px outset #0E324B; +} + +p{ + margin: 0px 10px 0px 10px; +} + +pre{ + margin: 0px 10px 0px 10px; + font-family: monospaced; + font-size: 10pt; +} +#license{ + font-size:8pt; +} + +</style> +<head> + +<body> +<h1>About eSim</h1> +<center><img src="../../images/logo.png" alt="eSim logo" height="100" width="100"></center> +<br/> +<p> +<b>eSim</b> is an open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using open source software such as KiCad (<a href=http://www.kicad-pcb.org>http://www.kicad-pcb.org</a>), Ngspice (<a href=http://ngspice.sourceforge.net>http://ngspice.sourceforge.net</a>) and GHDL (<a href=http://ghdl.free.fr>http://ghdl.free.fr</a>). eSim source is released under <b>GNU General Public License.</b> +</p> +<br/> +<p> +This tool is developed by the <b>FOSSEE team at IIT Bombay</b>. To know more about eSim, please visit: <a href=http://esim.fossee.in>http://esim.fossee.in</a>. + </p> +<br/> +<p> +To discuss more about eSim please visits at <a href=http://forums.fossee.in>http://forums.fossee.in</a> +</p> +<br /> +</body> + +</html> diff --git a/library/deviceModelLibrary/Diode/D.lib b/library/deviceModelLibrary/Diode/D.lib new file mode 100644 index 00000000..8a7fb4da --- /dev/null +++ b/library/deviceModelLibrary/Diode/D.lib @@ -0,0 +1,2 @@ +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/deviceModelLibrary/Diode/D.xml b/library/deviceModelLibrary/Diode/D.xml new file mode 100644 index 00000000..8b6b14c8 --- /dev/null +++ b/library/deviceModelLibrary/Diode/D.xml @@ -0,0 +1,15 @@ +<library> +<model_name>D</model_name> +<ref_model>1N4148</ref_model> +<param> + <Is>2.495E-09</Is> + <Rs>4.755E-01</Rs> + <N>1.679E+00</N> + <tt>3.030E-09</tt> + <Cjo>1.700E-12</Cjo> + <M>1.959E-01</M> + <Vj>1</Vj> + <Bv>1.000E+02</Bv> + <Ibv>1.000E-04</Ibv> +</param> +</library> diff --git a/library/deviceModelLibrary/Diode/LED.lib b/library/deviceModelLibrary/Diode/LED.lib new file mode 100644 index 00000000..000831b2 --- /dev/null +++ b/library/deviceModelLibrary/Diode/LED.lib @@ -0,0 +1,2 @@ +.model LED D(is=4.36625E-25 rs=3.00014 n=1.38167 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/deviceModelLibrary/Diode/LED.xml b/library/deviceModelLibrary/Diode/LED.xml new file mode 100644 index 00000000..91eb9169 --- /dev/null +++ b/library/deviceModelLibrary/Diode/LED.xml @@ -0,0 +1 @@ +<library><model_name>D</model_name><ref_model>LED</ref_model><param><cjo>1.700E-12</cjo><rs>4.755E-01</rs><is>2.495E-09</is><m>1.959E-01</m><n>1.679E00</n><bv>1.000E02</bv><ibv>1.000E-04</ibv><tt>3.030E-09</tt><vj>1</vj></param></library>
\ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/PowerDiode.lib b/library/deviceModelLibrary/Diode/PowerDiode.lib new file mode 100644 index 00000000..a2f61dce --- /dev/null +++ b/library/deviceModelLibrary/Diode/PowerDiode.lib @@ -0,0 +1,20 @@ +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/PowerDiode.xml b/library/deviceModelLibrary/Diode/PowerDiode.xml new file mode 100644 index 00000000..06dceda1 --- /dev/null +++ b/library/deviceModelLibrary/Diode/PowerDiode.xml @@ -0,0 +1 @@ +<library><model_name>D</model_name><ref_model>PowerDiode</ref_model><param><Vj>.75</Vj><Nbvl>14.976</Nbvl><Cjo>175p</Cjo><Rs>.25</Rs><Isr>1.859n</Isr><Eg>1.11</Eg><M>.5516</M><Nbv>1.6989</Nbv><N>1</N><Tbv1>-21.277u</Tbv1><bv>1800</bv><Fc>.5</Fc><Ikf>0</Ikf><Nr>2</Nr><Ibv>20.245m</Ibv><Is>2.2E-15</Is><Xti>3</Xti><Ibvl>1.9556m</Ibvl></param></library>
\ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/ZenerD1N750.lib b/library/deviceModelLibrary/Diode/ZenerD1N750.lib new file mode 100644 index 00000000..890c37fe --- /dev/null +++ b/library/deviceModelLibrary/Diode/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/library/deviceModelLibrary/Diode/ZenerD1N750.xml b/library/deviceModelLibrary/Diode/ZenerD1N750.xml new file mode 100644 index 00000000..546d1156 --- /dev/null +++ b/library/deviceModelLibrary/Diode/ZenerD1N750.xml @@ -0,0 +1,24 @@ +<library> +<model_name>D</model_name> +<ref_model>D1N750</ref_model> +<param> + <Is>880.5E-18</Is> + <Rs>.25</Rs> + <Ikf>0</Ikf> + <N>1</N> + <Xti>3</Xti> + <Eg>1.11</Eg> + <Cjo>175p</Cjo> + <M>.5516</M> + <Vj>.75</Vj> + <Fc>.5</Fc> + <Isr>1.859n</Isr> + <Nr>2</Nr> + <Bv>8.1</Bv> + <Ibv>20.245m</Ibv> + <Nbv>1.6989</Nbv> + <Ibvl>1.9556m</Ibvl> + <Nbvl>14.976</Nbvl> + <Tbv1>-21.277u</Tbv1> +</param> +</library> diff --git a/library/deviceModelLibrary/IGBT/NIGBT.lib b/library/deviceModelLibrary/IGBT/NIGBT.lib new file mode 100644 index 00000000..86cd1b4e --- /dev/null +++ b/library/deviceModelLibrary/IGBT/NIGBT.lib @@ -0,0 +1,11 @@ +.MODEL IXGH40N60 NIGBT( ++ TAU=287.56E-9 ++ KF=.36047 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ KP=50.034 ++ VT=4.1822 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570 +)
\ No newline at end of file diff --git a/library/deviceModelLibrary/IGBT/NIGBT.xml b/library/deviceModelLibrary/IGBT/NIGBT.xml new file mode 100644 index 00000000..38d9d094 --- /dev/null +++ b/library/deviceModelLibrary/IGBT/NIGBT.xml @@ -0,0 +1,4 @@ +<library> +<model_name>NIGBT</model_name> +<ref_model>IXGH40N60</ref_model> +<param><TAU>287.56E-9</TAU><KF>.36047</KF><AREA>37.500E-6</AREA><AGD>18.750E-6</AGD><KP>50.034</KP><VT>4.1822</VT><CGS>31.942E-9</CGS><COXD>53.188E-9</COXD><VTD>2.6570</VTD></param></library>
\ No newline at end of file diff --git a/library/deviceModelLibrary/IGBT/PIGBT.lib b/library/deviceModelLibrary/IGBT/PIGBT.lib new file mode 100644 index 00000000..d4f9e814 --- /dev/null +++ b/library/deviceModelLibrary/IGBT/PIGBT.lib @@ -0,0 +1,10 @@ +.MODEL IXGH40N60 PIGBT ( ++ TAU=287.56E-9 ++ KP=50.034 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ VT=4.1822 ++ KF=.36047 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570) diff --git a/library/deviceModelLibrary/IGBT/PIGBT.xml b/library/deviceModelLibrary/IGBT/PIGBT.xml new file mode 100644 index 00000000..1e57f2e3 --- /dev/null +++ b/library/deviceModelLibrary/IGBT/PIGBT.xml @@ -0,0 +1,15 @@ +<library> +<model_name>PIGBT</model_name> +<ref_model>IXGH40N60</ref_model> +<param> +<TAU>287.56E-9</TAU> +<KP>50.034</KP> +<AREA>37.500E-6</AREA> +<AGD>18.750E-6</AGD> +<VT>4.1822</VT> +<KF>.36047</KF> +<CGS>31.942E-9</CGS> +<COXD>53.188E-9</COXD> +<VTD>2.6570 </VTD> +</param> +</library> diff --git a/library/deviceModelLibrary/JFET/NJF.lib b/library/deviceModelLibrary/JFET/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/deviceModelLibrary/JFET/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/deviceModelLibrary/JFET/NJF.xml b/library/deviceModelLibrary/JFET/NJF.xml new file mode 100644 index 00000000..94753691 --- /dev/null +++ b/library/deviceModelLibrary/JFET/NJF.xml @@ -0,0 +1,29 @@ +<library> +<model_name>NJF</model_name> +<ref_model>J2N3819</ref_model> +<param> +<Beta>1.304m</Beta> +<Betatce>-.5</Betatce> +<Rd>1 </Rd> +<Rs>1 </Rs> +<Lambda>2.25m</Lambda> +<Vto>-3</Vto> +<Vtotc>-2.5m</Vtotc> +<Is>33.57f </Is> +<Isr>322.4f </Isr> +<N>1</N> +<Nr>2</Nr> +<Xti>3</Xti> +<Alpha>311.7u</Alpha> +<Vk>243.6 </Vk> +<Cgd>1.6p </Cgd> +<M>.3622 </M> +<Pb>1</Pb> +<Fc>.5</Fc> +<Cgs>2.414p</Cgs> +<Kf>9.882E-18</Kf> +<Af>1</Af> + + +</param> +</library> diff --git a/library/deviceModelLibrary/JFET/PJF.lib b/library/deviceModelLibrary/JFET/PJF.lib new file mode 100644 index 00000000..5589571d --- /dev/null +++ b/library/deviceModelLibrary/JFET/PJF.lib @@ -0,0 +1,5 @@ +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/library/deviceModelLibrary/JFET/PJF.xml b/library/deviceModelLibrary/JFET/PJF.xml new file mode 100644 index 00000000..f682f8cb --- /dev/null +++ b/library/deviceModelLibrary/JFET/PJF.xml @@ -0,0 +1,27 @@ +<library> +<model_name>PJF</model_name> +<ref_model>J2N3820</ref_model> +<param> +<Beta>1.304m </Beta> +<Betatce>-.5</Betatce> +<Rd>1 </Rd> +<Rs>1 </Rs> +<Lambda>2.25m</Lambda> +<Vto>-3</Vto> +<Vtotc>-2.5m </Vtotc> +<Is>33.57f </Is> +<Isr>322.4f</Isr> +<N>1 </N> +<Nr>2 </Nr> +<Xti>3 </Xti> +<Alpha>311.7u</Alpha> +<Vk>243.6 </Vk> +<Cgd>1.6p </Cgd> +<M>.3622 </M> +<Pb>1 </Pb> +<Fc>.5 </Fc> +<Cgs>2.414p </Cgs> +<Kf>9.882E-18</Kf> +<Af>1</Af> +</param> +</library> diff --git a/library/deviceModelLibrary/MOS/NMOS-0.5um.lib b/library/deviceModelLibrary/MOS/NMOS-0.5um.lib new file mode 100644 index 00000000..2e6f4635 --- /dev/null +++ b/library/deviceModelLibrary/MOS/NMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 )
\ No newline at end of file diff --git a/library/deviceModelLibrary/MOS/NMOS-0.5um.xml b/library/deviceModelLibrary/MOS/NMOS-0.5um.xml new file mode 100644 index 00000000..08fdf0e3 --- /dev/null +++ b/library/deviceModelLibrary/MOS/NMOS-0.5um.xml @@ -0,0 +1,32 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>mos_n</ref_model> +<param> +<TPG>1</TPG> +<TOX>9.5n </TOX> +<CJ>550u </CJ> +<ETA>0.02125 </ETA> +<VMAX>1.8E05</VMAX> +<GAMMA>0.62</GAMMA> +<CGSO>0.3n </CGSO> +<LD>50n </LD> +<MJSW>0.35 </MJSW> +<PB>1.1</PB> +<CGBO>0.45n </CGBO> +<XJ>0.2U </XJ> +<CGDO>0.3n </CGDO> +<KAPPA>0.1 </KAPPA> +<LEVEL>3 </LEVEL> +<VTO>0.6 </VTO> +<NFS>7.20E11 </NFS> +<THETA>0.23 </THETA> +<CJSW>0.3n </CJSW> +<PHI>0.7 </PHI> +<RSH>2.0 </RSH> +<MJ>0.6 </MJ> +<UO>420</UO> +<KP>156u </KP> +<DELTA>0.88</DELTA> +<NSUB>1.40E17</NSUB> +</param> +</library> diff --git a/library/deviceModelLibrary/MOS/NMOS-180nm.lib b/library/deviceModelLibrary/MOS/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/deviceModelLibrary/MOS/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/deviceModelLibrary/MOS/NMOS-180nm.xml b/library/deviceModelLibrary/MOS/NMOS-180nm.xml new file mode 100644 index 00000000..d0249bb6 --- /dev/null +++ b/library/deviceModelLibrary/MOS/NMOS-180nm.xml @@ -0,0 +1,112 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>CMOSN</ref_model> +<param> +<LEVEL>8 </LEVEL> +<VERSION>3.2 </VERSION> +<TNOM>27 </TNOM> +<TOX>4.1E-9 </TOX> +<XJ>1E-7 </XJ> +<NCH>2.3549E17 </NCH> +<VTH0>0.3823463 </VTH0> +<K1>0.5810697 </K1> +<K2>4.774618E-3 </K2> +<K3>0.0431669 </K3> +<K3B>1.1498346</K3B> +<W0>1E-7 </W0> +<NLX>1.910552E-7 </NLX> +<DVT0W>0 </DVT0W> +<DVT1W>0 </DVT1W> +<DVT2W>0 </DVT2W> +<DVT0>1.2894824 </DVT0> +<DVT1>0.3622063 </DVT1> +<DVT2>0.0713729 </DVT2> +<U0>280.633249 </U0> +<UA>-1.208537E-9 </UA> +<UB>2.158625E-18</UB> +<UC>5.342807E-11 </UC> +<VSAT>9.366802E4</VSAT> +<A0>1.7593146 </A0> +<AGS>0.3939741 </AGS> +<B0>-6.413949E-9 </B0> +<B1>-1E-7 </B1> +<KETA>-5.180424E-4</KETA> +<A1>0 </A1> +<A2>1 </A2> +<RDSW>105.5517558</RDSW> +<PRWG>0.5 </PRWG> +<PRWB>-0.1998871 </PRWB> +<WR>1 </WR> +<WINT>7.904732E-10 </WINT> +<LINT>1.571424E-8 </LINT> +<XL>0</XL> +<XW>-1E-8 </XW> +<DWG>1.297221E-9 </DWG> +<DWB>1.479041E-9</DWB> +<VOFF>-0.0955434 </VOFF> +<NFACTOR>2.4358891 </NFACTOR> +<CIT>0 </CIT> +<CDSC>2.4E-4 </CDSC> +<CDSCD>0</CDSCD> +<CDSCB>0 </CDSCB> +<ETA0>=3.104851E-3 </ETA0> +<ETAB>-2.512384E-5 </ETAB> +<DSUB>0.0167075 </DSUB> +<PCLM>0.8073191 </PCLM> +<PDIBLC1>0.1666161 </PDIBLC1> +<PDIBLC2>3.112892E-3 </PDIBLC2> +<PDIBLCB>-0.1 </PDIBLCB> +<DROUT>0.7875618 </DROUT> +<PSCBE1>8E10 </PSCBE1> +<PSCBE2>9.213635E-10 </PSCBE2> +<PVAG>3.85243E-3 </PVAG> +<DELTA>0.01 </DELTA> +<RSH>6.7 </RSH> +<MOBMOD>1</MOBMOD> +<PRT>0 </PRT> +<UTE>-1.5 </UTE> +<KT1>-0.11 </KT1> +<KT1L>0 </KT1L> +<KT2>0.022 </KT2> +<UA1>4.31E-9 </UA1> +<UB1>-7.61E-18 </UB1> +<UC1>-5.6E-11 </UC1> +<AT>3.3E4 </AT> +<WL>0 </WL> +<WLN>1</WLN> +<WW>0 </WW> +<WWN>1 </WWN> +<WWL>0 </WWL> +<LL>0 </LL> +<LLN>1 </LLN> +<LW>0 </LW> +<LWN>1 </LWN> +<LWL>0 </LWL> +<CAPMOD>2 </CAPMOD> +<XPART>0.5 </XPART> +<CGDO>7.08E-10 </CGDO> +<CGSO>7.08E-10 </CGSO>/ +<CGBO>1E-12</CGBO> +<CJ>9.68858E-4 </CJ> +<PB>0.8 </PB> +<MJ>0.3864502 </MJ> +<CJSW>2.512138E-10 </CJSW> +<PBSW>0.809286 </PBSW> +<MJSW>0.1060414 </MJSW> +<CJSWG>3.3E-10 </CJSWG> +<PBSWG>0.809286 </PBSWG> +<MJSWG>0.1060414 </MJSWG> +<CF>0 </CF> +<PVTH0>-1.192722E-3 </PVTH0> +<PRDSW>-5 </PRDSW> +<PK2>6.450505E-5 </PK2> +<WKETA>-4.27294E-4 </WKETA> +<LKETA>-0.0104078 </LKETA> +<PU0>6.3268729 </PU0> +<PUA>2.226552E-11 </PUA> +<PUB>0 </PUB> +<PVSAT>969.1480157</PVSAT> +<PETA0>1E-4 </PETA0> +<PKETA>-1.049509E-3</PKETA> +</param> +</library> diff --git a/library/deviceModelLibrary/MOS/NMOS-5um.lib b/library/deviceModelLibrary/MOS/NMOS-5um.lib new file mode 100644 index 00000000..a237e1fe --- /dev/null +++ b/library/deviceModelLibrary/MOS/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/deviceModelLibrary/MOS/NMOS-5um.xml b/library/deviceModelLibrary/MOS/NMOS-5um.xml new file mode 100644 index 00000000..358fbdbe --- /dev/null +++ b/library/deviceModelLibrary/MOS/NMOS-5um.xml @@ -0,0 +1,24 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>mos_n</ref_model> +<param> +<Cgso>0.4n</Cgso> +<Tox>85n</Tox> +<Vto>1</Vto> +<phi>0.7</phi> +<Level>1</Level> +<Mj>.5</Mj> +<UO>750</UO> +<Cgdo>0.4n</Cgdo> +<Gamma>1.4</Gamma> +<LAMBDA>0.01 </LAMBDA> +<LD>0.7u </LD> +<JS>1u </JS> +<CJ>0.4m</CJ> +<CJSW>0.8n</CJSW> +<MJSW>0.5 </MJSW> +<PB>0.7</PB> +<CGBO>0.2n</CGBO> + +</param> +</library> diff --git a/library/deviceModelLibrary/MOS/PMOS-0.5um.lib b/library/deviceModelLibrary/MOS/PMOS-0.5um.lib new file mode 100644 index 00000000..848e8b05 --- /dev/null +++ b/library/deviceModelLibrary/MOS/PMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u ++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 ++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 ++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 ++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 ++ NSUB=1.0E17 )
\ No newline at end of file diff --git a/library/deviceModelLibrary/MOS/PMOS-0.5um.xml b/library/deviceModelLibrary/MOS/PMOS-0.5um.xml new file mode 100644 index 00000000..013d461c --- /dev/null +++ b/library/deviceModelLibrary/MOS/PMOS-0.5um.xml @@ -0,0 +1,32 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>mos_p</ref_model> +<param> +<TPG>-1 </TPG> +<TOX>9.5n </TOX> +<CJ>950u </CJ> +<ETA>0.025 </ETA> +<VMAX>0.3u </VMAX> +<GAMMA>0.52 </GAMMA> +<CGSO>0.35n </CGSO> +<LD>70n </LD> +<MJSW>0.25 </MJSW> +<PB>1 </PB> +<CGBO>0.45n </CGBO> +<XJ>0.2U </XJ> +<CGDO>0.35n </CGDO> +<KAPPA>8.0 </KAPPA> +<LEVEL>3 </LEVEL> +<VTO>-0.6 </VTO> +<NFS>6.50E11 </NFS> +<THETA>0.2 </THETA> +<CJSW>0.2n </CJSW> +<PHI>0.7 </PHI> +<RSH>2.5 </RSH> +<MJ>0.5</MJ> +<UO>130 </UO> +<KP>48u </KP> +<DELTA>0.25 </DELTA> +<NSUB>1.0E17</NSUB> +</param> +</library> diff --git a/library/deviceModelLibrary/MOS/PMOS-180nm.lib b/library/deviceModelLibrary/MOS/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/deviceModelLibrary/MOS/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/deviceModelLibrary/MOS/PMOS-180nm.xml b/library/deviceModelLibrary/MOS/PMOS-180nm.xml new file mode 100644 index 00000000..6696752d --- /dev/null +++ b/library/deviceModelLibrary/MOS/PMOS-180nm.xml @@ -0,0 +1,112 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>CMOSP</ref_model> +<param> +<LEVEL>8 </LEVEL> +<VERSION>3.2 </VERSION> +<TNOM>27 </TNOM> +<TOX>4.1E-9 </TOX> +<XJ>1E-7 </XJ> +<NCH>4.1589E17 </NCH> +<VTH0>-0.3938813 </VTH0> +<K1>0.5479015</K1> +<K2>0.0360586 </K2> +<K3>0.0993095 </K3> +<K3B>5.7086622</K3B> +<W0>1E-6 </W0> +<NLX>1.313191E-7 </NLX> +<DVT0W>0 </DVT0W> +<DVT1W>0 </DVT1W> +<DVT2W>0 </DVT2W> +<DVT0>0.4911363</DVT0> +<DVT1>0.2227356</DVT1> +<DVT2>0.1 </DVT2> +<U0>115.6852975 </U0> +<UA>1.505832E-9</UA> +<UB>1E-21 </UB> +<UC>-1E-10 </UC> +<VSAT>1.329694E5 </VSAT> +<A0>1.7590478 </A0> +<AGS>0.3641621 </AGS> +<B0>3.427126E-7 </B0> +<B1>1.062928E-6 </B1> +<KETA>0.0134667 </KETA> +<A1>0.6859506 </A1> +<A2>0.3506788 </A2> +<RDSW>168.5705677</RDSW> +<PRWG>0.5 </PRWG> +<PRWB>-0.4987371 </PRWB> +<WR>1 </WR> +<WINT>0 </WINT> +<LINT>3.028832E-8 </LINT> +<XL>0 </XL> +<XW>-1E-8 </XW> +<DWG>-2.349633E-8 </DWG> +<DWB>-7.152486E-9 </DWB> +<VOFF>-0.0994037 </VOFF> +<NFACTOR>1.9424315 </NFACTOR> +<CIT>0 </CIT> +<CDSC>2.4E-4 </CDSC> +<CDSCD>0 </CDSCD> +<CDSCB>0 </CDSCB> +<ETA0>0.0608072 </ETA0> +<ETAB>-0.0426148</ETAB> +<DSUB>0.7343015 </DSUB> +<PCLM>3.2579974 </PCLM> +<PDIBLC1>7.229527E-6 </PDIBLC1> +<PDIBLC2>0.025389 </PDIBLC2> +<PDIBLCB>-1E-3 </PDIBLCB> +<DROUT>0 </DROUT> +<PSCBE1>1.454878E10</PSCBE1> +<PSCBE2>4.202027E-9 </PSCBE2> +<PVAG>15 </PVAG> +<DELTA>0.01 </DELTA> +<RSH>7.8 </RSH> +<MOBMOD>1 </MOBMOD> +<PRT>0 </PRT> +<UTE>-1.5 </UTE> +<KT1>-0.11 </KT1> +<KT1L>0 </KT1L> +<KT2>0.022 </KT2> +<UA1>4.31E-9</UA1> +<UB1>-7.61E-18 </UB1> +<UC1>-5.6E-11 </UC1> +<AT>3.3E4 </AT> +<WL>0 </WL> +<WLN>1 </WLN> +<WW>0 </WW> +<WWN>1 </WWN> +<WWL>0 </WWL> +<LL>0 </LL> +<LLN>1 </LLN> +<LW>0 </LW> +<LWN>1 </LWN> +<LWL>0 </LWL> +<CAPMOD>2 </CAPMOD> +<XPART>0.5</XPART> +<CGDO>6.32E-10 </CGDO> +<CGSO>6.32E-10 </CGSO> +<CGBO>1E-12 </CGBO> +<CJ>1.172138E-3 </CJ> +<PB>0.8421173 </PB> +<MJ>0.4109788 </MJ> +<CJSW>2.242609E-10 </CJSW> +<PBSW>0.8</PBSW> +<MJSW>0.3752089 </MJSW> +<CJSWG>4.22E-10 </CJSWG> +<PBSWG>0.8 </PBSWG> +<MJSWG>0.3752089 </MJSWG> +<CF>0 </CF> +<PVTH0>1.888482E-3 </PVTH0> +<PRDSW>11.5315407 </PRDSW> +<PK2>1.559399E-3 </PK2> +<WKETA>0.0319301 </WKETA> +<LKETA>2.955547E-3 </LKETA> +<PU0>-1.1105313 </PU0> +<PUA>-4.62102E-11</PUA> +<PUB>1E-21 </PUB> +<PVSAT>50 </PVSAT> +<PETA0>1E-4 </PETA0> +<PKETA>-4.346368E-3 </PKETA> +</param> +</library> diff --git a/library/deviceModelLibrary/MOS/PMOS-5um.lib b/library/deviceModelLibrary/MOS/PMOS-5um.lib new file mode 100644 index 00000000..9c3ed976 --- /dev/null +++ b/library/deviceModelLibrary/MOS/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/deviceModelLibrary/MOS/PMOS-5um.xml b/library/deviceModelLibrary/MOS/PMOS-5um.xml new file mode 100644 index 00000000..f68bada2 --- /dev/null +++ b/library/deviceModelLibrary/MOS/PMOS-5um.xml @@ -0,0 +1,23 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>mos_p</ref_model> +<param> +<Cgso>0.4n </Cgso> +<Tox>85n </Tox> +<Vto>-1 </Vto> +<phi>0.65</phi> +<Level>1</Level> +<Mj>.5 </Mj> +<UO>250 </UO> +<Cgdo>0.4n </Cgdo> +<Gamma>0.65 </Gamma> +<LAMBDA>0.03 </LAMBDA> +<LD>0.6u </LD> +<JS>1u </JS> +<CJ>0.18m </CJ> +<CJSW>0.6n </CJSW> +<MJSW>0.5 </MJSW> +<PB>0.7 </PB> +<CGBO>0.2n</CGBO> +</param> +</library> diff --git a/library/deviceModelLibrary/Misc/CORE.lib b/library/deviceModelLibrary/Misc/CORE.lib new file mode 100644 index 00000000..a7581029 --- /dev/null +++ b/library/deviceModelLibrary/Misc/CORE.lib @@ -0,0 +1,9 @@ +.MODEL K3019PL_3C8 Core( ++ A=44.82 ++ C=.4112 ++ abc=123 ++ Area=1.38 ++ K=25.74 ++ MS=415.2K ++ Path=4.52 +)
\ No newline at end of file diff --git a/library/deviceModelLibrary/Misc/CORE.xml b/library/deviceModelLibrary/Misc/CORE.xml new file mode 100644 index 00000000..c95d9db0 --- /dev/null +++ b/library/deviceModelLibrary/Misc/CORE.xml @@ -0,0 +1,4 @@ +<library> +<model_name>Core</model_name> +<ref_model>K3019PL_3C8</ref_model> +<param><A>44.82 </A><C>.4112</C><abc>123</abc><Area>1.38</Area><K>25.74</K><MS>415.2K</MS><Path>4.52</Path></param></library> diff --git a/library/deviceModelLibrary/Templates/CORE.lib b/library/deviceModelLibrary/Templates/CORE.lib new file mode 100644 index 00000000..a7581029 --- /dev/null +++ b/library/deviceModelLibrary/Templates/CORE.lib @@ -0,0 +1,9 @@ +.MODEL K3019PL_3C8 Core( ++ A=44.82 ++ C=.4112 ++ abc=123 ++ Area=1.38 ++ K=25.74 ++ MS=415.2K ++ Path=4.52 +)
\ No newline at end of file diff --git a/library/deviceModelLibrary/Templates/CORE.xml b/library/deviceModelLibrary/Templates/CORE.xml new file mode 100644 index 00000000..c95d9db0 --- /dev/null +++ b/library/deviceModelLibrary/Templates/CORE.xml @@ -0,0 +1,4 @@ +<library> +<model_name>Core</model_name> +<ref_model>K3019PL_3C8</ref_model> +<param><A>44.82 </A><C>.4112</C><abc>123</abc><Area>1.38</Area><K>25.74</K><MS>415.2K</MS><Path>4.52</Path></param></library> diff --git a/library/deviceModelLibrary/Templates/D.lib b/library/deviceModelLibrary/Templates/D.lib new file mode 100644 index 00000000..8a7fb4da --- /dev/null +++ b/library/deviceModelLibrary/Templates/D.lib @@ -0,0 +1,2 @@ +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/deviceModelLibrary/Templates/D.xml b/library/deviceModelLibrary/Templates/D.xml new file mode 100644 index 00000000..8b6b14c8 --- /dev/null +++ b/library/deviceModelLibrary/Templates/D.xml @@ -0,0 +1,15 @@ +<library> +<model_name>D</model_name> +<ref_model>1N4148</ref_model> +<param> + <Is>2.495E-09</Is> + <Rs>4.755E-01</Rs> + <N>1.679E+00</N> + <tt>3.030E-09</tt> + <Cjo>1.700E-12</Cjo> + <M>1.959E-01</M> + <Vj>1</Vj> + <Bv>1.000E+02</Bv> + <Ibv>1.000E-04</Ibv> +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/NIGBT.lib b/library/deviceModelLibrary/Templates/NIGBT.lib new file mode 100644 index 00000000..8c09dcbc --- /dev/null +++ b/library/deviceModelLibrary/Templates/NIGBT.lib @@ -0,0 +1,10 @@ +.MODEL IXGH40N60 NIGBT ( ++ TAU=287.56E-9 ++ KP=50.034 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ VT=4.1822 ++ KF=.36047 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570) diff --git a/library/deviceModelLibrary/Templates/NIGBT.xml b/library/deviceModelLibrary/Templates/NIGBT.xml new file mode 100644 index 00000000..97f33196 --- /dev/null +++ b/library/deviceModelLibrary/Templates/NIGBT.xml @@ -0,0 +1,15 @@ +<library> +<model_name>NIGBT</model_name> +<ref_model>IXGH40N60</ref_model> +<param> +<TAU>287.56E-9</TAU> +<KP>50.034</KP> +<AREA>37.500E-6</AREA> +<AGD>18.750E-6</AGD> +<VT>4.1822</VT> +<KF>.36047</KF> +<CGS>31.942E-9</CGS> +<COXD>53.188E-9</COXD> +<VTD>2.6570</VTD> +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/NJF.lib b/library/deviceModelLibrary/Templates/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/deviceModelLibrary/Templates/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/deviceModelLibrary/Templates/NJF.xml b/library/deviceModelLibrary/Templates/NJF.xml new file mode 100644 index 00000000..94753691 --- /dev/null +++ b/library/deviceModelLibrary/Templates/NJF.xml @@ -0,0 +1,29 @@ +<library> +<model_name>NJF</model_name> +<ref_model>J2N3819</ref_model> +<param> +<Beta>1.304m</Beta> +<Betatce>-.5</Betatce> +<Rd>1 </Rd> +<Rs>1 </Rs> +<Lambda>2.25m</Lambda> +<Vto>-3</Vto> +<Vtotc>-2.5m</Vtotc> +<Is>33.57f </Is> +<Isr>322.4f </Isr> +<N>1</N> +<Nr>2</Nr> +<Xti>3</Xti> +<Alpha>311.7u</Alpha> +<Vk>243.6 </Vk> +<Cgd>1.6p </Cgd> +<M>.3622 </M> +<Pb>1</Pb> +<Fc>.5</Fc> +<Cgs>2.414p</Cgs> +<Kf>9.882E-18</Kf> +<Af>1</Af> + + +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/NMOS-0.5um.lib b/library/deviceModelLibrary/Templates/NMOS-0.5um.lib new file mode 100644 index 00000000..2e6f4635 --- /dev/null +++ b/library/deviceModelLibrary/Templates/NMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 )
\ No newline at end of file diff --git a/library/deviceModelLibrary/Templates/NMOS-0.5um.xml b/library/deviceModelLibrary/Templates/NMOS-0.5um.xml new file mode 100644 index 00000000..08fdf0e3 --- /dev/null +++ b/library/deviceModelLibrary/Templates/NMOS-0.5um.xml @@ -0,0 +1,32 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>mos_n</ref_model> +<param> +<TPG>1</TPG> +<TOX>9.5n </TOX> +<CJ>550u </CJ> +<ETA>0.02125 </ETA> +<VMAX>1.8E05</VMAX> +<GAMMA>0.62</GAMMA> +<CGSO>0.3n </CGSO> +<LD>50n </LD> +<MJSW>0.35 </MJSW> +<PB>1.1</PB> +<CGBO>0.45n </CGBO> +<XJ>0.2U </XJ> +<CGDO>0.3n </CGDO> +<KAPPA>0.1 </KAPPA> +<LEVEL>3 </LEVEL> +<VTO>0.6 </VTO> +<NFS>7.20E11 </NFS> +<THETA>0.23 </THETA> +<CJSW>0.3n </CJSW> +<PHI>0.7 </PHI> +<RSH>2.0 </RSH> +<MJ>0.6 </MJ> +<UO>420</UO> +<KP>156u </KP> +<DELTA>0.88</DELTA> +<NSUB>1.40E17</NSUB> +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/NMOS-180nm.lib b/library/deviceModelLibrary/Templates/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/deviceModelLibrary/Templates/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/deviceModelLibrary/Templates/NMOS-180nm.xml b/library/deviceModelLibrary/Templates/NMOS-180nm.xml new file mode 100644 index 00000000..d0249bb6 --- /dev/null +++ b/library/deviceModelLibrary/Templates/NMOS-180nm.xml @@ -0,0 +1,112 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>CMOSN</ref_model> +<param> +<LEVEL>8 </LEVEL> +<VERSION>3.2 </VERSION> +<TNOM>27 </TNOM> +<TOX>4.1E-9 </TOX> +<XJ>1E-7 </XJ> +<NCH>2.3549E17 </NCH> +<VTH0>0.3823463 </VTH0> +<K1>0.5810697 </K1> +<K2>4.774618E-3 </K2> +<K3>0.0431669 </K3> +<K3B>1.1498346</K3B> +<W0>1E-7 </W0> +<NLX>1.910552E-7 </NLX> +<DVT0W>0 </DVT0W> +<DVT1W>0 </DVT1W> +<DVT2W>0 </DVT2W> +<DVT0>1.2894824 </DVT0> +<DVT1>0.3622063 </DVT1> +<DVT2>0.0713729 </DVT2> +<U0>280.633249 </U0> +<UA>-1.208537E-9 </UA> +<UB>2.158625E-18</UB> +<UC>5.342807E-11 </UC> +<VSAT>9.366802E4</VSAT> +<A0>1.7593146 </A0> +<AGS>0.3939741 </AGS> +<B0>-6.413949E-9 </B0> +<B1>-1E-7 </B1> +<KETA>-5.180424E-4</KETA> +<A1>0 </A1> +<A2>1 </A2> +<RDSW>105.5517558</RDSW> +<PRWG>0.5 </PRWG> +<PRWB>-0.1998871 </PRWB> +<WR>1 </WR> +<WINT>7.904732E-10 </WINT> +<LINT>1.571424E-8 </LINT> +<XL>0</XL> +<XW>-1E-8 </XW> +<DWG>1.297221E-9 </DWG> +<DWB>1.479041E-9</DWB> +<VOFF>-0.0955434 </VOFF> +<NFACTOR>2.4358891 </NFACTOR> +<CIT>0 </CIT> +<CDSC>2.4E-4 </CDSC> +<CDSCD>0</CDSCD> +<CDSCB>0 </CDSCB> +<ETA0>=3.104851E-3 </ETA0> +<ETAB>-2.512384E-5 </ETAB> +<DSUB>0.0167075 </DSUB> +<PCLM>0.8073191 </PCLM> +<PDIBLC1>0.1666161 </PDIBLC1> +<PDIBLC2>3.112892E-3 </PDIBLC2> +<PDIBLCB>-0.1 </PDIBLCB> +<DROUT>0.7875618 </DROUT> +<PSCBE1>8E10 </PSCBE1> +<PSCBE2>9.213635E-10 </PSCBE2> +<PVAG>3.85243E-3 </PVAG> +<DELTA>0.01 </DELTA> +<RSH>6.7 </RSH> +<MOBMOD>1</MOBMOD> +<PRT>0 </PRT> +<UTE>-1.5 </UTE> +<KT1>-0.11 </KT1> +<KT1L>0 </KT1L> +<KT2>0.022 </KT2> +<UA1>4.31E-9 </UA1> +<UB1>-7.61E-18 </UB1> +<UC1>-5.6E-11 </UC1> +<AT>3.3E4 </AT> +<WL>0 </WL> +<WLN>1</WLN> +<WW>0 </WW> +<WWN>1 </WWN> +<WWL>0 </WWL> +<LL>0 </LL> +<LLN>1 </LLN> +<LW>0 </LW> +<LWN>1 </LWN> +<LWL>0 </LWL> +<CAPMOD>2 </CAPMOD> +<XPART>0.5 </XPART> +<CGDO>7.08E-10 </CGDO> +<CGSO>7.08E-10 </CGSO>/ +<CGBO>1E-12</CGBO> +<CJ>9.68858E-4 </CJ> +<PB>0.8 </PB> +<MJ>0.3864502 </MJ> +<CJSW>2.512138E-10 </CJSW> +<PBSW>0.809286 </PBSW> +<MJSW>0.1060414 </MJSW> +<CJSWG>3.3E-10 </CJSWG> +<PBSWG>0.809286 </PBSWG> +<MJSWG>0.1060414 </MJSWG> +<CF>0 </CF> +<PVTH0>-1.192722E-3 </PVTH0> +<PRDSW>-5 </PRDSW> +<PK2>6.450505E-5 </PK2> +<WKETA>-4.27294E-4 </WKETA> +<LKETA>-0.0104078 </LKETA> +<PU0>6.3268729 </PU0> +<PUA>2.226552E-11 </PUA> +<PUB>0 </PUB> +<PVSAT>969.1480157</PVSAT> +<PETA0>1E-4 </PETA0> +<PKETA>-1.049509E-3</PKETA> +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/NMOS-5um.lib b/library/deviceModelLibrary/Templates/NMOS-5um.lib new file mode 100644 index 00000000..a237e1fe --- /dev/null +++ b/library/deviceModelLibrary/Templates/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/deviceModelLibrary/Templates/NMOS-5um.xml b/library/deviceModelLibrary/Templates/NMOS-5um.xml new file mode 100644 index 00000000..358fbdbe --- /dev/null +++ b/library/deviceModelLibrary/Templates/NMOS-5um.xml @@ -0,0 +1,24 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>mos_n</ref_model> +<param> +<Cgso>0.4n</Cgso> +<Tox>85n</Tox> +<Vto>1</Vto> +<phi>0.7</phi> +<Level>1</Level> +<Mj>.5</Mj> +<UO>750</UO> +<Cgdo>0.4n</Cgdo> +<Gamma>1.4</Gamma> +<LAMBDA>0.01 </LAMBDA> +<LD>0.7u </LD> +<JS>1u </JS> +<CJ>0.4m</CJ> +<CJSW>0.8n</CJSW> +<MJSW>0.5 </MJSW> +<PB>0.7</PB> +<CGBO>0.2n</CGBO> + +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/NPN.lib b/library/deviceModelLibrary/Templates/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/deviceModelLibrary/Templates/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/deviceModelLibrary/Templates/NPN.xml b/library/deviceModelLibrary/Templates/NPN.xml new file mode 100644 index 00000000..b2698bb1 --- /dev/null +++ b/library/deviceModelLibrary/Templates/NPN.xml @@ -0,0 +1,33 @@ +<library> +<model_name>NPN</model_name> +<ref_model>Q2N2222</ref_model> +<param> +<Is>14.34f </Is> +<Xti>3 </Xti> +<Eg>1.11 </Eg> +<Vaf>74.03 </Vaf> +<Bf>400 </Bf> +<Ne>1.307 </Ne> +<Ise>14.34f </Ise> +<Ikf>.2847 </Ikf> +<Xtb>1.5 </Xtb> +<Br>6.092 </Br> +<Nc>2 </Nc> +<Isc>0 </Isc> +<Ikr>0 </Ikr> +<Rc>1 </Rc> +<Cjc>7.306p </Cjc> +<Mjc>.3416 </Mjc> +<Vjc>.75 </Vjc> +<Fc>.5 </Fc> +<Cje>22.01p </Cje> +<Mje>.377 </Mje> +<Vje>.75 </Vje> +<Tr>46.91n </Tr> +<Tf>411.1p </Tf> +<Itf>.6 </Itf> +<Vtf>1.7 </Vtf> +<Xtf>3 </Xtf> +<Rb>10 </Rb> +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/PIGBT.lib b/library/deviceModelLibrary/Templates/PIGBT.lib new file mode 100644 index 00000000..d4f9e814 --- /dev/null +++ b/library/deviceModelLibrary/Templates/PIGBT.lib @@ -0,0 +1,10 @@ +.MODEL IXGH40N60 PIGBT ( ++ TAU=287.56E-9 ++ KP=50.034 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ VT=4.1822 ++ KF=.36047 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570) diff --git a/library/deviceModelLibrary/Templates/PIGBT.xml b/library/deviceModelLibrary/Templates/PIGBT.xml new file mode 100644 index 00000000..1e57f2e3 --- /dev/null +++ b/library/deviceModelLibrary/Templates/PIGBT.xml @@ -0,0 +1,15 @@ +<library> +<model_name>PIGBT</model_name> +<ref_model>IXGH40N60</ref_model> +<param> +<TAU>287.56E-9</TAU> +<KP>50.034</KP> +<AREA>37.500E-6</AREA> +<AGD>18.750E-6</AGD> +<VT>4.1822</VT> +<KF>.36047</KF> +<CGS>31.942E-9</CGS> +<COXD>53.188E-9</COXD> +<VTD>2.6570 </VTD> +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/PJF.lib b/library/deviceModelLibrary/Templates/PJF.lib new file mode 100644 index 00000000..5589571d --- /dev/null +++ b/library/deviceModelLibrary/Templates/PJF.lib @@ -0,0 +1,5 @@ +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/library/deviceModelLibrary/Templates/PJF.xml b/library/deviceModelLibrary/Templates/PJF.xml new file mode 100644 index 00000000..f682f8cb --- /dev/null +++ b/library/deviceModelLibrary/Templates/PJF.xml @@ -0,0 +1,27 @@ +<library> +<model_name>PJF</model_name> +<ref_model>J2N3820</ref_model> +<param> +<Beta>1.304m </Beta> +<Betatce>-.5</Betatce> +<Rd>1 </Rd> +<Rs>1 </Rs> +<Lambda>2.25m</Lambda> +<Vto>-3</Vto> +<Vtotc>-2.5m </Vtotc> +<Is>33.57f </Is> +<Isr>322.4f</Isr> +<N>1 </N> +<Nr>2 </Nr> +<Xti>3 </Xti> +<Alpha>311.7u</Alpha> +<Vk>243.6 </Vk> +<Cgd>1.6p </Cgd> +<M>.3622 </M> +<Pb>1 </Pb> +<Fc>.5 </Fc> +<Cgs>2.414p </Cgs> +<Kf>9.882E-18</Kf> +<Af>1</Af> +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/PMOS-0.5um.lib b/library/deviceModelLibrary/Templates/PMOS-0.5um.lib new file mode 100644 index 00000000..848e8b05 --- /dev/null +++ b/library/deviceModelLibrary/Templates/PMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u ++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 ++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 ++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 ++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 ++ NSUB=1.0E17 )
\ No newline at end of file diff --git a/library/deviceModelLibrary/Templates/PMOS-0.5um.xml b/library/deviceModelLibrary/Templates/PMOS-0.5um.xml new file mode 100644 index 00000000..013d461c --- /dev/null +++ b/library/deviceModelLibrary/Templates/PMOS-0.5um.xml @@ -0,0 +1,32 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>mos_p</ref_model> +<param> +<TPG>-1 </TPG> +<TOX>9.5n </TOX> +<CJ>950u </CJ> +<ETA>0.025 </ETA> +<VMAX>0.3u </VMAX> +<GAMMA>0.52 </GAMMA> +<CGSO>0.35n </CGSO> +<LD>70n </LD> +<MJSW>0.25 </MJSW> +<PB>1 </PB> +<CGBO>0.45n </CGBO> +<XJ>0.2U </XJ> +<CGDO>0.35n </CGDO> +<KAPPA>8.0 </KAPPA> +<LEVEL>3 </LEVEL> +<VTO>-0.6 </VTO> +<NFS>6.50E11 </NFS> +<THETA>0.2 </THETA> +<CJSW>0.2n </CJSW> +<PHI>0.7 </PHI> +<RSH>2.5 </RSH> +<MJ>0.5</MJ> +<UO>130 </UO> +<KP>48u </KP> +<DELTA>0.25 </DELTA> +<NSUB>1.0E17</NSUB> +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/PMOS-180nm.lib b/library/deviceModelLibrary/Templates/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/deviceModelLibrary/Templates/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/deviceModelLibrary/Templates/PMOS-180nm.xml b/library/deviceModelLibrary/Templates/PMOS-180nm.xml new file mode 100644 index 00000000..6696752d --- /dev/null +++ b/library/deviceModelLibrary/Templates/PMOS-180nm.xml @@ -0,0 +1,112 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>CMOSP</ref_model> +<param> +<LEVEL>8 </LEVEL> +<VERSION>3.2 </VERSION> +<TNOM>27 </TNOM> +<TOX>4.1E-9 </TOX> +<XJ>1E-7 </XJ> +<NCH>4.1589E17 </NCH> +<VTH0>-0.3938813 </VTH0> +<K1>0.5479015</K1> +<K2>0.0360586 </K2> +<K3>0.0993095 </K3> +<K3B>5.7086622</K3B> +<W0>1E-6 </W0> +<NLX>1.313191E-7 </NLX> +<DVT0W>0 </DVT0W> +<DVT1W>0 </DVT1W> +<DVT2W>0 </DVT2W> +<DVT0>0.4911363</DVT0> +<DVT1>0.2227356</DVT1> +<DVT2>0.1 </DVT2> +<U0>115.6852975 </U0> +<UA>1.505832E-9</UA> +<UB>1E-21 </UB> +<UC>-1E-10 </UC> +<VSAT>1.329694E5 </VSAT> +<A0>1.7590478 </A0> +<AGS>0.3641621 </AGS> +<B0>3.427126E-7 </B0> +<B1>1.062928E-6 </B1> +<KETA>0.0134667 </KETA> +<A1>0.6859506 </A1> +<A2>0.3506788 </A2> +<RDSW>168.5705677</RDSW> +<PRWG>0.5 </PRWG> +<PRWB>-0.4987371 </PRWB> +<WR>1 </WR> +<WINT>0 </WINT> +<LINT>3.028832E-8 </LINT> +<XL>0 </XL> +<XW>-1E-8 </XW> +<DWG>-2.349633E-8 </DWG> +<DWB>-7.152486E-9 </DWB> +<VOFF>-0.0994037 </VOFF> +<NFACTOR>1.9424315 </NFACTOR> +<CIT>0 </CIT> +<CDSC>2.4E-4 </CDSC> +<CDSCD>0 </CDSCD> +<CDSCB>0 </CDSCB> +<ETA0>0.0608072 </ETA0> +<ETAB>-0.0426148</ETAB> +<DSUB>0.7343015 </DSUB> +<PCLM>3.2579974 </PCLM> +<PDIBLC1>7.229527E-6 </PDIBLC1> +<PDIBLC2>0.025389 </PDIBLC2> +<PDIBLCB>-1E-3 </PDIBLCB> +<DROUT>0 </DROUT> +<PSCBE1>1.454878E10</PSCBE1> +<PSCBE2>4.202027E-9 </PSCBE2> +<PVAG>15 </PVAG> +<DELTA>0.01 </DELTA> +<RSH>7.8 </RSH> +<MOBMOD>1 </MOBMOD> +<PRT>0 </PRT> +<UTE>-1.5 </UTE> +<KT1>-0.11 </KT1> +<KT1L>0 </KT1L> +<KT2>0.022 </KT2> +<UA1>4.31E-9</UA1> +<UB1>-7.61E-18 </UB1> +<UC1>-5.6E-11 </UC1> +<AT>3.3E4 </AT> +<WL>0 </WL> +<WLN>1 </WLN> +<WW>0 </WW> +<WWN>1 </WWN> +<WWL>0 </WWL> +<LL>0 </LL> +<LLN>1 </LLN> +<LW>0 </LW> +<LWN>1 </LWN> +<LWL>0 </LWL> +<CAPMOD>2 </CAPMOD> +<XPART>0.5</XPART> +<CGDO>6.32E-10 </CGDO> +<CGSO>6.32E-10 </CGSO> +<CGBO>1E-12 </CGBO> +<CJ>1.172138E-3 </CJ> +<PB>0.8421173 </PB> +<MJ>0.4109788 </MJ> +<CJSW>2.242609E-10 </CJSW> +<PBSW>0.8</PBSW> +<MJSW>0.3752089 </MJSW> +<CJSWG>4.22E-10 </CJSWG> +<PBSWG>0.8 </PBSWG> +<MJSWG>0.3752089 </MJSWG> +<CF>0 </CF> +<PVTH0>1.888482E-3 </PVTH0> +<PRDSW>11.5315407 </PRDSW> +<PK2>1.559399E-3 </PK2> +<WKETA>0.0319301 </WKETA> +<LKETA>2.955547E-3 </LKETA> +<PU0>-1.1105313 </PU0> +<PUA>-4.62102E-11</PUA> +<PUB>1E-21 </PUB> +<PVSAT>50 </PVSAT> +<PETA0>1E-4 </PETA0> +<PKETA>-4.346368E-3 </PKETA> +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/PMOS-5um.lib b/library/deviceModelLibrary/Templates/PMOS-5um.lib new file mode 100644 index 00000000..9c3ed976 --- /dev/null +++ b/library/deviceModelLibrary/Templates/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/deviceModelLibrary/Templates/PMOS-5um.xml b/library/deviceModelLibrary/Templates/PMOS-5um.xml new file mode 100644 index 00000000..f68bada2 --- /dev/null +++ b/library/deviceModelLibrary/Templates/PMOS-5um.xml @@ -0,0 +1,23 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>mos_p</ref_model> +<param> +<Cgso>0.4n </Cgso> +<Tox>85n </Tox> +<Vto>-1 </Vto> +<phi>0.65</phi> +<Level>1</Level> +<Mj>.5 </Mj> +<UO>250 </UO> +<Cgdo>0.4n </Cgdo> +<Gamma>0.65 </Gamma> +<LAMBDA>0.03 </LAMBDA> +<LD>0.6u </LD> +<JS>1u </JS> +<CJ>0.18m </CJ> +<CJSW>0.6n </CJSW> +<MJSW>0.5 </MJSW> +<PB>0.7 </PB> +<CGBO>0.2n</CGBO> +</param> +</library> diff --git a/library/deviceModelLibrary/Templates/PNP.lib b/library/deviceModelLibrary/Templates/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/deviceModelLibrary/Templates/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/deviceModelLibrary/Templates/PNP.xml b/library/deviceModelLibrary/Templates/PNP.xml new file mode 100644 index 00000000..681b3fd9 --- /dev/null +++ b/library/deviceModelLibrary/Templates/PNP.xml @@ -0,0 +1,33 @@ +<library> +<model_name>PNP</model_name> +<ref_model>Q2N2907A</ref_model> +<param> +<Is>650.6E-18</Is> +<Xti>3 </Xti> +<Eg>1.11 </Eg> +<Vaf>115.7 </Vaf> +<Bf>231.7 </Bf> +<Ne>1.829</Ne> +<Ise>54.81f </Ise> +<Ikf>1.079 </Ikf> +<Xtb>1.5 </Xtb> +<Br>3.563 </Br> +<Nc>2 </Nc> +<Isc>0 </Isc> +<Ikr>0</Ikr> +<Rc>.715</Rc> +<Cjc>14.76p </Cjc> +<Mjc>.5383 </Mjc> +<Vjc>.75 </Vjc> +<Fc>.5 </Fc> +<Cje>19.82p </Cje> +<Mje>.3357 </Mje> +<Vje>.75</Vje> +<Tr>111.3n </Tr> +<Tf>603.7p </Tf> +<Itf>.65 </Itf> +<Vtf>5 </Vtf> +<Xtf>1.7 </Xtf> +<Rb>10</Rb> +</param> +</library> diff --git a/library/deviceModelLibrary/Transistor/BC547B.lib b/library/deviceModelLibrary/Transistor/BC547B.lib new file mode 100644 index 00000000..723537a7 --- /dev/null +++ b/library/deviceModelLibrary/Transistor/BC547B.lib @@ -0,0 +1 @@ +.model BC547B NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14 NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56 RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8) diff --git a/library/deviceModelLibrary/Transistor/BC547B.xml b/library/deviceModelLibrary/Transistor/BC547B.xml new file mode 100644 index 00000000..da06e5c4 --- /dev/null +++ b/library/deviceModelLibrary/Transistor/BC547B.xml @@ -0,0 +1 @@ +<library><model_name>NPN</model_name><ref_model>BC547B</ref_model><param><Vtf>1.7 </Vtf><Cjc>7.306p </Cjc><Nc>2 </Nc><Tr>46.91n </Tr><Ne>1.307 </Ne><Cje>22.01p </Cje><Isc>0 </Isc><Xtb>1.5 </Xtb><Rb>10 </Rb><Rc>1 </Rc><Tf>411.1p </Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400 </Bf><Fc>.5 </Fc><Ise>14.34f </Ise><Br>6.092 </Br><Ikf>.2847 </Ikf><Mje>.377 </Mje><Mjc>.3416 </Mjc><Vaf>74.03 </Vaf><Vjc>.75 </Vjc><Vje>.75 </Vje><Xtf>3 </Xtf><Itf>.6 </Itf><Is>14.34f </Is><Eg>1.11 </Eg></param></library>
\ No newline at end of file diff --git a/library/deviceModelLibrary/Transistor/NPN.lib b/library/deviceModelLibrary/Transistor/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/deviceModelLibrary/Transistor/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/deviceModelLibrary/Transistor/NPN.xml b/library/deviceModelLibrary/Transistor/NPN.xml new file mode 100644 index 00000000..ee2abcbc --- /dev/null +++ b/library/deviceModelLibrary/Transistor/NPN.xml @@ -0,0 +1 @@ +<library><model_name>NPN</model_name><ref_model>Q2N2222</ref_model><param><Vtf>1.7 </Vtf><Cjc>7.306p </Cjc><Nc>2 </Nc><Tr>46.91n </Tr><Ne>1.307 </Ne><Cje>22.01p </Cje><Vjc>.75 </Vjc><Xtb>1.5 </Xtb><Rb>10 </Rb><Rc>1 </Rc><Tf>411.1p </Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400</Bf><Fc>.5 </Fc><Ikf>.2847 </Ikf><Br>6.092 </Br><Mje>.377 </Mje><Mjc>.3416 </Mjc><Vaf>74.03 </Vaf><Isc>0 </Isc><Ise>14.34f </Ise><Xtf>3 </Xtf><Vje>.75 </Vje><Is>14.34f </Is><Itf>.6 </Itf><Eg>1.11 </Eg></param></library>
\ No newline at end of file diff --git a/library/deviceModelLibrary/Transistor/PNP.lib b/library/deviceModelLibrary/Transistor/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/deviceModelLibrary/Transistor/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/deviceModelLibrary/Transistor/PNP.xml b/library/deviceModelLibrary/Transistor/PNP.xml new file mode 100644 index 00000000..681b3fd9 --- /dev/null +++ b/library/deviceModelLibrary/Transistor/PNP.xml @@ -0,0 +1,33 @@ +<library> +<model_name>PNP</model_name> +<ref_model>Q2N2907A</ref_model> +<param> +<Is>650.6E-18</Is> +<Xti>3 </Xti> +<Eg>1.11 </Eg> +<Vaf>115.7 </Vaf> +<Bf>231.7 </Bf> +<Ne>1.829</Ne> +<Ise>54.81f </Ise> +<Ikf>1.079 </Ikf> +<Xtb>1.5 </Xtb> +<Br>3.563 </Br> +<Nc>2 </Nc> +<Isc>0 </Isc> +<Ikr>0</Ikr> +<Rc>.715</Rc> +<Cjc>14.76p </Cjc> +<Mjc>.5383 </Mjc> +<Vjc>.75 </Vjc> +<Fc>.5 </Fc> +<Cje>19.82p </Cje> +<Mje>.3357 </Mje> +<Vje>.75</Vje> +<Tr>111.3n </Tr> +<Tf>603.7p </Tf> +<Itf>.65 </Itf> +<Vtf>5 </Vtf> +<Xtf>1.7 </Xtf> +<Rb>10</Rb> +</param> +</library> diff --git a/library/deviceModelLibrary/User Libraries/userDiode.lib b/library/deviceModelLibrary/User Libraries/userDiode.lib new file mode 100644 index 00000000..ef18bb50 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/userDiode.lib @@ -0,0 +1,20 @@ +.MODEL D1N750 D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ Bv=8.1 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=880.5E-18 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/userDiode.xml b/library/deviceModelLibrary/User Libraries/userDiode.xml new file mode 100644 index 00000000..d8584e1d --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/userDiode.xml @@ -0,0 +1 @@ +<library><model_name>D</model_name><ref_model>D1N750</ref_model><param><Is>880.5E-18</Is><Nbvl>14.976</Nbvl><Cjo>175p</Cjo><Rs>.25</Rs><Isr>1.859n</Isr><Eg>1.11</Eg><M>.5516</M><Nbv>1.6989</Nbv><N>1</N><Tbv1>-21.277u</Tbv1><Bv>8.1</Bv><Fc>.5</Fc><Ikf>0</Ikf><Xti>3</Xti><Nr>2</Nr><Vj>.75</Vj><Ibv>20.245m</Ibv><Ibvl>1.9556m</Ibvl></param></library>
\ No newline at end of file diff --git a/library/kicadLibrary.tar.xz b/library/kicadLibrary.tar.xz Binary files differnew file mode 100644 index 00000000..338d3fb9 --- /dev/null +++ b/library/kicadLibrary.tar.xz diff --git a/library/modelParamXML/Analog/aswitch.xml b/library/modelParamXML/Analog/aswitch.xml new file mode 100644 index 00000000..fe50ecd3 --- /dev/null +++ b/library/modelParamXML/Analog/aswitch.xml @@ -0,0 +1,14 @@ +<model> +<name>aswitch</name> +<type>Analog</type> +<node_number>3</node_number> +<title>Add Parameters for Analog Switch</title> +<split>1-NV:2-V</split> +<param> + <cntl_off default="0.0">Enter Control OFF value (default=0.0)</cntl_off> + <cntl_on default="1.0">Enter Control ON value(default=1.0)</cntl_on> + <r_off default="1.0e12">Enter OFF Resistance (default=1.0e12)</r_off> + <r_on default="1.0">Enter ON Resistance (default=1.0)</r_on> + <log default="TRUE">Enter Log (default=TRUE)</log> +</param> +</model> diff --git a/library/modelParamXML/Analog/climit.xml b/library/modelParamXML/Analog/climit.xml new file mode 100644 index 00000000..0d1f9c7e --- /dev/null +++ b/library/modelParamXML/Analog/climit.xml @@ -0,0 +1,15 @@ +<model> +<name>climit</name> +<type>Analog</type> +<node_number>4</node_number> +<title>Add Parameters for Controlled Limiter</title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset> + <gain default="1.0">Enter value for Gain (default=1.0)</gain> + <upper_delta default="0.0">Enter Output Upper Delta (default=0.0)</upper_delta> + <lower_delta default="0.0">Enter Output Lower Delta (default=0.0)</lower_delta> + <limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range> + <fraction default="false">Enter Fraction (default=false)</fraction> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Analog/d_dt.xml b/library/modelParamXML/Analog/d_dt.xml new file mode 100644 index 00000000..65494392 --- /dev/null +++ b/library/modelParamXML/Analog/d_dt.xml @@ -0,0 +1,14 @@ +<model> +<name>d_dt</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for Differentiator</title> +<split>None</split> +<param> + <gain default="1.0">Enter value for Gain (default=1.0)</gain> + <out_offset default="0.0">Enter offset for Output (default=0.0)</out_offset> + <out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit> + <out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit> + <limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range> +</param> +</model> diff --git a/library/modelParamXML/Analog/divide.xml b/library/modelParamXML/Analog/divide.xml new file mode 100644 index 00000000..d501ae4e --- /dev/null +++ b/library/modelParamXML/Analog/divide.xml @@ -0,0 +1,18 @@ +<model> +<name>divide</name> +<type>Analog</type> +<node_number>3</node_number> +<title>Add Parameters for Multiplier</title> +<split>None</split> +<param> + <num_offset default="0.0">Enter offset for Numerator (default=0.0)</num_offset> + <num_gain default="1.0">Enter gain for Numerator (default=1.0)</num_gain> + <den_offset default="0.0">Enter offset for Denominator (default=0.0)</den_offset> + <den_gain default="1.0">Enter gain for Denominator (default=1.0)</den_gain> + <den_lower_limit default="1.0e-10">Enter Denominator Lower Limit (default=1.0e-10)</den_lower_limit> + <den_domain default="1.0e-10">Enter Denominator Domain (default=1.0e-10)</den_domain> + <fraction default="false">Enter Fraction (default=false)</fraction> + <out_gain default="1.0">Enter gain for output (default=1.0)</out_gain> + <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> +</param> +</model> diff --git a/library/modelParamXML/Analog/gain.xml b/library/modelParamXML/Analog/gain.xml new file mode 100644 index 00000000..a8656072 --- /dev/null +++ b/library/modelParamXML/Analog/gain.xml @@ -0,0 +1,12 @@ +<model> +<name>gain</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for model Gain</title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for input (default=0.0)</in_offset> + <gain vector="1" default="1.0">Enter gain (default=1.0)</gain> + <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Analog/hyst.xml b/library/modelParamXML/Analog/hyst.xml new file mode 100644 index 00000000..56a60c0f --- /dev/null +++ b/library/modelParamXML/Analog/hyst.xml @@ -0,0 +1,16 @@ +<model> +<name>hyst</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for Hysteresis</title> +<split>None</split> +<param> + <in_low default="0.0">Enter Input Low Value (default=0.0)</in_low> + <in_high default="1.0">Enter Input High Value (default=1.0)</in_high> + <hyst default="0.1">Enter Hysteresis (default=0.1)</hyst> + <out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit> + <out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit> + <input_domain default="0.01">Enter Input Domain Value (default=0.01)</input_domain> + <fraction default="TRUE">Enter Fraction (default=TRUE)</fraction> +</param> +</model> diff --git a/library/modelParamXML/Analog/ilimit.xml b/library/modelParamXML/Analog/ilimit.xml new file mode 100644 index 00000000..32b2149f --- /dev/null +++ b/library/modelParamXML/Analog/ilimit.xml @@ -0,0 +1,19 @@ +<model> +<name>ilimit</name> +<type>Analog</type> +<node_number>4</node_number> +<title>Add Parameters for Current Limiter </title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset> + <gain default="1.0">Enter value for Gain (default=1.0)</gain> + <r_out_source default="1.0">Enter value for Sourcing Resistance (default=1.0)</r_out_source> + <r_out_sink default="1.0">Enter value for Sinking Resistance (default=1.0)</r_out_sink> + <i_limit_source default="1.0e-12">Enter Current Sourcing Limit (default=1.0e-12)</i_limit_source> + <i_limit_sink default="1.0e-12">Enter Current Sinking Limit (default=1.0e-12)</i_limit_sink> + <v_pwr_range default="1.0e-6">Enter Power Supply Range (default=1.0e-6)</v_pwr_range> + <i_source_range default="1.0e-9">Enter Current Sourcing Range (default=1.0e-9)</i_source_range> + <i_sink_range default="1.0e-9">Enter Current Sinking Range (default=1.0e-9)</i_sink_range> + <r_out_domain default="1.0e-9">Enter Voltage Delta Range (default=1.0e-9)</r_out_domain> +</param> +</model> diff --git a/library/modelParamXML/Analog/int.xml b/library/modelParamXML/Analog/int.xml new file mode 100644 index 00000000..6ccec625 --- /dev/null +++ b/library/modelParamXML/Analog/int.xml @@ -0,0 +1,15 @@ +<model> +<name>int</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for int</title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset> + <gain default="1.0">Enter value for Gain (default=1.0)</gain> + <out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit> + <out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit> + <limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range> + <out_ic default="0.0">Enter Output Initial Condition (default=0.0)</out_ic> +</param> +</model> diff --git a/library/modelParamXML/Analog/limit.xml b/library/modelParamXML/Analog/limit.xml new file mode 100644 index 00000000..c2a1f382 --- /dev/null +++ b/library/modelParamXML/Analog/limit.xml @@ -0,0 +1,15 @@ +<model> +<name>limit</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for Limiter</title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset> + <gain default="1.0">Enter value for Gain (default=1.0)</gain> + <out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit> + <out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit> + <limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range> + <fraction default="false">Enter Fraction (default=false)</fraction> +</param> +</model> diff --git a/library/modelParamXML/Analog/mult.xml b/library/modelParamXML/Analog/mult.xml new file mode 100644 index 00000000..e41463ff --- /dev/null +++ b/library/modelParamXML/Analog/mult.xml @@ -0,0 +1,13 @@ +<model> +<name>mult</name> +<type>Analog</type> +<node_number>3</node_number> +<title>Add Parameters for Multiplier</title> +<split>2-V:1-NV</split> +<param> + <in_offset vector="2" default="0.0">Enter offset for input (default=0.0)</in_offset> + <in_gain vector="2" default="1.0">Enter gain for input(default=1.0)</in_gain> + <out_gain default="1.0">Enter gain for output (default=1.0)</out_gain> + <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> +</param> +</model> diff --git a/library/modelParamXML/Analog/slew.xml b/library/modelParamXML/Analog/slew.xml new file mode 100644 index 00000000..2eafde2d --- /dev/null +++ b/library/modelParamXML/Analog/slew.xml @@ -0,0 +1,12 @@ +<model> +<name>slew</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for slew</title> +<split>None</split> +<param> + <rise_slope default="1.0e9">Enter Rising Slope Value (default=1.0e9)</rise_slope> + <fall_slop default="1.0e9">Enter Falling Slope Value (default=1.0e9)</fall_slop> + <range default="0.1">Enter Range (default=0.1)</range> +</param> +</model> diff --git a/library/modelParamXML/Analog/summer.xml b/library/modelParamXML/Analog/summer.xml new file mode 100644 index 00000000..d9856b62 --- /dev/null +++ b/library/modelParamXML/Analog/summer.xml @@ -0,0 +1,13 @@ +<model> +<name>summer</name> +<type>Analog</type> +<node_number>3</node_number> +<title>Add Parameters for Summer</title> +<split>2-V:1-NV</split> +<param> + <in_offset vector="2" default="0.0">Enter offset for input (default=0.0)</in_offset> + <in_gain vector="2" default="1.0">Enter gain for input(default=1.0)</in_gain> + <out_gain default="1.0">Enter gain for output (default=1.0)</out_gain> + <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> +</param> +</model> diff --git a/library/modelParamXML/Analog/temp.xml b/library/modelParamXML/Analog/temp.xml new file mode 100644 index 00000000..20f00004 --- /dev/null +++ b/library/modelParamXML/Analog/temp.xml @@ -0,0 +1,12 @@ +<model> +<name>gain</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameter for model gain</title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for input (default=0.0)</in_offset> + <gain vector="2" default="1.0">Enter gain (default=1.0)</gain> + <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Analog/zener.xml b/library/modelParamXML/Analog/zener.xml new file mode 100644 index 00000000..c6e32c36 --- /dev/null +++ b/library/modelParamXML/Analog/zener.xml @@ -0,0 +1,14 @@ +<model> +<name>zener</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for Zener Diode</title> +<split>None</split> +<param> + <v_breakdown default="5.6">Enter Breakdown Voltage (default=5.6)</v_breakdown> + <i_breakdown default="2.0e-2">Enter Breakdown Current (default=2.0e-2)</i_breakdown> + <i_sat default="1.0e-12">Enter Saturation Current (default=1.0e-12)</i_sat> + <n_forward default="1.0">Enter Forward Emission Coefficient (default=1.0)</n_forward> + <limit_switch default="FALSE">Enter Switch for Limiting (default=FALSE)</limit_switch> +</param> +</model> diff --git a/library/modelParamXML/Digital/d_and.xml b/library/modelParamXML/Digital/d_and.xml new file mode 100644 index 00000000..cd4a1c76 --- /dev/null +++ b/library/modelParamXML/Digital/d_and.xml @@ -0,0 +1,12 @@ +<model> +<name>d_and</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for And Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_buffer.xml b/library/modelParamXML/Digital/d_buffer.xml new file mode 100644 index 00000000..e0661910 --- /dev/null +++ b/library/modelParamXML/Digital/d_buffer.xml @@ -0,0 +1,12 @@ +<model> +<name>d_buffer</name> +<type>Digital</type> +<node_number>2</node_number> +<title>Add Parameters for Buffer</title> +<split>None</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_dff.xml b/library/modelParamXML/Digital/d_dff.xml new file mode 100644 index 00000000..d5010e02 --- /dev/null +++ b/library/modelParamXML/Digital/d_dff.xml @@ -0,0 +1,19 @@ +<model> +<name>d_dff</name> +<type>Digital</type> +<node_number>6</node_number> +<title>Add Parameters for D Flipflop</title> +<split>None</split> +<param> + <clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <data_load default ="1.0e-12">Enter value for Data Load (default=1.0e-12)</data_load> + <clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_dlatch.xml b/library/modelParamXML/Digital/d_dlatch.xml new file mode 100644 index 00000000..34e26418 --- /dev/null +++ b/library/modelParamXML/Digital/d_dlatch.xml @@ -0,0 +1,20 @@ +<model> +<name>d_dlatch</name> +<type>Digital</type> +<node_number>6</node_number> +<title>Add Parameters for D Latch</title> +<split>None</split> +<param> + <data_delay default ="1.0e-9">Enter Data Delay (default=1.0e-9)</data_delay> + <enable_delay default ="1.0e-9">Enter Enable Delay (default=1.0e-9)</enable_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0e-9">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <data_load default ="1.0e-12">Enter value for Data Load (default=1.0e-12)</data_load> + <enable_load default ="1.0e-12">Enter value for Enable Load (default=1.0e-12)</enable_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_fdiv.xml b/library/modelParamXML/Digital/d_fdiv.xml new file mode 100644 index 00000000..bab4f0d6 --- /dev/null +++ b/library/modelParamXML/Digital/d_fdiv.xml @@ -0,0 +1,15 @@ +<model> +<name>d_fdiv</name> +<type>Digital</type> +<node_number>2</node_number> +<title>Add Parameters for Frequency Divider</title> +<split>None</split> +<param> + <div_factor default ="2">Enter Divide Factor (default=2)</div_factor> + <high_cycles default ="1">Enter value for High Cycles (default=1)</high_cycles> + <i_count default = "0">Enter Initial Count (default=0)</i_count> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <freq_in_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</freq_in_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_inverter.xml b/library/modelParamXML/Digital/d_inverter.xml new file mode 100644 index 00000000..e104712a --- /dev/null +++ b/library/modelParamXML/Digital/d_inverter.xml @@ -0,0 +1,12 @@ +<model> +<name>d_inverter</name> +<type>Digital</type> +<node_number>2</node_number> +<title>Add Parameters for Inverter</title> +<split>None</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_jkff.xml b/library/modelParamXML/Digital/d_jkff.xml new file mode 100644 index 00000000..78ce59cd --- /dev/null +++ b/library/modelParamXML/Digital/d_jkff.xml @@ -0,0 +1,19 @@ +<model> +<name>d_jkff</name> +<type>Digital</type> +<node_number>7</node_number> +<title>Add Parameters for JK Flipflop</title> +<split>None</split> +<param> + <clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <jk_load default ="1.0e-12">Enter value for JK Load (default=1.0e-12)</jk_load> + <clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_nand.xml b/library/modelParamXML/Digital/d_nand.xml new file mode 100644 index 00000000..0041419a --- /dev/null +++ b/library/modelParamXML/Digital/d_nand.xml @@ -0,0 +1,12 @@ +<model> +<name>d_nand</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Nand Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_nor.xml b/library/modelParamXML/Digital/d_nor.xml new file mode 100644 index 00000000..17a60fd5 --- /dev/null +++ b/library/modelParamXML/Digital/d_nor.xml @@ -0,0 +1,12 @@ +<model> +<name>d_nor</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Nor Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_or.xml b/library/modelParamXML/Digital/d_or.xml new file mode 100644 index 00000000..8362e1b3 --- /dev/null +++ b/library/modelParamXML/Digital/d_or.xml @@ -0,0 +1,12 @@ +<model> +<name>d_or</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Or Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_pulldown.xml b/library/modelParamXML/Digital/d_pulldown.xml new file mode 100644 index 00000000..affd1745 --- /dev/null +++ b/library/modelParamXML/Digital/d_pulldown.xml @@ -0,0 +1,10 @@ +<model> +<name>d_pulldown</name> +<type>Digital</type> +<node_number>1</node_number> +<title>Add Parameters for Pulldown</title> +<split>None</split> +<param> + <load default="1.0e-12">Enter value of Load</load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_pullup.xml b/library/modelParamXML/Digital/d_pullup.xml new file mode 100644 index 00000000..1ce491ff --- /dev/null +++ b/library/modelParamXML/Digital/d_pullup.xml @@ -0,0 +1,10 @@ +<model> +<name>d_pullup</name> +<type>Digital</type> +<node_number>1</node_number> +<title>Add Parameters for Pullup</title> +<split>None</split> +<param> + <load default="1.0e-12">Enter value of Load</load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_ram.xml b/library/modelParamXML/Digital/d_ram.xml new file mode 100644 index 00000000..73074201 --- /dev/null +++ b/library/modelParamXML/Digital/d_ram.xml @@ -0,0 +1,16 @@ +<model> +<name>d_ram</name> +<type>Digital</type> +<node_number>5</node_number> +<title>Add Parameters for RAM</title> +<split>4-V:4-V:8-V:1-NV:3-V</split> +<param> + <select_value default ="1">Enter Select Value (default=1)</select_value> + <ic default ="2">Enter IC (default=2)</ic> + <read_delay default ="100.0e-9">Enter Read Delay (default=100.0e-9)</read_delay> + <data_load default ="1.0e-12">Enter value for Data Load (default=1.0e-12)</data_load> + <address_load default ="1.0e-12">Enter value for Address Load (default=1.0e-12)</address_load> + <select_load default ="1.0e-12">Enter value for Select Load (default=1.0e-12)</select_load> + <enable_load default ="1.0e-12">Enter value for Enable Load (default=1.0e-12)</enable_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_source.xml b/library/modelParamXML/Digital/d_source.xml new file mode 100644 index 00000000..9bd4347c --- /dev/null +++ b/library/modelParamXML/Digital/d_source.xml @@ -0,0 +1,11 @@ +<model> +<name>d_source</name> +<type>Digital</type> +<node_number>1</node_number> +<title>Add Parameters for Digital Source</title> +<split>4-V</split> +<param> + <input_file default ="source.txt">Enter Input File (default=source.txt)</input_file> + <input_load default ="1.0e-12">Enter Input Load</input_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_srff.xml b/library/modelParamXML/Digital/d_srff.xml new file mode 100644 index 00000000..9eb65175 --- /dev/null +++ b/library/modelParamXML/Digital/d_srff.xml @@ -0,0 +1,19 @@ +<model> +<name>d_srff</name> +<type>Digital</type> +<node_number>7</node_number> +<title>Add Parameters for SR Flipflop</title> +<split>None</split> +<param> + <clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <sr_load default ="1.0e-12">Enter value for SR Load (default=1.0e-12)</sr_load> + <clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_srlatch.xml b/library/modelParamXML/Digital/d_srlatch.xml new file mode 100644 index 00000000..35dbc061 --- /dev/null +++ b/library/modelParamXML/Digital/d_srlatch.xml @@ -0,0 +1,20 @@ +<model> +<name>d_srlatch</name> +<type>Digital</type> +<node_number>7</node_number> +<title>Add Parameters for SR Latch</title> +<split>None</split> +<param> + <sr_delay default ="1.0e-9">Enter SR Delay (default=1.0e-9)</sr_delay> + <enable_delay default ="1.0e-9">Enter Enable Delay (default=1.0e-9)</enable_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0e-9">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <sr_load default ="1.0e-12">Enter value for SR Load (default=1.0e-12)</sr_load> + <enable_load default ="1.0e-12">Enter value for Enable Load (default=1.0e-12)</enable_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_state.xml b/library/modelParamXML/Digital/d_state.xml new file mode 100644 index 00000000..2290a117 --- /dev/null +++ b/library/modelParamXML/Digital/d_state.xml @@ -0,0 +1,16 @@ +<model> +<name>d_state</name> +<type>Digital</type> +<node_number>4</node_number> +<title>Add Parameters for State Machine</title> +<split>4-V:2-NV:8-V</split> +<param> + <clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay> + <reset_delay default ="1.0e-9">Enter Reset Delay (default=1.0e-9)</reset_delay> + <state_file default ="state.txt">Enter State File (default=state.txt)</state_file> + <reset_state default ="0">Enter Reset Value (default=0)</reset_state> + <input_load default ="1.0e-12">Enter value for Input Load (default=1.0e-12)</input_load> + <clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_tff.xml b/library/modelParamXML/Digital/d_tff.xml new file mode 100644 index 00000000..ed519d2c --- /dev/null +++ b/library/modelParamXML/Digital/d_tff.xml @@ -0,0 +1,19 @@ +<model> +<name>d_tff</name> +<type>Digital</type> +<node_number>6</node_number> +<title>Add Parameters for T Flipflop</title> +<split>None</split> +<param> + <clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <t_load default ="1.0e-12">Enter value for T Load (default=1.0e-12)</t_load> + <clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_tristate.xml b/library/modelParamXML/Digital/d_tristate.xml new file mode 100644 index 00000000..2835da30 --- /dev/null +++ b/library/modelParamXML/Digital/d_tristate.xml @@ -0,0 +1,12 @@ +<model> +<name>d_tristate</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Tristate Buffer</title> +<split>None</split> +<param> + <delay default ="1.0e-9">Enter Delay (default=1.0e-9)</delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> + <enable_load default ="1.0e-12">Enter Enable Load (default=1.0e-12)</enable_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_xnor.xml b/library/modelParamXML/Digital/d_xnor.xml new file mode 100644 index 00000000..4b27bc4c --- /dev/null +++ b/library/modelParamXML/Digital/d_xnor.xml @@ -0,0 +1,12 @@ +<model> +<name>d_xnor</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Xnor Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Digital/d_xor.xml b/library/modelParamXML/Digital/d_xor.xml new file mode 100644 index 00000000..ab238c6d --- /dev/null +++ b/library/modelParamXML/Digital/d_xor.xml @@ -0,0 +1,12 @@ +<model> +<name>d_xor</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Xor Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/adc_bridge_1.xml b/library/modelParamXML/Hybrid/adc_bridge_1.xml new file mode 100644 index 00000000..8d84cd01 --- /dev/null +++ b/library/modelParamXML/Hybrid/adc_bridge_1.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>1-V:1-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model> diff --git a/library/modelParamXML/Hybrid/adc_bridge_2.xml b/library/modelParamXML/Hybrid/adc_bridge_2.xml new file mode 100644 index 00000000..1e0ced95 --- /dev/null +++ b/library/modelParamXML/Hybrid/adc_bridge_2.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>2-V:2-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/adc_bridge_3.xml b/library/modelParamXML/Hybrid/adc_bridge_3.xml new file mode 100644 index 00000000..09d41850 --- /dev/null +++ b/library/modelParamXML/Hybrid/adc_bridge_3.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>3-V:3-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/adc_bridge_4.xml b/library/modelParamXML/Hybrid/adc_bridge_4.xml new file mode 100644 index 00000000..b29201f5 --- /dev/null +++ b/library/modelParamXML/Hybrid/adc_bridge_4.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>4-V:4-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/adc_bridge_5.xml b/library/modelParamXML/Hybrid/adc_bridge_5.xml new file mode 100644 index 00000000..bdacf1db --- /dev/null +++ b/library/modelParamXML/Hybrid/adc_bridge_5.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>5-V:5-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/adc_bridge_6.xml b/library/modelParamXML/Hybrid/adc_bridge_6.xml new file mode 100644 index 00000000..ee60247f --- /dev/null +++ b/library/modelParamXML/Hybrid/adc_bridge_6.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>6-V:6-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/adc_bridge_7.xml b/library/modelParamXML/Hybrid/adc_bridge_7.xml new file mode 100644 index 00000000..df96b366 --- /dev/null +++ b/library/modelParamXML/Hybrid/adc_bridge_7.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>7-V:7-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/adc_bridge_8.xml b/library/modelParamXML/Hybrid/adc_bridge_8.xml new file mode 100644 index 00000000..cdd7afaa --- /dev/null +++ b/library/modelParamXML/Hybrid/adc_bridge_8.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>8-V:8-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/dac_bridge_1.xml b/library/modelParamXML/Hybrid/dac_bridge_1.xml new file mode 100644 index 00000000..c9e4eed1 --- /dev/null +++ b/library/modelParamXML/Hybrid/dac_bridge_1.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>1-V:1-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model> diff --git a/library/modelParamXML/Hybrid/dac_bridge_2.xml b/library/modelParamXML/Hybrid/dac_bridge_2.xml new file mode 100644 index 00000000..c67b22bf --- /dev/null +++ b/library/modelParamXML/Hybrid/dac_bridge_2.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>2-V:2-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/dac_bridge_3.xml b/library/modelParamXML/Hybrid/dac_bridge_3.xml new file mode 100644 index 00000000..d080f94d --- /dev/null +++ b/library/modelParamXML/Hybrid/dac_bridge_3.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>3-V:3-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/dac_bridge_4.xml b/library/modelParamXML/Hybrid/dac_bridge_4.xml new file mode 100644 index 00000000..988b575a --- /dev/null +++ b/library/modelParamXML/Hybrid/dac_bridge_4.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>4-V:4-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/dac_bridge_5.xml b/library/modelParamXML/Hybrid/dac_bridge_5.xml new file mode 100644 index 00000000..39d8f2d2 --- /dev/null +++ b/library/modelParamXML/Hybrid/dac_bridge_5.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>5-V:5-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/dac_bridge_6.xml b/library/modelParamXML/Hybrid/dac_bridge_6.xml new file mode 100644 index 00000000..2016f971 --- /dev/null +++ b/library/modelParamXML/Hybrid/dac_bridge_6.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>6-V:6-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/dac_bridge_7.xml b/library/modelParamXML/Hybrid/dac_bridge_7.xml new file mode 100644 index 00000000..37fb936b --- /dev/null +++ b/library/modelParamXML/Hybrid/dac_bridge_7.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>7-V:7-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Hybrid/dac_bridge_8.xml b/library/modelParamXML/Hybrid/dac_bridge_8.xml new file mode 100644 index 00000000..72644ad9 --- /dev/null +++ b/library/modelParamXML/Hybrid/dac_bridge_8.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>8-V:8-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/library/modelParamXML/Nghdl/.gitignore b/library/modelParamXML/Nghdl/.gitignore new file mode 100644 index 00000000..86d0cb27 --- /dev/null +++ b/library/modelParamXML/Nghdl/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore
\ No newline at end of file diff --git a/library/ngspicetoModelica/Mapping.json b/library/ngspicetoModelica/Mapping.json new file mode 100644 index 00000000..e254d66a --- /dev/null +++ b/library/ngspicetoModelica/Mapping.json @@ -0,0 +1,281 @@ +{ + "Components":{ + "R" : "Analog.Basic.Resistor", + "C" : "Analog.Basic.Capacitor", + "L" : "Analog.Basic.Inductor", + "e" : "Analog.Basic.VCV", + "g" : "Analog.Basic.VCC", + "f" : "Analog.Basic.CCC", + "h" : "Analog.Basic.CCV", + "0" : "Analog.Basic.Ground", + "gnd" : "Analog.Basic.Ground" + + }, + "Sources":{ + "v":{ + "pulse":"Analog.Sources.TrapezoidVoltage", + "sine":"Analog.Sources.SineVoltage", + "pwl" : "Analog.Sources.TableVoltage", + "dc" : "Analog.Sources.ConstantVoltage" + }, + + "i":{ + "dc":"Analog.Sources.ConstantCurrent" + } + + }, + "Devices":{ + "d":{ + "import":"Analog.Semiconductors.Diode", + "mapping":{ + + "is":"Ids" + }, + "default":{ + "Ids":"880.5e-18", + "Vt":"0.025", + "R":"1e12" + } + + }, + + "m":{ + "import":"BondLib.Electrical.Analog.Spice", + "mapping":{ + "tnom":"Tnom", + "vto":"VT0", + "gamma":"GAMMA", + "phi":"PHI", + "ld":"LD", + "uo":"U0", + "lambda":"LAMBDA", + "tox":"TOX", + "pb":"PB", + "cj":"CJ", + "cjsw":"CJSW", + "mj":"MJ", + "mjsw":"MJSW", + "cgdo":"CGD0", + "js":"JS", + "cgbo":"CGB0", + "cgso":"CGS0" + + + }, + "default":{ + "Tnom":"300", + "VT0":"0", + "GAMMA":"0", + "PHI":"0", + "LD":"0", + "U0":"0", + "LAMBDA":"0", + "TOX":"3e-9", + "PB":"0.8", + "CJ":"0", + "CJSW":"1e-9", + "MJ":"0.33", + "MJSW":"0.33", + "CGD0":"0", + "JS":"0", + "CGB0":"0", + "CGS0":"0" + + + } + + }, + "q":{ + "import":"Analog.Semiconductors", + "mapping":{ + "bf":"Bf", + "br":"Br", + "is":"Is", + "vak":"Vak", + "tf":"Tauf", + "tr":"Taur", + "cjs":"Ccs", + "cje":"Cje", + "cjc":"Cjc", + "vje":"Phie", + "mje":"Me", + "vjc":"Phic", + "mjc":"Mc" + }, + "default":{ + "Bf":"50", + "Br":"0.1", + "Is":"1e-16", + "Tauf":"1.2e-10", + "Taur":"5e-9", + "Vak":"0.02", + "Ccs":"1e-12", + "Cje":"4e-12", + "Cjc":"5e-13", + "Phie":"0.8", + "Me":"0.4", + "Phic":"0.8", + "Mc":"0.333" + + } + + }, + + "j":{ + "import":"Spice3.Internal.JFET", + "mapping":{ + "kf":"KF", + "rs":"RS", + "is":"IS", + "cgd":"CGD", + "vto":"VTO", + "rd":"RD", + "pb":"PB", + "beta":"BETA", + "fc":"FC", + "af":"AF", + "cgs":"CGS", + "lambda":"LAMBDA", + "b" : "B" + + }, + + "default":{ + "KF":"0", + "RS":"0", + "IS":"1e-14", + "CGD":"0", + "VTO":"-2", + "RD":"0", + "PB":"1", + "BETA":"1e-4", + "FC":"0.5", + "AF":"1", + "CGS":"0", + "LAMBDA":"0", + "B":"1" + + + } + } + + }, + + + "Models":{ + "zener":{ + "import":"Analog.Semiconductors.ZDiode", + "mapping":{ + "v_breakdown":"Bv", + "i_breakdown":"Ibv", + "i_sat":"Ids", + "n_forward":"Nbv" + + }, + "default":{ + "Ids":"880.5e-18", + "Vt":"0.025", + "R":"1e12", + "Bv":"8.1", + "Ibv":"0.020245", + "Nbv":"1.6989" + + } + + } + }, + + "Units":{ + "k":"e3", + "u":"e-6", + "p":"e-12", + "t":"e12", + "f":"e-15", + "g":"e9", + "m":"e-3", + "meg":"e6", + "n":"e-9", + + "v":"", + "a":"", + "s":"", + "hz":"", + "ohm":"", + "mho":"", + "h":"", + + + "kv":"e3", + "ka":"e3", + "ks":"e3", + "khz":"e3", + "kohm":"e3", + "kmho":"e3", + "kh":"e3", + + + "uv":"e-06", + "ua":"e-06", + "us":"e-06", + "uhz":"e-06", + "uohm":"e-06", + "umho":"e-06", + "uh":"e-06", + + "pv":"e-12", + "pa":"e-12", + "ps":"e-12", + "phz":"e-12", + "pohm":"e-12", + "pmho":"e-12", + "ph":"e-12", + + + "tv":"e12", + "ta":"e12", + "ts":"e12", + "thz":"e12", + "tohm":"e12", + "tmho":"e12", + "th":"e12", + + + "gv":"e9", + "ga":"e9", + "gs":"e9", + "ghz":"e9", + "gohm":"e9", + "gmho":"e9", + "gh":"e9", + + + "mv":"e-03", + "ma":"e-03", + "ms":"e-03", + "mhz":"e-03", + "mohm":"e-03", + "mmho":"e-03", + "mh":"e-03", + + + "megv":"e06", + "mega":"e06", + "megs":"e06", + "meghz":"e06", + "megohm":"e06", + "megmho":"e06", + "megh":"e06", + + + + "nv":"e-09", + "na":"e-09", + "ns":"e-09", + "nhz":"e-09", + "nohm":"e-09", + "nmho":"e-09", + "nh":"e-09" + + } + +} diff --git a/library/supportFiles/fp-lib-table b/library/supportFiles/fp-lib-table new file mode 100644 index 00000000..ff605eaf --- /dev/null +++ b/library/supportFiles/fp-lib-table @@ -0,0 +1,92 @@ +(fp_lib_table + (lib (name Battery_Holders)(type KiCad)(uri ${KISYSMOD}/Battery_Holders.pretty)(options "")(descr "Batteries and battery holders")) + (lib (name Buttons_Switches_SMD)(type KiCad)(uri ${KISYSMOD}/Buttons_Switches_SMD.pretty)(options "")(descr "Buttons and switches, surface mount")) + (lib (name Buttons_Switches_THT)(type KiCad)(uri ${KISYSMOD}/Buttons_Switches_THT.pretty)(options "")(descr "Buttons and switches, through hole")) + (lib (name Buzzers_Beepers)(type KiCad)(uri ${KISYSMOD}/Buzzers_Beepers.pretty)(options "")(descr "Audio signalling devices")) + (lib (name Capacitors_SMD)(type KiCad)(uri ${KISYSMOD}/Capacitors_SMD.pretty)(options "")(descr "Capacitors, surface mount")) + (lib (name Capacitors_Tantalum_SMD)(type KiCad)(uri ${KISYSMOD}/Capacitors_Tantalum_SMD.pretty)(options "")(descr "Tantalum capacitors, surface mount")) + (lib (name Capacitors_THT)(type KiCad)(uri ${KISYSMOD}/Capacitors_THT.pretty)(options "")(descr "Capacitors, through hole")) + (lib (name Connectors_Card)(type KiCad)(uri ${KISYSMOD}/Connectors_Card.pretty)(options "")(descr "Footprints for cards and card holders")) + (lib (name Connectors_Harwin)(type KiCad)(uri ${KISYSMOD}/Connectors_Harwin.pretty)(options "")(descr "Harwin connector footprints www.harwin.com")) + (lib (name Connectors_HDMI)(type KiCad)(uri ${KISYSMOD}/Connectors_HDMI.pretty)(options "")(descr "HDMI connector footprints")) + (lib (name Connectors_Hirose)(type KiCad)(uri ${KISYSMOD}/Connectors_Hirose.pretty)(options "")(descr "Hirose connector footprints www.hirose.com")) + (lib (name Connectors_IEC_DIN)(type KiCad)(uri ${KISYSMOD}/Connectors_IEC_DIN.pretty)(options "")(descr "DIN connector footprints")) + (lib (name Connectors_JAE)(type KiCad)(uri ${KISYSMOD}/Connectors_JAE.pretty)(options "")(descr "JAE connector footprints http://www.jae.com/jccom/en/connectors")) + (lib (name Connectors_JST)(type KiCad)(uri ${KISYSMOD}/Connectors_JST.pretty)(options "")(descr "JST connector footprints www.jst.com")) + (lib (name Connectors_Mini-Universal)(type KiCad)(uri ${KISYSMOD}/Connectors_Mini-Universal.pretty)(options "")(descr Mate-N-Lok)) + (lib (name Connectors_Molex)(type KiCad)(uri ${KISYSMOD}/Connectors_Molex.pretty)(options "")(descr "Molex connector foottprints www.molex.com")) + (lib (name Connectors_Multicomp)(type KiCad)(uri ${KISYSMOD}/Connectors_Multicomp.pretty)(options "")(descr "Multicomp connector footprints")) + (lib (name Connectors_Phoenix)(type KiCad)(uri ${KISYSMOD}/Connectors_Phoenix.pretty)(options "")(descr "Phoenix connector footprints")) + (lib (name Connectors_Samtec)(type KiCad)(uri ${KISYSMOD}/Connectors_Samtec.pretty)(options "")(descr "Samtec connector footprints")) + (lib (name Connectors_TE-Connectivity)(type KiCad)(uri ${KISYSMOD}/Connectors_TE-Connectivity.pretty)(options "")(descr "TE Connectivity connector footprints www.te.com")) + (lib (name Connectors_Terminal_Blocks)(type KiCad)(uri ${KISYSMOD}/Connectors_Terminal_Blocks.pretty)(options "")(descr "Terminal block connectors")) + (lib (name Connectors_WAGO)(type KiCad)(uri ${KISYSMOD}/Connectors_WAGO.pretty)(options "")(descr "WAGO connector footprints www.wago.com")) + (lib (name Connectors_USB)(type KiCad)(uri ${KISYSMOD}/Connectors_USB.pretty)(options "")(descr "USB connector footprints")) + (lib (name Connectors)(type KiCad)(uri ${KISYSMOD}/Connectors.pretty)(options "")(descr "Assorted connector footprints")) + (lib (name Converters_DCDC_ACDC)(type KiCad)(uri ${KISYSMOD}/Converters_DCDC_ACDC.pretty)(options "")(descr "DC-DC and AC-DC convertor modules")) + (lib (name Crystals)(type KiCad)(uri ${KISYSMOD}/Crystals.pretty)(options "")(descr "Crystals and oscillators")) + (lib (name Diodes_SMD)(type KiCad)(uri ${KISYSMOD}/Diodes_SMD.pretty)(options "")(descr "Diodes, surface mount")) + (lib (name Diodes_THT)(type KiCad)(uri ${KISYSMOD}/Diodes_THT.pretty)(options "")(descr "Diodes, through hole")) + (lib (name Displays_7-Segment)(type KiCad)(uri ${KISYSMOD}/Displays_7-Segment.pretty)(options "")(descr "Seven segment displays")) + (lib (name Displays)(type KiCad)(uri ${KISYSMOD}/Displays.pretty)(options "")(descr "Display modules")) + (lib (name Enclosures)(type KiCad)(uri ${KISYSMOD}/Enclosures.pretty)(options "")(descr "Electronics enclosures and housings")) + (lib (name EuroBoard_Outline)(type KiCad)(uri ${KISYSMOD}/EuroBoard_Outline.pretty)(options "")(descr "Deprecated - will be removed")) + (lib (name Fiducials)(type KiCad)(uri ${KISYSMOD}/Fiducials.pretty)(options "")(descr "Fiducial markings")) + (lib (name Fuse_Holders_and_Fuses)(type KiCad)(uri ${KISYSMOD}/Fuse_Holders_and_Fuses.pretty)(options "")(descr "Fuses and fuse holders")) + (lib (name Hall-Effect_Transducers_LEM)(type KiCad)(uri ${KISYSMOD}/Hall-Effect_Transducers_LEM.pretty)(options "")(descr "LEM hall effect transducers")) + (lib (name Heatsinks)(type KiCad)(uri ${KISYSMOD}/Heatsinks.pretty)(options "")(descr "Heatsinks and thermal products")) + (lib (name Housings_BGA)(type KiCad)(uri ${KISYSMOD}/Housings_BGA.pretty)(options "")(descr "Ball Grid Array (BGA)")) + (lib (name Housings_CSP)(type KiCad)(uri ${KISYSMOD}/Housings_CSP.pretty)(options "")(descr "Chip Scale Packages (CSP)")) + (lib (name Housings_DFN_QFN)(type KiCad)(uri ${KISYSMOD}/Housings_DFN_QFN.pretty)(options "")(descr "Surface mount IC packages, DFN / LGA / QFN")) + (lib (name Housings_DIP)(type KiCad)(uri ${KISYSMOD}/Housings_DIP.pretty)(options "")(descr "Through hole IC packages, DIP")) + (lib (name Housings_LCC)(type KiCad)(uri ${KISYSMOD}/Housings_LCC.pretty)(options "")(descr "Leaded Chip Carriers (LCC)")) + (lib (name Housings_LGA)(type KiCad)(uri ${KISYSMOD}/Housings_LGA.pretty)(options "")(descr "Land Grid Array (LGA)")) + (lib (name Housings_PGA)(type KiCad)(uri ${KISYSMOD}/Housings_PGA.pretty)(options "")(descr "Pin Grid Array (PGA)")) + (lib (name Housings_QFP)(type KiCad)(uri ${KISYSMOD}/Housings_QFP.pretty)(options "")(descr "Quad Flat Package (QFP)")) + (lib (name Housings_SIP)(type KiCad)(uri ${KISYSMOD}/Housings_SIP.pretty)(options "")(descr "Single Inline Package (SIP)")) + (lib (name Housings_SOIC)(type KiCad)(uri ${KISYSMOD}/Housings_SOIC.pretty)(options "")(descr "Small Outline Integrated Circuits (SOIC)")) + (lib (name Housings_SON)(type KiCad)(uri ${KISYSMOD}/Housings_SON.pretty)(options "")(descr "Small Outline No-Lead (SON)")) + (lib (name Housings_SSOP)(type KiCad)(uri ${KISYSMOD}/Housings_SSOP.pretty)(options "")(descr "SSOP, TSSOP, MSOP, QSOP, VSO packages")) + (lib (name Inductors_SMD)(type KiCad)(uri ${KISYSMOD}/Inductors_SMD.pretty)(options "")(descr "Inductors, surface mount")) + (lib (name Inductors_THT)(type KiCad)(uri ${KISYSMOD}/Inductors_THT.pretty)(options "")(descr "Inductors, through hole")) + (lib (name IR-DirectFETs)(type KiCad)(uri ${KISYSMOD}/IR-DirectFETs.pretty)(options "")(descr "DirectFet packets from International Rectifier")) + (lib (name LEDs)(type KiCad)(uri ${KISYSMOD}/LEDs.pretty)(options "")(descr "Light emitting diodes (LEDs)")) + (lib (name Measurement_Points)(type KiCad)(uri ${KISYSMOD}/Measurement_Points.pretty)(options "")(descr "Terminals for test equipment")) + (lib (name Measurement_Scales)(type KiCad)(uri ${KISYSMOD}/Measurement_Scales.pretty)(options "")(descr "Measurement scales and gauges")) + (lib (name Microwave)(type KiCad)(uri ${KISYSMOD}/Microwave.pretty)(options "")(descr Microwave)) + (lib (name Modules)(type KiCad)(uri ${KISYSMOD}/Modules.pretty)(options "")(descr "Board-level devices integrating system functionality into a single module")) + (lib (name Mounting_Holes)(type KiCad)(uri ${KISYSMOD}/Mounting_Holes.pretty)(options "")(descr "Mechanical fasteners")) + (lib (name Opto-Devices)(type KiCad)(uri ${KISYSMOD}/Opto-Devices.pretty)(options "")(descr "Optocouplers, light sensors, and other optical devices")) + (lib (name Oscillators)(type KiCad)(uri ${KISYSMOD}/Oscillators.pretty)(options "")(descr "Precicision oscillator modules")) + (lib (name PFF_PSF_PSS_Leadforms)(type KiCad)(uri ${KISYSMOD}/PFF_PSF_PSS_Leadforms.pretty)(options "")(descr "Allegro leadform packages")) + (lib (name Pin_Headers)(type KiCad)(uri ${KISYSMOD}/Pin_Headers.pretty)(options "")(descr "Male pin headers")) + (lib (name Potentiometers)(type KiCad)(uri ${KISYSMOD}/Potentiometers.pretty)(options "")(descr "Potentiometers / variable resistors")) + (lib (name Power_Integrations)(type KiCad)(uri ${KISYSMOD}/Power_Integrations.pretty)(options "")(descr "Power Integrations footprints")) + (lib (name Relays_SMD)(type KiCad)(uri ${KISYSMOD}/Relays_SMD.pretty)(options "")(descr "Surface mount relay packages")) + (lib (name Relays_THT)(type KiCad)(uri ${KISYSMOD}/Relays_THT.pretty)(options "")(descr "Through hole relay packages")) + (lib (name Resistors_SMD)(type KiCad)(uri ${KISYSMOD}/Resistors_SMD.pretty)(options "")(descr "Resistors, surface mount")) + (lib (name Resistors_THT)(type KiCad)(uri ${KISYSMOD}/Resistors_THT.pretty)(options "")(descr "Resistors, through hole")) + (lib (name Resistors_Universal)(type KiCad)(uri ${KISYSMOD}/Resistors_Universal.pretty)(options "")(descr Experimental)) + (lib (name RF_Antennas)(type KiCad)(uri ${KISYSMOD}/RF_Antennas.pretty)(options "")(descr "Radio-frequency / wireless antenna footprints")) + (lib (name RF_Modules)(type KiCad)(uri ${KISYSMOD}/RF_Modules.pretty)(options "")(descr "Radio-frequency / wireless modules")) + (lib (name Shielding_Cabinets)(type KiCad)(uri ${KISYSMOD}/Shielding_Cabinets.pretty)(options "")(descr "RF / EMI shields")) + (lib (name SMD_Packages)(type KiCad)(uri ${KISYSMOD}/SMD_Packages.pretty)(options "")(descr "Various SMD packages. Read only - footprints will be moved to other libraries")) + (lib (name Socket_Strips)(type KiCad)(uri ${KISYSMOD}/Socket_Strips.pretty)(options "")(descr "Female socket strips")) + (lib (name Sockets)(type KiCad)(uri ${KISYSMOD}/Sockets.pretty)(options "")(descr "IC sockets")) + (lib (name Symbols)(type KiCad)(uri ${KISYSMOD}/Symbols.pretty)(options "")(descr "PCB symbols")) + (lib (name TerminalBlocks_Phoenix)(type KiCad)(uri ${KISYSMOD}/TerminalBlocks_Phoenix.pretty)(options "")(descr "Phoenix Contact terminal blocks")) + (lib (name TerminalBlocks_WAGO)(type KiCad)(uri ${KISYSMOD}/TerminalBlocks_WAGO.pretty)(options "")(descr "WAGO terminal blocks")) + (lib (name TO_SOT_Packages_SMD)(type KiCad)(uri ${KISYSMOD}/TO_SOT_Packages_SMD.pretty)(options "")(descr "Surface mount transistor packages")) + (lib (name TO_SOT_Packages_THT)(type KiCad)(uri ${KISYSMOD}/TO_SOT_Packages_THT.pretty)(options "")(descr "Through hole transistor packages")) + (lib (name Transformers_SMD)(type KiCad)(uri ${KISYSMOD}/Transformers_SMD.pretty)(options "")(descr "Surface mount transformers")) + (lib (name Transformers_THT)(type KiCad)(uri ${KISYSMOD}/Transformers_THT.pretty)(options "")(descr "Through hole transformers")) + (lib (name Transistors_OldSowjetAera)(type KiCad)(uri ${KISYSMOD}/Transistors_OldSowjetAera.pretty)(options "")(descr "Sowjet transistors")) + (lib (name Valves)(type KiCad)(uri ${KISYSMOD}/Valves.pretty)(options "")(descr Valves)) + (lib (name Varistors)(type KiCad)(uri ${KISYSMOD}/Varistors.pretty)(options "")(descr Varistors)) + (lib (name Wire_Connections_Bridges)(type KiCad)(uri ${KISYSMOD}/Wire_Connections_Bridges.pretty)(options "")(descr "PCB bridging points")) + (lib (name Wire_Pads)(type KiCad)(uri ${KISYSMOD}/Wire_Pads.pretty)(options "")(descr "Direct wire-to-board connection points")) + (lib (name Choke_Common-Mode_Wurth)(type KiCad)(uri "$(KISYSMOD)Choke_Common-Mode_Wurth.pretty")(options "")(descr "")) + (lib (name Choke_Radial_ThroughHole)(type KiCad)(uri "$(KISYSMOD)Choke_Radial_ThroughHole.pretty")(options "")(descr "")) + (lib (name Choke_SMD)(type KiCad)(uri "$(KISYSMOD)Choke_SMD.pretty")(options "")(descr "")) + (lib (name Choke_Toroid_ThroughHole)(type KiCad)(uri "$(KISYSMOD)Choke_Toroid_ThroughHole.pretty")(options "")(descr "")) +) diff --git a/library/supportFiles/fp-lib-table-online b/library/supportFiles/fp-lib-table-online new file mode 100644 index 00000000..5b4081ff --- /dev/null +++ b/library/supportFiles/fp-lib-table-online @@ -0,0 +1,88 @@ +(fp_lib_table + (lib (name Battery_Holders)(type Github)(uri ${KIGITHUB}/Battery_Holders.pretty)(options "")(descr "Batteries and battery holders")) + (lib (name Buttons_Switches_SMD)(type Github)(uri ${KIGITHUB}/Buttons_Switches_SMD.pretty)(options "")(descr "Buttons and switches, surface mount")) + (lib (name Buttons_Switches_THT)(type Github)(uri ${KIGITHUB}/Buttons_Switches_THT.pretty)(options "")(descr "Buttons and switches, through hole")) + (lib (name Buzzers_Beepers)(type Github)(uri ${KIGITHUB}/Buzzers_Beepers.pretty)(options "")(descr "Audio signalling devices")) + (lib (name Capacitors_SMD)(type Github)(uri ${KIGITHUB}/Capacitors_SMD.pretty)(options "")(descr "Capacitors, surface mount")) + (lib (name Capacitors_Tantalum_SMD)(type Github)(uri ${KIGITHUB}/Capacitors_Tantalum_SMD.pretty)(options "")(descr "Tantalum capacitors, surface mount")) + (lib (name Capacitors_THT)(type Github)(uri ${KIGITHUB}/Capacitors_THT.pretty)(options "")(descr "Capacitors, through hole")) + (lib (name Connectors_Card)(type Github)(uri ${KIGITHUB}/Connectors_Card.pretty)(options "")(descr "Footprints for cards and card holders")) + (lib (name Connectors_Harwin)(type Github)(uri ${KIGITHUB}/Connectors_Harwin.pretty)(options "")(descr "Harwin connector footprints www.harwin.com")) + (lib (name Connectors_HDMI)(type Github)(uri ${KIGITHUB}/Connectors_HDMI.pretty)(options "")(descr "HDMI connector footprints")) + (lib (name Connectors_Hirose)(type Github)(uri ${KIGITHUB}/Connectors_Hirose.pretty)(options "")(descr "Hirose connector footprints www.hirose.com")) + (lib (name Connectors_IEC_DIN)(type Github)(uri ${KIGITHUB}/Connectors_IEC_DIN.pretty)(options "")(descr "DIN connector footprints")) + (lib (name Connectors_JAE)(type Github)(uri ${KIGITHUB}/Connectors_JAE.pretty)(options "")(descr "JAE connector footprints http://www.jae.com/jccom/en/connectors")) + (lib (name Connectors_JST)(type Github)(uri ${KIGITHUB}/Connectors_JST.pretty)(options "")(descr "JST connector footprints www.jst.com")) + (lib (name Connectors_Mini-Universal)(type Github)(uri ${KIGITHUB}/Connectors_Mini-Universal.pretty)(options "")(descr Mate-N-Lok)) + (lib (name Connectors_Molex)(type Github)(uri ${KIGITHUB}/Connectors_Molex.pretty)(options "")(descr "Molex connector foottprints www.molex.com")) + (lib (name Connectors_Multicomp)(type Github)(uri ${KIGITHUB}/Connectors_Multicomp.pretty)(options "")(descr "Multicomp connector footprints")) + (lib (name Connectors_Phoenix)(type Github)(uri ${KIGITHUB}/Connectors_Phoenix.pretty)(options "")(descr "Phoenix connector footprints")) + (lib (name Connectors_Samtec)(type Github)(uri ${KIGITHUB}/Connectors_Samtec.pretty)(options "")(descr "Samtec connector footprints")) + (lib (name Connectors_TE-Connectivity)(type Github)(uri ${KIGITHUB}/Connectors_TE-Connectivity.pretty)(options "")(descr "TE Connectivity connector footprints www.te.com")) + (lib (name Connectors_Terminal_Blocks)(type Github)(uri ${KIGITHUB}/Connectors_Terminal_Blocks.pretty)(options "")(descr "Terminal block connectors")) + (lib (name Connectors_WAGO)(type Github)(uri ${KIGITHUB}/Connectors_WAGO.pretty)(options "")(descr "WAGO connector footprints www.wago.com")) + (lib (name Connectors_USB)(type Github)(uri ${KIGITHUB}/Connectors_USB.pretty)(options "")(descr "USB connector footprints")) + (lib (name Connectors)(type Github)(uri ${KIGITHUB}/Connectors.pretty)(options "")(descr "Assorted connector footprints")) + (lib (name Converters_DCDC_ACDC)(type Github)(uri ${KIGITHUB}/Converters_DCDC_ACDC.pretty)(options "")(descr "DC-DC and AC-DC convertor modules")) + (lib (name Crystals)(type Github)(uri ${KIGITHUB}/Crystals.pretty)(options "")(descr "Crystals and oscillators")) + (lib (name Diodes_SMD)(type Github)(uri ${KIGITHUB}/Diodes_SMD.pretty)(options "")(descr "Diodes, surface mount")) + (lib (name Diodes_THT)(type Github)(uri ${KIGITHUB}/Diodes_THT.pretty)(options "")(descr "Diodes, through hole")) + (lib (name Displays_7-Segment)(type Github)(uri ${KIGITHUB}/Displays_7-Segment.pretty)(options "")(descr "Seven segment displays")) + (lib (name Displays)(type Github)(uri ${KIGITHUB}/Displays.pretty)(options "")(descr "Display modules")) + (lib (name Enclosures)(type Github)(uri ${KIGITHUB}/Enclosures.pretty)(options "")(descr "Electronics enclosures and housings")) + (lib (name EuroBoard_Outline)(type Github)(uri ${KIGITHUB}/EuroBoard_Outline.pretty)(options "")(descr "Deprecated - will be removed")) + (lib (name Fiducials)(type Github)(uri ${KIGITHUB}/Fiducials.pretty)(options "")(descr "Fiducial markings")) + (lib (name Fuse_Holders_and_Fuses)(type Github)(uri ${KIGITHUB}/Fuse_Holders_and_Fuses.pretty)(options "")(descr "Fuses and fuse holders")) + (lib (name Hall-Effect_Transducers_LEM)(type Github)(uri ${KIGITHUB}/Hall-Effect_Transducers_LEM.pretty)(options "")(descr "LEM hall effect transducers")) + (lib (name Heatsinks)(type Github)(uri ${KIGITHUB}/Heatsinks.pretty)(options "")(descr "Heatsinks and thermal products")) + (lib (name Housings_BGA)(type Github)(uri ${KIGITHUB}/Housings_BGA.pretty)(options "")(descr "Ball Grid Array (BGA)")) + (lib (name Housings_CSP)(type Github)(uri ${KIGITHUB}/Housings_CSP.pretty)(options "")(descr "Chip Scale Packages (CSP)")) + (lib (name Housings_DFN_QFN)(type Github)(uri ${KIGITHUB}/Housings_DFN_QFN.pretty)(options "")(descr "Surface mount IC packages, DFN / LGA / QFN")) + (lib (name Housings_DIP)(type Github)(uri ${KIGITHUB}/Housings_DIP.pretty)(options "")(descr "Through hole IC packages, DIP")) + (lib (name Housings_LCC)(type Github)(uri ${KIGITHUB}/Housings_LCC.pretty)(options "")(descr "Leaded Chip Carriers (LCC)")) + (lib (name Housings_LGA)(type Github)(uri ${KIGITHUB}/Housings_LGA.pretty)(options "")(descr "Land Grid Array (LGA)")) + (lib (name Housings_PGA)(type Github)(uri ${KIGITHUB}/Housings_PGA.pretty)(options "")(descr "Pin Grid Array (PGA)")) + (lib (name Housings_QFP)(type Github)(uri ${KIGITHUB}/Housings_QFP.pretty)(options "")(descr "Quad Flat Package (QFP)")) + (lib (name Housings_SIP)(type Github)(uri ${KIGITHUB}/Housings_SIP.pretty)(options "")(descr "Single Inline Package (SIP)")) + (lib (name Housings_SOIC)(type Github)(uri ${KIGITHUB}/Housings_SOIC.pretty)(options "")(descr "Small Outline Integrated Circuits (SOIC)")) + (lib (name Housings_SON)(type Github)(uri ${KIGITHUB}/Housings_SON.pretty)(options "")(descr "Small Outline No-Lead (SON)")) + (lib (name Housings_SSOP)(type Github)(uri ${KIGITHUB}/Housings_SSOP.pretty)(options "")(descr "SSOP, TSSOP, MSOP, QSOP, VSO packages")) + (lib (name Inductors_SMD)(type Github)(uri ${KIGITHUB}/Inductors_SMD.pretty)(options "")(descr "Inductors, surface mount")) + (lib (name Inductors_THT)(type Github)(uri ${KIGITHUB}/Inductors_THT.pretty)(options "")(descr "Inductors, through hole")) + (lib (name IR-DirectFETs)(type Github)(uri ${KIGITHUB}/IR-DirectFETs.pretty)(options "")(descr "DirectFet packets from International Rectifier")) + (lib (name LEDs)(type Github)(uri ${KIGITHUB}/LEDs.pretty)(options "")(descr "Light emitting diodes (LEDs)")) + (lib (name Measurement_Points)(type Github)(uri ${KIGITHUB}/Measurement_Points.pretty)(options "")(descr "Terminals for test equipment")) + (lib (name Measurement_Scales)(type Github)(uri ${KIGITHUB}/Measurement_Scales.pretty)(options "")(descr "Measurement scales and gauges")) + (lib (name Microwave)(type Github)(uri ${KIGITHUB}/Microwave.pretty)(options "")(descr "Microwave")) + (lib (name Modules)(type Github)(uri ${KIGITHUB}/Modules.pretty)(options "")(descr "Board-level devices integrating system functionality into a single module")) + (lib (name Mounting_Holes)(type Github)(uri ${KIGITHUB}/Mounting_Holes.pretty)(options "")(descr "Mechanical fasteners")) + (lib (name Opto-Devices)(type Github)(uri ${KIGITHUB}/Opto-Devices.pretty)(options "")(descr "Optocouplers, light sensors, and other optical devices")) + (lib (name Oscillators)(type Github)(uri ${KIGITHUB}/Oscillators.pretty)(options "")(descr "Precicision oscillator modules")) + (lib (name PFF_PSF_PSS_Leadforms)(type Github)(uri ${KIGITHUB}/PFF_PSF_PSS_Leadforms.pretty)(options "")(descr "Allegro leadform packages")) + (lib (name Pin_Headers)(type Github)(uri ${KIGITHUB}/Pin_Headers.pretty)(options "")(descr "Male pin headers")) + (lib (name Potentiometers)(type Github)(uri ${KIGITHUB}/Potentiometers.pretty)(options "")(descr "Potentiometers / variable resistors")) + (lib (name Power_Integrations)(type Github)(uri ${KIGITHUB}/Power_Integrations.pretty)(options "")(descr "Power Integrations footprints")) + (lib (name Relays_SMD)(type Github)(uri ${KIGITHUB}/Relays_SMD.pretty)(options "")(descr "Surface mount relay packages")) + (lib (name Relays_THT)(type Github)(uri ${KIGITHUB}/Relays_THT.pretty)(options "")(descr "Through hole relay packages")) + (lib (name Resistors_SMD)(type Github)(uri ${KIGITHUB}/Resistors_SMD.pretty)(options "")(descr "Resistors, surface mount")) + (lib (name Resistors_THT)(type Github)(uri ${KIGITHUB}/Resistors_THT.pretty)(options "")(descr "Resistors, through hole")) + (lib (name Resistors_Universal)(type Github)(uri ${KIGITHUB}/Resistors_Universal.pretty)(options "")(descr Experimental)) + (lib (name RF_Antennas)(type Github)(uri ${KIGITHUB}/RF_Antennas.pretty)(options "")(descr "Radio-frequency / wireless antenna footprints")) + (lib (name RF_Modules)(type Github)(uri ${KIGITHUB}/RF_Modules.pretty)(options "")(descr "Radio-frequency / wireless modules")) + (lib (name Shielding_Cabinets)(type Github)(uri ${KIGITHUB}/Shielding_Cabinets.pretty)(options "")(descr "RF / EMI shields")) + (lib (name SMD_Packages)(type Github)(uri ${KIGITHUB}/SMD_Packages.pretty)(options "")(descr "Various SMD packages. Read only - footprints will be moved to other libraries")) + (lib (name Socket_Strips)(type Github)(uri ${KIGITHUB}/Socket_Strips.pretty)(options "")(descr "Female socket strips")) + (lib (name Sockets)(type Github)(uri ${KIGITHUB}/Sockets.pretty)(options "")(descr "IC sockets")) + (lib (name Symbols)(type Github)(uri ${KIGITHUB}/Symbols.pretty)(options "")(descr "PCB symbols")) + (lib (name TerminalBlocks_Phoenix)(type Github)(uri ${KIGITHUB}/TerminalBlocks_Phoenix.pretty)(options "")(descr "Phoenix Contact terminal blocks")) + (lib (name TerminalBlocks_WAGO)(type Github)(uri ${KIGITHUB}/TerminalBlocks_WAGO.pretty)(options "")(descr "WAGO terminal blocks")) + (lib (name TO_SOT_Packages_SMD)(type Github)(uri ${KIGITHUB}/TO_SOT_Packages_SMD.pretty)(options "")(descr "Surface mount transistor packages")) + (lib (name TO_SOT_Packages_THT)(type Github)(uri ${KIGITHUB}/TO_SOT_Packages_THT.pretty)(options "")(descr "Through hole transistor packages")) + (lib (name Transformers_SMD)(type Github)(uri ${KIGITHUB}/Transformers_SMD.pretty)(options "")(descr "Surface mount transformers")) + (lib (name Transformers_THT)(type Github)(uri ${KIGITHUB}/Transformers_THT.pretty)(options "")(descr "Through hole transformers")) + (lib (name Transistors_OldSowjetAera)(type Github)(uri ${KIGITHUB}/Transistors_OldSowjetAera.pretty)(options "")(descr "Sowjet transistors")) + (lib (name Valves)(type Github)(uri ${KIGITHUB}/Valves.pretty)(options "")(descr "Valves")) + (lib (name Varistors)(type Github)(uri ${KIGITHUB}/Varistors.pretty)(options "")(descr "Varistors")) + (lib (name Wire_Connections_Bridges)(type Github)(uri ${KIGITHUB}/Wire_Connections_Bridges.pretty)(options "")(descr "PCB bridging points")) + (lib (name Wire_Pads)(type Github)(uri ${KIGITHUB}/Wire_Pads.pretty)(options "")(descr "Direct wire-to-board connection points")) +) |
