diff options
Diffstat (limited to 'library/kicadLibrary/library/74xx.dcm')
| -rw-r--r-- | library/kicadLibrary/library/74xx.dcm | 853 |
1 files changed, 853 insertions, 0 deletions
diff --git a/library/kicadLibrary/library/74xx.dcm b/library/kicadLibrary/library/74xx.dcm new file mode 100644 index 00000000..38a47c9d --- /dev/null +++ b/library/kicadLibrary/library/74xx.dcm @@ -0,0 +1,853 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP 7400 +D Quad nand2 +K TTL nand2 +$ENDCMP +# +$CMP 7402 +D Quad Nor2 +K TTL Nor2 +$ENDCMP +# +$CMP 74AHC1G14 +D inverting buffer with Schmitt trigger. +F 74xx/74ahc_ahct1g14.pdf +$ENDCMP +# +$CMP 74HC00 +D Quad nand2 +K HCMOS nand2 +$ENDCMP +# +$CMP 74HC02 +D Quad Nor2 +K HCMOS Nor2 +$ENDCMP +# +$CMP 74HC04 +D Hex Inverseur +K HCMOS not inv +$ENDCMP +# +$CMP 74HC240 +D 8bits Buffer/Line Driver 3 state Inverting +K TTL BUFFER 3State inv +F http://www.nxp.com/documents/data_sheet/74HC_HCT240.pdf +$ENDCMP +# +$CMP 74HC244 +D 8bits Buffer/Line Driver 3 state +K TTL BUFFER 3State +F http://www.nxp.com/documents/data_sheet/74HC_HCT244.pdf +$ENDCMP +# +$CMP 74HC245 +D Octal BUS Transceivers, 3 State out +K HCMOS BUS 3State +$ENDCMP +# +$CMP 74HC595 +D 8 bits serial in // out Shift Register 3 State Out +K HCMOS SR 3State +F 74xx/74HC595.pdf +$ENDCMP +# +$CMP 74HC74 +D Dual D FlipFlop, Set & Reset +K TTL DFF +F 74xx/74hc_hct74.pdf +$ENDCMP +# +$CMP 74HCT00 +D Quad nand2 +K HCTMOS nand2 +$ENDCMP +# +$CMP 74HCT02 +D Quad Nor2 +K HCTMOS Nor2 +$ENDCMP +# +$CMP 74HCT04 +D Hex Inverseur +K HCTMOS not inv +$ENDCMP +# +$CMP 74HCT240 +D 8 bit buffer; 3-state; inverting +K octal buffer line driver inverting +F http://www.nxp.com/documents/data_sheet/74HC_HCT240.pdf +$ENDCMP +# +$CMP 74HCT244 +D 8bits Buffer/Line Driver 3 state +K TTL BUFFER 3State +F http://www.nxp.com/documents/data_sheet/74HC_HCT244.pdf +$ENDCMP +# +$CMP 74HCT541_PWR +D 8bits Buffer/Line Driver 3 state Out +K TTL BUFFER 3State BUS +$ENDCMP +# +$CMP 74HCT574_PWR +D 8 bits Register, 3 state Out, with visible Pins power +K TTL REG DFF DFF8 3State +$ENDCMP +# +$CMP 74LS00 +D Quad nand2 +K TTL nand2 +$ENDCMP +# +$CMP 74LS01 +D Quad nand2 open collect. +K TTL nand2 opencol +$ENDCMP +# +$CMP 74LS02 +D Quad Nor2 +K TTL Nor2 +$ENDCMP +# +$CMP 74LS03 +D Quad Nand2 open collect +K TTL Nand2 OpenCol +$ENDCMP +# +$CMP 74LS04 +D Hex Inverseur +K TTL not inv +$ENDCMP +# +$CMP 74LS05 +D Inverseur Open Collect +K TTL not inv OpenCol +$ENDCMP +# +$CMP 74LS08 +D Quad And2 +K TTL and2 +$ENDCMP +# +$CMP 74LS09 +D Quad And2 Open Collect +K TTL and2 OpenCol +$ENDCMP +# +$CMP 74LS10 +D Triple Nand3 +K TTL Nand3 +$ENDCMP +# +$CMP 74LS107 +D Double JK FlipFlop, reset +K TTL JK +$ENDCMP +# +$CMP 74LS109 +D Double JK FlipFlop, Set & Reset +K TTL JK +$ENDCMP +# +$CMP 74LS11 +D Triple And3 +K TTL And3 +$ENDCMP +# +$CMP 74LS112 +D Double JK FlipFlop, Set & Reset +K TTL JK +$ENDCMP +# +$CMP 74LS113 +D Double JK, Set +K TTL JK +$ENDCMP +# +$CMP 74LS114 +D Double JK, common Clock & Reset, Set +K TTL JK +$ENDCMP +# +$CMP 74LS12 +D Triple Nand3 Open Collect +K TTL Nand3 OpenCol +$ENDCMP +# +$CMP 74LS122 +D Retriggerable Monostable +K TTL monostable +$ENDCMP +# +$CMP 74LS123 +D Dual retriggerable Monostable +K TTL monostable +$ENDCMP +# +$CMP 74LS125 +D Quad buffer 3 State out +K TTL buffer 3State +$ENDCMP +# +$CMP 74LS126 +D Quad buffer 3 State out +K TTL Buffer 3State +$ENDCMP +# +$CMP 74LS13 +D Double Nand4 schmitt trigger +K TTL Nand4 +$ENDCMP +# +$CMP 74LS132 +D Quad Nand2 schmitt trigger +K TTL Nand2 +$ENDCMP +# +$CMP 74LS133 +D Nand 13 inputs +K TTL Nand13 +$ENDCMP +# +$CMP 74LS136 +D Quad Exclusive Or 2-inputs, Open Collect. +K TTL XOR2 OpenCol +F http://www.ti.com/lit/ds/symlink/sn54ls136.pdf +$ENDCMP +# +$CMP 74LS137 +D Decoder 3 to 8, addr latches. +K TTL DECOD8 DECOD +$ENDCMP +# +$CMP 74LS138 +D Decoder 3 to 8 (active low outputs) +K TTL DECOD DECOD8 +$ENDCMP +# +$CMP 74LS139 +D Dual Decoder 1 of 4, Active low outputs +K TTL DECOD4 +$ENDCMP +# +$CMP 74LS14 +D Hex inverseur schmitt trigger +K TTL not inv +$ENDCMP +# +$CMP 74LS145 +D Decoder 1 to 10, Open Collect. +K TTL DECOD10 OpenColl +$ENDCMP +# +$CMP 74LS147 +D Priority Encodeur, 10 to 4 +K TTL ENCOD +$ENDCMP +# +$CMP 74LS148 +D Priority Encoder 3 to 8 cascadable +K TTL ENCOD +$ENDCMP +# +$CMP 74LS15 +D Triple And 3 inputs +K TTL And3 +$ENDCMP +# +$CMP 74LS151 +D Multiplexer 8 to 1 +K TTL MUX8 +$ENDCMP +# +$CMP 74LS153 +D Dual Multiplexer 4 to 1 +K TTL Mux4 +$ENDCMP +# +$CMP 74LS154 +D Decoder 4 to 16 +K TTL DECOD16 DECOD +$ENDCMP +# +$CMP 74LS155 +D Dual 2 to 4 lines Decoder/Demultiplexer +K TTL DECOD8 DECOD4 DEMUX4 DEMUX8 DEMUX DECOD +$ENDCMP +# +$CMP 74LS156 +D Dual 2 to 4 lines Decoder/Demultiplexer, Open Collect. +K TTL DECOD8 DECOD4 DEMUX4 DEMUX8 OpenCol +$ENDCMP +# +$CMP 74LS157 +D Quad 2 to 1 line Multiplexer +K TTL MUX MUX2 +$ENDCMP +# +$CMP 74LS158 +D Quad 2 to 1 multiplexer +K TTL Mux MUX2 +$ENDCMP +# +$CMP 74LS160 +D Sychronous 4 bits programmable decimal Counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS161 +D Sychronous 4 bits programmable binary Counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS162 +D Sychronous 4 bits programmable decimal Counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS163 +D Sychronous 4 bits programmable binary Counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS165 +D Shift Register 8 bits, parallel load +K TTL SR SR8 +$ENDCMP +# +$CMP 74LS166 +D Shift Register 8 bits, parallel load +K TTL SR SR8 +$ENDCMP +# +$CMP 74LS168 +D Synchronous 4 bits Up/Down Decimal counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS169 +D Synchronous 4 bits Up/Down binary counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS170 +D 4 x 4 Register Files Open Collect. +K TTL Register OpenCol +$ENDCMP +# +$CMP 74LS173 +D 4 bits D-type Register, 3 state out +K TTL REG REG4 3State DFF +$ENDCMP +# +$CMP 74LS174 +D Hex D-type FlipFlop, reset +K TTL REG REG6 DFF +$ENDCMP +# +$CMP 74LS175 +D 4 bits D FlipFlop, reset +K TTL REG REG4 DFF +$ENDCMP +# +$CMP 74LS181 +D Arithmetic logic unit +K TTL ALU ARITH +F 74xx/74F181.pdf +$ENDCMP +# +$CMP 74LS182 +D Carry generator +K TTL ALU ARITH +$ENDCMP +# +$CMP 74LS190 +D 4 bits Synchronous 4 bits Up/Down BCD Counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS191 +D 4 bits Synchronous 4 bits Up/Down binary Counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS192 +D Synchronous 4 bits Up/Down (2 clk) counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS193 +D Synchronous 4 bits Up/Down (2 clk) counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS194 +D Shift Register 4 bits Bidirectionnel +K TTL RS SR4 +$ENDCMP +# +$CMP 74LS195 +D Shift Register 4 bits, parallel +K TTL SR SR4 +$ENDCMP +# +$CMP 74LS196 +D 4 (3 + 1 ) bits presettable BCD counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS197 +D 4 (3 + 1 ) bits presettable binary counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS20 +D Dual Nand 4 inputs +K TTL Nand4 +$ENDCMP +# +$CMP 74LS21 +D Dual And 4 inputs +K TTL And4 +$ENDCMP +# +$CMP 74LS22 +D Dual Nand 4 inputs Open Collect. +K TTL Nand4 OpenCol +$ENDCMP +# +$CMP 74LS221 +D Dual Monostable +K TTL Monostable +$ENDCMP +# +$CMP 74LS240 +D 8 bits BUS Buffer (Inverter) 3 State out +K TTL Buffer BUS 3State +$ENDCMP +# +$CMP 74LS241 +D 8 bits Bus Buffer 3 State out +K TTL Buffer BUS 3State +$ENDCMP +# +$CMP 74LS243 +D 4 bits Bus Tranceiver +K TTL Buffer 3State BUS BIDI +$ENDCMP +# +$CMP 74LS244 +D 8 bits Bus Buffer 3 State out +K TTL Buffer BUS 3State +$ENDCMP +# +$CMP 74LS245 +D Octal BUS Transceivers, 3 State out +K TTL BUS 3State +$ENDCMP +# +$CMP 74LS246 +D BDC to 7 segments Decoder Open Collec. active Low +K TTL DECOD +$ENDCMP +# +$CMP 74LS247 +D BDC to 7 segments Decoder Open Collec. active Low +K TTL DECOD +$ENDCMP +# +$CMP 74LS248 +D BCD to 7 segments Decoder, Active High +K TTL DECOD +$ENDCMP +# +$CMP 74LS249 +D BCD to 7 segments Decoder, Open collect, Active High +K TTL DECOD OpenCol +$ENDCMP +# +$CMP 74LS251 +D Multiplexer 8 to 1, 3 state Out +K TTL MUX MUX8 3State +$ENDCMP +# +$CMP 74LS253 +D Dual Multiplexer 4 to 1, 3 State Out +K TTL MUX MUX4 3State +$ENDCMP +# +$CMP 74LS257 +D Quad 2 to 1 Multiplexer +K TTL MUX MUX2 +$ENDCMP +# +$CMP 74LS258 +D Quad 2 to 1 Multiplexer,invert +K TTL MUX MUX2 +$ENDCMP +# +$CMP 74LS259 +D 8 bits addressable latch +K TTL REG DFF +$ENDCMP +# +$CMP 74LS26 +D Quad Nand 2 inputs Open collect. +K TTL Nand2 OpenCol +$ENDCMP +# +$CMP 74LS27 +D Triple Nr 3 inputs +K TTL Nor3 +$ENDCMP +# +$CMP 74LS273 +D 8 bits D FlipFlop, reset +K TTL DFF DFF8 +$ENDCMP +# +$CMP 74LS28 +D Quad Buffer Nor2 +K TTL Nor2 Buffer +$ENDCMP +# +$CMP 74LS280 +D Parity Generator/Checker +K TTL ALU Arith +$ENDCMP +# +$CMP 74LS283 +D 4 bits full Adder +K TTL ADD Arith ALU +$ENDCMP +# +$CMP 74LS290 +D 4 bits BCD counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS293 +D 4 bits binary counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS298 +D Quad 2 to 1 multiplexer with storage +K TTL MUX MUX2 +$ENDCMP +# +$CMP 74LS299 +D 8 bits Universer shift/storage Register +K TTL REG SR SR8 +$ENDCMP +# +$CMP 74LS30 +D Nand 8 inputs +K TTL Nand8 +$ENDCMP +# +$CMP 74LS32 +D Quad Or 2 inputs +K TTL Or2 +$ENDCMP +# +$CMP 74LS323 +D 8 bits Universal Shift/Storage Register +K TTL REG SR SR8 +$ENDCMP +# +$CMP 74LS33 +D Quad Nand 2 inputs, Open collect. +K TTL Nand8 OpenCol +$ENDCMP +# +$CMP 74LS348 +D 8 to 3 lines Priority Encoder +K TTL ENCOD Arith +$ENDCMP +# +$CMP 74LS352 +D Dual 4 to 1 line Multiplexer +K TTL Mux MUX4 +$ENDCMP +# +$CMP 74LS353 +D Dual 4 to 1 line Multiplexer, inverter +K TTL MUX MUX2 +$ENDCMP +# +$CMP 74LS365 +D Hex Bus Driver, 3 State Out +K TTL Buffer BUS 3State +$ENDCMP +# +$CMP 74LS366 +D Hex Bus Driver inverter, 3 state out +K TTL Buffer BUS 3State +$ENDCMP +# +$CMP 74LS367 +D Hex Bus Driver 3 state Out +K TTL Buffer BUS 3State +$ENDCMP +# +$CMP 74LS368 +D Hex Bus Driver inverter, 3 state Out +K TTL Buffer BUS 3State +$ENDCMP +# +$CMP 74LS37 +D Quad Buffer nand2 +K TTL nand2 buffer +$ENDCMP +# +$CMP 74LS373 +D 8 bits Latch, 3 state Out +K TTL REG DFF DFF8 LATCH +$ENDCMP +# +$CMP 74LS374 +D 8 bits Register, 3 state Out +K TTL DFF DFF8 REG 3State +$ENDCMP +# +$CMP 74LS375 +D 4 bits Latch +K TTL DFF DFF4 Latch +$ENDCMP +# +$CMP 74LS377 +D 8 bit Register +K TTL REG DFF DFF8 +$ENDCMP +# +$CMP 74LS378 +D 6 bits Register +K TTL REG DFF DFF6 +$ENDCMP +# +$CMP 74LS379 +D 4 bits Register +K TTL REG DFF DFF4 +$ENDCMP +# +$CMP 74LS38 +D Quad Buffer Nand 2 inputs Open collect. +K TTL Nand2 OpenCol Buffer +$ENDCMP +# +$CMP 74LS385 +D Quad serial Adder +K TTL ADD Arith ALU +$ENDCMP +# +$CMP 74LS386 +D Quad 2 input XOR +K TTL XOR2 +$ENDCMP +# +$CMP 74LS390 +D Dual BDC 4 bits counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS393 +D Dual BDC 4 bits counter +K TTL CNT CNT4 +F 74xx\74LS393.pdf +$ENDCMP +# +$CMP 74LS395 +D 4 bits universal shift register, 3 state out +K TTL SR SR4 REG 3State +$ENDCMP +# +$CMP 74LS398 +D Quad 2 to 1 line Multiplexer, 3 state out +K TTL MUX MUX2 3State +$ENDCMP +# +$CMP 74LS399 +D Quad 2 to 1 line multiplexer with storage +K TTL MUX MUX2 +$ENDCMP +# +$CMP 74LS40 +D Dual Nand 4 inputs +K TTL Nand4 +$ENDCMP +# +$CMP 74LS42 +D 4 to 10 line DECODER +K TTL DECOD DECOD10 +$ENDCMP +# +$CMP 74LS46 +D BCD to 7 segments Driver, Open Collect, 15V outputs +K TTL DECOD DECOD7 OpenCol +$ENDCMP +# +$CMP 74LS47 +D BCD to 7 segments Driver, Open Collect, 30V outputs +K TTL DECOD DECOD7 OpenCol +$ENDCMP +# +$CMP 74LS48 +D BCD to 7 segments Decoder/driver, Active High outputs +K TTL DECOD DECOD7 +$ENDCMP +# +$CMP 74LS49 +D BDC to 7 segments decoder/driver, Open collect. +K TTL DECOD DECOD7 OpenCol +F http://www.ti.com/lit/ds/symlink/sn74ls49.pdf +$ENDCMP +# +$CMP 74LS51 +D Dual 3- and 2-input AND-NOR ( S = /(AB[C] + DE[F]) ) +K TTL ANDNOR +F http://www.ti.com/lit/ds/symlink/sn74ls51.pdf +$ENDCMP +# +$CMP 74LS54 +D And-Nor (S = /(AB + CD + EF + GH) ) +K TTL ANDNOR +$ENDCMP +# +$CMP 74LS540 +D 8 bits Buffer/Line driver Inverter, 3 state Out +K BUFFER BUS TTL 3State +$ENDCMP +# +$CMP 74LS541 +D 8bits Buffer/Line Driver 3 state Out +K TTL BUFFER 3State BUS +$ENDCMP +# +$CMP 74LS55 +D AND-NOR ( S = / (ABCD + EFGH) ) +K TTL ANDNOR +$ENDCMP +# +$CMP 74LS573 +D 8 bits Latch 3 state Out +K TTL DFF DFF8 LATCH 3State +F 74xx/74hc573.pdf +$ENDCMP +# +$CMP 74LS574 +D 8 bits Register, 3 state Out +K TTL REG DFF DFF8 3State +$ENDCMP +# +$CMP 74LS595 +D 8 bits serial in // out Shift Register 3 State Out +K TTL SR 3State +$ENDCMP +# +$CMP 74LS596 +D 8 bits serial in // out Shift Register Open Collect. +K HCMOS SR OpenCol +$ENDCMP +# +$CMP 74LS688 +D 8 bits Comparator +K TTL DECOD Arith +$ENDCMP +# +$CMP 74LS73 +D Dual JK FlipFlop, reset +K TTL JK JKFF +$ENDCMP +# +$CMP 74LS74 +D Dual D FlipFlop, Set & Reset +K TTL DFF +F 74xx/74hc_hct74.pdf +$ENDCMP +# +$CMP 74LS75 +D 4 bits Latch +K TTL DFF Latch +$ENDCMP +# +$CMP 74LS76 +D Dual JK FlipFlop, Set & Reset +K TTL JK JKFF +$ENDCMP +# +$CMP 74LS77 +D 4 bits Latch +K TTL DFF Latch +$ENDCMP +# +$CMP 74LS78 +D Dual JK FlipFlop, preset , common clock & reset +K TTL JK JKFF +$ENDCMP +# +$CMP 74LS83 +D 4 bits Full Adder +K TTL ADD ARITH ALU +$ENDCMP +# +$CMP 74LS85 +D 4 bits Comparateur +K TTL COMP ARITH +$ENDCMP +# +$CMP 74LS86 +D Quad XOR 2 inputs +K TTL XOR2 +F 74xx/74ls86.pdf +$ENDCMP +# +$CMP 74LS90 +D BCD Counter ( div 2 & div 5 ) +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS91 +D 8 bits Serial Register +K TTL SR SR8 +$ENDCMP +# +$CMP 74LS92 +D Divide by 12 counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS93 +D Divide by 2 & 8 counter +K TTL CNT CNT4 +$ENDCMP +# +$CMP 74LS95 +D Shift Register 5 bits ( // in // out ) +K TTL SR SR4 +$ENDCMP +# +$CMP 74LV14 +D Hex Inverseur +K TTL not inv +$ENDCMP +# +$CMP 74LVC125 +D Quad buffer 3 State out +K TTL buffer 3State +$ENDCMP +# +$CMP 74ls670 +D 4 x 4 Register Files 3 State Out +K TTL Register 3State +$ENDCMP +# +$CMP SN74LVC1G332 +D 3-input OR Gate +K 3 input OR +F http://www.ti.com/lit/ds/symlink/sn74lvc1g332.pdf +$ENDCMP +# +#End Doc Library |