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-rw-r--r--library/SubcircuitLibrary/FCT827/FCT827-cache.lib90
-rw-r--r--library/SubcircuitLibrary/FCT827/FCT827.cir24
-rw-r--r--library/SubcircuitLibrary/FCT827/FCT827.cir.out64
-rw-r--r--library/SubcircuitLibrary/FCT827/FCT827.pro73
-rw-r--r--library/SubcircuitLibrary/FCT827/FCT827.sch518
-rw-r--r--library/SubcircuitLibrary/FCT827/FCT827.sub58
-rw-r--r--library/SubcircuitLibrary/FCT827/FCT827_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/FCT827/analysis1
8 files changed, 829 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/FCT827/FCT827-cache.lib b/library/SubcircuitLibrary/FCT827/FCT827-cache.lib
new file mode 100644
index 00000000..2c79a539
--- /dev/null
+++ b/library/SubcircuitLibrary/FCT827/FCT827-cache.lib
@@ -0,0 +1,90 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_tristate
+#
+DEF d_tristate U 0 40 Y Y 1 F N
+F0 "U" -250 250 60 H V C CNN
+F1 "d_tristate" -200 450 60 H V C CNN
+F2 "" -100 350 60 H V C CNN
+F3 "" -100 350 60 H V C CNN
+DRAW
+P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N
+X IN 1 -600 350 200 R 50 50 1 1 I
+X EN 2 -50 50 193 U 50 50 1 1 I
+X OUT 3 550 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/FCT827/FCT827.cir b/library/SubcircuitLibrary/FCT827/FCT827.cir
new file mode 100644
index 00000000..a059c52c
--- /dev/null
+++ b/library/SubcircuitLibrary/FCT827/FCT827.cir
@@ -0,0 +1,24 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\FCT827\FCT827.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/10/24 02:15:36
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U4 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U10-Pad2_ d_and
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter
+U5 Net-_U1-Pad3_ Net-_U10-Pad2_ Net-_U1-Pad13_ d_tristate
+U6 Net-_U1-Pad4_ Net-_U10-Pad2_ Net-_U1-Pad14_ d_tristate
+U7 Net-_U1-Pad5_ Net-_U10-Pad2_ Net-_U1-Pad15_ d_tristate
+U8 Net-_U1-Pad6_ Net-_U10-Pad2_ Net-_U1-Pad16_ d_tristate
+U9 Net-_U1-Pad7_ Net-_U10-Pad2_ Net-_U1-Pad17_ d_tristate
+U10 Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U1-Pad18_ d_tristate
+U11 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U1-Pad19_ d_tristate
+U12 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U1-Pad20_ d_tristate
+U13 Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U1-Pad21_ d_tristate
+U14 Net-_U1-Pad12_ Net-_U10-Pad2_ Net-_U1-Pad22_ d_tristate
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/FCT827/FCT827.cir.out b/library/SubcircuitLibrary/FCT827/FCT827.cir.out
new file mode 100644
index 00000000..8d3b557a
--- /dev/null
+++ b/library/SubcircuitLibrary/FCT827/FCT827.cir.out
@@ -0,0 +1,64 @@
+* c:\fossee\esim\library\subcircuitlibrary\fct827\fct827.cir
+
+* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u10-pad2_ d_and
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u5 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad13_ d_tristate
+* u6 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad14_ d_tristate
+* u7 net-_u1-pad5_ net-_u10-pad2_ net-_u1-pad15_ d_tristate
+* u8 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad16_ d_tristate
+* u9 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad17_ d_tristate
+* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad18_ d_tristate
+* u11 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad19_ d_tristate
+* u12 net-_u1-pad10_ net-_u10-pad2_ net-_u1-pad20_ d_tristate
+* u13 net-_u1-pad11_ net-_u10-pad2_ net-_u1-pad21_ d_tristate
+* u14 net-_u1-pad12_ net-_u10-pad2_ net-_u1-pad22_ d_tristate
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ port
+a1 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u10-pad2_ u4
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 net-_u1-pad2_ net-_u3-pad2_ u3
+a4 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad13_ u5
+a5 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad14_ u6
+a6 net-_u1-pad5_ net-_u10-pad2_ net-_u1-pad15_ u7
+a7 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad16_ u8
+a8 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad17_ u9
+a9 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad18_ u10
+a10 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad19_ u11
+a11 net-_u1-pad10_ net-_u10-pad2_ net-_u1-pad20_ u12
+a12 net-_u1-pad11_ net-_u10-pad2_ net-_u1-pad21_ u13
+a13 net-_u1-pad12_ net-_u10-pad2_ net-_u1-pad22_ u14
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u7 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+.tran 10e-03 1e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/FCT827/FCT827.pro b/library/SubcircuitLibrary/FCT827/FCT827.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/FCT827/FCT827.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/FCT827/FCT827.sch b/library/SubcircuitLibrary/FCT827/FCT827.sch
new file mode 100644
index 00000000..1ba486c9
--- /dev/null
+++ b/library/SubcircuitLibrary/FCT827/FCT827.sch
@@ -0,0 +1,518 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
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+L PORT U1
+U 1 1 666631FF
+P 2250 1050
+F 0 "U1" H 2300 1150 30 0000 C CNN
+F 1 "PORT" H 2250 1050 30 0000 C CNN
+F 2 "" H 2250 1050 60 0000 C CNN
+F 3 "" H 2250 1050 60 0000 C CNN
+ 1 2250 1050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 66663234
+P 2250 1150
+F 0 "U1" H 2300 1250 30 0000 C CNN
+F 1 "PORT" H 2250 1150 30 0000 C CNN
+F 2 "" H 2250 1150 60 0000 C CNN
+F 3 "" H 2250 1150 60 0000 C CNN
+ 2 2250 1150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 66663285
+P 2250 1800
+F 0 "U1" H 2300 1900 30 0000 C CNN
+F 1 "PORT" H 2250 1800 30 0000 C CNN
+F 2 "" H 2250 1800 60 0000 C CNN
+F 3 "" H 2250 1800 60 0000 C CNN
+ 3 2250 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 666632F6
+P 2250 2400
+F 0 "U1" H 2300 2500 30 0000 C CNN
+F 1 "PORT" H 2250 2400 30 0000 C CNN
+F 2 "" H 2250 2400 60 0000 C CNN
+F 3 "" H 2250 2400 60 0000 C CNN
+ 4 2250 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 66663371
+P 2250 3000
+F 0 "U1" H 2300 3100 30 0000 C CNN
+F 1 "PORT" H 2250 3000 30 0000 C CNN
+F 2 "" H 2250 3000 60 0000 C CNN
+F 3 "" H 2250 3000 60 0000 C CNN
+ 5 2250 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 666633AA
+P 2250 3600
+F 0 "U1" H 2300 3700 30 0000 C CNN
+F 1 "PORT" H 2250 3600 30 0000 C CNN
+F 2 "" H 2250 3600 60 0000 C CNN
+F 3 "" H 2250 3600 60 0000 C CNN
+ 6 2250 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 666634B6
+P 2250 4200
+F 0 "U1" H 2300 4300 30 0000 C CNN
+F 1 "PORT" H 2250 4200 30 0000 C CNN
+F 2 "" H 2250 4200 60 0000 C CNN
+F 3 "" H 2250 4200 60 0000 C CNN
+ 7 2250 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 666634F3
+P 2250 4800
+F 0 "U1" H 2300 4900 30 0000 C CNN
+F 1 "PORT" H 2250 4800 30 0000 C CNN
+F 2 "" H 2250 4800 60 0000 C CNN
+F 3 "" H 2250 4800 60 0000 C CNN
+ 8 2250 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 66663532
+P 2250 5400
+F 0 "U1" H 2300 5500 30 0000 C CNN
+F 1 "PORT" H 2250 5400 30 0000 C CNN
+F 2 "" H 2250 5400 60 0000 C CNN
+F 3 "" H 2250 5400 60 0000 C CNN
+ 9 2250 5400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 66663573
+P 2250 6000
+F 0 "U1" H 2300 6100 30 0000 C CNN
+F 1 "PORT" H 2250 6000 30 0000 C CNN
+F 2 "" H 2250 6000 60 0000 C CNN
+F 3 "" H 2250 6000 60 0000 C CNN
+ 10 2250 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 666635B6
+P 2250 6600
+F 0 "U1" H 2300 6700 30 0000 C CNN
+F 1 "PORT" H 2250 6600 30 0000 C CNN
+F 2 "" H 2250 6600 60 0000 C CNN
+F 3 "" H 2250 6600 60 0000 C CNN
+ 11 2250 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 66663613
+P 2250 7200
+F 0 "U1" H 2300 7300 30 0000 C CNN
+F 1 "PORT" H 2250 7200 30 0000 C CNN
+F 2 "" H 2250 7200 60 0000 C CNN
+F 3 "" H 2250 7200 60 0000 C CNN
+ 12 2250 7200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 666636F0
+P 6000 1800
+F 0 "U1" H 6050 1900 30 0000 C CNN
+F 1 "PORT" H 6000 1800 30 0000 C CNN
+F 2 "" H 6000 1800 60 0000 C CNN
+F 3 "" H 6000 1800 60 0000 C CNN
+ 13 6000 1800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6666373D
+P 6000 2400
+F 0 "U1" H 6050 2500 30 0000 C CNN
+F 1 "PORT" H 6000 2400 30 0000 C CNN
+F 2 "" H 6000 2400 60 0000 C CNN
+F 3 "" H 6000 2400 60 0000 C CNN
+ 14 6000 2400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 6666378C
+P 6000 3000
+F 0 "U1" H 6050 3100 30 0000 C CNN
+F 1 "PORT" H 6000 3000 30 0000 C CNN
+F 2 "" H 6000 3000 60 0000 C CNN
+F 3 "" H 6000 3000 60 0000 C CNN
+ 15 6000 3000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 666637DD
+P 6000 3600
+F 0 "U1" H 6050 3700 30 0000 C CNN
+F 1 "PORT" H 6000 3600 30 0000 C CNN
+F 2 "" H 6000 3600 60 0000 C CNN
+F 3 "" H 6000 3600 60 0000 C CNN
+ 16 6000 3600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 66663887
+P 6000 4200
+F 0 "U1" H 6050 4300 30 0000 C CNN
+F 1 "PORT" H 6000 4200 30 0000 C CNN
+F 2 "" H 6000 4200 60 0000 C CNN
+F 3 "" H 6000 4200 60 0000 C CNN
+ 17 6000 4200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 666638DE
+P 6000 4800
+F 0 "U1" H 6050 4900 30 0000 C CNN
+F 1 "PORT" H 6000 4800 30 0000 C CNN
+F 2 "" H 6000 4800 60 0000 C CNN
+F 3 "" H 6000 4800 60 0000 C CNN
+ 18 6000 4800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 19 1 66663935
+P 6000 5400
+F 0 "U1" H 6050 5500 30 0000 C CNN
+F 1 "PORT" H 6000 5400 30 0000 C CNN
+F 2 "" H 6000 5400 60 0000 C CNN
+F 3 "" H 6000 5400 60 0000 C CNN
+ 19 6000 5400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 20 1 6666398E
+P 6000 6000
+F 0 "U1" H 6050 6100 30 0000 C CNN
+F 1 "PORT" H 6000 6000 30 0000 C CNN
+F 2 "" H 6000 6000 60 0000 C CNN
+F 3 "" H 6000 6000 60 0000 C CNN
+ 20 6000 6000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 21 1 666639E9
+P 6000 6600
+F 0 "U1" H 6050 6700 30 0000 C CNN
+F 1 "PORT" H 6000 6600 30 0000 C CNN
+F 2 "" H 6000 6600 60 0000 C CNN
+F 3 "" H 6000 6600 60 0000 C CNN
+ 21 6000 6600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 22 1 66663A46
+P 6000 7200
+F 0 "U1" H 6050 7300 30 0000 C CNN
+F 1 "PORT" H 6000 7200 30 0000 C CNN
+F 2 "" H 6000 7200 60 0000 C CNN
+F 3 "" H 6000 7200 60 0000 C CNN
+ 22 6000 7200
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/FCT827/FCT827.sub b/library/SubcircuitLibrary/FCT827/FCT827.sub
new file mode 100644
index 00000000..ba51bdf9
--- /dev/null
+++ b/library/SubcircuitLibrary/FCT827/FCT827.sub
@@ -0,0 +1,58 @@
+* Subcircuit FCT827
+.subckt FCT827 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_
+* c:\fossee\esim\library\subcircuitlibrary\fct827\fct827.cir
+* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u10-pad2_ d_and
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u5 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad13_ d_tristate
+* u6 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad14_ d_tristate
+* u7 net-_u1-pad5_ net-_u10-pad2_ net-_u1-pad15_ d_tristate
+* u8 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad16_ d_tristate
+* u9 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad17_ d_tristate
+* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad18_ d_tristate
+* u11 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad19_ d_tristate
+* u12 net-_u1-pad10_ net-_u10-pad2_ net-_u1-pad20_ d_tristate
+* u13 net-_u1-pad11_ net-_u10-pad2_ net-_u1-pad21_ d_tristate
+* u14 net-_u1-pad12_ net-_u10-pad2_ net-_u1-pad22_ d_tristate
+a1 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u10-pad2_ u4
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 net-_u1-pad2_ net-_u3-pad2_ u3
+a4 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad13_ u5
+a5 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad14_ u6
+a6 net-_u1-pad5_ net-_u10-pad2_ net-_u1-pad15_ u7
+a7 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad16_ u8
+a8 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad17_ u9
+a9 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad18_ u10
+a10 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad19_ u11
+a11 net-_u1-pad10_ net-_u10-pad2_ net-_u1-pad20_ u12
+a12 net-_u1-pad11_ net-_u10-pad2_ net-_u1-pad21_ u13
+a13 net-_u1-pad12_ net-_u10-pad2_ net-_u1-pad22_ u14
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u7 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Control Statements
+
+.ends FCT827 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/FCT827/FCT827_Previous_Values.xml b/library/SubcircuitLibrary/FCT827/FCT827_Previous_Values.xml
new file mode 100644
index 00000000..0677af1e
--- /dev/null
+++ b/library/SubcircuitLibrary/FCT827/FCT827_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">1</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u4 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u4><u2 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_tristate<field10 name="Enter Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Enable Load (default=1.0e-12)" /></u5><u6 name="type">d_tristate<field13 name="Enter Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Enable Load (default=1.0e-12)" /></u6><u7 name="type">d_tristate<field16 name="Enter Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Enable Load (default=1.0e-12)" /></u7><u8 name="type">d_tristate<field19 name="Enter Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Enable Load (default=1.0e-12)" /></u8><u9 name="type">d_tristate<field22 name="Enter Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Enable Load (default=1.0e-12)" /></u9><u10 name="type">d_tristate<field25 name="Enter Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Enable Load (default=1.0e-12)" /></u10><u11 name="type">d_tristate<field28 name="Enter Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Enable Load (default=1.0e-12)" /></u11><u12 name="type">d_tristate<field31 name="Enter Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Enable Load (default=1.0e-12)" /></u12><u13 name="type">d_tristate<field34 name="Enter Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Enable Load (default=1.0e-12)" /></u13><u14 name="type">d_tristate<field37 name="Enter Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Enable Load (default=1.0e-12)" /></u14></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/FCT827/analysis b/library/SubcircuitLibrary/FCT827/analysis
new file mode 100644
index 00000000..55ca3c83
--- /dev/null
+++ b/library/SubcircuitLibrary/FCT827/analysis
@@ -0,0 +1 @@
+.tran 10e-03 1e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-20 19:29:02 +0000