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-rw-r--r--library/SubcircuitLibrary/lm102_sub/D.lib2
-rw-r--r--library/SubcircuitLibrary/lm102_sub/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/lm102_sub/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/lm102_sub/analysis1
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub-cache.lib162
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub.cir51
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub.cir.out61
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub.pro73
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub.sch801
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub.sub55
-rw-r--r--library/SubcircuitLibrary/lm102_sub/lm102_sub_Previous_Values.xml1
11 files changed, 1215 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/lm102_sub/D.lib b/library/SubcircuitLibrary/lm102_sub/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/lm102_sub/NPN.lib b/library/SubcircuitLibrary/lm102_sub/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/lm102_sub/PNP.lib b/library/SubcircuitLibrary/lm102_sub/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/lm102_sub/analysis b/library/SubcircuitLibrary/lm102_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub-cache.lib b/library/SubcircuitLibrary/lm102_sub/lm102_sub-cache.lib
new file mode 100644
index 00000000..c751ab9b
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub-cache.lib
@@ -0,0 +1,162 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir b/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir
new file mode 100644
index 00000000..1ab6c226
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir
@@ -0,0 +1,51 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\lm102_sub\lm102_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 30/05/2024 11:41:12 AM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad3_ eSim_NPN
+Q5 Net-_C1-Pad1_ Net-_Q10-Pad2_ Net-_Q5-Pad3_ eSim_NPN
+Q2 Net-_Q15-Pad2_ Net-_Q1-Pad1_ Net-_Q10-Pad2_ eSim_PNP
+R5 Net-_Q1-Pad3_ Net-_Q5-Pad3_ 6k
+R12 Net-_Q1-Pad3_ Net-_Q10-Pad3_ 3k
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q15 Net-_Q12-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN
+R15 Net-_Q1-Pad3_ Net-_Q15-Pad3_ 270
+Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_D1-Pad1_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_Q10-Pad1_ eSim_NPN
+Q9 Net-_D1-Pad2_ Net-_Q8-Pad3_ Net-_Q11-Pad3_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+Q8 Net-_D1-Pad2_ Net-_D1-Pad1_ Net-_Q8-Pad3_ eSim_NPN
+Q14 Net-_Q11-Pad1_ Net-_C2-Pad2_ Net-_Q11-Pad2_ eSim_NPN
+R10 Net-_Q13-Pad1_ Net-_Q8-Pad3_ 80k
+R13 Net-_Q13-Pad1_ Net-_Q11-Pad2_ 80k
+R14 Net-_C2-Pad2_ Net-_Q12-Pad1_ 3k
+R17 Net-_Q12-Pad1_ Net-_D1-Pad2_ 250
+R16 Net-_D1-Pad2_ Net-_Q16-Pad2_ 4k
+Q16 Net-_C2-Pad1_ Net-_Q16-Pad2_ Net-_Q11-Pad1_ eSim_NPN
+Q18 Net-_Q18-Pad1_ Net-_C2-Pad1_ Net-_Q16-Pad2_ eSim_NPN
+Q19 Net-_Q18-Pad1_ Net-_Q16-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q17 Net-_C2-Pad1_ Net-_D1-Pad2_ Net-_Q12-Pad1_ eSim_NPN
+C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 20pF
+Q6 Net-_C1-Pad1_ Net-_Q6-Pad2_ Net-_Q6-Pad3_ eSim_PNP
+Q7 Net-_C2-Pad1_ Net-_Q6-Pad2_ Net-_Q7-Pad3_ eSim_PNP
+R3 Net-_R3-Pad1_ Net-_Q18-Pad1_ 500
+R8 Net-_R8-Pad1_ Net-_Q18-Pad1_ 500
+R9 Net-_Q7-Pad3_ Net-_R8-Pad1_ 1k
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+R4 Net-_Q6-Pad3_ Net-_R3-Pad1_ 1k
+R11 Net-_Q10-Pad1_ Net-_Q11-Pad3_ 200
+R1 Net-_Q10-Pad2_ Net-_Q3-Pad3_ 10K
+U2 Net-_U2-PadIN_ Net-_Q6-Pad2_ zener
+U3 Net-_C1-Pad2_ Net-_U2-PadIN_ zener
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10pF
+R6 Net-_Q3-Pad3_ Net-_C1-Pad2_ 2k
+Q4 Net-_Q18-Pad1_ Net-_C1-Pad1_ Net-_Q3-Pad2_ eSim_NPN
+Q3 Net-_Q18-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN
+R2 Net-_Q3-Pad3_ Net-_Q3-Pad2_ 4k
+U1 Net-_R3-Pad1_ Net-_R8-Pad1_ Net-_D1-Pad1_ Net-_Q1-Pad3_ Net-_Q15-Pad3_ Net-_Q12-Pad1_ Net-_Q18-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir.out b/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir.out
new file mode 100644
index 00000000..91abf6b9
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub.cir.out
@@ -0,0 +1,61 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm102_sub\lm102_sub.cir
+
+.include D.lib
+.include PNP.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2222
+q5 net-_c1-pad1_ net-_q10-pad2_ net-_q5-pad3_ Q2N2222
+q2 net-_q15-pad2_ net-_q1-pad1_ net-_q10-pad2_ Q2N2907A
+r5 net-_q1-pad3_ net-_q5-pad3_ 6k
+r12 net-_q1-pad3_ net-_q10-pad3_ 3k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q15 net-_q12-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222
+r15 net-_q1-pad3_ net-_q15-pad3_ 270
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_d1-pad1_ Q2N2222
+q13 net-_q13-pad1_ net-_q13-pad1_ net-_q10-pad1_ Q2N2222
+q9 net-_d1-pad2_ net-_q8-pad3_ net-_q11-pad3_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q8 net-_d1-pad2_ net-_d1-pad1_ net-_q8-pad3_ Q2N2222
+q14 net-_q11-pad1_ net-_c2-pad2_ net-_q11-pad2_ Q2N2222
+r10 net-_q13-pad1_ net-_q8-pad3_ 200k
+r13 net-_q13-pad1_ net-_q11-pad2_ 200k
+r14 net-_c2-pad2_ net-_q12-pad1_ 3k
+r17 net-_q12-pad1_ net-_d1-pad2_ 246
+r16 net-_d1-pad2_ net-_q16-pad2_ 3k
+q16 net-_c2-pad1_ net-_q16-pad2_ net-_q11-pad1_ Q2N2222
+q18 net-_q18-pad1_ net-_c2-pad1_ net-_q16-pad2_ Q2N2222
+q19 net-_q18-pad1_ net-_q16-pad2_ net-_d1-pad2_ Q2N2222
+q17 net-_c2-pad1_ net-_d1-pad2_ net-_q12-pad1_ Q2N2222
+c2 net-_c2-pad1_ net-_c2-pad2_ 20pf
+q6 net-_c1-pad1_ net-_q6-pad2_ net-_q6-pad3_ Q2N2907A
+q7 net-_c2-pad1_ net-_q6-pad2_ net-_q7-pad3_ Q2N2907A
+r3 net-_r3-pad1_ net-_q18-pad1_ 500
+r8 net-_r8-pad1_ net-_q18-pad1_ 500
+r9 net-_q7-pad3_ net-_r8-pad1_ 1k
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r4 net-_q6-pad3_ net-_r3-pad1_ 1k
+r11 net-_q10-pad1_ net-_q11-pad3_ 200
+r1 net-_q10-pad2_ net-_q3-pad3_ 10k
+* u2 net-_u2-padin_ net-_q6-pad2_ zener
+* u3 net-_c1-pad2_ net-_u2-padin_ zener
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+r6 net-_q3-pad3_ net-_c1-pad2_ 2k
+q4 net-_q18-pad1_ net-_c1-pad1_ net-_q3-pad2_ Q2N2222
+q3 net-_q18-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+r2 net-_q3-pad3_ net-_q3-pad2_ 4k
+* u1 net-_r3-pad1_ net-_r8-pad1_ net-_d1-pad1_ net-_q1-pad3_ net-_q15-pad3_ net-_q12-pad1_ net-_q18-pad1_ port
+a1 net-_u2-padin_ net-_q6-pad2_ u2
+a2 net-_c1-pad2_ net-_u2-padin_ u3
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub.pro b/library/SubcircuitLibrary/lm102_sub/lm102_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub.sch b/library/SubcircuitLibrary/lm102_sub/lm102_sub.sch
new file mode 100644
index 00000000..b9c59ddf
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub.sch
@@ -0,0 +1,801 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:lm102_sub-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q1
+U 1 1 665422D7
+P 1550 6800
+F 0 "Q1" H 1450 6850 50 0000 R CNN
+F 1 "eSim_NPN" H 1500 6950 50 0000 R CNN
+F 2 "" H 1750 6900 29 0000 C CNN
+F 3 "" H 1550 6800 60 0000 C CNN
+ 1 1550 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 665422D8
+P 2500 5800
+F 0 "Q5" H 2400 5850 50 0000 R CNN
+F 1 "eSim_NPN" H 2450 5950 50 0000 R CNN
+F 2 "" H 2700 5900 29 0000 C CNN
+F 3 "" H 2500 5800 60 0000 C CNN
+ 1 2500 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q2
+U 1 1 665422D9
+P 1850 6100
+F 0 "Q2" H 1750 6150 50 0000 R CNN
+F 1 "eSim_PNP" H 1800 6250 50 0000 R CNN
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+$Comp
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+F 3 "" H 6550 7400 60 0000 C CNN
+ 4 6550 7400
+ 0 -1 -1 0
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+F 1 "PORT" H 7100 6550 30 0000 C CNN
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+F 3 "" H 7100 6550 60 0000 C CNN
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+ 7 8400 850
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+F 3 "" H 1350 2950 60 0000 C CNN
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 1950 4050 1950 5900
+Wire Wire Line
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+Wire Wire Line
+ 1350 6100 1650 6100
+Connection ~ 1950 5800
+Wire Wire Line
+ 1650 7050 1650 7000
+Wire Wire Line
+ 2600 7050 2600 6950
+Connection ~ 1650 7050
+Wire Wire Line
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+Wire Wire Line
+ 3500 1400 3500 1350
+Wire Wire Line
+ 2900 1600 3200 1600
+Connection ~ 3050 1600
+Connection ~ 3500 1800
+Wire Wire Line
+ 4700 7050 4700 6950
+Connection ~ 2600 7050
+Wire Wire Line
+ 4400 4900 1950 4900
+Connection ~ 1950 4900
+Wire Wire Line
+ 1950 6300 6250 6300
+Wire Wire Line
+ 6550 6500 6550 6650
+Connection ~ 4700 7050
+Wire Wire Line
+ 7000 4600 5600 4600
+Wire Wire Line
+ 6550 4600 6550 6100
+Wire Wire Line
+ 5400 4900 5900 4900
+Wire Wire Line
+ 5900 4900 5900 4600
+Connection ~ 5900 4600
+Wire Wire Line
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+Wire Wire Line
+ 4250 3700 4250 3750
+Wire Wire Line
+ 4250 3750 5600 3750
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 5300 3750
+Connection ~ 5600 3750
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4700 3650
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4250 3350
+Wire Wire Line
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+Wire Wire Line
+ 5450 3350 5600 3350
+Connection ~ 5600 3350
+Wire Wire Line
+ 4700 4150 4700 4700
+Wire Wire Line
+ 5600 4300 4700 4300
+Connection ~ 4700 4300
+Wire Wire Line
+ 5200 4600 3500 4600
+Wire Wire Line
+ 3500 4600 3500 2550
+Wire Wire Line
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+Connection ~ 3500 2950
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 6550 1800 6550 1850
+Connection ~ 5900 1800
+Wire Wire Line
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+Wire Wire Line
+ 6550 2750 6550 2250
+Connection ~ 6550 1800
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 5900 2900 6000 2900
+Wire Wire Line
+ 6000 2900 6000 2950
+Connection ~ 6000 2950
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 6600 2950 6750 2950
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 7450 3400
+Wire Wire Line
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+Connection ~ 7000 3400
+Connection ~ 6550 4600
+Wire Wire Line
+ 7300 2950 7450 2950
+Connection ~ 7450 2950
+Wire Wire Line
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+Connection ~ 7000 1800
+Wire Wire Line
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+Connection ~ 7450 2050
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 7450 2750
+Wire Wire Line
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+Wire Wire Line
+ 4250 2750 4250 2550
+Connection ~ 4250 2550
+Wire Wire Line
+ 4700 3150 4700 2550
+Connection ~ 4700 2550
+Wire Wire Line
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+Connection ~ 5600 2750
+Wire Wire Line
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+Connection ~ 7450 850
+Wire Wire Line
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+Connection ~ 7850 850
+Connection ~ 6550 7050
+Wire Wire Line
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+Connection ~ 6550 6550
+Wire Wire Line
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+Wire Wire Line
+ 3500 1050 3500 950
+Wire Wire Line
+ 2600 1000 2900 1000
+Wire Wire Line
+ 2900 1000 2900 550
+Connection ~ 2600 1000
+Wire Wire Line
+ 3500 1000 3200 1000
+Wire Wire Line
+ 3200 1000 3200 550
+Connection ~ 3500 1000
+Wire Wire Line
+ 1950 650 3750 650
+Connection ~ 2600 650
+Wire Wire Line
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+Connection ~ 3500 650
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 3050 2850 3000 2850
+Wire Wire Line
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+Connection ~ 1950 2850
+Wire Wire Line
+ 1950 2250 1950 3750
+Wire Wire Line
+ 2250 2000 2250 2250
+Connection ~ 2250 2050
+Wire Wire Line
+ 2250 2550 2250 2850
+Connection ~ 2250 2850
+Wire Wire Line
+ 1950 1850 1950 650
+Wire Wire Line
+ 2250 1600 1950 1600
+Connection ~ 1950 1600
+Wire Wire Line
+ 2700 2700 2600 2700
+Connection ~ 2600 2700
+Wire Wire Line
+ 2550 1800 2600 1800
+Wire Wire Line
+ 3750 850 8150 850
+Wire Wire Line
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+Wire Wire Line
+ 1600 2950 3950 2950
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+Wire Wire Line
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+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub.sub b/library/SubcircuitLibrary/lm102_sub/lm102_sub.sub
new file mode 100644
index 00000000..8a4eee3b
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub.sub
@@ -0,0 +1,55 @@
+* Subcircuit lm102_sub
+.subckt lm102_sub net-_r3-pad1_ net-_r8-pad1_ net-_d1-pad1_ net-_q1-pad3_ net-_q15-pad3_ net-_q12-pad1_ net-_q18-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\lm102_sub\lm102_sub.cir
+.include D.lib
+.include PNP.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2222
+q5 net-_c1-pad1_ net-_q10-pad2_ net-_q5-pad3_ Q2N2222
+q2 net-_q15-pad2_ net-_q1-pad1_ net-_q10-pad2_ Q2N2907A
+r5 net-_q1-pad3_ net-_q5-pad3_ 6k
+r12 net-_q1-pad3_ net-_q10-pad3_ 3k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q15 net-_q12-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222
+r15 net-_q1-pad3_ net-_q15-pad3_ 270
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_d1-pad1_ Q2N2222
+q13 net-_q13-pad1_ net-_q13-pad1_ net-_q10-pad1_ Q2N2222
+q9 net-_d1-pad2_ net-_q8-pad3_ net-_q11-pad3_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q8 net-_d1-pad2_ net-_d1-pad1_ net-_q8-pad3_ Q2N2222
+q14 net-_q11-pad1_ net-_c2-pad2_ net-_q11-pad2_ Q2N2222
+r10 net-_q13-pad1_ net-_q8-pad3_ 200k
+r13 net-_q13-pad1_ net-_q11-pad2_ 200k
+r14 net-_c2-pad2_ net-_q12-pad1_ 3k
+r17 net-_q12-pad1_ net-_d1-pad2_ 246
+r16 net-_d1-pad2_ net-_q16-pad2_ 3k
+q16 net-_c2-pad1_ net-_q16-pad2_ net-_q11-pad1_ Q2N2222
+q18 net-_q18-pad1_ net-_c2-pad1_ net-_q16-pad2_ Q2N2222
+q19 net-_q18-pad1_ net-_q16-pad2_ net-_d1-pad2_ Q2N2222
+q17 net-_c2-pad1_ net-_d1-pad2_ net-_q12-pad1_ Q2N2222
+c2 net-_c2-pad1_ net-_c2-pad2_ 20pf
+q6 net-_c1-pad1_ net-_q6-pad2_ net-_q6-pad3_ Q2N2907A
+q7 net-_c2-pad1_ net-_q6-pad2_ net-_q7-pad3_ Q2N2907A
+r3 net-_r3-pad1_ net-_q18-pad1_ 500
+r8 net-_r8-pad1_ net-_q18-pad1_ 500
+r9 net-_q7-pad3_ net-_r8-pad1_ 1k
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r4 net-_q6-pad3_ net-_r3-pad1_ 1k
+r11 net-_q10-pad1_ net-_q11-pad3_ 200
+r1 net-_q10-pad2_ net-_q3-pad3_ 10k
+* u2 net-_u2-padin_ net-_q6-pad2_ zener
+* u3 net-_c1-pad2_ net-_u2-padin_ zener
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+r6 net-_q3-pad3_ net-_c1-pad2_ 2k
+q4 net-_q18-pad1_ net-_c1-pad1_ net-_q3-pad2_ Q2N2222
+q3 net-_q18-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+r2 net-_q3-pad3_ net-_q3-pad2_ 4k
+a1 net-_u2-padin_ net-_q6-pad2_ u2
+a2 net-_c1-pad2_ net-_u2-padin_ u3
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Control Statements
+
+.ends lm102_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/lm102_sub/lm102_sub_Previous_Values.xml b/library/SubcircuitLibrary/lm102_sub/lm102_sub_Previous_Values.xml
new file mode 100644
index 00000000..04d007d7
--- /dev/null
+++ b/library/SubcircuitLibrary/lm102_sub/lm102_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u2><u3 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u3></model><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-19 19:23:37 +0000