diff options
Diffstat (limited to 'library/SubcircuitLibrary')
378 files changed, 26151 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul-cache.lib b/library/SubcircuitLibrary/2bitmul/2bitmul-cache.lib new file mode 100644 index 00000000..e16831e4 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul-cache.lib @@ -0,0 +1,77 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul.cir b/library/SubcircuitLibrary/2bitmul/2bitmul.cir new file mode 100644 index 00000000..0f4deb6c --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul.cir @@ -0,0 +1,17 @@ +* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and +U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and +U3 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and +U2 Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and +X2 Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder +X1 Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT + +.end diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/library/SubcircuitLibrary/2bitmul/2bitmul.cir.out new file mode 100644 index 00000000..71766bd8 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul.cir.out @@ -0,0 +1,31 @@ +* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir + +.include half_adder.sub +* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and +x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder +x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul.pro b/library/SubcircuitLibrary/2bitmul/2bitmul.pro new file mode 100644 index 00000000..eafbfb80 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul.pro @@ -0,0 +1,74 @@ +update=03/07/19 09:55:40 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul.sch b/library/SubcircuitLibrary/2bitmul/2bitmul.sch new file mode 100644 index 00000000..0ba61912 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul.sch @@ -0,0 +1,284 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:2bitmul-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U5 +U 1 1 5C7FC048 +P 8150 2950 +F 0 "U5" H 8150 2950 60 0000 C CNN +F 1 "d_and" H 8200 3050 60 0000 C CNN +F 2 "" H 8150 2950 60 0000 C CNN +F 3 "" H 8150 2950 60 0000 C CNN + 1 8150 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FC0BC +P 7450 2950 +F 0 "U4" H 7450 2950 60 0000 C CNN +F 1 "d_and" H 7500 3050 60 0000 C CNN +F 2 "" H 7450 2950 60 0000 C CNN +F 3 "" H 7450 2950 60 0000 C CNN + 1 7450 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5C7FC0F4 +P 6950 2950 +F 0 "U3" H 6950 2950 60 0000 C CNN +F 1 "d_and" H 7000 3050 60 0000 C CNN +F 2 "" H 6950 2950 60 0000 C CNN +F 3 "" H 6950 2950 60 0000 C CNN + 1 6950 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U2 +U 1 1 5C7FC11D +P 6400 2950 +F 0 "U2" H 6400 2950 60 0000 C CNN +F 1 "d_and" H 6450 3050 60 0000 C CNN +F 2 "" H 6400 2950 60 0000 C CNN +F 3 "" H 6400 2950 60 0000 C CNN + 1 6400 2950 + 0 1 1 0 +$EndComp +Wire Wire Line + 8150 2500 8150 2350 +Wire Wire Line + 8150 2350 7450 2350 +Wire Wire Line + 7450 2100 7450 2500 +Wire Wire Line + 6950 2500 6950 2350 +Wire Wire Line + 6950 2350 6400 2350 +Wire Wire Line + 6400 2350 6400 2500 +Wire Wire Line + 8250 1100 8250 2500 +Wire Wire Line + 8250 2250 7050 2250 +Wire Wire Line + 7050 2250 7050 2500 +Wire Wire Line + 7550 2150 7550 2500 +Wire Wire Line + 7550 2450 6500 2450 +Wire Wire Line + 6500 2450 6500 2500 +$Comp +L half_adder X2 +U 1 1 5C7FC23A +P 7200 3350 +F 0 "X2" H 8100 3850 60 0000 C CNN +F 1 "half_adder" H 8100 3750 60 0000 C CNN +F 2 "" H 7200 3350 60 0000 C CNN +F 3 "" H 7200 3350 60 0000 C CNN + 1 7200 3350 + 0 1 1 0 +$EndComp +$Comp +L half_adder X1 +U 1 1 5C7FC324 +P 6050 3350 +F 0 "X1" H 6950 3850 60 0000 C CNN +F 1 "half_adder" H 6950 3750 60 0000 C CNN +F 2 "" H 6050 3350 60 0000 C CNN +F 3 "" H 6050 3350 60 0000 C CNN + 1 6050 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 7500 3400 7900 3400 +Wire Wire Line + 7900 3400 7900 3650 +Wire Wire Line + 7000 3400 7300 3400 +Wire Wire Line + 7300 3400 7300 3650 +Wire Wire Line + 7300 4800 7050 4800 +Wire Wire Line + 7050 4800 7050 3600 +Wire Wire Line + 7050 3600 6750 3600 +Wire Wire Line + 6750 3600 6750 3650 +Wire Wire Line + 6450 3400 6450 3650 +Wire Wire Line + 6450 3650 6150 3650 +$Comp +L PORT U1 +U 5 1 5C7FC4F8 +P 8200 5300 +F 0 "U1" H 8250 5400 30 0000 C CNN +F 1 "PORT" H 8200 5300 30 0000 C CNN +F 2 "" H 8200 5300 60 0000 C CNN +F 3 "" H 8200 5300 60 0000 C CNN + 5 8200 5300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 5C7FC5D7 +P 7300 5300 +F 0 "U1" H 7350 5400 30 0000 C CNN +F 1 "PORT" H 7300 5300 30 0000 C CNN +F 2 "" H 7300 5300 60 0000 C CNN +F 3 "" H 7300 5300 60 0000 C CNN + 6 7300 5300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C7FC641 +P 6750 5150 +F 0 "U1" H 6800 5250 30 0000 C CNN +F 1 "PORT" H 6750 5150 30 0000 C CNN +F 2 "" H 6750 5150 60 0000 C CNN +F 3 "" H 6750 5150 60 0000 C CNN + 7 6750 5150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C7FC698 +P 6150 5250 +F 0 "U1" H 6200 5350 30 0000 C CNN +F 1 "PORT" H 6150 5250 30 0000 C CNN +F 2 "" H 6150 5250 60 0000 C CNN +F 3 "" H 6150 5250 60 0000 C CNN + 8 6150 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5C7FC6EC +P 8250 850 +F 0 "U1" H 8300 950 30 0000 C CNN +F 1 "PORT" H 8250 850 30 0000 C CNN +F 2 "" H 8250 850 60 0000 C CNN +F 3 "" H 8250 850 60 0000 C CNN + 1 8250 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FC815 +P 7900 850 +F 0 "U1" H 7950 950 30 0000 C CNN +F 1 "PORT" H 7900 850 30 0000 C CNN +F 2 "" H 7900 850 60 0000 C CNN +F 3 "" H 7900 850 60 0000 C CNN + 2 7900 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FC857 +P 7550 850 +F 0 "U1" H 7600 950 30 0000 C CNN +F 1 "PORT" H 7550 850 30 0000 C CNN +F 2 "" H 7550 850 60 0000 C CNN +F 3 "" H 7550 850 60 0000 C CNN + 3 7550 850 + 0 1 1 0 +$EndComp +Connection ~ 8250 2250 +Wire Wire Line + 7900 1100 7900 2150 +Wire Wire Line + 7900 2150 7550 2150 +Connection ~ 7550 2450 +Wire Wire Line + 7550 1100 7550 2100 +Wire Wire Line + 7550 2100 7450 2100 +Connection ~ 7450 2350 +Wire Wire Line + 7200 1050 7200 2100 +Wire Wire Line + 7200 2100 6800 2100 +Wire Wire Line + 6800 2100 6800 2350 +Connection ~ 6800 2350 +Wire Wire Line + 8200 3400 8200 5050 +$Comp +L PORT U1 +U 4 1 5C7FC898 +P 7200 800 +F 0 "U1" H 7250 900 30 0000 C CNN +F 1 "PORT" H 7200 800 30 0000 C CNN +F 2 "" H 7200 800 60 0000 C CNN +F 3 "" H 7200 800 60 0000 C CNN + 4 7200 800 + 0 1 1 0 +$EndComp +Wire Wire Line + 7300 5050 7300 4850 +Wire Wire Line + 7300 4850 7900 4850 +Wire Wire Line + 7900 4850 7900 4800 +Wire Wire Line + 6750 4800 6750 4900 +Wire Wire Line + 6150 4800 6150 5000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul.sub b/library/SubcircuitLibrary/2bitmul/2bitmul.sub new file mode 100644 index 00000000..e77495a6 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul.sub @@ -0,0 +1,25 @@ +* Subcircuit 2bitmul +.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir +.include half_adder.sub +* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and +x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder +x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 2bitmul
\ No newline at end of file diff --git a/library/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml b/library/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml new file mode 100644 index 00000000..8a55af97 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u5 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/2bitmul/analysis b/library/SubcircuitLibrary/2bitmul/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/2bitmul/half_adder-cache.lib b/library/SubcircuitLibrary/2bitmul/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.cir b/library/SubcircuitLibrary/2bitmul/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.cir.out b/library/SubcircuitLibrary/2bitmul/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.pro b/library/SubcircuitLibrary/2bitmul/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.sch b/library/SubcircuitLibrary/2bitmul/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.sub b/library/SubcircuitLibrary/2bitmul/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml b/library/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/library/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/3_and/3_and-cache.lib b/library/SubcircuitLibrary/3_and/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/3_and/3_and.cir b/library/SubcircuitLibrary/3_and/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/3_and/3_and.cir.out b/library/SubcircuitLibrary/3_and/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/3_and/3_and.pro b/library/SubcircuitLibrary/3_and/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/3_and/3_and.sch b/library/SubcircuitLibrary/3_and/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/3_and/3_and.sub b/library/SubcircuitLibrary/3_and/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/3_and/3_and_Previous_Values.xml b/library/SubcircuitLibrary/3_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/3_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/3_and/analysis b/library/SubcircuitLibrary/3_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/3_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4002/4002-cache.lib b/library/SubcircuitLibrary/4002/4002-cache.lib new file mode 100644 index 00000000..677411a9 --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4002/4002.cir b/library/SubcircuitLibrary/4002/4002.cir new file mode 100644 index 00000000..5d5c1ed7 --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or +U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor + +.end diff --git a/library/SubcircuitLibrary/4002/4002.cir.out b/library/SubcircuitLibrary/4002/4002.cir.out new file mode 100644 index 00000000..e9cc6862 --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir + +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or +* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 +a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4002/4002.pro b/library/SubcircuitLibrary/4002/4002.pro new file mode 100644 index 00000000..225ef82a --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002.pro @@ -0,0 +1,44 @@ +update=05/31/19 09:35:41 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog +LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices +LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital +LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid +LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot +LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power +LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources +LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt +LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User +LibName11=power diff --git a/library/SubcircuitLibrary/4002/4002.sch b/library/SubcircuitLibrary/4002/4002.sch new file mode 100644 index 00000000..545f46fe --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002.sch @@ -0,0 +1,315 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5CEE059A +P 4750 2900 +F 0 "U2" H 4750 2900 60 0000 C CNN +F 1 "d_or" H 4750 3000 60 0000 C CNN +F 2 "" H 4750 2900 60 0000 C CNN +F 3 "" H 4750 2900 60 0000 C CNN + 1 4750 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5CEE0629 +P 4750 3450 +F 0 "U3" H 4750 3450 60 0000 C CNN +F 1 "d_or" H 4750 3550 60 0000 C CNN +F 2 "" H 4750 3450 60 0000 C CNN +F 3 "" H 4750 3450 60 0000 C CNN + 1 4750 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 5CEE0663 +P 6000 3100 +F 0 "U6" H 6000 3100 60 0000 C CNN +F 1 "d_nor" H 6050 3200 60 0000 C CNN +F 2 "" H 6000 3100 60 0000 C CNN +F 3 "" H 6000 3100 60 0000 C CNN + 1 6000 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 2850 5400 2850 +Wire Wire Line + 5400 2850 5400 3000 +Wire Wire Line + 5400 3000 5550 3000 +Wire Wire Line + 5200 3400 5400 3400 +Wire Wire Line + 5400 3400 5400 3100 +Wire Wire Line + 5400 3100 5550 3100 +Wire Wire Line + 5650 5350 6050 5350 +Wire Wire Line + 5650 5550 6050 5550 +Wire Wire Line + 5650 5800 6050 5800 +Wire Wire Line + 5650 6000 6050 6000 +NoConn ~ 5650 5350 +NoConn ~ 5650 5550 +NoConn ~ 5650 5800 +NoConn ~ 5650 6000 +$Comp +L PORT U1 +U 2 1 5CEE1C41 +P 3850 2800 +F 0 "U1" H 3900 2900 30 0000 C CNN +F 1 "PORT" H 3850 2800 30 0000 C CNN +F 2 "" H 3850 2800 60 0000 C CNN +F 3 "" H 3850 2800 60 0000 C CNN + 2 3850 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE22EE +P 3900 3050 +F 0 "U1" H 3950 3150 30 0000 C CNN +F 1 "PORT" H 3900 3050 30 0000 C CNN +F 2 "" H 3900 3050 60 0000 C CNN +F 3 "" H 3900 3050 60 0000 C CNN + 3 3900 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE2322 +P 3900 3250 +F 0 "U1" H 3950 3350 30 0000 C CNN +F 1 "PORT" H 3900 3250 30 0000 C CNN +F 2 "" H 3900 3250 60 0000 C CNN +F 3 "" H 3900 3250 60 0000 C CNN + 5 3900 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE2351 +P 3900 3550 +F 0 "U1" H 3950 3650 30 0000 C CNN +F 1 "PORT" H 3900 3550 30 0000 C CNN +F 2 "" H 3900 3550 60 0000 C CNN +F 3 "" H 3900 3550 60 0000 C CNN + 4 3900 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE2387 +P 6950 3050 +F 0 "U1" H 7000 3150 30 0000 C CNN +F 1 "PORT" H 6950 3050 30 0000 C CNN +F 2 "" H 6950 3050 60 0000 C CNN +F 3 "" H 6950 3050 60 0000 C CNN + 1 6950 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 4100 2800 4300 2800 +Wire Wire Line + 4150 3050 4150 2900 +Wire Wire Line + 4150 2900 4300 2900 +Wire Wire Line + 4150 3250 4300 3250 +Wire Wire Line + 4300 3250 4300 3350 +Wire Wire Line + 4150 3550 4150 3450 +Wire Wire Line + 4150 3450 4300 3450 +Wire Wire Line + 6700 3050 6450 3050 +$Comp +L d_or U4 +U 1 1 5CEE4ED7 +P 4900 4100 +F 0 "U4" H 4900 4100 60 0000 C CNN +F 1 "d_or" H 4900 4200 60 0000 C CNN +F 2 "" H 4900 4100 60 0000 C CNN +F 3 "" H 4900 4100 60 0000 C CNN + 1 4900 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U5 +U 1 1 5CEE4EDD +P 4900 4650 +F 0 "U5" H 4900 4650 60 0000 C CNN +F 1 "d_or" H 4900 4750 60 0000 C CNN +F 2 "" H 4900 4650 60 0000 C CNN +F 3 "" H 4900 4650 60 0000 C CNN + 1 4900 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 5CEE4EE3 +P 6150 4300 +F 0 "U7" H 6150 4300 60 0000 C CNN +F 1 "d_nor" H 6200 4400 60 0000 C CNN +F 2 "" H 6150 4300 60 0000 C CNN +F 3 "" H 6150 4300 60 0000 C CNN + 1 6150 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 4050 5550 4050 +Wire Wire Line + 5550 4050 5550 4200 +Wire Wire Line + 5550 4200 5700 4200 +Wire Wire Line + 5350 4600 5550 4600 +Wire Wire Line + 5550 4600 5550 4300 +Wire Wire Line + 5550 4300 5700 4300 +$Comp +L PORT U1 +U 9 1 5CEE4EEF +P 4000 4000 +F 0 "U1" H 4050 4100 30 0000 C CNN +F 1 "PORT" H 4000 4000 30 0000 C CNN +F 2 "" H 4000 4000 60 0000 C CNN +F 3 "" H 4000 4000 60 0000 C CNN + 9 4000 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE4EF5 +P 4050 4250 +F 0 "U1" H 4100 4350 30 0000 C CNN +F 1 "PORT" H 4050 4250 30 0000 C CNN +F 2 "" H 4050 4250 60 0000 C CNN +F 3 "" H 4050 4250 60 0000 C CNN + 10 4050 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE4EFB +P 4050 4450 +F 0 "U1" H 4100 4550 30 0000 C CNN +F 1 "PORT" H 4050 4450 30 0000 C CNN +F 2 "" H 4050 4450 60 0000 C CNN +F 3 "" H 4050 4450 60 0000 C CNN + 11 4050 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE4F01 +P 4050 4750 +F 0 "U1" H 4100 4850 30 0000 C CNN +F 1 "PORT" H 4050 4750 30 0000 C CNN +F 2 "" H 4050 4750 60 0000 C CNN +F 3 "" H 4050 4750 60 0000 C CNN + 12 4050 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CEE4F07 +P 7100 4250 +F 0 "U1" H 7150 4350 30 0000 C CNN +F 1 "PORT" H 7100 4250 30 0000 C CNN +F 2 "" H 7100 4250 60 0000 C CNN +F 3 "" H 7100 4250 60 0000 C CNN + 13 7100 4250 + -1 0 0 1 +$EndComp +Wire Wire Line + 4250 4000 4450 4000 +Wire Wire Line + 4300 4250 4300 4100 +Wire Wire Line + 4300 4100 4450 4100 +Wire Wire Line + 4300 4450 4450 4450 +Wire Wire Line + 4450 4450 4450 4550 +Wire Wire Line + 4300 4750 4300 4650 +Wire Wire Line + 4300 4650 4450 4650 +Wire Wire Line + 6850 4250 6600 4250 +$Comp +L PORT U1 +U 6 1 5CEE51A5 +P 6300 5350 +F 0 "U1" H 6350 5450 30 0000 C CNN +F 1 "PORT" H 6300 5350 30 0000 C CNN +F 2 "" H 6300 5350 60 0000 C CNN +F 3 "" H 6300 5350 60 0000 C CNN + 6 6300 5350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE522C +P 6300 5550 +F 0 "U1" H 6350 5650 30 0000 C CNN +F 1 "PORT" H 6300 5550 30 0000 C CNN +F 2 "" H 6300 5550 60 0000 C CNN +F 3 "" H 6300 5550 60 0000 C CNN + 7 6300 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE5276 +P 6300 5800 +F 0 "U1" H 6350 5900 30 0000 C CNN +F 1 "PORT" H 6300 5800 30 0000 C CNN +F 2 "" H 6300 5800 60 0000 C CNN +F 3 "" H 6300 5800 60 0000 C CNN + 8 6300 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CEE52C5 +P 6300 6000 +F 0 "U1" H 6350 6100 30 0000 C CNN +F 1 "PORT" H 6300 6000 30 0000 C CNN +F 2 "" H 6300 6000 60 0000 C CNN +F 3 "" H 6300 6000 60 0000 C CNN + 14 6300 6000 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4002/4002.sub b/library/SubcircuitLibrary/4002/4002.sub new file mode 100644 index 00000000..b9726625 --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002.sub @@ -0,0 +1,30 @@ +* Subcircuit 4002 +.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or +* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 +a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4002
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4002/4002_Previous_Values.xml b/library/SubcircuitLibrary/4002/4002_Previous_Values.xml new file mode 100644 index 00000000..75360e5e --- /dev/null +++ b/library/SubcircuitLibrary/4002/4002_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4002/analysis b/library/SubcircuitLibrary/4002/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4002/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4012/4012-cache.lib b/library/SubcircuitLibrary/4012/4012-cache.lib new file mode 100644 index 00000000..ea0d2d70 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4012/4012.cir b/library/SubcircuitLibrary/4012/4012.cir new file mode 100644 index 00000000..a88a9da4 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter +U9 Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and +U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and +U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and + +.end diff --git a/library/SubcircuitLibrary/4012/4012.cir.out b/library/SubcircuitLibrary/4012/4012.cir.out new file mode 100644 index 00000000..c43dda8c --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.cir.out @@ -0,0 +1,44 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir + +* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter +* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +a1 net-_u6-pad3_ net-_u1-pad1_ u8 +a2 net-_u7-pad3_ net-_u1-pad13_ u9 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4012/4012.pro b/library/SubcircuitLibrary/4012/4012.pro new file mode 100644 index 00000000..0f76f4bb --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.pro @@ -0,0 +1,44 @@ +update=06/01/19 13:10:32 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_User +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/4012/4012.sch b/library/SubcircuitLibrary/4012/4012.sch new file mode 100644 index 00000000..b3320871 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.sch @@ -0,0 +1,342 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4012-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3350 2600 2550 2600 +Wire Wire Line + 3350 2700 3150 2700 +Wire Wire Line + 3150 2700 3150 2850 +Wire Wire Line + 3150 2850 2550 2850 +Wire Wire Line + 3350 3200 3150 3200 +Wire Wire Line + 3150 3200 3150 3100 +Wire Wire Line + 3150 3100 2550 3100 +Wire Wire Line + 3350 3300 2550 3300 +Wire Wire Line + 5200 2950 5500 2950 +$Comp +L d_inverter U8 +U 1 1 5CEE55AB +P 5800 2950 +F 0 "U8" H 5800 2850 60 0000 C CNN +F 1 "d_inverter" H 5800 3100 60 0000 C CNN +F 2 "" H 5850 2900 60 0000 C CNN +F 3 "" H 5850 2900 60 0000 C CNN + 1 5800 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 2950 6500 2950 +Wire Wire Line + 3400 3950 2600 3950 +Wire Wire Line + 3400 4050 3200 4050 +Wire Wire Line + 3200 4050 3200 4200 +Wire Wire Line + 3200 4200 2600 4200 +Wire Wire Line + 3400 4550 3200 4550 +Wire Wire Line + 3200 4550 3200 4450 +Wire Wire Line + 3200 4450 2600 4450 +Wire Wire Line + 3400 4650 2600 4650 +Wire Wire Line + 5250 4300 5550 4300 +$Comp +L d_inverter U9 +U 1 1 5CEE5715 +P 5850 4300 +F 0 "U9" H 5850 4200 60 0000 C CNN +F 1 "d_inverter" H 5850 4450 60 0000 C CNN +F 2 "" H 5900 4250 60 0000 C CNN +F 3 "" H 5900 4250 60 0000 C CNN + 1 5850 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 4300 6550 4300 +$Comp +L PORT U1 +U 2 1 5CEE57D6 +P 2300 2600 +F 0 "U1" H 2350 2700 30 0000 C CNN +F 1 "PORT" H 2300 2600 30 0000 C CNN +F 2 "" H 2300 2600 60 0000 C CNN +F 3 "" H 2300 2600 60 0000 C CNN + 2 2300 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE587B +P 2300 2850 +F 0 "U1" H 2350 2950 30 0000 C CNN +F 1 "PORT" H 2300 2850 30 0000 C CNN +F 2 "" H 2300 2850 60 0000 C CNN +F 3 "" H 2300 2850 60 0000 C CNN + 3 2300 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE58AF +P 2300 3100 +F 0 "U1" H 2350 3200 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN +F 2 "" H 2300 3100 60 0000 C CNN +F 3 "" H 2300 3100 60 0000 C CNN + 4 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CEE58E6 +P 6800 4300 +F 0 "U1" H 6850 4400 30 0000 C CNN +F 1 "PORT" H 6800 4300 30 0000 C CNN +F 2 "" H 6800 4300 60 0000 C CNN +F 3 "" H 6800 4300 60 0000 C CNN + 13 6800 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE5922 +P 2300 3300 +AR Path="/5CEE58E6" Ref="U1" Part="1" +AR Path="/5CEE5922" Ref="U1" Part="5" +F 0 "U1" H 2350 3400 30 0000 C CNN +F 1 "PORT" H 2300 3300 30 0000 C CNN +F 2 "" H 2300 3300 60 0000 C CNN +F 3 "" H 2300 3300 60 0000 C CNN + 5 2300 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CEE596F +P 2350 3950 +AR Path="/5CEE5922" Ref="U1" Part="5" +AR Path="/5CEE596F" Ref="U1" Part="9" +F 0 "U1" H 2400 4050 30 0000 C CNN +F 1 "PORT" H 2350 3950 30 0000 C CNN +F 2 "" H 2350 3950 60 0000 C CNN +F 3 "" H 2350 3950 60 0000 C CNN + 9 2350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE59AF +P 2350 4200 +AR Path="/5CEE596F" Ref="U1" Part="6" +AR Path="/5CEE59AF" Ref="U1" Part="10" +F 0 "U1" H 2400 4300 30 0000 C CNN +F 1 "PORT" H 2350 4200 30 0000 C CNN +F 2 "" H 2350 4200 60 0000 C CNN +F 3 "" H 2350 4200 60 0000 C CNN + 10 2350 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE59F6 +P 2350 4450 +AR Path="/5CEE59AF" Ref="U1" Part="7" +AR Path="/5CEE59F6" Ref="U1" Part="11" +F 0 "U1" H 2400 4550 30 0000 C CNN +F 1 "PORT" H 2350 4450 30 0000 C CNN +F 2 "" H 2350 4450 60 0000 C CNN +F 3 "" H 2350 4450 60 0000 C CNN + 11 2350 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE5A6A +P 2350 4650 +AR Path="/5CEE59F6" Ref="U1" Part="8" +AR Path="/5CEE5A6A" Ref="U1" Part="12" +F 0 "U1" H 2400 4750 30 0000 C CNN +F 1 "PORT" H 2350 4650 30 0000 C CNN +F 2 "" H 2350 4650 60 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 12 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE5BF8 +P 6750 2950 +AR Path="/5CEE5A6A" Ref="U1" Part="9" +AR Path="/5CEE5BF8" Ref="U1" Part="1" +F 0 "U1" H 6800 3050 30 0000 C CNN +F 1 "PORT" H 6750 2950 30 0000 C CNN +F 2 "" H 6750 2950 60 0000 C CNN +F 3 "" H 6750 2950 60 0000 C CNN + 1 6750 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CEE5C72 +P 7850 1450 +F 0 "U1" H 7900 1550 30 0000 C CNN +F 1 "PORT" H 7850 1450 30 0000 C CNN +F 2 "" H 7850 1450 60 0000 C CNN +F 3 "" H 7850 1450 60 0000 C CNN + 6 7850 1450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE5D23 +P 7850 1700 +F 0 "U1" H 7900 1800 30 0000 C CNN +F 1 "PORT" H 7850 1700 30 0000 C CNN +F 2 "" H 7850 1700 60 0000 C CNN +F 3 "" H 7850 1700 60 0000 C CNN + 7 7850 1700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CEE5D75 +P 7850 1950 +F 0 "U1" H 7900 2050 30 0000 C CNN +F 1 "PORT" H 7850 1950 30 0000 C CNN +F 2 "" H 7850 1950 60 0000 C CNN +F 3 "" H 7850 1950 60 0000 C CNN + 14 7850 1950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE5DCA +P 7850 2250 +F 0 "U1" H 7900 2350 30 0000 C CNN +F 1 "PORT" H 7850 2250 30 0000 C CNN +F 2 "" H 7850 2250 60 0000 C CNN +F 3 "" H 7850 2250 60 0000 C CNN + 8 7850 2250 + -1 0 0 1 +$EndComp +NoConn ~ 7600 1450 +NoConn ~ 7600 1700 +NoConn ~ 7600 1950 +NoConn ~ 7600 2250 +$Comp +L d_and U4 +U 1 1 5CEE56F6 +P 3850 4050 +F 0 "U4" H 3850 4050 60 0000 C CNN +F 1 "d_and" H 3900 4150 60 0000 C CNN +F 2 "" H 3850 4050 60 0000 C CNN +F 3 "" H 3850 4050 60 0000 C CNN + 1 3850 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5CEE56FC +P 3850 4650 +F 0 "U5" H 3850 4650 60 0000 C CNN +F 1 "d_and" H 3900 4750 60 0000 C CNN +F 2 "" H 3850 4650 60 0000 C CNN +F 3 "" H 3850 4650 60 0000 C CNN + 1 3850 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 4600 4300 4600 +Wire Wire Line + 4350 4350 4350 4600 +Wire Wire Line + 4350 4000 4350 4250 +Wire Wire Line + 4300 4000 4350 4000 +$Comp +L d_and U7 +U 1 1 5CEE5702 +P 4800 4350 +F 0 "U7" H 4800 4350 60 0000 C CNN +F 1 "d_and" H 4850 4450 60 0000 C CNN +F 2 "" H 4800 4350 60 0000 C CNN +F 3 "" H 4800 4350 60 0000 C CNN + 1 4800 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4250 2650 4300 2650 +Wire Wire Line + 4300 3250 4250 3250 +Wire Wire Line + 4300 2650 4300 2900 +Wire Wire Line + 4300 3000 4300 3250 +$Comp +L d_and U6 +U 1 1 5CEE5432 +P 4750 3000 +F 0 "U6" H 4750 3000 60 0000 C CNN +F 1 "d_and" H 4800 3100 60 0000 C CNN +F 2 "" H 4750 3000 60 0000 C CNN +F 3 "" H 4750 3000 60 0000 C CNN + 1 4750 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5CEE540C +P 3800 3300 +F 0 "U3" H 3800 3300 60 0000 C CNN +F 1 "d_and" H 3850 3400 60 0000 C CNN +F 2 "" H 3800 3300 60 0000 C CNN +F 3 "" H 3800 3300 60 0000 C CNN + 1 3800 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5CEE53DC +P 3800 2700 +F 0 "U2" H 3800 2700 60 0000 C CNN +F 1 "d_and" H 3850 2800 60 0000 C CNN +F 2 "" H 3800 2700 60 0000 C CNN +F 3 "" H 3800 2700 60 0000 C CNN + 1 3800 2700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4012/4012.sub b/library/SubcircuitLibrary/4012/4012.sub new file mode 100644 index 00000000..65263f03 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.sub @@ -0,0 +1,38 @@ +* Subcircuit 4012 +.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir +* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter +* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +a1 net-_u6-pad3_ net-_u1-pad1_ u8 +a2 net-_u7-pad3_ net-_u1-pad13_ u9 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4012
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4012/4012_Previous_Values.xml b/library/SubcircuitLibrary/4012/4012_Previous_Values.xml new file mode 100644 index 00000000..4e7e73b2 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4012/analysis b/library/SubcircuitLibrary/4012/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4012/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4017/4017-cache.lib b/library/SubcircuitLibrary/4017/4017-cache.lib new file mode 100644 index 00000000..efa6746f --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4017/4017.cir b/library/SubcircuitLibrary/4017/4017.cir new file mode 100644 index 00000000..67ac9971 --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017.cir @@ -0,0 +1,26 @@ +* C:\esim\eSim\src\SubcircuitLibrary\4017\4017.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/19 11:20:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U7 Net-_U2-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad1_ Net-_U2-Pad2_ d_dff +U11 Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad5_ Net-_U10-Pad1_ d_dff +U15 Net-_U11-Pad5_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U12-Pad1_ d_dff +U19 Net-_U10-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U13-Pad1_ d_dff +U22 Net-_U12-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U13-Pad2_ Net-_U2-Pad1_ d_dff +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad1_ d_and +U3 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U1-Pad2_ d_and +U4 Net-_U11-Pad5_ Net-_U12-Pad1_ Net-_U1-Pad3_ d_and +U5 Net-_U10-Pad2_ Net-_U13-Pad1_ Net-_U1-Pad4_ d_and +U6 Net-_U12-Pad2_ Net-_U2-Pad1_ Net-_U1-Pad5_ d_and +U8 Net-_U13-Pad2_ Net-_U11-Pad1_ Net-_U1-Pad6_ d_and +U9 Net-_U2-Pad2_ Net-_U11-Pad5_ Net-_U1-Pad7_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad8_ d_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U1-Pad9_ d_and +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad10_ d_and + +.end diff --git a/library/SubcircuitLibrary/4017/4017.cir.out b/library/SubcircuitLibrary/4017/4017.cir.out new file mode 100644 index 00000000..e3a384c5 --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017.cir.out @@ -0,0 +1,72 @@ +* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir + +* u7 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff +* u11 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff +* u15 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff +* u19 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff +* u22 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and +* u3 net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and +* u4 net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and +* u5 net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and +* u6 net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and +* u8 net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and +* u9 net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and +a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7 +a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11 +a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15 +a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19 +a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22 +a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2 +a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3 +a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4 +a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5 +a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6 +a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8 +a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10 +a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 5e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4017/4017.pro b/library/SubcircuitLibrary/4017/4017.pro new file mode 100644 index 00000000..8cdecd6c --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017.pro @@ -0,0 +1,72 @@ +update=Fri Jun 14 10:14:54 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot + diff --git a/library/SubcircuitLibrary/4017/4017.sch b/library/SubcircuitLibrary/4017/4017.sch new file mode 100644 index 00000000..05549a32 --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017.sch @@ -0,0 +1,580 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:4017-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U7 +U 1 1 5C7B9B95 +P 2300 4100 +F 0 "U7" H 2300 4100 60 0000 C CNN +F 1 "d_dff" H 2300 4250 60 0000 C CNN +F 2 "" H 2300 4100 60 0000 C CNN +F 3 "" H 2300 4100 60 0000 C CNN + 1 2300 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U11 +U 1 1 5C7B9CEE +P 3700 4100 +F 0 "U11" H 3700 4100 60 0000 C CNN +F 1 "d_dff" H 3700 4250 60 0000 C CNN +F 2 "" H 3700 4100 60 0000 C CNN +F 3 "" H 3700 4100 60 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U15 +U 1 1 5C7B9D3E +P 5150 4100 +F 0 "U15" H 5150 4100 60 0000 C CNN +F 1 "d_dff" H 5150 4250 60 0000 C CNN +F 2 "" H 5150 4100 60 0000 C CNN +F 3 "" H 5150 4100 60 0000 C CNN + 1 5150 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U19 +U 1 1 5C7B9D85 +P 6550 4100 +F 0 "U19" H 6550 4100 60 0000 C CNN +F 1 "d_dff" H 6550 4250 60 0000 C CNN +F 2 "" H 6550 4100 60 0000 C CNN +F 3 "" H 6550 4100 60 0000 C CNN + 1 6550 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U22 +U 1 1 5C7B9DD9 +P 8050 4100 +F 0 "U22" H 8050 4100 60 0000 C CNN +F 1 "d_dff" H 8050 4250 60 0000 C CNN +F 2 "" H 8050 4100 60 0000 C CNN +F 3 "" H 8050 4100 60 0000 C CNN + 1 8050 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 4400 1500 4400 +Wire Wire Line + 1500 4400 1500 5350 +Wire Wire Line + 1500 5350 7500 5350 +Wire Wire Line + 7500 5350 7500 4400 +Wire Wire Line + 2300 4700 2300 6700 +Wire Wire Line + 2300 4900 8050 4900 +Wire Wire Line + 8050 4900 8050 4700 +Wire Wire Line + 3700 4700 3700 4900 +Connection ~ 3700 4900 +Wire Wire Line + 5150 4700 5150 4900 +Connection ~ 5150 4900 +Wire Wire Line + 6550 4700 6550 4900 +Connection ~ 6550 4900 +Wire Wire Line + 6000 4400 6000 5350 +Connection ~ 6000 5350 +Wire Wire Line + 4600 4400 4600 5350 +Connection ~ 4600 5350 +Wire Wire Line + 3150 4400 3150 5350 +Connection ~ 3150 5350 +Wire Wire Line + 2300 3450 2300 3350 +Wire Wire Line + 1550 3350 8050 3350 +Wire Wire Line + 8050 3350 8050 3450 +Wire Wire Line + 6550 3450 6550 3350 +Connection ~ 6550 3350 +Wire Wire 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950 +F 0 "U1" H 3450 1050 30 0000 C CNN +F 1 "PORT" H 3400 950 30 0000 C CNN +F 2 "" H 3400 950 60 0000 C CNN +F 3 "" H 3400 950 60 0000 C CNN + 3 3400 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C7BCAA7 +P 5850 950 +F 0 "U1" H 5900 1050 30 0000 C CNN +F 1 "PORT" H 5850 950 30 0000 C CNN +F 2 "" H 5850 950 60 0000 C CNN +F 3 "" H 5850 950 60 0000 C CNN + 7 5850 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C7BCB20 +P 6400 1000 +F 0 "U1" H 6450 1100 30 0000 C CNN +F 1 "PORT" H 6400 1000 30 0000 C CNN +F 2 "" H 6400 1000 60 0000 C CNN +F 3 "" H 6400 1000 60 0000 C CNN + 8 6400 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7BCBB1 +P 3950 950 +F 0 "U1" H 4000 1050 30 0000 C CNN +F 1 "PORT" H 3950 950 30 0000 C CNN +F 2 "" H 3950 950 60 0000 C CNN +F 3 "" H 3950 950 60 0000 C CNN + 4 3950 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 5C7BCF23 +P 7050 1000 +F 0 "U1" H 7100 1100 30 0000 C CNN +F 1 "PORT" H 7050 1000 30 0000 C CNN +F 2 "" H 7050 1000 60 0000 C CNN +F 3 "" H 7050 1000 60 0000 C CNN + 9 7050 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 5C7BCFC0 +P 4600 950 +F 0 "U1" H 4650 1050 30 0000 C CNN +F 1 "PORT" H 4600 950 30 0000 C CNN +F 2 "" H 4600 950 60 0000 C CNN +F 3 "" H 4600 950 60 0000 C CNN + 5 4600 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5C7BD0A5 +P 7750 1000 +F 0 "U1" H 7800 1100 30 0000 C CNN +F 1 "PORT" H 7750 1000 30 0000 C CNN +F 2 "" H 7750 1000 60 0000 C CNN +F 3 "" H 7750 1000 60 0000 C CNN + 10 7750 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 5C7BD5BB +P 850 6700 +F 0 "U1" H 900 6800 30 0000 C CNN +F 1 "PORT" H 850 6700 30 0000 C CNN +F 2 "" H 850 6700 60 0000 C CNN +F 3 "" H 850 6700 60 0000 C CNN + 11 850 6700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 1200 2050 1400 +Wire Wire Line + 2700 1250 2700 1400 +Wire Wire Line + 3400 1200 3400 1400 +Wire Wire Line + 3950 1200 3950 1400 +Wire Wire Line + 4600 1200 4600 1400 +Wire Wire Line + 5850 1200 5850 1400 +Wire Wire Line + 6400 1250 6400 1400 +Wire Wire Line + 7050 1250 7050 1400 +Wire Wire Line + 7750 1250 7750 1400 +$Comp +L PORT U1 +U 12 1 5C8A0119 +P 2450 7200 +F 0 "U1" H 2500 7300 30 0000 C CNN +F 1 "PORT" H 2450 7200 30 0000 C CNN +F 2 "" H 2450 7200 60 0000 C CNN +F 3 "" H 2450 7200 60 0000 C CNN + 12 2450 7200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C89F7BC +P 2100 1850 +F 0 "U2" H 2100 1850 60 0000 C CNN +F 1 "d_and" H 2150 1950 60 0000 C CNN +F 2 "" H 2100 1850 60 0000 C CNN +F 3 "" H 2100 1850 60 0000 C CNN + 1 2100 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5C89FA46 +P 2750 1850 +F 0 "U3" H 2750 1850 60 0000 C CNN +F 1 "d_and" H 2800 1950 60 0000 C CNN +F 2 "" H 2750 1850 60 0000 C CNN +F 3 "" H 2750 1850 60 0000 C CNN + 1 2750 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U4 +U 1 1 5C89FAD5 +P 3450 1850 +F 0 "U4" H 3450 1850 60 0000 C CNN +F 1 "d_and" H 3500 1950 60 0000 C CNN +F 2 "" H 3450 1850 60 0000 C CNN +F 3 "" H 3450 1850 60 0000 C CNN + 1 3450 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U5 +U 1 1 5C89FB62 +P 4000 1850 +F 0 "U5" H 4000 1850 60 0000 C CNN +F 1 "d_and" H 4050 1950 60 0000 C CNN +F 2 "" H 4000 1850 60 0000 C CNN +F 3 "" H 4000 1850 60 0000 C CNN + 1 4000 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U6 +U 1 1 5C89FEBF +P 4650 1850 +F 0 "U6" H 4650 1850 60 0000 C CNN +F 1 "d_and" H 4700 1950 60 0000 C CNN +F 2 "" H 4650 1850 60 0000 C CNN +F 3 "" H 4650 1850 60 0000 C CNN + 1 4650 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U8 +U 1 1 5C89FF2C +P 5350 1850 +F 0 "U8" H 5350 1850 60 0000 C CNN +F 1 "d_and" H 5400 1950 60 0000 C CNN +F 2 "" H 5350 1850 60 0000 C CNN +F 3 "" H 5350 1850 60 0000 C CNN + 1 5350 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U9 +U 1 1 5C89FF96 +P 5900 1850 +F 0 "U9" H 5900 1850 60 0000 C CNN +F 1 "d_and" H 5950 1950 60 0000 C CNN +F 2 "" H 5900 1850 60 0000 C CNN +F 3 "" H 5900 1850 60 0000 C CNN + 1 5900 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U10 +U 1 1 5C8A066D +P 6450 1850 +F 0 "U10" H 6450 1850 60 0000 C CNN +F 1 "d_and" H 6500 1950 60 0000 C CNN +F 2 "" H 6450 1850 60 0000 C CNN +F 3 "" H 6450 1850 60 0000 C CNN + 1 6450 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U12 +U 1 1 5C8A06D8 +P 7100 1850 +F 0 "U12" H 7100 1850 60 0000 C CNN +F 1 "d_and" H 7150 1950 60 0000 C CNN +F 2 "" H 7100 1850 60 0000 C CNN +F 3 "" H 7100 1850 60 0000 C CNN + 1 7100 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U13 +U 1 1 5C8A12F5 +P 7800 1850 +F 0 "U13" H 7800 1850 60 0000 C CNN +F 1 "d_and" H 7850 1950 60 0000 C CNN +F 2 "" H 7800 1850 60 0000 C CNN +F 3 "" H 7800 1850 60 0000 C CNN + 1 7800 1850 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4017/4017.sub b/library/SubcircuitLibrary/4017/4017.sub new file mode 100644 index 00000000..2e27ab61 --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017.sub @@ -0,0 +1,66 @@ +* Subcircuit 4017 +.subckt 4017 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ +* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir +* u7 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff +* u11 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff +* u15 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff +* u19 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff +* u22 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and +* u3 net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and +* u4 net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and +* u5 net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and +* u6 net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and +* u8 net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and +* u9 net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and +a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7 +a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11 +a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15 +a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19 +a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22 +a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2 +a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3 +a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4 +a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5 +a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6 +a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8 +a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10 +a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4017
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4017/4017_Previous_Values.xml b/library/SubcircuitLibrary/4017/4017_Previous_Values.xml new file mode 100644 index 00000000..9dfd97a3 --- /dev/null +++ b/library/SubcircuitLibrary/4017/4017_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u7 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u7><u11 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u11><u15 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u19 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u22><u9 name="type">d_nand<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u9><u13 name="type">d_nor<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u13><u5 name="type">d_nand<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u5><u8 name="type">d_nand<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_nand<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_nand<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u12><u14 name="type">d_nand<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_nand<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_nand<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_nand<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u18><u20 name="type">d_nand<field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_nand<field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /></u21><u4 name="type">d_inverter<field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_inverter<field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /></u6><u23 name="type">d_inverter<field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /></u23><u24 name="type">d_buffer<field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /></u24><u2 name="type">d_and<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_and<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_and<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4017/D.lib b/library/SubcircuitLibrary/4017/D.lib new file mode 100644 index 00000000..adbdfb35 --- /dev/null +++ b/library/SubcircuitLibrary/4017/D.lib @@ -0,0 +1,11 @@ +.MODEL 1N4148 D( ++ Vj=1 ++ Cjo=1.700E-12 ++ Rs=4.755E-01 ++ Is=2.495E-09 ++ M=1.959E-01 ++ N=1.679E+00 ++ Bv=1.000E+02 ++ tt=3.030E-09 ++ Ibv=1.000E-04 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4017/analysis b/library/SubcircuitLibrary/4017/analysis new file mode 100644 index 00000000..40bd9d97 --- /dev/null +++ b/library/SubcircuitLibrary/4017/analysis @@ -0,0 +1 @@ +.tran 5e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4023/3_and-cache.lib b/library/SubcircuitLibrary/4023/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4023/3_and.cir b/library/SubcircuitLibrary/4023/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/4023/3_and.cir.out b/library/SubcircuitLibrary/4023/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4023/3_and.pro b/library/SubcircuitLibrary/4023/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/4023/3_and.sch b/library/SubcircuitLibrary/4023/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4023/3_and.sub b/library/SubcircuitLibrary/4023/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4023/3_and_Previous_Values.xml b/library/SubcircuitLibrary/4023/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/4023/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4023/4023-cache.lib b/library/SubcircuitLibrary/4023/4023-cache.lib new file mode 100644 index 00000000..c989d8c7 --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4023/4023.cir b/library/SubcircuitLibrary/4023/4023.cir new file mode 100644 index 00000000..6aad9b84 --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023.cir @@ -0,0 +1,17 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4023\4023.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 15:33:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X3 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and +U4 Net-_U4-Pad1_ Net-_U1-Pad10_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U3 Net-_U3-Pad1_ Net-_U1-Pad6_ d_inverter +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad9_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/4023/4023.cir.out b/library/SubcircuitLibrary/4023/4023.cir.out new file mode 100644 index 00000000..7f48d16f --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023.cir.out @@ -0,0 +1,28 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir + +.include 3_and.sub +x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and +* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter +a1 net-_u4-pad1_ net-_u1-pad10_ u4 +a2 net-_u3-pad1_ net-_u1-pad6_ u3 +a3 net-_u2-pad1_ net-_u1-pad9_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4023/4023.pro b/library/SubcircuitLibrary/4023/4023.pro new file mode 100644 index 00000000..5a5ce355 --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:32:35 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/4023/4023.sch b/library/SubcircuitLibrary/4023/4023.sch new file mode 100644 index 00000000..57dd7868 --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023.sch @@ -0,0 +1,309 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X3 +U 1 1 5CF0FA82 +P 4800 2500 +F 0 "X3" H 4900 2450 60 0000 C CNN +F 1 "3_and" H 4950 2650 60 0000 C CNN +F 2 "" H 4800 2500 60 0000 C CNN +F 3 "" H 4800 2500 60 0000 C CNN + 1 4800 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF0FB13 +P 6150 2450 +F 0 "U4" H 6150 2350 60 0000 C CNN +F 1 "d_inverter" H 6150 2600 60 0000 C CNN +F 2 "" H 6200 2400 60 0000 C CNN +F 3 "" H 6200 2400 60 0000 C CNN + 1 6150 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF0FB34 +P 3100 1950 +F 0 "U1" H 3150 2050 30 0000 C CNN +F 1 "PORT" H 3100 1950 30 0000 C CNN +F 2 "" H 3100 1950 60 0000 C CNN +F 3 "" H 3100 1950 60 0000 C CNN + 11 3100 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF0FB90 +P 3100 2350 +F 0 "U1" H 3150 2450 30 0000 C CNN +F 1 "PORT" H 3100 2350 30 0000 C CNN +F 2 "" H 3100 2350 60 0000 C CNN +F 3 "" H 3100 2350 60 0000 C CNN + 12 3100 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF0FBB8 +P 3100 2750 +F 0 "U1" H 3150 2850 30 0000 C CNN +F 1 "PORT" H 3100 2750 30 0000 C CNN +F 2 "" H 3100 2750 60 0000 C CNN +F 3 "" H 3100 2750 60 0000 C CNN + 13 3100 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF0FBED +P 7800 2450 +F 0 "U1" H 7850 2550 30 0000 C CNN +F 1 "PORT" H 7800 2450 30 0000 C CNN +F 2 "" H 7800 2450 60 0000 C CNN +F 3 "" H 7800 2450 60 0000 C CNN + 10 7800 2450 + -1 0 0 1 +$EndComp +Wire Wire Line + 7550 2450 6450 2450 +Wire Wire Line + 5850 2450 5300 2450 +Wire Wire Line + 4450 2350 4450 1950 +Wire Wire Line + 4450 1950 3350 1950 +Wire Wire Line + 4450 2450 4100 2450 +Wire Wire Line + 4100 2450 4100 2350 +Wire Wire Line + 4100 2350 3350 2350 +Wire Wire Line + 3350 2750 3950 2750 +Wire Wire Line + 3950 2750 3950 2550 +Wire Wire Line + 3950 2550 4450 2550 +$Comp +L 3_and X2 +U 1 1 5CF0FF35 +P 4700 3800 +F 0 "X2" H 4800 3750 60 0000 C CNN +F 1 "3_and" H 4850 3950 60 0000 C CNN +F 2 "" H 4700 3800 60 0000 C CNN +F 3 "" H 4700 3800 60 0000 C CNN + 1 4700 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5CF0FF3B +P 6050 3750 +F 0 "U3" H 6050 3650 60 0000 C CNN +F 1 "d_inverter" H 6050 3900 60 0000 C CNN +F 2 "" H 6100 3700 60 0000 C CNN +F 3 "" H 6100 3700 60 0000 C CNN + 1 6050 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF0FF41 +P 3000 3250 +F 0 "U1" H 3050 3350 30 0000 C CNN +F 1 "PORT" H 3000 3250 30 0000 C CNN +F 2 "" H 3000 3250 60 0000 C CNN +F 3 "" H 3000 3250 60 0000 C CNN + 4 3000 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF0FF47 +P 3000 3650 +F 0 "U1" H 3050 3750 30 0000 C CNN +F 1 "PORT" H 3000 3650 30 0000 C CNN +F 2 "" H 3000 3650 60 0000 C CNN +F 3 "" H 3000 3650 60 0000 C CNN + 5 3000 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF0FF4D +P 3000 4050 +F 0 "U1" H 3050 4150 30 0000 C CNN +F 1 "PORT" H 3000 4050 30 0000 C CNN +F 2 "" H 3000 4050 60 0000 C CNN +F 3 "" H 3000 4050 60 0000 C CNN + 3 3000 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF0FF53 +P 7700 3750 +F 0 "U1" H 7750 3850 30 0000 C CNN +F 1 "PORT" H 7700 3750 30 0000 C CNN +F 2 "" H 7700 3750 60 0000 C CNN +F 3 "" H 7700 3750 60 0000 C CNN + 6 7700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 7450 3750 6350 3750 +Wire Wire Line + 5750 3750 5200 3750 +Wire Wire Line + 4350 3650 4350 3250 +Wire Wire Line + 4350 3250 3250 3250 +Wire Wire Line + 4350 3750 4000 3750 +Wire Wire Line + 4000 3750 4000 3650 +Wire Wire Line + 4000 3650 3250 3650 +Wire Wire Line + 3250 4050 3850 4050 +Wire Wire Line + 3850 4050 3850 3850 +Wire Wire Line + 3850 3850 4350 3850 +$Comp +L 3_and X1 +U 1 1 5CF100B9 +P 4650 5100 +F 0 "X1" H 4750 5050 60 0000 C CNN +F 1 "3_and" H 4800 5250 60 0000 C CNN +F 2 "" H 4650 5100 60 0000 C CNN +F 3 "" H 4650 5100 60 0000 C CNN + 1 4650 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5CF100BF +P 6000 5050 +F 0 "U2" H 6000 4950 60 0000 C CNN +F 1 "d_inverter" H 6000 5200 60 0000 C CNN +F 2 "" H 6050 5000 60 0000 C CNN +F 3 "" H 6050 5000 60 0000 C CNN + 1 6000 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF100C5 +P 2950 4550 +F 0 "U1" H 3000 4650 30 0000 C CNN +F 1 "PORT" H 2950 4550 30 0000 C CNN +F 2 "" H 2950 4550 60 0000 C CNN +F 3 "" H 2950 4550 60 0000 C CNN + 1 2950 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF100CB +P 2950 4950 +F 0 "U1" H 3000 5050 30 0000 C CNN +F 1 "PORT" H 2950 4950 30 0000 C CNN +F 2 "" H 2950 4950 60 0000 C CNN +F 3 "" H 2950 4950 60 0000 C CNN + 2 2950 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF100D1 +P 2950 5350 +F 0 "U1" H 3000 5450 30 0000 C CNN +F 1 "PORT" H 2950 5350 30 0000 C CNN +F 2 "" H 2950 5350 60 0000 C CNN +F 3 "" H 2950 5350 60 0000 C CNN + 8 2950 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF100D7 +P 7650 5050 +F 0 "U1" H 7700 5150 30 0000 C CNN +F 1 "PORT" H 7650 5050 30 0000 C CNN +F 2 "" H 7650 5050 60 0000 C CNN +F 3 "" H 7650 5050 60 0000 C CNN + 9 7650 5050 + -1 0 0 1 +$EndComp +Wire Wire Line + 7400 5050 6300 5050 +Wire Wire Line + 5700 5050 5150 5050 +Wire Wire Line + 4300 4950 4300 4550 +Wire Wire Line + 4300 4550 3200 4550 +Wire Wire Line + 4300 5050 3950 5050 +Wire Wire Line + 3950 5050 3950 4950 +Wire Wire Line + 3950 4950 3200 4950 +Wire Wire Line + 3200 5350 3800 5350 +Wire Wire Line + 3800 5350 3800 5150 +Wire Wire Line + 3800 5150 4300 5150 +$Comp +L PORT U1 +U 7 1 5CF101BF +P 9950 3350 +F 0 "U1" H 10000 3450 30 0000 C CNN +F 1 "PORT" H 9950 3350 30 0000 C CNN +F 2 "" H 9950 3350 60 0000 C CNN +F 3 "" H 9950 3350 60 0000 C CNN + 7 9950 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF1025C +P 9950 3900 +F 0 "U1" H 10000 4000 30 0000 C CNN +F 1 "PORT" H 9950 3900 30 0000 C CNN +F 2 "" H 9950 3900 60 0000 C CNN +F 3 "" H 9950 3900 60 0000 C CNN + 14 9950 3900 + -1 0 0 1 +$EndComp +NoConn ~ 9700 3350 +NoConn ~ 9700 3900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4023/4023.sub b/library/SubcircuitLibrary/4023/4023.sub new file mode 100644 index 00000000..b953da2e --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023.sub @@ -0,0 +1,22 @@ +* Subcircuit 4023 +.subckt 4023 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir +.include 3_and.sub +x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and +* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter +a1 net-_u4-pad1_ net-_u1-pad10_ u4 +a2 net-_u3-pad1_ net-_u1-pad6_ u3 +a3 net-_u2-pad1_ net-_u1-pad9_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4023
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4023/4023_Previous_Values.xml b/library/SubcircuitLibrary/4023/4023_Previous_Values.xml new file mode 100644 index 00000000..ad900de2 --- /dev/null +++ b/library/SubcircuitLibrary/4023/4023_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u4 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4023/analysis b/library/SubcircuitLibrary/4023/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4023/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4028/4028-cache.lib b/library/SubcircuitLibrary/4028/4028-cache.lib new file mode 100644 index 00000000..5b7e8ebd --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4028/4028.cir b/library/SubcircuitLibrary/4028/4028.cir new file mode 100644 index 00000000..ff25eb55 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U9 Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor +U10 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor +U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor +U6 Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor +U7 Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor +U8 Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor +U2 Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter +U3 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter +U4 Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter +U15 Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and +U16 Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and +U17 Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and +U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and +U19 Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and +U20 Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and +U21 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and +U13 Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U22 Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and + +.end diff --git a/library/SubcircuitLibrary/4028/4028.cir.out b/library/SubcircuitLibrary/4028/4028.cir.out new file mode 100644 index 00000000..882115b7 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028.cir.out @@ -0,0 +1,96 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir + +* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor +* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor +* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor +* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor +* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor +* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor +* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter +* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter +* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and +* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and +* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and +* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and +* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and +* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and +a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9 +a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12 +a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6 +a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7 +a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8 +a8 net-_u1-pad10_ net-_u11-pad1_ u2 +a9 net-_u1-pad13_ net-_u10-pad2_ u3 +a10 net-_u1-pad12_ net-_u4-pad2_ u4 +a11 net-_u1-pad11_ net-_u5-pad2_ u5 +a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15 +a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16 +a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17 +a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18 +a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19 +a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20 +a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21 +a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13 +a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14 +a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4028/4028.pro b/library/SubcircuitLibrary/4028/4028.pro new file mode 100644 index 00000000..a63207b3 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:43:40 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/4028/4028.sch b/library/SubcircuitLibrary/4028/4028.sch new file mode 100644 index 00000000..373a95e6 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028.sch @@ -0,0 +1,628 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nor U9 +U 1 1 5CF0FE64 +P 3750 2500 +F 0 "U9" H 3750 2500 60 0000 C CNN +F 1 "d_nor" H 3800 2600 60 0000 C CNN +F 2 "" H 3750 2500 60 0000 C CNN +F 3 "" H 3750 2500 60 0000 C CNN + 1 3750 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U10 +U 1 1 5CF0FEA4 +P 3750 3050 +F 0 "U10" H 3750 3050 60 0000 C CNN +F 1 "d_nor" H 3800 3150 60 0000 C CNN +F 2 "" H 3750 3050 60 0000 C CNN +F 3 "" H 3750 3050 60 0000 C CNN + 1 3750 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U11 +U 1 1 5CF0FECC +P 3750 3550 +F 0 "U11" H 3750 3550 60 0000 C CNN +F 1 "d_nor" H 3800 3650 60 0000 C CNN +F 2 "" H 3750 3550 60 0000 C CNN +F 3 "" H 3750 3550 60 0000 C CNN + 1 3750 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U12 +U 1 1 5CF0FEF5 +P 3750 4150 +F 0 "U12" H 3750 4150 60 0000 C CNN +F 1 "d_nor" H 3800 4250 60 0000 C CNN +F 2 "" H 3750 4150 60 0000 C CNN +F 3 "" H 3750 4150 60 0000 C CNN + 1 3750 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 5CF0FF23 +P 3700 4750 +F 0 "U6" H 3700 4750 60 0000 C CNN +F 1 "d_nor" H 3750 4850 60 0000 C CNN +F 2 "" H 3700 4750 60 0000 C CNN +F 3 "" H 3700 4750 60 0000 C CNN + 1 3700 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 5CF0FF59 +P 3700 5250 +F 0 "U7" H 3700 5250 60 0000 C CNN +F 1 "d_nor" H 3750 5350 60 0000 C CNN +F 2 "" H 3700 5250 60 0000 C CNN +F 3 "" H 3700 5250 60 0000 C CNN + 1 3700 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U8 +U 1 1 5CF0FFA9 +P 3750 2000 +F 0 "U8" H 3750 2000 60 0000 C CNN +F 1 "d_nor" H 3800 2100 60 0000 C CNN +F 2 "" H 3750 2000 60 0000 C CNN +F 3 "" H 3750 2000 60 0000 C CNN + 1 3750 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5CF1003A +P 2150 2400 +F 0 "U2" H 2150 2300 60 0000 C CNN +F 1 "d_inverter" H 2150 2550 60 0000 C CNN +F 2 "" H 2200 2350 60 0000 C CNN +F 3 "" H 2200 2350 60 0000 C CNN + 1 2150 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5CF1007F +P 2150 3300 +F 0 "U3" H 2150 3200 60 0000 C CNN +F 1 "d_inverter" H 2150 3450 60 0000 C CNN +F 2 "" H 2200 3250 60 0000 C CNN +F 3 "" H 2200 3250 60 0000 C CNN + 1 2150 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF100CC +P 2150 4150 +F 0 "U4" H 2150 4050 60 0000 C CNN +F 1 "d_inverter" H 2150 4300 60 0000 C CNN +F 2 "" H 2200 4100 60 0000 C CNN +F 3 "" H 2200 4100 60 0000 C CNN + 1 2150 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5CF10114 +P 2150 4900 +F 0 "U5" H 2150 4800 60 0000 C CNN +F 1 "d_inverter" H 2150 5050 60 0000 C CNN +F 2 "" H 2200 4850 60 0000 C CNN +F 3 "" H 2200 4850 60 0000 C CNN + 1 2150 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2400 1850 2400 +Wire Wire Line + 1400 3300 1850 3300 +Wire Wire Line + 1450 4150 1850 4150 +Wire Wire Line + 1450 4900 1850 4900 +Wire Wire Line + 2450 4900 2500 4900 +Wire Wire Line + 2500 4900 2500 5250 +Wire Wire Line + 2500 5250 3250 5250 +Wire Wire Line + 2450 4150 2550 4150 +Wire Wire Line + 2550 4150 2550 4650 +Wire Wire Line + 2550 4650 3250 4650 +Wire Wire Line + 2450 3300 2550 3300 +Wire Wire Line + 2550 3300 2550 3550 +Wire Wire Line + 2550 3550 3300 3550 +Wire Wire Line + 2450 2400 2450 2500 +Wire Wire Line + 2450 2500 3300 2500 +Wire Wire Line + 2800 2500 2800 3450 +Wire Wire Line + 2800 3450 3300 3450 +Connection ~ 2800 2500 +Wire Wire Line + 1650 2400 1650 1900 +Wire Wire Line + 1650 1900 3300 1900 +Connection ~ 1650 2400 +Wire Wire Line + 3300 2000 2850 2000 +Wire Wire Line + 2850 2000 2850 3000 +Wire Wire Line + 2850 3000 1650 3000 +Wire Wire Line + 1650 3000 1650 3300 +Connection ~ 1650 3300 +Wire Wire Line + 2850 2400 3300 2400 +Connection ~ 2850 2400 +Wire Wire Line + 2950 1900 2950 2950 +Wire Wire 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60 0000 C CNN +F 3 "" H 6600 2350 60 0000 C CNN + 1 6600 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 5CF107A1 +P 6600 2800 +F 0 "U17" H 6600 2800 60 0000 C CNN +F 1 "d_and" H 6650 2900 60 0000 C CNN +F 2 "" H 6600 2800 60 0000 C CNN +F 3 "" H 6600 2800 60 0000 C CNN + 1 6600 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5CF107E9 +P 6600 3200 +F 0 "U18" H 6600 3200 60 0000 C CNN +F 1 "d_and" H 6650 3300 60 0000 C CNN +F 2 "" H 6600 3200 60 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5CF10834 +P 6600 3650 +F 0 "U19" H 6600 3650 60 0000 C CNN +F 1 "d_and" H 6650 3750 60 0000 C CNN +F 2 "" H 6600 3650 60 0000 C CNN +F 3 "" H 6600 3650 60 0000 C CNN + 1 6600 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 5CF1087E +P 6600 4050 +F 0 "U20" H 6600 4050 60 0000 C CNN +F 1 "d_and" H 6650 4150 60 0000 C CNN +F 2 "" H 6600 4050 60 0000 C CNN +F 3 "" H 6600 4050 60 0000 C CNN + 1 6600 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 5CF108F9 +P 6600 4450 +F 0 "U21" H 6600 4450 60 0000 C CNN +F 1 "d_and" H 6650 4550 60 0000 C CNN +F 2 "" H 6600 4450 60 0000 C CNN +F 3 "" H 6600 4450 60 0000 C CNN + 1 6600 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 5CF1094D +P 6550 4900 +F 0 "U13" H 6550 4900 60 0000 C CNN +F 1 "d_and" H 6600 5000 60 0000 C CNN +F 2 "" H 6550 4900 60 0000 C CNN +F 3 "" H 6550 4900 60 0000 C CNN + 1 6550 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 5CF109A6 +P 6550 5350 +F 0 "U14" H 6550 5350 60 0000 C CNN +F 1 "d_and" H 6600 5450 60 0000 C CNN +F 2 "" H 6550 5350 60 0000 C CNN +F 3 "" H 6550 5350 60 0000 C CNN + 1 6550 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF11966 +P 1150 2400 +F 0 "U1" H 1200 2500 30 0000 C CNN +F 1 "PORT" H 1150 2400 30 0000 C CNN +F 2 "" H 1150 2400 60 0000 C CNN +F 3 "" H 1150 2400 60 0000 C CNN + 10 1150 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF119D4 +P 1150 3300 +F 0 "U1" H 1200 3400 30 0000 C CNN +F 1 "PORT" H 1150 3300 30 0000 C CNN +F 2 "" H 1150 3300 60 0000 C CNN +F 3 "" H 1150 3300 60 0000 C CNN + 13 1150 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF11AFC +P 1200 4150 +F 0 "U1" H 1250 4250 30 0000 C CNN +F 1 "PORT" H 1200 4150 30 0000 C CNN +F 2 "" H 1200 4150 60 0000 C CNN +F 3 "" H 1200 4150 60 0000 C CNN + 12 1200 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF11B6B +P 1200 4900 +F 0 "U1" H 1250 5000 30 0000 C CNN +F 1 "PORT" H 1200 4900 30 0000 C CNN +F 2 "" H 1200 4900 60 0000 C CNN +F 3 "" H 1200 4900 60 0000 C CNN + 11 1200 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF11BDB +P 8000 1800 +F 0 "U1" H 8050 1900 30 0000 C CNN +F 1 "PORT" H 8000 1800 30 0000 C CNN +F 2 "" H 8000 1800 60 0000 C CNN +F 3 "" H 8000 1800 60 0000 C CNN + 3 8000 1800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF11F59 +P 8000 2300 +F 0 "U1" H 8050 2400 30 0000 C CNN +F 1 "PORT" H 8000 2300 30 0000 C CNN +F 2 "" H 8000 2300 60 0000 C CNN +F 3 "" H 8000 2300 60 0000 C CNN + 14 8000 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF11FC5 +P 8000 2750 +F 0 "U1" H 8050 2850 30 0000 C CNN +F 1 "PORT" H 8000 2750 30 0000 C CNN +F 2 "" H 8000 2750 60 0000 C CNN +F 3 "" H 8000 2750 60 0000 C CNN + 2 8000 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 5CF1204F +P 8000 3150 +F 0 "U1" H 8050 3250 30 0000 C CNN +F 1 "PORT" H 8000 3150 30 0000 C CNN +F 2 "" H 8000 3150 60 0000 C CNN +F 3 "" H 8000 3150 60 0000 C CNN + 15 8000 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF120C5 +P 7950 3600 +F 0 "U1" H 8000 3700 30 0000 C CNN +F 1 "PORT" H 7950 3600 30 0000 C CNN +F 2 "" H 7950 3600 60 0000 C CNN +F 3 "" H 7950 3600 60 0000 C CNN + 1 7950 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF1213C +P 7950 4000 +F 0 "U1" H 8000 4100 30 0000 C CNN +F 1 "PORT" H 7950 4000 30 0000 C CNN +F 2 "" H 7950 4000 60 0000 C CNN +F 3 "" H 7950 4000 60 0000 C CNN + 6 7950 4000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CF121B2 +P 7900 4400 +F 0 "U1" H 7950 4500 30 0000 C CNN +F 1 "PORT" H 7900 4400 30 0000 C CNN +F 2 "" H 7900 4400 60 0000 C CNN +F 3 "" H 7900 4400 60 0000 C CNN + 7 7900 4400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF1223D +P 7900 4850 +F 0 "U1" H 7950 4950 30 0000 C CNN +F 1 "PORT" H 7900 4850 30 0000 C CNN +F 2 "" H 7900 4850 60 0000 C CNN +F 3 "" H 7900 4850 60 0000 C CNN + 4 7900 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF1237B +P 7900 5300 +F 0 "U1" H 7950 5400 30 0000 C CNN +F 1 "PORT" H 7900 5300 30 0000 C CNN +F 2 "" H 7900 5300 60 0000 C CNN +F 3 "" H 7900 5300 60 0000 C CNN + 9 7900 5300 + -1 0 0 1 +$EndComp +Wire Wire Line + 7750 1800 7050 1800 +Wire Wire Line + 7050 2300 7750 2300 +Wire Wire Line + 7750 2750 7050 2750 +Wire Wire Line + 7050 3150 7750 3150 +Wire Wire Line + 7700 3600 7050 3600 +Wire Wire Line + 7050 4000 7700 4000 +Wire Wire Line + 7650 4400 7050 4400 +Wire Wire Line + 7000 4850 7650 4850 +Wire Wire Line + 7650 5300 7000 5300 +$Comp +L d_and U22 +U 1 1 5CF14904 +P 6550 5800 +F 0 "U22" H 6550 5800 60 0000 C CNN +F 1 "d_and" H 6600 5900 60 0000 C CNN +F 2 "" H 6550 5800 60 0000 C CNN +F 3 "" H 6550 5800 60 0000 C CNN + 1 6550 5800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 1950 4600 1950 +Wire Wire Line + 4600 1750 4600 5250 +Wire Wire Line + 4600 1750 6150 1750 +Wire Wire Line + 4600 5250 6100 5250 +Connection ~ 4600 1950 +Wire Wire Line + 6100 5800 5900 5800 +Wire Wire Line + 5900 5800 5900 5350 +Wire Wire Line + 5900 5350 6100 5350 +Wire Wire Line + 5850 4900 6100 4900 +Wire Wire Line + 5850 3650 5850 4900 +Wire Wire Line + 5850 4450 6150 4450 +Wire Wire Line + 5850 4050 6150 4050 +Connection ~ 5850 4450 +Wire Wire Line + 5850 3650 6150 3650 +Connection ~ 5850 4050 +Wire Wire Line + 5050 3200 6150 3200 +Wire Wire Line + 5850 1850 5850 3200 +Wire Wire Line + 5850 2800 6150 2800 +Wire Wire Line + 5850 2350 6150 2350 +Connection ~ 5850 2800 +Wire Wire Line + 5850 1850 6150 1850 +Connection ~ 5850 2350 +Wire Wire Line + 4200 2450 4700 2450 +Wire Wire Line + 4700 2250 4700 5700 +Wire Wire Line + 4700 2250 6150 2250 +Wire Wire Line + 4200 3000 4800 3000 +Wire Wire Line + 4800 2700 4800 4350 +Wire Wire Line + 4800 2700 6150 2700 +Wire Wire Line + 4700 5700 6100 5700 +Connection ~ 4700 2450 +Wire Wire Line + 6150 3550 4600 3550 +Connection ~ 4600 3550 +Wire Wire Line + 6150 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4800 4350 6150 4350 +Connection ~ 4800 3000 +Wire Wire Line + 4200 3500 4900 3500 +Wire Wire Line + 4900 3100 4900 4800 +Wire Wire Line + 4900 3100 6150 3100 +Wire Wire Line + 4900 4800 6100 4800 +Connection ~ 4900 3500 +Wire Wire Line + 4200 4100 5050 4100 +Wire Wire Line + 5050 4100 5050 3200 +Connection ~ 5850 3200 +Wire Wire Line + 4150 4700 5850 4700 +Connection ~ 5850 4700 +Wire Wire Line + 4150 5200 4500 5200 +Wire Wire Line + 4500 5200 4500 5550 +Wire Wire Line + 4500 5550 5900 5550 +Connection ~ 5900 5550 +$Comp +L PORT U1 +U 5 1 5CF1563E +P 7950 5750 +F 0 "U1" H 8000 5850 30 0000 C CNN +F 1 "PORT" H 7950 5750 30 0000 C CNN +F 2 "" H 7950 5750 60 0000 C CNN +F 3 "" H 7950 5750 60 0000 C CNN + 5 7950 5750 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 5750 7000 5750 +$Comp +L PORT U1 +U 8 1 5CF15953 +P 9550 4800 +F 0 "U1" H 9600 4900 30 0000 C CNN +F 1 "PORT" H 9550 4800 30 0000 C CNN +F 2 "" H 9550 4800 60 0000 C CNN +F 3 "" H 9550 4800 60 0000 C CNN + 8 9550 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 5CF15A07 +P 9550 5250 +F 0 "U1" H 9600 5350 30 0000 C CNN +F 1 "PORT" H 9550 5250 30 0000 C CNN +F 2 "" H 9550 5250 60 0000 C CNN +F 3 "" H 9550 5250 60 0000 C CNN + 16 9550 5250 + -1 0 0 1 +$EndComp +NoConn ~ 9300 4800 +NoConn ~ 9300 5250 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4028/4028.sub b/library/SubcircuitLibrary/4028/4028.sub new file mode 100644 index 00000000..828e0b67 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028.sub @@ -0,0 +1,90 @@ +* Subcircuit 4028 +.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir +* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor +* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor +* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor +* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor +* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor +* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor +* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter +* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter +* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and +* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and +* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and +* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and +* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and +* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and +* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and +a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9 +a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12 +a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6 +a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7 +a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8 +a8 net-_u1-pad10_ net-_u11-pad1_ u2 +a9 net-_u1-pad13_ net-_u10-pad2_ u3 +a10 net-_u1-pad12_ net-_u4-pad2_ u4 +a11 net-_u1-pad11_ net-_u5-pad2_ u5 +a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15 +a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16 +a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17 +a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18 +a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19 +a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20 +a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21 +a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13 +a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14 +a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4028
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4028/4028_Previous_Values.xml b/library/SubcircuitLibrary/4028/4028_Previous_Values.xml new file mode 100644 index 00000000..189fb200 --- /dev/null +++ b/library/SubcircuitLibrary/4028/4028_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4028/analysis b/library/SubcircuitLibrary/4028/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4028/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4073/3_and-cache.lib b/library/SubcircuitLibrary/4073/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4073/3_and.cir b/library/SubcircuitLibrary/4073/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/4073/3_and.cir.out b/library/SubcircuitLibrary/4073/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4073/3_and.pro b/library/SubcircuitLibrary/4073/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/4073/3_and.sch b/library/SubcircuitLibrary/4073/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4073/3_and.sub b/library/SubcircuitLibrary/4073/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4073/3_and_Previous_Values.xml b/library/SubcircuitLibrary/4073/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/4073/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4073/4073-cache.lib b/library/SubcircuitLibrary/4073/4073-cache.lib new file mode 100644 index 00000000..4ee605a2 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4073/4073.cir b/library/SubcircuitLibrary/4073/4073.cir new file mode 100644 index 00000000..e159f055 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and +X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and + +.end diff --git a/library/SubcircuitLibrary/4073/4073.cir.out b/library/SubcircuitLibrary/4073/4073.cir.out new file mode 100644 index 00000000..b25337cd --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073.cir.out @@ -0,0 +1,16 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4073/4073.pro b/library/SubcircuitLibrary/4073/4073.pro new file mode 100644 index 00000000..94cd9bd4 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073.pro @@ -0,0 +1,43 @@ +update=05/31/19 16:37:06 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/4073/4073.sch b/library/SubcircuitLibrary/4073/4073.sch new file mode 100644 index 00000000..045208e6 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073.sch @@ -0,0 +1,263 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5CF10AEA +P 4550 2650 +F 0 "X1" H 4650 2600 60 0000 C CNN +F 1 "3_and" H 4700 2800 60 0000 C CNN +F 2 "" H 4550 2650 60 0000 C CNN +F 3 "" H 4550 2650 60 0000 C CNN + 1 4550 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF10B72 +P 3100 2200 +F 0 "U1" H 3150 2300 30 0000 C CNN +F 1 "PORT" H 3100 2200 30 0000 C CNN +F 2 "" H 3100 2200 60 0000 C CNN +F 3 "" H 3100 2200 60 0000 C CNN + 1 3100 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF10BC9 +P 3100 2500 +F 0 "U1" H 3150 2600 30 0000 C CNN +F 1 "PORT" H 3100 2500 30 0000 C CNN +F 2 "" H 3100 2500 60 0000 C CNN +F 3 "" H 3100 2500 60 0000 C CNN + 2 3100 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF10BEA +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 8 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF10C10 +P 6200 2600 +F 0 "U1" H 6250 2700 30 0000 C CNN +F 1 "PORT" H 6200 2600 30 0000 C CNN +F 2 "" H 6200 2600 60 0000 C CNN +F 3 "" H 6200 2600 60 0000 C CNN + 9 6200 2600 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2600 5050 2600 +Wire Wire Line + 4200 2500 4200 2200 +Wire Wire Line + 4200 2200 3350 2200 +Wire Wire Line + 3350 2500 3850 2500 +Wire Wire Line + 3850 2500 3850 2600 +Wire Wire Line + 3850 2600 4200 2600 +Wire Wire Line + 4200 2700 4200 2850 +Wire Wire Line + 4200 2850 3350 2850 +$Comp +L 3_and X3 +U 1 1 5CF10DE5 +P 4600 4100 +F 0 "X3" H 4700 4050 60 0000 C CNN +F 1 "3_and" H 4750 4250 60 0000 C CNN +F 2 "" H 4600 4100 60 0000 C CNN +F 3 "" H 4600 4100 60 0000 C CNN + 1 4600 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF10DEB +P 3150 3650 +F 0 "U1" H 3200 3750 30 0000 C CNN +F 1 "PORT" H 3150 3650 30 0000 C CNN +F 2 "" H 3150 3650 60 0000 C CNN +F 3 "" H 3150 3650 60 0000 C CNN + 3 3150 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF10DF1 +P 3150 3950 +F 0 "U1" H 3200 4050 30 0000 C CNN +F 1 "PORT" H 3150 3950 30 0000 C CNN +F 2 "" H 3150 3950 60 0000 C CNN +F 3 "" H 3150 3950 60 0000 C CNN + 4 3150 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF10DF7 +P 3150 4300 +F 0 "U1" H 3200 4400 30 0000 C CNN +F 1 "PORT" H 3150 4300 30 0000 C CNN +F 2 "" H 3150 4300 60 0000 C CNN +F 3 "" H 3150 4300 60 0000 C CNN + 5 3150 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF10DFD +P 6250 4050 +F 0 "U1" H 6300 4150 30 0000 C CNN +F 1 "PORT" H 6250 4050 30 0000 C CNN +F 2 "" H 6250 4050 60 0000 C CNN +F 3 "" H 6250 4050 60 0000 C CNN + 6 6250 4050 + -1 0 0 1 +$EndComp +Wire Wire Line + 6000 4050 5100 4050 +Wire Wire Line + 4250 3950 4250 3650 +Wire Wire Line + 4250 3650 3400 3650 +Wire Wire Line + 3400 3950 3900 3950 +Wire Wire Line + 3900 3950 3900 4050 +Wire Wire Line + 3900 4050 4250 4050 +Wire Wire Line + 4250 4150 4250 4300 +Wire Wire Line + 4250 4300 3400 4300 +$Comp +L 3_and X2 +U 1 1 5CF10E9C +P 4550 5450 +F 0 "X2" H 4650 5400 60 0000 C CNN +F 1 "3_and" H 4700 5600 60 0000 C CNN +F 2 "" H 4550 5450 60 0000 C CNN +F 3 "" H 4550 5450 60 0000 C CNN + 1 4550 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF10EA2 +P 3100 5000 +F 0 "U1" H 3150 5100 30 0000 C CNN +F 1 "PORT" H 3100 5000 30 0000 C CNN +F 2 "" H 3100 5000 60 0000 C CNN +F 3 "" H 3100 5000 60 0000 C CNN + 11 3100 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF10EA8 +P 3100 5300 +F 0 "U1" H 3150 5400 30 0000 C CNN +F 1 "PORT" H 3100 5300 30 0000 C CNN +F 2 "" H 3100 5300 60 0000 C CNN +F 3 "" H 3100 5300 60 0000 C CNN + 12 3100 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF10EAE +P 3100 5650 +F 0 "U1" H 3150 5750 30 0000 C CNN +F 1 "PORT" H 3100 5650 30 0000 C CNN +F 2 "" H 3100 5650 60 0000 C CNN +F 3 "" H 3100 5650 60 0000 C CNN + 13 3100 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF10EB4 +P 6200 5400 +F 0 "U1" H 6250 5500 30 0000 C CNN +F 1 "PORT" H 6200 5400 30 0000 C CNN +F 2 "" H 6200 5400 60 0000 C CNN +F 3 "" H 6200 5400 60 0000 C CNN + 10 6200 5400 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 5400 5050 5400 +Wire Wire Line + 4200 5300 4200 5000 +Wire Wire Line + 4200 5000 3350 5000 +Wire Wire Line + 3350 5300 3850 5300 +Wire Wire Line + 3850 5300 3850 5400 +Wire Wire Line + 3850 5400 4200 5400 +Wire Wire Line + 4200 5500 4200 5650 +Wire Wire Line + 4200 5650 3350 5650 +$Comp +L PORT U1 +U 7 1 5CF11A2A +P 7500 4100 +F 0 "U1" H 7550 4200 30 0000 C CNN +F 1 "PORT" H 7500 4100 30 0000 C CNN +F 2 "" H 7500 4100 60 0000 C CNN +F 3 "" H 7500 4100 60 0000 C CNN + 7 7500 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF11A8A +P 7550 4600 +F 0 "U1" H 7600 4700 30 0000 C CNN +F 1 "PORT" H 7550 4600 30 0000 C CNN +F 2 "" H 7550 4600 60 0000 C CNN +F 3 "" H 7550 4600 60 0000 C CNN + 14 7550 4600 + -1 0 0 1 +$EndComp +NoConn ~ 7250 4100 +NoConn ~ 7300 4600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4073/4073.sub b/library/SubcircuitLibrary/4073/4073.sub new file mode 100644 index 00000000..15208169 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073.sub @@ -0,0 +1,10 @@ +* Subcircuit 4073 +.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +* Control Statements + +.ends 4073
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4073/4073_Previous_Values.xml b/library/SubcircuitLibrary/4073/4073_Previous_Values.xml new file mode 100644 index 00000000..5acac768 --- /dev/null +++ b/library/SubcircuitLibrary/4073/4073_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4073/analysis b/library/SubcircuitLibrary/4073/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4073/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_OR/4_OR-cache.lib b/library/SubcircuitLibrary/4_OR/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4_OR/4_OR.cir b/library/SubcircuitLibrary/4_OR/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/4_OR/4_OR.cir.out b/library/SubcircuitLibrary/4_OR/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4_OR/4_OR.pro b/library/SubcircuitLibrary/4_OR/4_OR.pro new file mode 100644 index 00000000..9daf26bc --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR.pro @@ -0,0 +1,45 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/library/SubcircuitLibrary/4_OR/4_OR.sch b/library/SubcircuitLibrary/4_OR/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4_OR/4_OR.sub b/library/SubcircuitLibrary/4_OR/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_OR/analysis b/library/SubcircuitLibrary/4_OR/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4_OR/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_and/3_and-cache.lib b/library/SubcircuitLibrary/4_and/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4_and/3_and.cir b/library/SubcircuitLibrary/4_and/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/4_and/3_and.cir.out b/library/SubcircuitLibrary/4_and/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4_and/3_and.pro b/library/SubcircuitLibrary/4_and/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/4_and/3_and.sch b/library/SubcircuitLibrary/4_and/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4_and/3_and.sub b/library/SubcircuitLibrary/4_and/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_and/3_and_Previous_Values.xml b/library/SubcircuitLibrary/4_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/4_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_and/4_and-cache.lib b/library/SubcircuitLibrary/4_and/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4_and/4_and-rescue.lib b/library/SubcircuitLibrary/4_and/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4_and/4_and.cir b/library/SubcircuitLibrary/4_and/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/4_and/4_and.cir.out b/library/SubcircuitLibrary/4_and/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4_and/4_and.pro b/library/SubcircuitLibrary/4_and/4_and.pro new file mode 100644 index 00000000..9c0be79e --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and.pro @@ -0,0 +1,58 @@ +update=06/01/19 15:08:42 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/library/SubcircuitLibrary/4_and/4_and.sch b/library/SubcircuitLibrary/4_and/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4_and/4_and.sub b/library/SubcircuitLibrary/4_and/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_and/4_and_Previous_Values.xml b/library/SubcircuitLibrary/4_and/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4_and/analysis b/library/SubcircuitLibrary/4_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/3_and-cache.lib b/library/SubcircuitLibrary/4to16_demux/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4to16_demux/3_and.cir b/library/SubcircuitLibrary/4to16_demux/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/4to16_demux/3_and.cir.out b/library/SubcircuitLibrary/4to16_demux/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4to16_demux/3_and.pro b/library/SubcircuitLibrary/4to16_demux/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/4to16_demux/3_and.sch b/library/SubcircuitLibrary/4to16_demux/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4to16_demux/3_and.sub b/library/SubcircuitLibrary/4to16_demux/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml b/library/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib b/library/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib new file mode 100644 index 00000000..898ea926 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_nand +# +DEF 5_nand X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_nand" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir b/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir new file mode 100644 index 00000000..c97c2f8b --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir @@ -0,0 +1,32 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 17:01:07 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad23_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad22_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad21_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad20_ Net-_U6-Pad2_ d_inverter +U2 Net-_U1-Pad19_ Net-_U1-Pad18_ Net-_U2-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ ? Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ ? PORT +X1 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad1_ 5_nand +X2 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad2_ 5_nand +X3 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad3_ 5_nand +X4 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad4_ 5_nand +X5 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad5_ 5_nand +X6 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad6_ 5_nand +X7 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad7_ 5_nand +X8 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad8_ 5_nand +X9 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad9_ 5_nand +X10 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad10_ 5_nand +X11 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad11_ 5_nand +X12 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad13_ 5_nand +X13 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad14_ 5_nand +X14 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad15_ 5_nand +X15 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad16_ 5_nand +X16 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad17_ 5_nand + +.end diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out b/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out new file mode 100644 index 00000000..eecdfb06 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out @@ -0,0 +1,49 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir + +.include 5_nand.sub +* u3 net-_u1-pad23_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad22_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad21_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad20_ net-_u6-pad2_ d_inverter +* u2 net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? port +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand +x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand +x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand +x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand +x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand +x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand +x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand +x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand +x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand +x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand +x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand +x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand +x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand +x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand +x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand +x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand +a1 net-_u1-pad23_ net-_u3-pad2_ u3 +a2 net-_u1-pad22_ net-_u4-pad2_ u4 +a3 net-_u1-pad21_ net-_u5-pad2_ u5 +a4 net-_u1-pad20_ net-_u6-pad2_ u6 +a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux.pro b/library/SubcircuitLibrary/4to16_demux/4to16_demux.pro new file mode 100644 index 00000000..5a167cd9 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux.pro @@ -0,0 +1,43 @@ +update=Fri Jun 21 16:58:10 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_User +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux.sch b/library/SubcircuitLibrary/4to16_demux/4to16_demux.sch new file mode 100644 index 00000000..c9142e27 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux.sch @@ -0,0 +1,889 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4to16_demux-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 5CF2315F +P 4700 1900 +F 0 "U3" H 4700 1800 60 0000 C CNN +F 1 "d_inverter" H 4700 2050 60 0000 C CNN +F 2 "" H 4750 1850 60 0000 C CNN +F 3 "" H 4750 1850 60 0000 C CNN + 1 4700 1900 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF231D7 +P 5600 1850 +F 0 "U4" H 5600 1750 60 0000 C CNN +F 1 "d_inverter" H 5600 2000 60 0000 C CNN +F 2 "" H 5650 1800 60 0000 C CNN +F 3 "" H 5650 1800 60 0000 C CNN + 1 5600 1850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5CF23245 +P 6550 1850 +F 0 "U5" H 6550 1750 60 0000 C CNN +F 1 "d_inverter" H 6550 2000 60 0000 C CNN +F 2 "" H 6600 1800 60 0000 C CNN +F 3 "" H 6600 1800 60 0000 C CNN + 1 6550 1850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5CF232B2 +P 7500 1800 +F 0 "U6" H 7500 1700 60 0000 C CNN +F 1 "d_inverter" H 7500 1950 60 0000 C CNN +F 2 "" H 7550 1750 60 0000 C CNN +F 3 "" H 7550 1750 60 0000 C CNN + 1 7500 1800 + 0 1 1 0 +$EndComp +Text Notes 1300 5450 0 60 ~ 0 +~Y0 +Text Notes 1950 5450 0 60 ~ 0 +~Y1\n +Text Notes 2500 5450 0 60 ~ 0 +~Y2\n +Text Notes 3050 5450 0 60 ~ 0 +~Y3\n +Text Notes 3600 5450 0 60 ~ 0 +~Y4\n +Text Notes 4150 5500 0 60 ~ 0 +~Y5\n +Text Notes 4700 5500 0 60 ~ 0 +~Y6\n +Text Notes 5250 5500 0 60 ~ 0 +~Y7\n +Text Notes 5800 5500 0 60 ~ 0 +~Y8\n +Text Notes 6400 5500 0 60 ~ 0 +~Y9\n +Text Notes 6950 5500 0 60 ~ 0 +~Y10\n +Text Notes 7500 5500 0 60 ~ 0 +~Y11\n +Text Notes 8050 5500 0 60 ~ 0 +~Y12\n +Text Notes 8600 5500 0 60 ~ 0 +~Y13\n +Text Notes 9150 5500 0 60 ~ 0 +~Y14\n +Text Notes 9700 5500 0 60 ~ 0 +~Y15\n +Wire Wire Line + 4700 1250 4700 1600 +Wire Wire Line + 5600 1150 5600 1550 +Wire Wire Line + 6550 1100 6550 1550 +Wire Wire Line + 7500 1050 7500 1500 +Wire Wire Line + 1400 4400 1400 2950 +Wire Wire Line + 1400 2950 9700 2950 +Wire Wire Line + 1950 2950 1950 4400 +Wire Wire Line + 2500 2950 2500 4400 +Connection ~ 1950 2950 +Wire Wire Line + 3050 2950 3050 4400 +Connection ~ 2500 2950 +Wire Wire Line + 3600 2950 3600 4400 +Connection ~ 3050 2950 +Wire Wire Line + 4150 2950 4150 4400 +Connection ~ 3600 2950 +Wire Wire Line + 4700 2950 4700 4400 +Connection ~ 4150 2950 +Wire Wire Line + 5250 2950 5250 4400 +Connection ~ 4700 2950 +Wire Wire Line + 5800 2950 5800 4400 +Connection ~ 5250 2950 +Wire Wire Line + 6400 2950 6400 4400 +Connection ~ 5800 2950 +Wire Wire Line + 6950 2950 6950 4400 +Connection ~ 6400 2950 +Wire Wire Line + 7500 2950 7500 4400 +Connection ~ 6950 2950 +Wire Wire Line + 8050 2950 8050 4400 +Connection ~ 7500 2950 +Wire Wire Line + 8600 2950 8600 4400 +Connection ~ 8050 2950 +Wire Wire Line + 9150 2950 9150 4400 +Connection ~ 8600 2950 +Wire Wire Line + 9700 2950 9700 4400 +Connection ~ 9150 2950 +Wire Wire Line + 7500 2100 7500 2800 +Wire Wire Line + 7500 2800 7400 2800 +Wire Wire Line + 7400 2800 7400 3050 +Wire Wire Line + 7400 3050 1500 3050 +Wire Wire Line + 1500 3050 1500 4400 +Wire Wire Line + 2050 4400 2050 3050 +Connection ~ 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"" H 5450 6200 60 0000 C CNN + 8 5450 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF2E651 +P 6000 6200 +F 0 "U1" H 6050 6300 30 0000 C CNN +F 1 "PORT" H 6000 6200 30 0000 C CNN +F 2 "" H 6000 6200 60 0000 C CNN +F 3 "" H 6000 6200 60 0000 C CNN + 9 6000 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF2E6E3 +P 6600 6150 +F 0 "U1" H 6650 6250 30 0000 C CNN +F 1 "PORT" H 6600 6150 30 0000 C CNN +F 2 "" H 6600 6150 60 0000 C CNN +F 3 "" H 6600 6150 60 0000 C CNN + 10 6600 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF2E770 +P 7150 6150 +F 0 "U1" H 7200 6250 30 0000 C CNN +F 1 "PORT" H 7150 6150 30 0000 C CNN +F 2 "" H 7150 6150 60 0000 C CNN +F 3 "" H 7150 6150 60 0000 C CNN + 11 7150 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF2E7F8 +P 7700 6150 +F 0 "U1" H 7750 6250 30 0000 C CNN +F 1 "PORT" H 7700 6150 30 0000 C CNN +F 2 "" H 7700 6150 60 0000 C CNN +F 3 "" H 7700 6150 60 0000 C CNN + 13 7700 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 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+Wire Wire Line + 8250 5400 8250 5900 +Wire Wire Line + 7700 5400 7700 5900 +Wire Wire Line + 7150 5400 7150 5900 +Wire Wire Line + 6600 5400 6600 5900 +Wire Wire Line + 6000 5400 6000 5950 +Wire Wire Line + 5450 5400 5450 5950 +Wire Wire Line + 4900 5400 4900 5950 +Wire Wire Line + 4350 5400 4350 5950 +Wire Wire Line + 3800 5400 3800 5950 +Wire Wire Line + 3250 5400 3250 5950 +Wire Wire Line + 2700 5400 2700 5950 +Wire Wire Line + 2150 5400 2150 5950 +Wire Wire Line + 1600 5400 1600 5950 +$Comp +L PORT U1 +U 24 1 5CF327C1 +P 6500 6950 +F 0 "U1" H 6550 7050 30 0000 C CNN +F 1 "PORT" H 6500 6950 30 0000 C CNN +F 2 "" H 6500 6950 60 0000 C CNN +F 3 "" H 6500 6950 60 0000 C CNN + 24 6500 6950 + 0 -1 -1 0 +$EndComp +NoConn ~ 6500 6700 +$Comp +L PORT U1 +U 12 1 5CF33A86 +P 3400 900 +F 0 "U1" H 3450 1000 30 0000 C CNN +F 1 "PORT" H 3400 900 30 0000 C CNN +F 2 "" H 3400 900 60 0000 C CNN +F 3 "" H 3400 900 60 0000 C CNN + 12 3400 900 + 0 1 1 0 +$EndComp +NoConn ~ 3400 1150 +$Comp +L 5_nand X1 +U 1 1 5D0CC4BF +P 1600 4850 +F 0 "X1" H 1650 4750 60 0000 C CNN +F 1 "5_nand" H 1700 5000 60 0000 C CNN +F 2 "" H 1600 4850 60 0000 C CNN +F 3 "" H 1600 4850 60 0000 C CNN + 1 1600 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X2 +U 1 1 5D0CC967 +P 2150 4850 +F 0 "X2" H 2200 4750 60 0000 C CNN +F 1 "5_nand" H 2250 5000 60 0000 C CNN +F 2 "" H 2150 4850 60 0000 C CNN +F 3 "" H 2150 4850 60 0000 C CNN + 1 2150 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X3 +U 1 1 5D0CC9F8 +P 2700 4850 +F 0 "X3" H 2750 4750 60 0000 C CNN +F 1 "5_nand" H 2800 5000 60 0000 C CNN +F 2 "" H 2700 4850 60 0000 C CNN +F 3 "" H 2700 4850 60 0000 C CNN + 1 2700 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X4 +U 1 1 5D0CCA7E +P 3250 4850 +F 0 "X4" H 3300 4750 60 0000 C CNN +F 1 "5_nand" H 3350 5000 60 0000 C CNN +F 2 "" H 3250 4850 60 0000 C CNN +F 3 "" H 3250 4850 60 0000 C CNN + 1 3250 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X5 +U 1 1 5D0CCB6A +P 3800 4850 +F 0 "X5" H 3850 4750 60 0000 C CNN +F 1 "5_nand" H 3900 5000 60 0000 C CNN +F 2 "" H 3800 4850 60 0000 C CNN +F 3 "" H 3800 4850 60 0000 C CNN + 1 3800 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X6 +U 1 1 5D0CCBF6 +P 4350 4850 +F 0 "X6" H 4400 4750 60 0000 C CNN +F 1 "5_nand" H 4450 5000 60 0000 C CNN +F 2 "" H 4350 4850 60 0000 C CNN +F 3 "" H 4350 4850 60 0000 C CNN + 1 4350 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X7 +U 1 1 5D0CCC81 +P 4900 4850 +F 0 "X7" H 4950 4750 60 0000 C CNN +F 1 "5_nand" H 5000 5000 60 0000 C CNN +F 2 "" H 4900 4850 60 0000 C CNN +F 3 "" H 4900 4850 60 0000 C CNN + 1 4900 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X8 +U 1 1 5D0CCD0B +P 5450 4850 +F 0 "X8" H 5500 4750 60 0000 C CNN +F 1 "5_nand" H 5550 5000 60 0000 C CNN +F 2 "" H 5450 4850 60 0000 C CNN +F 3 "" H 5450 4850 60 0000 C CNN + 1 5450 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X9 +U 1 1 5D0CCE34 +P 6000 4850 +F 0 "X9" H 6050 4750 60 0000 C CNN +F 1 "5_nand" H 6100 5000 60 0000 C CNN +F 2 "" H 6000 4850 60 0000 C CNN +F 3 "" H 6000 4850 60 0000 C CNN + 1 6000 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X10 +U 1 1 5D0CCECA +P 6600 4850 +F 0 "X10" H 6650 4750 60 0000 C CNN +F 1 "5_nand" H 6700 5000 60 0000 C CNN +F 2 "" H 6600 4850 60 0000 C CNN +F 3 "" H 6600 4850 60 0000 C CNN + 1 6600 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X11 +U 1 1 5D0CCF63 +P 7150 4850 +F 0 "X11" H 7200 4750 60 0000 C CNN +F 1 "5_nand" H 7250 5000 60 0000 C CNN +F 2 "" H 7150 4850 60 0000 C CNN +F 3 "" H 7150 4850 60 0000 C CNN + 1 7150 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X12 +U 1 1 5D0CD07D +P 7700 4850 +F 0 "X12" H 7750 4750 60 0000 C CNN +F 1 "5_nand" H 7800 5000 60 0000 C CNN +F 2 "" H 7700 4850 60 0000 C CNN +F 3 "" H 7700 4850 60 0000 C CNN + 1 7700 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X13 +U 1 1 5D0CD124 +P 8250 4850 +F 0 "X13" H 8300 4750 60 0000 C CNN +F 1 "5_nand" H 8350 5000 60 0000 C CNN +F 2 "" H 8250 4850 60 0000 C CNN +F 3 "" H 8250 4850 60 0000 C CNN + 1 8250 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X14 +U 1 1 5D0CD1C6 +P 8800 4850 +F 0 "X14" H 8850 4750 60 0000 C CNN +F 1 "5_nand" H 8900 5000 60 0000 C CNN +F 2 "" H 8800 4850 60 0000 C CNN +F 3 "" H 8800 4850 60 0000 C CNN + 1 8800 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X15 +U 1 1 5D0CD348 +P 9350 4850 +F 0 "X15" H 9400 4750 60 0000 C CNN +F 1 "5_nand" H 9450 5000 60 0000 C CNN +F 2 "" H 9350 4850 60 0000 C CNN +F 3 "" H 9350 4850 60 0000 C CNN + 1 9350 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X16 +U 1 1 5D0CD3EE +P 9900 4850 +F 0 "X16" H 9950 4750 60 0000 C CNN +F 1 "5_nand" H 10000 5000 60 0000 C CNN +F 2 "" H 9900 4850 60 0000 C CNN +F 3 "" H 9900 4850 60 0000 C CNN + 1 9900 4850 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux.sub b/library/SubcircuitLibrary/4to16_demux/4to16_demux.sub new file mode 100644 index 00000000..4f7595da --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux.sub @@ -0,0 +1,43 @@ +* Subcircuit 4to16_demux +.subckt 4to16_demux net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir +.include 5_nand.sub +* u3 net-_u1-pad23_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad22_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad21_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad20_ net-_u6-pad2_ d_inverter +* u2 net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand +x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand +x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand +x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand +x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand +x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand +x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand +x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand +x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand +x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand +x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand +x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand +x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand +x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand +x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand +x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand +a1 net-_u1-pad23_ net-_u3-pad2_ u3 +a2 net-_u1-pad22_ net-_u4-pad2_ u4 +a3 net-_u1-pad21_ net-_u5-pad2_ u5 +a4 net-_u1-pad20_ net-_u6-pad2_ u6 +a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4to16_demux
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml b/library/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml new file mode 100644 index 00000000..93c6f25a --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x13><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x13><x14><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x14><x15><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x15><x10><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x10><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x9><x16><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x16><x11><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x11><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x3><x12><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x12><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/5_and-cache.lib b/library/SubcircuitLibrary/4to16_demux/5_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4to16_demux/5_and.cir b/library/SubcircuitLibrary/4to16_demux/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/4to16_demux/5_and.cir.out b/library/SubcircuitLibrary/4to16_demux/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4to16_demux/5_and.pro b/library/SubcircuitLibrary/4to16_demux/5_and.pro new file mode 100644 index 00000000..7a2f090e --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/library/SubcircuitLibrary/4to16_demux/5_and.sch b/library/SubcircuitLibrary/4to16_demux/5_and.sch new file mode 100644 index 00000000..e9eb58ee --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4to16_demux/5_and.sub b/library/SubcircuitLibrary/4to16_demux/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml b/library/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand-cache.lib b/library/SubcircuitLibrary/4to16_demux/5_nand-cache.lib new file mode 100644 index 00000000..cb517be1 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand-cache.lib @@ -0,0 +1,78 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.cir b/library/SubcircuitLibrary/4to16_demux/5_nand.cir new file mode 100644 index 00000000..e833d0f4 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand.cir @@ -0,0 +1,13 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and +U2 Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.cir.out b/library/SubcircuitLibrary/4to16_demux/5_nand.cir.out new file mode 100644 index 00000000..164de911 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand.cir.out @@ -0,0 +1,18 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir + +.include 5_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and +* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 net-_u2-pad1_ net-_u1-pad6_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.pro b/library/SubcircuitLibrary/4to16_demux/5_nand.pro new file mode 100644 index 00000000..b7d23f44 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand.pro @@ -0,0 +1,83 @@ +update=Fri Jun 21 16:46:10 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName41=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName42=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName43=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName44=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName45=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName46=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName47=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName48=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User + diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.sch b/library/SubcircuitLibrary/4to16_demux/5_nand.sch new file mode 100644 index 00000000..86379b08 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand.sch @@ -0,0 +1,175 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5D0CBD44 +P 4150 3700 +F 0 "X1" H 4200 3600 60 0000 C CNN +F 1 "5_and" H 4250 3850 60 0000 C CNN +F 2 "" H 4150 3700 60 0000 C CNN +F 3 "" H 4150 3700 60 0000 C CNN + 1 4150 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5D0CBD97 +P 5150 3700 +F 0 "U2" H 5150 3600 60 0000 C CNN +F 1 "d_inverter" H 5150 3850 60 0000 C CNN +F 2 "" H 5200 3650 60 0000 C CNN +F 3 "" H 5200 3650 60 0000 C CNN + 1 5150 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5D0CBDBE +P 2900 2900 +F 0 "U1" H 2950 3000 30 0000 C CNN +F 1 "PORT" H 2900 2900 30 0000 C CNN +F 2 "" H 2900 2900 60 0000 C CNN +F 3 "" H 2900 2900 60 0000 C CNN + 1 2900 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D0CBDF4 +P 2900 3150 +F 0 "U1" H 2950 3250 30 0000 C CNN +F 1 "PORT" H 2900 3150 30 0000 C CNN +F 2 "" H 2900 3150 60 0000 C CNN +F 3 "" H 2900 3150 60 0000 C CNN + 2 2900 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5D0CBE16 +P 2900 3400 +F 0 "U1" H 2950 3500 30 0000 C CNN +F 1 "PORT" H 2900 3400 30 0000 C CNN +F 2 "" H 2900 3400 60 0000 C CNN +F 3 "" H 2900 3400 60 0000 C CNN + 3 2900 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5D0CBE3F +P 2900 3750 +F 0 "U1" H 2950 3850 30 0000 C CNN +F 1 "PORT" H 2900 3750 30 0000 C CNN +F 2 "" H 2900 3750 60 0000 C CNN +F 3 "" H 2900 3750 60 0000 C CNN + 4 2900 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5D0CBE6B +P 2900 4150 +F 0 "U1" H 2950 4250 30 0000 C CNN +F 1 "PORT" H 2900 4150 30 0000 C CNN +F 2 "" H 2900 4150 60 0000 C CNN +F 3 "" H 2900 4150 60 0000 C CNN + 5 2900 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5D0CBE9C +P 6200 3700 +F 0 "U1" H 6250 3800 30 0000 C CNN +F 1 "PORT" H 6200 3700 30 0000 C CNN +F 2 "" H 6200 3700 60 0000 C CNN +F 3 "" H 6200 3700 60 0000 C CNN + 6 6200 3700 + -1 0 0 1 +$EndComp +Wire Wire Line + 3150 2900 3700 2900 +Wire Wire Line + 3700 2900 3700 3500 +Wire Wire Line + 3700 3600 3500 3600 +Wire Wire Line + 3500 3600 3500 3150 +Wire Wire Line + 3500 3150 3150 3150 +Wire Wire Line + 3150 3400 3350 3400 +Wire Wire Line + 3350 3400 3350 3700 +Wire Wire Line + 3350 3700 3700 3700 +Wire Wire Line + 3700 3800 3250 3800 +Wire Wire Line + 3250 3800 3250 3750 +Wire Wire Line + 3250 3750 3150 3750 +Wire Wire Line + 3150 4150 3350 4150 +Wire Wire Line + 3350 4150 3350 3900 +Wire Wire Line + 3350 3900 3700 3900 +Wire Wire Line + 4700 3700 4850 3700 +Wire Wire Line + 5450 3700 5950 3700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.sub b/library/SubcircuitLibrary/4to16_demux/5_nand.sub new file mode 100644 index 00000000..c3e041fa --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand.sub @@ -0,0 +1,12 @@ +* Subcircuit 5_nand +.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir +.include 5_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and +* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter +a1 net-_u2-pad1_ net-_u1-pad6_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_nand
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml b/library/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml new file mode 100644 index 00000000..c4b4cde2 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/4to16_demux/analysis b/library/SubcircuitLibrary/4to16_demux/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/4to16_demux/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/556/556-cache.lib b/library/SubcircuitLibrary/556/556-cache.lib new file mode 100644 index 00000000..75d610da --- /dev/null +++ b/library/SubcircuitLibrary/556/556-cache.lib @@ -0,0 +1,64 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/556/556.cir b/library/SubcircuitLibrary/556/556.cir new file mode 100644 index 00000000..48baa73e --- /dev/null +++ b/library/SubcircuitLibrary/556/556.cir @@ -0,0 +1,13 @@ +* C:\esim\eSim\src\SubcircuitLibrary\556\556.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/18/19 18:30:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad14_ LM555N +X2 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ LM555N +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/556/556.cir.out b/library/SubcircuitLibrary/556/556.cir.out new file mode 100644 index 00000000..c74aab7c --- /dev/null +++ b/library/SubcircuitLibrary/556/556.cir.out @@ -0,0 +1,15 @@ +* c:\esim\esim\src\subcircuitlibrary\556\556.cir + +.include lm555n.sub +x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n +x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/556/556.pro b/library/SubcircuitLibrary/556/556.pro new file mode 100644 index 00000000..a165313d --- /dev/null +++ b/library/SubcircuitLibrary/556/556.pro @@ -0,0 +1,72 @@ +update=03/18/19 18:13:51 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=regul +LibName6=74xx +LibName7=cmos4000 +LibName8=adc-dac +LibName9=memory +LibName10=xilinx +LibName11=microcontrollers +LibName12=dsp +LibName13=microchip +LibName14=analog_switches +LibName15=motorola +LibName16=texas +LibName17=intel +LibName18=audio +LibName19=interface +LibName20=digital-audio +LibName21=philips +LibName22=display +LibName23=cypress +LibName24=siliconi +LibName25=opto +LibName26=atmel +LibName27=contrib +LibName28=valves +LibName29=eSim_User +LibName30=eSim_Subckt +LibName31=eSim_Sources +LibName32=eSim_PSpice +LibName33=eSim_Power +LibName34=eSim_Plot +LibName35=eSim_Miscellaneous +LibName36=eSim_Hybrid +LibName37=eSim_Digital +LibName38=eSim_Devices +LibName39=eSim_Analog diff --git a/library/SubcircuitLibrary/556/556.sch b/library/SubcircuitLibrary/556/556.sch new file mode 100644 index 00000000..af4e1bc9 --- /dev/null +++ b/library/SubcircuitLibrary/556/556.sch @@ -0,0 +1,275 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L LM555N X1 +U 1 1 5C8F9298 +P 4150 3850 +F 0 "X1" H 4150 3800 60 0000 C CNN +F 1 "LM555N" H 4150 3950 60 0000 C CNN +F 2 "" H 4100 3850 60 0000 C CNN +F 3 "" H 4100 3850 60 0000 C CNN + 1 4150 3850 + 1 0 0 -1 +$EndComp +$Comp +L LM555N X2 +U 1 1 5C8F92E5 +P 7100 3850 +F 0 "X2" H 7100 3800 60 0000 C CNN +F 1 "LM555N" H 7100 3950 60 0000 C CNN +F 2 "" H 7050 3850 60 0000 C CNN +F 3 "" H 7050 3850 60 0000 C CNN + 1 7100 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4150 3250 4150 3000 +Wire Wire Line + 4150 3000 7100 3000 +Wire Wire Line + 4150 4450 4150 4650 +Wire Wire Line + 4150 4650 7100 4650 +$Comp +L PORT U1 +U 14 1 5C8F93E6 +P 4650 2600 +F 0 "U1" H 4700 2700 30 0000 C CNN +F 1 "PORT" H 4650 2600 30 0000 C CNN +F 2 "" H 4650 2600 60 0000 C CNN +F 3 "" H 4650 2600 60 0000 C CNN + 14 4650 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4900 2600 5000 2600 +Wire Wire Line + 5000 2600 5000 3000 +Connection ~ 5000 3000 +$Comp +L PORT U1 +U 6 1 5C8F94B6 +P 3050 3600 +F 0 "U1" H 3100 3700 30 0000 C CNN +F 1 "PORT" H 3050 3600 30 0000 C CNN +F 2 "" H 3050 3600 60 0000 C CNN +F 3 "" H 3050 3600 60 0000 C CNN + 6 3050 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C8F95C0 +P 3050 3850 +F 0 "U1" H 3100 3950 30 0000 C CNN +F 1 "PORT" H 3050 3850 30 0000 C CNN +F 2 "" H 3050 3850 60 0000 C CNN +F 3 "" H 3050 3850 60 0000 C CNN + 3 3050 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C8F95E7 +P 3050 4100 +F 0 "U1" H 3100 4200 30 0000 C CNN +F 1 "PORT" H 3050 4100 30 0000 C CNN +F 2 "" H 3050 4100 60 0000 C CNN +F 3 "" H 3050 4100 60 0000 C CNN + 4 3050 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7100 3000 7100 3250 +Wire Wire Line + 7100 4650 7100 4450 +$Comp +L PORT U1 +U 8 1 5C8F9C35 +P 6000 3600 +F 0 "U1" H 6050 3700 30 0000 C CNN +F 1 "PORT" H 6000 3600 30 0000 C CNN +F 2 "" H 6000 3600 60 0000 C CNN +F 3 "" H 6000 3600 60 0000 C CNN + 8 6000 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C8F9C3B +P 6000 3850 +F 0 "U1" H 6050 3950 30 0000 C CNN +F 1 "PORT" H 6000 3850 30 0000 C CNN +F 2 "" H 6000 3850 60 0000 C CNN +F 3 "" H 6000 3850 60 0000 C CNN + 11 6000 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C8F9C41 +P 6000 4100 +F 0 "U1" H 6050 4200 30 0000 C CNN +F 1 "PORT" H 6000 4100 30 0000 C CNN +F 2 "" H 6000 4100 60 0000 C CNN +F 3 "" H 6000 4100 60 0000 C CNN + 10 6000 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C8F9D22 +P 5200 4100 +F 0 "U1" H 5250 4200 30 0000 C CNN +F 1 "PORT" H 5200 4100 30 0000 C CNN +F 2 "" H 5200 4100 60 0000 C CNN +F 3 "" H 5200 4100 60 0000 C CNN + 2 5200 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C8F9D28 +P 5200 3850 +F 0 "U1" H 5250 3950 30 0000 C CNN +F 1 "PORT" H 5200 3850 30 0000 C CNN +F 2 "" H 5200 3850 60 0000 C CNN +F 3 "" H 5200 3850 60 0000 C CNN + 1 5200 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C8F9D2E +P 5200 3600 +F 0 "U1" H 5250 3700 30 0000 C CNN +F 1 "PORT" H 5200 3600 30 0000 C CNN +F 2 "" H 5200 3600 60 0000 C CNN +F 3 "" H 5200 3600 60 0000 C CNN + 5 5200 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C8FA0FA +P 8250 4100 +F 0 "U1" H 8300 4200 30 0000 C CNN +F 1 "PORT" H 8250 4100 30 0000 C CNN +F 2 "" H 8250 4100 60 0000 C CNN +F 3 "" H 8250 4100 60 0000 C CNN + 12 8250 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C8FA100 +P 8250 3850 +F 0 "U1" H 8300 3950 30 0000 C CNN +F 1 "PORT" H 8250 3850 30 0000 C CNN +F 2 "" H 8250 3850 60 0000 C CNN +F 3 "" H 8250 3850 60 0000 C CNN + 13 8250 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C8FA106 +P 8250 3600 +F 0 "U1" H 8300 3700 30 0000 C CNN +F 1 "PORT" H 8250 3600 30 0000 C CNN +F 2 "" H 8250 3600 60 0000 C CNN +F 3 "" H 8250 3600 60 0000 C CNN + 9 8250 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C8FA319 +P 4950 5050 +F 0 "U1" H 5000 5150 30 0000 C CNN +F 1 "PORT" H 4950 5050 30 0000 C CNN +F 2 "" H 4950 5050 60 0000 C CNN +F 3 "" H 4950 5050 60 0000 C CNN + 7 4950 5050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 5050 5200 4650 +Connection ~ 5200 4650 +Wire Wire Line + 3300 3600 3600 3600 +Wire Wire Line + 3300 3850 3600 3850 +Wire Wire Line + 3300 4100 3600 4100 +Wire Wire Line + 4700 3600 4950 3600 +Wire Wire Line + 4700 3850 4950 3850 +Wire Wire Line + 4700 4100 4950 4100 +Wire Wire Line + 6250 3600 6550 3600 +Wire Wire Line + 6250 3850 6550 3850 +Wire Wire Line + 6250 4100 6550 4100 +Wire Wire Line + 8000 3600 7650 3600 +Wire Wire Line + 8000 3850 7650 3850 +Wire Wire Line + 8000 4100 7650 4100 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/556/556.sub b/library/SubcircuitLibrary/556/556.sub new file mode 100644 index 00000000..a370b703 --- /dev/null +++ b/library/SubcircuitLibrary/556/556.sub @@ -0,0 +1,9 @@ +* Subcircuit 556 +.subckt 556 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\esim\esim\src\subcircuitlibrary\556\556.cir +.include lm555n.sub +x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n +x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n +* Control Statements + +.ends 556
\ No newline at end of file diff --git a/library/SubcircuitLibrary/556/556_Previous_Values.xml b/library/SubcircuitLibrary/556/556_Previous_Values.xml new file mode 100644 index 00000000..c025c2d1 --- /dev/null +++ b/library/SubcircuitLibrary/556/556_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/5_and/3_and-cache.lib b/library/SubcircuitLibrary/5_and/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/5_and/3_and.cir b/library/SubcircuitLibrary/5_and/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/5_and/3_and.cir.out b/library/SubcircuitLibrary/5_and/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/5_and/3_and.pro b/library/SubcircuitLibrary/5_and/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/5_and/3_and.sch b/library/SubcircuitLibrary/5_and/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/5_and/3_and.sub b/library/SubcircuitLibrary/5_and/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/5_and/3_and_Previous_Values.xml b/library/SubcircuitLibrary/5_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/5_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/5_and/5_and-cache.lib b/library/SubcircuitLibrary/5_and/5_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/5_and/5_and.cir b/library/SubcircuitLibrary/5_and/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/5_and/5_and.cir.out b/library/SubcircuitLibrary/5_and/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/5_and/5_and.pro b/library/SubcircuitLibrary/5_and/5_and.pro new file mode 100644 index 00000000..7a2f090e --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/library/SubcircuitLibrary/5_and/5_and.sch b/library/SubcircuitLibrary/5_and/5_and.sch new file mode 100644 index 00000000..e9eb58ee --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/5_and/5_and.sub b/library/SubcircuitLibrary/5_and/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/5_and/5_and_Previous_Values.xml b/library/SubcircuitLibrary/5_and/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/5_and/analysis b/library/SubcircuitLibrary/5_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/5_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/3_and-cache.lib b/library/SubcircuitLibrary/74153/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/3_and.cir b/library/SubcircuitLibrary/74153/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74153/3_and.cir.out b/library/SubcircuitLibrary/74153/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/3_and.pro b/library/SubcircuitLibrary/74153/3_and.pro new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/library/SubcircuitLibrary/74153/3_and.sch b/library/SubcircuitLibrary/74153/3_and.sch new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/3_and.sub b/library/SubcircuitLibrary/74153/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74153/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/74153/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_OR-cache.lib b/library/SubcircuitLibrary/74153/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/4_OR.cir b/library/SubcircuitLibrary/74153/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/74153/4_OR.cir.out b/library/SubcircuitLibrary/74153/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/4_OR.pro b/library/SubcircuitLibrary/74153/4_OR.pro new file mode 100644 index 00000000..2c258cec --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.pro @@ -0,0 +1,45 @@ +update=03/28/19 22:43:48 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/library/SubcircuitLibrary/74153/4_OR.sch b/library/SubcircuitLibrary/74153/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/4_OR.sub b/library/SubcircuitLibrary/74153/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/74153/4_OR_Previous_Values.xml new file mode 100644 index 00000000..23698d37 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_and-cache.lib b/library/SubcircuitLibrary/74153/4_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/4_and.cir b/library/SubcircuitLibrary/74153/4_and.cir new file mode 100644 index 00000000..50d490fa --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/74153/4_and.cir.out b/library/SubcircuitLibrary/74153/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/4_and.pro b/library/SubcircuitLibrary/74153/4_and.pro new file mode 100644 index 00000000..6eb77fff --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.pro @@ -0,0 +1,57 @@ +update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/74153/4_and.sch b/library/SubcircuitLibrary/74153/4_and.sch new file mode 100644 index 00000000..883458e1 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/4_and.sub b/library/SubcircuitLibrary/74153/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/4_and_Previous_Values.xml b/library/SubcircuitLibrary/74153/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/74153/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/74153-cache.lib b/library/SubcircuitLibrary/74153/74153-cache.lib new file mode 100644 index 00000000..1e85854e --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 3900 3050 60 H V C CNN +F1 "4_OR" 3900 3250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900 +A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150 +A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150 +P 2 0 1 0 3550 2900 3900 2900 N +P 2 0 1 0 3550 3400 3900 3400 N +X in1 1 3400 3300 200 R 50 50 1 1 I +X in2 2 3400 3200 200 R 50 50 1 1 I +X in3 3 3400 3100 200 R 50 50 1 1 I +X in4 4 3400 3000 200 R 50 50 1 1 I +X out 5 4300 3150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/74153.cir b/library/SubcircuitLibrary/74153/74153.cir new file mode 100644 index 00000000..b20e6858 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.cir @@ -0,0 +1,25 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\74153.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:33:11 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad12_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U35 Net-_U1-Pad5_ Net-_U35-Pad2_ d_inverter +U34 Net-_U1-Pad10_ Net-_U34-Pad2_ d_inverter +X8 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad1_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and +X9 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad2_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and +X4 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and +X10 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and +X5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and +X6 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad7_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and +X3 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad8_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and +X7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad14_ 4_OR +X2 Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad13_ 4_OR + +.end diff --git a/library/SubcircuitLibrary/74153/74153.cir.out b/library/SubcircuitLibrary/74153/74153.cir.out new file mode 100644 index 00000000..c95e5ad9 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.cir.out @@ -0,0 +1,40 @@ +* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir + +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR +a1 net-_u1-pad12_ net-_u2-pad2_ u2 +a2 net-_u1-pad11_ net-_u3-pad2_ u3 +a3 net-_u1-pad5_ net-_u35-pad2_ u35 +a4 net-_u1-pad10_ net-_u34-pad2_ u34 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74153/74153.pro b/library/SubcircuitLibrary/74153/74153.pro new file mode 100644 index 00000000..ed8b8bf2 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.pro @@ -0,0 +1,59 @@ +update=03/28/19 23:27:36 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=texas +LibName4=intel +LibName5=audio +LibName6=interface +LibName7=digital-audio +LibName8=philips +LibName9=display +LibName10=cypress +LibName11=siliconi +LibName12=opto +LibName13=atmel +LibName14=contrib +LibName15=valves +LibName16=eSim_Analog +LibName17=eSim_Devices +LibName18=eSim_Digital +LibName19=eSim_Hybrid +LibName20=eSim_Miscellaneous +LibName21=eSim_Plot +LibName22=eSim_Power +LibName23=eSim_PSpice +LibName24=eSim_Sources +LibName25=eSim_User +LibName26=eSim_Subckt diff --git a/library/SubcircuitLibrary/74153/74153.sch b/library/SubcircuitLibrary/74153/74153.sch new file mode 100644 index 00000000..e0bcf950 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.sch @@ -0,0 +1,568 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:74153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 5C9378F6 +P 2650 1350 +F 0 "U2" H 2650 1250 60 0000 C CNN +F 1 "d_inverter" H 2650 1500 60 0000 C CNN +F 2 "" H 2700 1300 60 0000 C CNN +F 3 "" H 2700 1300 60 0000 C CNN + 1 2650 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C93798D +P 2700 950 +F 0 "U3" H 2700 850 60 0000 C CNN +F 1 "d_inverter" H 2700 1100 60 0000 C CNN +F 2 "" H 2750 900 60 0000 C CNN +F 3 "" H 2750 900 60 0000 C CNN + 1 2700 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C93A0F9 +P 1350 2050 +F 0 "U1" H 1400 2150 30 0000 C CNN +F 1 "PORT" H 1350 2050 30 0000 C CNN +F 2 "" H 1350 2050 60 0000 C CNN +F 3 "" H 1350 2050 60 0000 C CNN + 1 1350 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C93A174 +P 1350 4700 +F 0 "U1" H 1400 4800 30 0000 C CNN +F 1 "PORT" H 1350 4700 30 0000 C CNN +F 2 "" H 1350 4700 60 0000 C CNN +F 3 "" H 1350 4700 60 0000 C CNN + 6 1350 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C93AA3C +P 1350 2600 +F 0 "U1" H 1400 2700 30 0000 C CNN +F 1 "PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 2 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 3 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 4 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93AD97 +P 1350 5250 +F 0 "U1" H 1400 5350 30 0000 C CNN +F 1 "PORT" H 1350 5250 30 0000 C CNN +F 2 "" H 1350 5250 60 0000 C CNN +F 3 "" H 1350 5250 60 0000 C CNN + 7 1350 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C93ADFC +P 1350 5850 +F 0 "U1" H 1400 5950 30 0000 C CNN +F 1 "PORT" H 1350 5850 30 0000 C CNN +F 2 "" H 1350 5850 60 0000 C CNN +F 3 "" H 1350 5850 60 0000 C CNN + 8 1350 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C93AE63 +P 1350 6350 +F 0 "U1" H 1400 6450 30 0000 C CNN +F 1 "PORT" H 1350 6350 30 0000 C CNN +F 2 "" H 1350 6350 60 0000 C CNN +F 3 "" H 1350 6350 60 0000 C CNN + 9 1350 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C93AECA +P 1350 3950 +F 0 "U1" H 1400 4050 30 0000 C CNN +F 1 "PORT" H 1350 3950 30 0000 C CNN +F 2 "" H 1350 3950 60 0000 C CNN +F 3 "" H 1350 3950 60 0000 C CNN + 5 1350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C93AF79 +P 1350 6600 +F 0 "U1" H 1400 6700 30 0000 C CNN +F 1 "PORT" H 1350 6600 30 0000 C CNN +F 2 "" H 1350 6600 60 0000 C CNN +F 3 "" H 1350 6600 60 0000 C CNN + 10 1350 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C93B10A +P 1550 950 +F 0 "U1" H 1600 1050 30 0000 C CNN +F 1 "PORT" H 1550 950 30 0000 C CNN +F 2 "" H 1550 950 60 0000 C CNN +F 3 "" H 1550 950 60 0000 C CNN + 11 1550 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C93B179 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 5C95CBCC +P 2700 3950 +F 0 "U35" H 2700 3850 60 0000 C CNN +F 1 "d_inverter" H 2700 4100 60 0000 C CNN +F 2 "" H 2750 3900 60 0000 C CNN +F 3 "" H 2750 3900 60 0000 C CNN + 1 2700 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 5C95CC99 +P 2650 6600 +F 0 "U34" H 2650 6500 60 0000 C CNN +F 1 "d_inverter" H 2650 6750 60 0000 C CNN +F 2 "" H 2700 6550 60 0000 C CNN +F 3 "" H 2700 6550 60 0000 C CNN + 1 2650 6600 + 1 0 0 -1 +$EndComp +Text Notes 1750 2050 0 60 ~ 12 +A0 +Text Notes 1800 2600 0 60 ~ 12 +A1 +Text Notes 1800 3200 0 60 ~ 12 +A2 +Text Notes 1750 3700 0 60 ~ 12 +A3\n +Text Notes 1750 3950 0 60 ~ 12 +EnA\n +Text Notes 1800 4700 0 60 ~ 12 +B0\n +Text Notes 1800 5250 0 60 ~ 12 +B1 +Text Notes 1800 5850 0 60 ~ 12 +B2 +Text Notes 1750 6350 0 60 ~ 12 +B3 +Text Notes 1800 6600 0 60 ~ 12 +EnB +Text Notes 2000 950 0 60 ~ 12 +S1\n +Text Notes 2000 1350 0 60 ~ 12 +S0 +Text Notes 7350 2600 0 60 ~ 12 +YA +Text Notes 7400 5250 0 60 ~ 12 +YB +$Comp +L 4_and X8 +U 1 1 5C9D0C22 +P 2750 3050 +F 0 "X8" H 4250 4100 60 0000 C CNN +F 1 "4_and" H 4300 4250 60 0000 C CNN +F 2 "" H 2750 3050 60 0000 C CNN +F 3 "" H 2750 3050 60 0000 C CNN + 1 2750 3050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X9 +U 1 1 5C9D0CA2 +P 2750 3600 +F 0 "X9" H 4250 4650 60 0000 C CNN +F 1 "4_and" H 4300 4800 60 0000 C CNN +F 2 "" H 2750 3600 60 0000 C CNN +F 3 "" H 2750 3600 60 0000 C CNN + 1 2750 3600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 5C9D0D16 +P 2700 4200 +F 0 "X4" H 4200 5250 60 0000 C CNN +F 1 "4_and" H 4250 5400 60 0000 C CNN +F 2 "" H 2700 4200 60 0000 C CNN +F 3 "" H 2700 4200 60 0000 C CNN + 1 2700 4200 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X10 +U 1 1 5C9D0D93 +P 2750 4700 +F 0 "X10" H 4250 5750 60 0000 C CNN +F 1 "4_and" H 4300 5900 60 0000 C CNN +F 2 "" H 2750 4700 60 0000 C CNN +F 3 "" H 2750 4700 60 0000 C CNN + 1 2750 4700 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 5C9D182A +P 2700 5700 +F 0 "X5" H 4200 6750 60 0000 C CNN +F 1 "4_and" H 4250 6900 60 0000 C CNN +F 2 "" H 2700 5700 60 0000 C CNN +F 3 "" H 2700 5700 60 0000 C CNN + 1 2700 5700 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 5C9D1830 +P 2700 6250 +F 0 "X6" H 4200 7300 60 0000 C CNN +F 1 "4_and" H 4250 7450 60 0000 C CNN +F 2 "" H 2700 6250 60 0000 C CNN +F 3 "" H 2700 6250 60 0000 C CNN + 1 2700 6250 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 5C9D1836 +P 2650 6850 +F 0 "X3" H 4150 7900 60 0000 C CNN +F 1 "4_and" H 4200 8050 60 0000 C CNN +F 2 "" H 2650 6850 60 0000 C CNN +F 3 "" H 2650 6850 60 0000 C CNN + 1 2650 6850 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 5C9D183C +P 2700 7350 +F 0 "X7" H 4200 8400 60 0000 C CNN +F 1 "4_and" H 4250 8550 60 0000 C CNN +F 2 "" H 2700 7350 60 0000 C CNN +F 3 "" H 2700 7350 60 0000 C CNN + 1 2700 7350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 1800 3800 1800 +Wire Wire Line + 3100 1350 3100 5600 +Wire Wire Line + 3200 1900 3800 1900 +Wire Wire Line + 3200 950 3200 5100 +Wire Wire Line + 2950 1350 3100 1350 +Connection ~ 3100 1800 +Wire Wire Line + 3000 950 3200 950 +Connection ~ 3200 1900 +Wire Wire Line + 1800 950 2400 950 +Wire Wire Line + 1800 1350 2350 1350 +Wire Wire Line + 2200 950 2200 6200 +Connection ~ 2200 950 +Wire Wire Line + 2300 1350 2300 6100 +Wire Wire Line + 3300 2100 3800 2100 +Wire Wire Line + 3300 2100 3300 3800 +Wire Wire Line + 3300 2700 3800 2700 +Wire Wire Line + 3300 3300 3750 3300 +Connection ~ 3300 2700 +Wire Wire Line + 3000 3800 3800 3800 +Connection ~ 3300 3300 +Wire Wire Line + 1600 3700 3800 3700 +Wire Wire Line + 1600 3200 3750 3200 +Wire Wire Line + 3400 2600 1600 2600 +Wire Wire Line + 1600 2050 3800 2050 +Wire Wire Line + 3000 3800 3000 3950 +Wire Wire Line + 1600 3950 2400 3950 +Connection ~ 3300 3800 +Wire Wire Line + 3100 4450 3750 4450 +Wire Wire Line + 3200 4550 3750 4550 +Wire Wire Line + 3300 4800 3750 4800 +Wire Wire Line + 3300 4800 3300 6450 +Wire Wire Line + 3300 5350 3750 5350 +Wire Wire Line + 3300 5950 3700 5950 +Connection ~ 3300 5350 +Wire Wire Line + 3200 6450 3750 6450 +Connection ~ 3300 5950 +Wire Wire Line + 3350 6350 1600 6350 +Wire Wire Line + 1600 5850 3700 5850 +Wire Wire Line + 1600 5250 3750 5250 +Wire Wire Line + 3350 4700 1600 4700 +Wire Wire Line + 3200 6600 3200 6450 +Wire Wire Line + 2950 6600 3200 6600 +Wire Wire Line + 1600 6600 2350 6600 +Connection ~ 3300 6450 +Connection ~ 2300 1350 +Connection ~ 3100 4450 +Connection ~ 3200 4550 +Wire Wire Line + 6550 2600 7600 2600 +Wire Wire Line + 6450 5250 7650 5250 +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3750 5100 +Wire Wire Line + 2300 5000 3750 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3700 5600 +Wire Wire Line + 2200 5700 3700 5700 +Wire Wire Line + 2200 6200 3750 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3750 6100 +Wire Wire Line + 3200 2450 3800 2450 +Connection ~ 3200 2450 +Wire Wire Line + 2300 2350 3800 2350 +Connection ~ 2300 2350 +Wire Wire Line + 2200 3050 3750 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3100 2950 3750 2950 +Connection ~ 3100 2950 +Wire Wire Line + 2300 3450 3800 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 2200 3550 3800 3550 +Connection ~ 2200 3550 +Wire Wire Line + 3800 2050 3800 2000 +Wire Wire Line + 3400 2600 3400 2550 +Wire Wire Line + 3400 2550 3800 2550 +Wire Wire Line + 3800 2700 3800 2650 +Wire Wire Line + 3750 3200 3750 3150 +Wire Wire Line + 3750 3300 3750 3250 +Wire Wire Line + 3800 3700 3800 3650 +Wire Wire Line + 3800 3800 3800 3750 +Wire Wire Line + 3350 4700 3350 4650 +Wire Wire Line + 3350 4650 3750 4650 +Wire Wire Line + 3750 4800 3750 4750 +Wire Wire Line + 3750 5250 3750 5200 +Wire Wire Line + 3750 5350 3750 5300 +Wire Wire Line + 3700 5850 3700 5800 +Wire Wire Line + 3700 5950 3700 5900 +Wire Wire Line + 3350 6350 3350 6300 +Wire Wire Line + 3350 6300 3750 6300 +Wire Wire Line + 3750 6450 3750 6400 +$Comp +L 4_OR X1 +U 1 1 5C9D22F7 +P 2150 8400 +F 0 "X1" H 6050 11450 60 0000 C CNN +F 1 "4_OR" H 6050 11650 60 0000 C CNN +F 2 "" H 2150 8400 60 0000 C CNN +F 3 "" H 2150 8400 60 0000 C CNN + 1 2150 8400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 5100 5550 4600 +Wire Wire Line + 5550 4600 4650 4600 +Wire Wire Line + 5550 5200 4650 5200 +Wire Wire Line + 4650 5200 4650 5150 +Wire Wire Line + 4600 5750 4600 5300 +Wire Wire Line + 4600 5300 5550 5300 +Wire Wire Line + 4650 6250 4650 5400 +Wire Wire Line + 4650 5400 5550 5400 +$Comp +L 4_OR X2 +U 1 1 5C9D28DE +P 2250 5750 +F 0 "X2" H 6150 8800 60 0000 C CNN +F 1 "4_OR" H 6150 9000 60 0000 C CNN +F 2 "" H 2250 5750 60 0000 C CNN +F 3 "" H 2250 5750 60 0000 C CNN + 1 2250 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 1950 5650 1950 +Wire Wire Line + 5650 1950 5650 2450 +Wire Wire Line + 5650 2550 4700 2550 +Wire Wire Line + 4700 2550 4700 2500 +Wire Wire Line + 4650 3100 4650 2650 +Wire Wire Line + 4650 2650 5650 2650 +Wire Wire Line + 4700 3600 4700 2750 +Wire Wire Line + 4700 2750 5650 2750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/74153.sub b/library/SubcircuitLibrary/74153/74153.sub new file mode 100644 index 00000000..6e00261f --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153.sub @@ -0,0 +1,34 @@ +* Subcircuit 74153 +.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR +a1 net-_u1-pad12_ net-_u2-pad2_ u2 +a2 net-_u1-pad11_ net-_u3-pad2_ u3 +a3 net-_u1-pad5_ net-_u35-pad2_ u35 +a4 net-_u1-pad10_ net-_u34-pad2_ u34 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74153
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/74153_Previous_Values.xml b/library/SubcircuitLibrary/74153/74153_Previous_Values.xml new file mode 100644 index 00000000..ea70e6f3 --- /dev/null +++ b/library/SubcircuitLibrary/74153/74153_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u14 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u14><u25 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u25><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u20 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u20><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u21 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u21><u18 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u24 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u24><u28 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u29 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u29><u32 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u32><u2 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u15 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u15><u6 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u4><u16 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u27 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u27><u10 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u10><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u12><u23 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u23><u19 name="type">d_and<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u19><u26 name="type">d_and<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u26><u30 name="type">d_or<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u30><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u17 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u17><u11 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u11><u13 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u13><u9 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x9><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x10><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib b/library/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib new file mode 100644 index 00000000..10496d63 --- /dev/null +++ b/library/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74153/Dual4to1MUX.cir b/library/SubcircuitLibrary/74153/Dual4to1MUX.cir new file mode 100644 index 00000000..583c4a00 --- /dev/null +++ b/library/SubcircuitLibrary/74153/Dual4to1MUX.cir @@ -0,0 +1,45 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U14 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U25 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and +U5 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and +U7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and +U18 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and +U24 Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and +U28 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or +U29 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or +U32 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or +U2 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U3 Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter +U15 Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U6 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and +U8 Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and +U4 Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and +U16 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and +U27 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and +U22 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and +U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and +U23 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and +U19 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and +U26 Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and +U30 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or +U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or +U33 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or +U17 Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and +U11 Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U13 Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and +U9 Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U34 Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter +U35 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/74153/Dual4to1MUX.sch b/library/SubcircuitLibrary/74153/Dual4to1MUX.sch new file mode 100644 index 00000000..340b1a31 --- /dev/null +++ b/library/SubcircuitLibrary/74153/Dual4to1MUX.sch @@ -0,0 +1,814 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:74153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U14 +U 1 1 5C936BFE +P 3850 2450 +F 0 "U14" H 3850 2450 60 0000 C CNN +F 1 "d_and" H 3900 2550 60 0000 C CNN +F 2 "" H 3850 2450 60 0000 C CNN +F 3 "" H 3850 2450 60 0000 C CNN + 1 3850 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 5C936C8A +P 4850 2600 +F 0 "U25" H 4850 2600 60 0000 C CNN +F 1 "d_and" H 4900 2700 60 0000 C CNN +F 2 "" H 4850 2600 60 0000 C CNN +F 3 "" H 4850 2600 60 0000 C CNN + 1 4850 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5C936E84 +P 3800 3050 +F 0 "U5" H 3800 3050 60 0000 C CNN +F 1 "d_and" H 3850 3150 60 0000 C CNN +F 2 "" H 3800 3050 60 0000 C CNN +F 3 "" H 3800 3050 60 0000 C CNN + 1 3800 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 5C936E8A +P 4800 3200 +F 0 "U20" H 4800 3200 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"PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 2 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 3 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 4 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93AD97 +P 1350 5250 +F 0 "U1" H 1400 5350 30 0000 C CNN +F 1 "PORT" H 1350 5250 30 0000 C CNN +F 2 "" H 1350 5250 60 0000 C CNN +F 3 "" H 1350 5250 60 0000 C CNN + 7 1350 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C93ADFC +P 1350 5850 +F 0 "U1" H 1400 5950 30 0000 C CNN +F 1 "PORT" H 1350 5850 30 0000 C CNN +F 2 "" H 1350 5850 60 0000 C CNN +F 3 "" H 1350 5850 60 0000 C CNN + 8 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0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 2600 7600 2600 +Wire Wire Line + 7300 5250 7650 5250 +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3400 5100 +Wire Wire Line + 3400 5000 2300 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3350 5600 +Wire Wire Line + 2200 5700 3350 5700 +Wire Wire Line + 2200 6200 3350 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3350 6100 +Wire Wire Line + 3400 2450 3200 2450 +Connection ~ 3200 2450 +Wire Wire Line + 3400 2350 2300 2350 +Connection ~ 2300 2350 +Wire Wire Line + 3350 3050 2200 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3350 2950 3100 2950 +Connection ~ 3100 2950 +Wire Wire Line + 3350 3450 2300 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 3350 3550 2200 3550 +Connection ~ 2200 3550 +$Comp +L d_inverter U34 +U 1 1 5C95C9D0 +P 2650 3950 +F 0 "U34" H 2650 3850 60 0000 C CNN +F 1 "d_inverter" H 2650 4100 60 0000 C CNN +F 2 "" H 2700 3900 60 0000 C CNN +F 3 "" H 2700 3900 60 0000 C CNN + 1 2650 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 5C95CD17 +P 2700 6600 +F 0 "U35" H 2700 6500 60 0000 C CNN +F 1 "d_inverter" H 2700 6750 60 0000 C CNN +F 2 "" H 2750 6550 60 0000 C CNN +F 3 "" H 2750 6550 60 0000 C CNN + 1 2700 6600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74153/analysis b/library/SubcircuitLibrary/74153/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74153/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74157/3_and-cache.lib b/library/SubcircuitLibrary/74157/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74157/3_and.cir b/library/SubcircuitLibrary/74157/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74157/3_and.cir.out b/library/SubcircuitLibrary/74157/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74157/3_and.pro b/library/SubcircuitLibrary/74157/3_and.pro new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/library/SubcircuitLibrary/74157/3_and.sch b/library/SubcircuitLibrary/74157/3_and.sch new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74157/3_and.sub b/library/SubcircuitLibrary/74157/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74157/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74157/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/74157/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74157/74157-cache.lib b/library/SubcircuitLibrary/74157/74157-cache.lib new file mode 100644 index 00000000..de171255 --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74157/74157.cir b/library/SubcircuitLibrary/74157/74157.cir new file mode 100644 index 00000000..6920161c --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157.cir @@ -0,0 +1,25 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74157\74157.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:37:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad12_ d_or +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad13_ d_or +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad14_ d_or +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad11_ d_or +U3 Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter +X2 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U20-Pad1_ 3_and +X3 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U21-Pad1_ 3_and +X4 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U22-Pad1_ 3_and +X5 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U23-Pad1_ 3_and +X6 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad2_ 3_and +X7 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U21-Pad2_ 3_and +X1 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U22-Pad2_ 3_and +X8 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad8_ Net-_U23-Pad2_ 3_and + +.end diff --git a/library/SubcircuitLibrary/74157/74157.cir.out b/library/SubcircuitLibrary/74157/74157.cir.out new file mode 100644 index 00000000..3a11a42d --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157.cir.out @@ -0,0 +1,45 @@ +* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir + +.include 3_and.sub +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or +* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and +x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and +x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and +x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and +x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23 +a5 net-_u1-pad10_ net-_u3-pad2_ u3 +a6 net-_u1-pad9_ net-_u2-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74157/74157.pro b/library/SubcircuitLibrary/74157/74157.pro new file mode 100644 index 00000000..fcbb1fc8 --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157.pro @@ -0,0 +1,57 @@ +update=03/28/19 22:30:06 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_User +LibName24=eSim_Subckt diff --git a/library/SubcircuitLibrary/74157/74157.sch b/library/SubcircuitLibrary/74157/74157.sch new file mode 100644 index 00000000..7fd3609e --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157.sch @@ -0,0 +1,549 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:74157-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 1650 1850 2750 1850 +Wire Wire Line + 2750 3350 1650 3350 +Wire Wire Line + 2750 3050 2750 3350 +Wire Wire Line + 2800 4050 1650 4050 +Wire Wire Line + 2800 3550 2800 4050 +Wire Wire Line + 2200 2150 2200 4350 +Wire Wire Line + 2200 2150 1650 2150 +Wire Wire Line + 2150 2900 2150 4850 +Wire Wire Line + 2150 2900 1650 2900 +Wire Wire Line + 2100 3600 2100 5300 +Wire Wire Line + 2100 3600 1650 3600 +Wire Wire Line + 2050 4300 2050 5800 +Wire Wire Line + 1650 4300 2050 4300 +Wire Wire Line + 2200 5500 2200 6250 +$Comp +L d_or U20 +U 1 1 5C95E06C +P 6650 3300 +F 0 "U20" H 6650 3300 60 0000 C CNN +F 1 "d_or" H 6650 3400 60 0000 C CNN +F 2 "" H 6650 3300 60 0000 C CNN +F 3 "" H 6650 3300 60 0000 C CNN + 1 6650 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U21 +U 1 1 5C95E114 +P 6650 3800 +F 0 "U21" H 6650 3800 60 0000 C CNN +F 1 "d_or" H 6650 3900 60 0000 C CNN +F 2 "" H 6650 3800 60 0000 C CNN +F 3 "" H 6650 3800 60 0000 C CNN + 1 6650 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U22 +U 1 1 5C95E16E +P 6650 4250 +F 0 "U22" H 6650 4250 60 0000 C CNN +F 1 "d_or" H 6650 4350 60 0000 C CNN +F 2 "" H 6650 4250 60 0000 C CNN +F 3 "" H 6650 4250 60 0000 C CNN + 1 6650 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U23 +U 1 1 5C95E1C9 +P 6650 4750 +F 0 "U23" H 6650 4750 60 0000 C CNN +F 1 "d_or" H 6650 4850 60 0000 C CNN +F 2 "" H 6650 4750 60 0000 C CNN +F 3 "" H 6650 4750 60 0000 C CNN + 1 6650 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 3200 5950 3200 +Wire Wire Line + 5950 3200 5950 2000 +Wire Wire Line + 5950 2000 4750 2000 +Wire Wire Line + 6200 3700 5850 3700 +Wire Wire Line + 5850 3700 5850 2500 +Wire Wire Line + 5850 2500 4750 2500 +Wire Wire Line + 6200 4150 5750 4150 +Wire Wire Line + 5750 4150 5750 2950 +Wire Wire Line + 5750 2950 4750 2950 +Wire Wire Line + 6200 4650 5650 4650 +Wire Wire Line + 5650 4650 5650 3450 +Wire Wire Line + 5650 3450 4750 3450 +Wire Wire Line + 4750 4250 5450 4250 +Wire Wire Line + 5450 4250 5450 3300 +Wire Wire Line + 5450 3300 6200 3300 +Wire Wire Line + 4750 4750 5550 4750 +Wire Wire Line + 5550 4750 5550 3800 +Wire Wire Line + 5550 3800 6200 3800 +Wire Wire Line + 4700 5200 5600 5200 +Wire Wire Line + 5600 5200 5600 4250 +Wire Wire Line + 5600 4250 6200 4250 +Wire Wire Line + 4750 5700 5700 5700 +Wire Wire Line + 5700 5700 5700 4750 +Wire Wire Line + 5700 4750 6200 4750 +Wire Wire Line + 7100 3250 8300 3250 +Wire Wire Line + 7100 3750 8300 3750 +Wire Wire Line + 7100 4200 8300 4200 +Wire Wire Line + 7100 4700 8250 4700 +$Comp +L d_inverter U3 +U 1 1 5C95E74D +P 2750 6250 +F 0 "U3" H 2750 6150 60 0000 C CNN +F 1 "d_inverter" H 2750 6400 60 0000 C CNN +F 2 "" H 2800 6200 60 0000 C CNN +F 3 "" H 2800 6200 60 0000 C CNN + 1 2750 6250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1700 6250 2450 6250 +Connection ~ 2200 6250 +$Comp +L PORT U1 +U 1 1 5C95E920 +P 1400 1850 +F 0 "U1" H 1450 1950 30 0000 C CNN +F 1 "PORT" H 1400 1850 30 0000 C CNN +F 2 "" H 1400 1850 60 0000 C CNN +F 3 "" H 1400 1850 60 0000 C CNN + 1 1400 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C95E9CF +P 1400 2150 +F 0 "U1" H 1450 2250 30 0000 C CNN +F 1 "PORT" H 1400 2150 30 0000 C CNN +F 2 "" H 1400 2150 60 0000 C CNN +F 3 "" H 1400 2150 60 0000 C CNN + 2 1400 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C95EA28 +P 1400 2700 +F 0 "U1" H 1450 2800 30 0000 C CNN +F 1 "PORT" H 1400 2700 30 0000 C CNN +F 2 "" H 1400 2700 60 0000 C CNN +F 3 "" H 1400 2700 60 0000 C CNN + 3 1400 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C95EA9C +P 1400 2900 +F 0 "U1" H 1450 3000 30 0000 C CNN +F 1 "PORT" H 1400 2900 30 0000 C CNN +F 2 "" H 1400 2900 60 0000 C CNN +F 3 "" H 1400 2900 60 0000 C CNN + 4 1400 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C95EAFD +P 1400 3350 +F 0 "U1" H 1450 3450 30 0000 C CNN +F 1 "PORT" H 1400 3350 30 0000 C CNN +F 2 "" H 1400 3350 60 0000 C CNN +F 3 "" H 1400 3350 60 0000 C CNN + 5 1400 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C95EB63 +P 1400 3600 +F 0 "U1" H 1450 3700 30 0000 C CNN +F 1 "PORT" H 1400 3600 30 0000 C CNN +F 2 "" H 1400 3600 60 0000 C CNN +F 3 "" H 1400 3600 60 0000 C CNN + 6 1400 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C95EBC8 +P 1400 4050 +F 0 "U1" H 1450 4150 30 0000 C CNN +F 1 "PORT" H 1400 4050 30 0000 C CNN +F 2 "" H 1400 4050 60 0000 C CNN +F 3 "" H 1400 4050 60 0000 C CNN + 7 1400 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C95EC38 +P 1400 4300 +F 0 "U1" H 1450 4400 30 0000 C CNN +F 1 "PORT" H 1400 4300 30 0000 C CNN +F 2 "" H 1400 4300 60 0000 C CNN +F 3 "" H 1400 4300 60 0000 C CNN + 8 1400 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C95ECA1 +P 1450 6250 +F 0 "U1" H 1500 6350 30 0000 C CNN +F 1 "PORT" H 1450 6250 30 0000 C CNN +F 2 "" H 1450 6250 60 0000 C CNN +F 3 "" H 1450 6250 60 0000 C CNN + 10 1450 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C95ED51 +P 1400 6650 +F 0 "U1" H 1450 6750 30 0000 C CNN +F 1 "PORT" H 1400 6650 30 0000 C CNN +F 2 "" H 1400 6650 60 0000 C CNN +F 3 "" H 1400 6650 60 0000 C CNN + 9 1400 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C95EDCC +P 8550 3250 +F 0 "U1" H 8600 3350 30 0000 C CNN +F 1 "PORT" H 8550 3250 30 0000 C CNN +F 2 "" H 8550 3250 60 0000 C CNN +F 3 "" H 8550 3250 60 0000 C CNN + 12 8550 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C95EEA6 +P 8550 3750 +F 0 "U1" H 8600 3850 30 0000 C CNN +F 1 "PORT" H 8550 3750 30 0000 C CNN +F 2 "" H 8550 3750 60 0000 C CNN +F 3 "" H 8550 3750 60 0000 C CNN + 13 8550 3750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C95EF2D +P 8550 4200 +F 0 "U1" H 8600 4300 30 0000 C CNN +F 1 "PORT" H 8550 4200 30 0000 C CNN +F 2 "" H 8550 4200 60 0000 C CNN +F 3 "" H 8550 4200 60 0000 C CNN + 14 8550 4200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C95EFB5 +P 8500 4700 +F 0 "U1" H 8550 4800 30 0000 C CNN +F 1 "PORT" H 8500 4700 30 0000 C CNN +F 2 "" H 8500 4700 60 0000 C CNN +F 3 "" H 8500 4700 60 0000 C CNN + 11 8500 4700 + -1 0 0 1 +$EndComp +Text Notes 1950 1800 0 60 ~ 12 +A0\n +Text Notes 1950 2100 0 60 ~ 12 +A1 +Text Notes 1900 2650 0 60 ~ 12 +B0 +Text Notes 1900 2900 0 60 ~ 12 +B1\n +Text Notes 1900 3350 0 60 ~ 12 +C0\n +Text Notes 1900 3600 0 60 ~ 12 +C1\n +Text Notes 1800 4050 0 60 ~ 12 +D0 +Text Notes 1800 4300 0 60 ~ 12 +D1 +Text Notes 1850 6250 0 60 ~ 12 +SEL\n +Text Notes 1800 6650 0 60 ~ 12 +~EN +$Comp +L d_inverter U2 +U 1 1 5C95FD56 +P 2650 6650 +F 0 "U2" H 2650 6550 60 0000 C CNN +F 1 "d_inverter" H 2650 6800 60 0000 C CNN +F 2 "" H 2700 6600 60 0000 C CNN +F 3 "" H 2700 6600 60 0000 C CNN + 1 2650 6650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 6650 2950 6650 +Wire Wire Line + 1650 6650 2350 6650 +Text Notes 7850 3200 0 60 ~ 12 +YA +Text Notes 7850 3700 0 60 ~ 12 +YB +Text Notes 7850 4200 2 60 ~ 12 +YC +Text Notes 7800 4700 0 60 ~ 12 +YD +Wire Wire Line + 3450 2000 3900 2000 +Wire Wire Line + 3450 2000 3450 5700 +Wire Wire Line + 3450 2500 3900 2500 +Wire Wire Line + 3450 2950 3900 2950 +Connection ~ 3450 2500 +Wire Wire Line + 3450 3450 3900 3450 +Connection ~ 3450 2950 +Wire Wire Line + 3450 4250 3900 4250 +Connection ~ 3450 3450 +Wire Wire Line + 3450 4750 3900 4750 +Connection ~ 3450 4250 +Wire Wire Line + 3450 5200 3850 5200 +Connection ~ 3450 4750 +Wire Wire Line + 3400 5700 3900 5700 +Connection ~ 3450 5200 +Wire Wire Line + 3300 5600 3900 5600 +Wire Wire Line + 3300 4150 3300 5600 +Wire Wire Line + 3300 5100 3850 5100 +Wire Wire Line + 3300 4650 3900 4650 +Connection ~ 3300 5100 +Wire Wire Line + 3300 4150 3900 4150 +Connection ~ 3300 4650 +Wire Wire Line + 3250 3350 3900 3350 +Wire Wire Line + 3250 1900 3250 3350 +Wire Wire Line + 3250 2850 3900 2850 +Wire Wire Line + 3250 2400 3900 2400 +Connection ~ 3250 2850 +Wire Wire Line + 3250 1900 3900 1900 +Connection ~ 3250 2400 +Wire Wire Line + 3250 3000 3100 3000 +Wire Wire Line + 3100 3000 3100 6250 +Wire Wire Line + 3100 6250 3050 6250 +Connection ~ 3250 3000 +Wire Wire Line + 3300 5500 2200 5500 +Connection ~ 3300 5500 +Wire Wire Line + 3400 6650 3400 5700 +Connection ~ 3450 5700 +$Comp +L 3_and X2 +U 1 1 5C9D0110 +P 3450 2400 +F 0 "X2" H 4350 2700 60 0000 C CNN +F 1 "3_and" H 4400 2900 60 0000 C CNN +F 2 "" H 3450 2400 60 0000 C CNN +F 3 "" H 3450 2400 60 0000 C CNN + 1 3450 2400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 5C9D01B8 +P 3450 2900 +F 0 "X3" H 4350 3200 60 0000 C CNN +F 1 "3_and" H 4400 3400 60 0000 C CNN +F 2 "" H 3450 2900 60 0000 C CNN +F 3 "" H 3450 2900 60 0000 C CNN + 1 3450 2900 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 5C9D0222 +P 3450 3350 +F 0 "X4" H 4350 3650 60 0000 C CNN +F 1 "3_and" H 4400 3850 60 0000 C CNN +F 2 "" H 3450 3350 60 0000 C CNN +F 3 "" H 3450 3350 60 0000 C CNN + 1 3450 3350 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 5C9D0289 +P 3450 3850 +F 0 "X5" H 4350 4150 60 0000 C CNN +F 1 "3_and" H 4400 4350 60 0000 C CNN +F 2 "" H 3450 3850 60 0000 C CNN +F 3 "" H 3450 3850 60 0000 C CNN + 1 3450 3850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 5C9D0361 +P 3450 4650 +F 0 "X6" H 4350 4950 60 0000 C CNN +F 1 "3_and" H 4400 5150 60 0000 C CNN +F 2 "" H 3450 4650 60 0000 C CNN +F 3 "" H 3450 4650 60 0000 C CNN + 1 3450 4650 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X7 +U 1 1 5C9D0367 +P 3450 5150 +F 0 "X7" H 4350 5450 60 0000 C CNN +F 1 "3_and" H 4400 5650 60 0000 C CNN +F 2 "" H 3450 5150 60 0000 C CNN +F 3 "" H 3450 5150 60 0000 C CNN + 1 3450 5150 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 5C9D036D +P 3400 5600 +F 0 "X1" H 4300 5900 60 0000 C CNN +F 1 "3_and" H 4350 6100 60 0000 C CNN +F 2 "" H 3400 5600 60 0000 C CNN +F 3 "" H 3400 5600 60 0000 C CNN + 1 3400 5600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X8 +U 1 1 5C9D0373 +P 3450 6100 +F 0 "X8" H 4350 6400 60 0000 C CNN +F 1 "3_and" H 4400 6600 60 0000 C CNN +F 2 "" H 3450 6100 60 0000 C CNN +F 3 "" H 3450 6100 60 0000 C CNN + 1 3450 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 2100 2750 2100 +Wire Wire Line + 2750 2100 2750 1850 +Wire Wire Line + 3900 2600 1650 2600 +Wire Wire Line + 1650 2600 1650 2700 +Wire Wire Line + 3900 3050 2750 3050 +Wire Wire Line + 3900 3550 2800 3550 +Wire Wire Line + 2200 4350 3900 4350 +Wire Wire Line + 2150 4850 3900 4850 +Wire Wire Line + 2100 5300 3850 5300 +Wire Wire Line + 2050 5800 3900 5800 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74157/74157.sub b/library/SubcircuitLibrary/74157/74157.sub new file mode 100644 index 00000000..545741f5 --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157.sub @@ -0,0 +1,39 @@ +* Subcircuit 74157 +.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir +.include 3_and.sub +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or +* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and +x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and +x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and +x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and +x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23 +a5 net-_u1-pad10_ net-_u3-pad2_ u3 +a6 net-_u1-pad9_ net-_u2-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74157
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74157/74157_Previous_Values.xml b/library/SubcircuitLibrary/74157/74157_Previous_Values.xml new file mode 100644 index 00000000..85f14960 --- /dev/null +++ b/library/SubcircuitLibrary/74157/74157_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u4 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u12 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u13><u8 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u8><u16 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u16><u9 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u9><u17 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u17><u6 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u6><u14 name="type">d_and<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u7 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u7><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u10><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u22 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u23><u3 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74157/analysis b/library/SubcircuitLibrary/74157/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74157/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/3_and-cache.lib b/library/SubcircuitLibrary/7485/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/7485/3_and.cir b/library/SubcircuitLibrary/7485/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/7485/3_and.cir.out b/library/SubcircuitLibrary/7485/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/7485/3_and.pro b/library/SubcircuitLibrary/7485/3_and.pro new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/library/SubcircuitLibrary/7485/3_and.sch b/library/SubcircuitLibrary/7485/3_and.sch new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/3_and.sub b/library/SubcircuitLibrary/7485/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/3_and_Previous_Values.xml b/library/SubcircuitLibrary/7485/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/7485/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/4_and-cache.lib b/library/SubcircuitLibrary/7485/4_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/7485/4_and.cir b/library/SubcircuitLibrary/7485/4_and.cir new file mode 100644 index 00000000..50d490fa --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/7485/4_and.cir.out b/library/SubcircuitLibrary/7485/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/7485/4_and.pro b/library/SubcircuitLibrary/7485/4_and.pro new file mode 100644 index 00000000..6eb77fff --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and.pro @@ -0,0 +1,57 @@ +update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/7485/4_and.sch b/library/SubcircuitLibrary/7485/4_and.sch new file mode 100644 index 00000000..883458e1 --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/4_and.sub b/library/SubcircuitLibrary/7485/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/4_and_Previous_Values.xml b/library/SubcircuitLibrary/7485/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/7485/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/5_and-cache.lib b/library/SubcircuitLibrary/7485/5_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/7485/5_and.cir b/library/SubcircuitLibrary/7485/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/7485/5_and.cir.out b/library/SubcircuitLibrary/7485/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/7485/5_and.pro b/library/SubcircuitLibrary/7485/5_and.pro new file mode 100644 index 00000000..c82e4e6d --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and.pro @@ -0,0 +1,50 @@ +update=03/26/19 18:50:27 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/library/SubcircuitLibrary/7485/5_and.sch b/library/SubcircuitLibrary/7485/5_and.sch new file mode 100644 index 00000000..da927b09 --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and.sch @@ -0,0 +1,158 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/5_and.sub b/library/SubcircuitLibrary/7485/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/5_and_Previous_Values.xml b/library/SubcircuitLibrary/7485/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/7485/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/7485-cache.lib b/library/SubcircuitLibrary/7485/7485-cache.lib new file mode 100644 index 00000000..6edb5033 --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485-cache.lib @@ -0,0 +1,175 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# c_gate +# +DEF c_gate X 0 40 Y Y 1 F N +F0 "X" 5900 4450 60 H V C CNN +F1 "c_gate" 5950 4700 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250 +P 2 0 1 0 5550 4850 6100 4850 N +P 4 0 1 0 5550 4850 5550 4250 6050 4250 6100 4250 N +X in1 1 5350 4800 200 R 50 50 1 1 I I +X in2 2 5350 4700 200 R 50 50 1 1 I I +X in3 3 5350 4600 200 R 50 50 1 1 I I +X in4 4 5350 4500 200 R 50 50 1 1 I I +X in5 5 5350 4400 200 R 50 50 1 1 I I +X in6 6 5350 4300 200 R 50 50 1 1 I I +X out 7 6500 4550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/7485/7485.cir b/library/SubcircuitLibrary/7485/7485.cir new file mode 100644 index 00000000..e15a357f --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485.cir @@ -0,0 +1,42 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\7485\7485.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 20:14:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U6 Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U18-Pad2_ d_nand +U7 Net-_U18-Pad2_ Net-_U1-Pad5_ Net-_U14-Pad2_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor +U19 Net-_U1-Pad5_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and +X12 Net-_U1-Pad7_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad4_ 3_and +X7 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X2-Pad3_ 4_and +X9 Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X2-Pad4_ 5_and +X10 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad1_ Net-_X10-Pad6_ 5_and +X11 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X11-Pad6_ 5_and +X13 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad2_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad13_ 5_and +U18 Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +X8 Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad5_ 3_and +X3 Net-_U1-Pad8_ Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U15-Pad3_ Net-_X1-Pad4_ 4_and +X6 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X1-Pad3_ 5_and +X5 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X1-Pad2_ 5_and +X4 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X1-Pad1_ 5_and +U8 Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and +U3 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U3-Pad3_ d_nand +U9 Net-_U3-Pad3_ Net-_U1-Pad7_ Net-_U15-Pad2_ d_and +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor +U12 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U5 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U12-Pad2_ d_nand +U13 Net-_U12-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad3_ d_and +U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nor +U10 Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U4 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad2_ d_nand +U11 Net-_U10-Pad2_ Net-_U1-Pad9_ Net-_U11-Pad3_ d_and +U16 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_nor +X2 Net-_U19-Pad3_ Net-_X12-Pad4_ Net-_X2-Pad3_ Net-_X2-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad12_ c_gate +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad14_ c_gate +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/7485/7485.cir.out b/library/SubcircuitLibrary/7485/7485.cir.out new file mode 100644 index 00000000..afc7b865 --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485.cir.out @@ -0,0 +1,101 @@ +* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir + +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +.include c_gate.sub +* u6 net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u19 net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and +x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and +x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and +x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and +* u18 net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and +x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and +x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and +x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and +x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and +x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and +* u8 net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7 +a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9 +a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/7485/7485.pro b/library/SubcircuitLibrary/7485/7485.pro new file mode 100644 index 00000000..8fb4abb4 --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485.pro @@ -0,0 +1,58 @@ +update=03/26/19 19:27:48 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_User +LibName25=eSim_Subckt diff --git a/library/SubcircuitLibrary/7485/7485.sch b/library/SubcircuitLibrary/7485/7485.sch new file mode 100644 index 00000000..0db5f0d6 --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485.sch @@ -0,0 +1,1127 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:7485-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U6 +U 1 1 5C9A2432 +P 3150 1200 +F 0 "U6" H 3150 1200 60 0000 C CNN +F 1 "d_and" H 3200 1300 60 0000 C CNN +F 2 "" H 3150 1200 60 0000 C CNN +F 3 "" H 3150 1200 60 0000 C CNN + 1 3150 1200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U2 +U 1 1 5C9A246F +P 2100 1450 +F 0 "U2" H 2100 1450 60 0000 C CNN +F 1 "d_nand" H 2150 1550 60 0000 C CNN +F 2 "" H 2100 1450 60 0000 C CNN +F 3 "" H 2100 1450 60 0000 C CNN + 1 2100 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5C9A24BA +P 3150 1600 +F 0 "U7" H 3150 1600 60 0000 C CNN +F 1 "d_and" H 3200 1700 60 0000 C CNN +F 2 "" H 3150 1600 60 0000 C CNN +F 3 "" H 3150 1600 60 0000 C CNN + 1 3150 1600 + 1 0 0 -1 +$EndComp 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6950 5750 +Wire Wire Line + 6850 6250 6850 5850 +Wire Wire Line + 6850 5850 7350 5850 +Wire Wire Line + 7350 5850 7350 5500 +Wire Wire Line + 7350 5500 8200 5500 +Wire Wire Line + 6800 6950 6950 6950 +Wire Wire Line + 6950 6950 6950 6200 +Wire Wire Line + 6950 6200 7950 6200 +Wire Wire Line + 7950 6200 7950 5700 +Wire Wire Line + 7950 5700 8200 5700 +$Comp +L PORT U1 +U 4 1 5C9A8539 +P 850 1350 +F 0 "U1" H 900 1450 30 0000 C CNN +F 1 "PORT" H 850 1350 30 0000 C CNN +F 2 "" H 850 1350 60 0000 C CNN +F 3 "" H 850 1350 60 0000 C CNN + 4 850 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A8668 +P 850 1550 +F 0 "U1" H 900 1650 30 0000 C CNN +F 1 "PORT" H 850 1550 30 0000 C CNN +F 2 "" H 850 1550 60 0000 C CNN +F 3 "" H 850 1550 60 0000 C CNN + 5 850 1550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1100 1550 1100 1450 +$Comp +L PORT U1 +U 6 1 5C9A8815 +P 950 2650 +F 0 "U1" H 1000 2750 30 0000 C CNN +F 1 "PORT" H 950 2650 30 0000 C CNN +F 2 "" H 950 2650 60 0000 C CNN +F 3 "" H 950 2650 60 0000 C CNN + 6 950 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1200 2650 1200 2750 +$Comp +L PORT U1 +U 7 1 5C9A8B82 +P 950 2850 +F 0 "U1" H 1000 2950 30 0000 C CNN +F 1 "PORT" H 950 2850 30 0000 C CNN +F 2 "" H 950 2850 60 0000 C CNN +F 3 "" H 950 2850 60 0000 C CNN + 7 950 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C9A8C46 +P 950 3900 +F 0 "U1" H 1000 4000 30 0000 C CNN +F 1 "PORT" H 950 3900 30 0000 C CNN +F 2 "" H 950 3900 60 0000 C CNN +F 3 "" H 950 3900 60 0000 C CNN + 8 950 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C9A8D2C +P 950 4100 +F 0 "U1" H 1000 4200 30 0000 C CNN +F 1 "PORT" H 950 4100 30 0000 C CNN +F 2 "" H 950 4100 60 0000 C CNN +F 3 "" H 950 4100 60 0000 C CNN + 9 950 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C9A8DBD +P 1000 5100 +F 0 "U1" H 1050 5200 30 0000 C CNN +F 1 "PORT" H 1000 5100 30 0000 C CNN +F 2 "" H 1000 5100 60 0000 C CNN +F 3 "" H 1000 5100 60 0000 C CNN + 10 1000 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C9A8E65 +P 1000 5300 +F 0 "U1" H 1050 5400 30 0000 C CNN +F 1 "PORT" H 1000 5300 30 0000 C CNN +F 2 "" H 1000 5300 60 0000 C CNN +F 3 "" H 1000 5300 60 0000 C CNN + 11 1000 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A8EEE +P 800 3150 +F 0 "U1" H 850 3250 30 0000 C CNN +F 1 "PORT" H 800 3150 30 0000 C CNN +F 2 "" H 800 3150 60 0000 C CNN +F 3 "" H 800 3150 60 0000 C CNN + 1 800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A8F9C +P 800 3400 +F 0 "U1" H 850 3500 30 0000 C CNN +F 1 "PORT" H 800 3400 30 0000 C CNN +F 2 "" H 800 3400 60 0000 C CNN +F 3 "" H 800 3400 60 0000 C CNN + 2 800 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A9031 +P 800 3600 +F 0 "U1" H 850 3700 30 0000 C CNN +F 1 "PORT" H 800 3600 30 0000 C CNN +F 2 "" H 800 3600 60 0000 C CNN +F 3 "" H 800 3600 60 0000 C CNN + 3 800 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 3250 1050 3150 +Wire Wire Line + 1050 3550 1050 3600 +Wire Wire Line + 1350 4000 1350 4100 +Wire Wire Line + 1350 4100 1200 4100 +Wire Wire Line + 9550 2050 9850 2050 +Wire Wire Line + 9400 3950 9850 3950 +Wire Wire Line + 9350 5450 9900 5450 +$Comp +L PORT U1 +U 12 1 5C9A9B26 +P 10100 2050 +F 0 "U1" H 10150 2150 30 0000 C CNN +F 1 "PORT" H 10100 2050 30 0000 C CNN +F 2 "" H 10100 2050 60 0000 C CNN +F 3 "" H 10100 2050 60 0000 C CNN + 12 10100 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C9A9BCA +P 10100 3950 +F 0 "U1" H 10150 4050 30 0000 C CNN +F 1 "PORT" H 10100 3950 30 0000 C CNN +F 2 "" H 10100 3950 60 0000 C CNN +F 3 "" H 10100 3950 60 0000 C CNN + 13 10100 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C9A9CA0 +P 10150 5450 +F 0 "U1" H 10200 5550 30 0000 C CNN +F 1 "PORT" H 10150 5450 30 0000 C CNN +F 2 "" H 10150 5450 60 0000 C CNN +F 3 "" H 10150 5450 60 0000 C CNN + 14 10150 5450 + -1 0 0 1 +$EndComp +Text Notes 9650 2000 0 60 ~ 12 +A>B +Text Notes 9600 3900 0 60 ~ 12 +A=B\n +Text Notes 9600 5400 0 60 ~ 12 +A<B\n +Text Notes 1250 5100 0 60 ~ 12 +A0 +Text Notes 1200 5400 0 60 ~ 12 +B0 +Text Notes 1300 3900 2 60 ~ 12 +A1 +Text Notes 1300 4200 2 60 ~ 12 +B1 +Text Notes 1250 3250 2 60 ~ 12 +A<B +Text Notes 1250 3400 2 60 ~ 12 +A=B +Text Notes 1250 3550 2 60 ~ 12 +A>B +Text Notes 1350 2750 2 60 ~ 12 +A2 +Text Notes 1350 2950 2 60 ~ 12 +B2 +Text Notes 1300 1350 2 60 ~ 12 +A3 +Text Notes 1300 1550 2 60 ~ 12 +B3 +Wire Wire Line + 8200 5600 7450 5600 +Wire Wire Line + 7450 5600 7450 6050 +Wire Wire Line + 7450 6050 6900 6050 +Wire Wire Line + 6800 6650 6800 6300 +Wire Wire Line + 6800 6300 6900 6300 +Wire Wire Line + 6900 6300 6900 6050 +Wire Notes Line + 500 3000 1350 3000 +Wire Notes Line + 1350 3000 1350 3750 +Wire Notes Line + 1350 3750 500 3750 +Wire Notes Line + 500 3750 500 3000 +Text Notes 600 3000 3 60 ~ 12 +Cascading Inputs +Wire Notes Line + 9500 1550 9500 6050 +Wire Notes Line + 9500 6050 10550 6050 +Wire Notes Line + 10550 6050 10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +Wire Wire Line + 2600 3400 2050 3400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/7485.sub b/library/SubcircuitLibrary/7485/7485.sub new file mode 100644 index 00000000..5a45c57c --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485.sub @@ -0,0 +1,95 @@ +* Subcircuit 7485 +.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +.include c_gate.sub +* u6 net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u19 net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and +x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and +x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and +x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and +* u18 net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and +x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and +x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and +x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and +x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and +x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and +* u8 net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate +a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7 +a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9 +a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 7485
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/7485_Previous_Values.xml b/library/SubcircuitLibrary/7485/7485_Previous_Values.xml new file mode 100644 index 00000000..6d8f93b6 --- /dev/null +++ b/library/SubcircuitLibrary/7485/7485_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u6 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nand<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u7 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u7><u14 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u14><u19 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u19><u18 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u3 name="type">d_nand<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u3><u9 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u9><u15 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u12 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_nand<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u13><u17 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u10 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u10><u4 name="type">d_nand<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u4><u11 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u11><u16 name="type">d_nor<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x1><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x9><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x10><x11><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x11><x12><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x12><x13><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x13><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
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8050 5200 6950 5200 +Wire Wire Line + 8200 5400 7250 5400 +Wire Wire Line + 7250 5400 7250 5750 +Wire Wire Line + 7250 5750 6950 5750 +Wire Wire Line + 6850 6250 6850 5850 +Wire Wire Line + 6850 5850 7350 5850 +Wire Wire Line + 7350 5850 7350 5500 +Wire Wire Line + 7350 5500 8200 5500 +Wire Wire Line + 6800 6950 6950 6950 +Wire Wire Line + 6950 6950 6950 6200 +Wire Wire Line + 6950 6200 7950 6200 +Wire Wire Line + 7950 6200 7950 5700 +Wire Wire Line + 7950 5700 8200 5700 +$Comp +L PORT U1 +U 4 1 5C9A8539 +P 850 1350 +F 0 "U1" H 900 1450 30 0000 C CNN +F 1 "PORT" H 850 1350 30 0000 C CNN +F 2 "" H 850 1350 60 0000 C CNN +F 3 "" H 850 1350 60 0000 C CNN + 4 850 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A8668 +P 850 1550 +F 0 "U1" H 900 1650 30 0000 C CNN +F 1 "PORT" H 850 1550 30 0000 C CNN +F 2 "" H 850 1550 60 0000 C CNN +F 3 "" H 850 1550 60 0000 C CNN + 5 850 1550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1100 1550 1100 1450 +$Comp +L PORT U1 +U 6 1 5C9A8815 +P 950 2650 +F 0 "U1" H 1000 2750 30 0000 C CNN +F 1 "PORT" H 950 2650 30 0000 C CNN +F 2 "" H 950 2650 60 0000 C CNN +F 3 "" H 950 2650 60 0000 C CNN + 6 950 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1200 2650 1200 2750 +$Comp +L PORT U1 +U 7 1 5C9A8B82 +P 950 2850 +F 0 "U1" H 1000 2950 30 0000 C CNN +F 1 "PORT" H 950 2850 30 0000 C CNN +F 2 "" H 950 2850 60 0000 C CNN +F 3 "" H 950 2850 60 0000 C CNN + 7 950 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C9A8C46 +P 950 3900 +F 0 "U1" H 1000 4000 30 0000 C CNN +F 1 "PORT" H 950 3900 30 0000 C CNN +F 2 "" H 950 3900 60 0000 C CNN +F 3 "" H 950 3900 60 0000 C CNN + 8 950 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C9A8D2C +P 950 4100 +F 0 "U1" H 1000 4200 30 0000 C CNN +F 1 "PORT" H 950 4100 30 0000 C CNN +F 2 "" H 950 4100 60 0000 C CNN +F 3 "" H 950 4100 60 0000 C CNN + 9 950 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C9A8DBD +P 1000 5100 +F 0 "U1" H 1050 5200 30 0000 C CNN +F 1 "PORT" H 1000 5100 30 0000 C CNN +F 2 "" H 1000 5100 60 0000 C CNN +F 3 "" H 1000 5100 60 0000 C CNN + 10 1000 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C9A8E65 +P 1000 5300 +F 0 "U1" H 1050 5400 30 0000 C CNN +F 1 "PORT" H 1000 5300 30 0000 C CNN +F 2 "" H 1000 5300 60 0000 C CNN +F 3 "" H 1000 5300 60 0000 C CNN + 11 1000 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A8EEE +P 800 3150 +F 0 "U1" H 850 3250 30 0000 C CNN +F 1 "PORT" H 800 3150 30 0000 C CNN +F 2 "" H 800 3150 60 0000 C CNN +F 3 "" H 800 3150 60 0000 C CNN + 1 800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A8F9C +P 800 3400 +F 0 "U1" H 850 3500 30 0000 C CNN +F 1 "PORT" H 800 3400 30 0000 C CNN +F 2 "" H 800 3400 60 0000 C CNN +F 3 "" H 800 3400 60 0000 C CNN + 2 800 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A9031 +P 800 3600 +F 0 "U1" H 850 3700 30 0000 C CNN +F 1 "PORT" H 800 3600 30 0000 C CNN +F 2 "" H 800 3600 60 0000 C CNN +F 3 "" H 800 3600 60 0000 C CNN + 3 800 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 3250 1050 3150 +Wire Wire Line + 1050 3550 1050 3600 +Wire Wire Line + 1350 4000 1350 4100 +Wire Wire Line + 1350 4100 1200 4100 +Wire Wire Line + 9550 2050 9850 2050 +Wire Wire Line + 9400 3950 9850 3950 +Wire Wire Line + 9350 5450 9900 5450 +$Comp +L PORT U1 +U 12 1 5C9A9B26 +P 10100 2050 +F 0 "U1" H 10150 2150 30 0000 C CNN +F 1 "PORT" H 10100 2050 30 0000 C CNN +F 2 "" H 10100 2050 60 0000 C CNN +F 3 "" H 10100 2050 60 0000 C CNN + 12 10100 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C9A9BCA +P 10100 3950 +F 0 "U1" H 10150 4050 30 0000 C CNN +F 1 "PORT" H 10100 3950 30 0000 C CNN +F 2 "" H 10100 3950 60 0000 C CNN +F 3 "" H 10100 3950 60 0000 C CNN + 13 10100 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C9A9CA0 +P 10150 5450 +F 0 "U1" H 10200 5550 30 0000 C CNN +F 1 "PORT" H 10150 5450 30 0000 C CNN +F 2 "" H 10150 5450 60 0000 C CNN +F 3 "" H 10150 5450 60 0000 C CNN + 14 10150 5450 + -1 0 0 1 +$EndComp +Text Notes 9650 2000 0 60 ~ 12 +A>B +Text Notes 9600 3900 0 60 ~ 12 +A=B\n +Text Notes 9600 5400 0 60 ~ 12 +A<B\n +Text Notes 1250 5100 0 60 ~ 12 +A0 +Text Notes 1200 5400 0 60 ~ 12 +B0 +Text Notes 1300 3900 2 60 ~ 12 +A1 +Text Notes 1300 4200 2 60 ~ 12 +B1 +Text Notes 1250 3250 2 60 ~ 12 +A<B +Text Notes 1250 3400 2 60 ~ 12 +A=B +Text Notes 1250 3550 2 60 ~ 12 +A>B +Text Notes 1350 2750 2 60 ~ 12 +A2 +Text Notes 1350 2950 2 60 ~ 12 +B2 +Text Notes 1300 1350 2 60 ~ 12 +A3 +Text Notes 1300 1550 2 60 ~ 12 +B3 +Wire Wire Line + 8200 5600 7450 5600 +Wire Wire Line + 7450 5600 7450 6050 +Wire Wire Line + 7450 6050 6900 6050 +Wire Wire Line + 6800 6650 6800 6300 +Wire Wire Line + 6800 6300 6900 6300 +Wire Wire Line + 6900 6300 6900 6050 +Wire Notes Line + 500 3000 1350 3000 +Wire Notes Line + 1350 3000 1350 3750 +Wire Notes Line + 1350 3750 500 3750 +Wire Notes Line + 500 3750 500 3000 +Text Notes 600 3000 3 60 ~ 12 +Cascading Inputs +Wire Notes Line + 9500 1550 9500 6050 +Wire Notes Line + 9500 6050 10550 6050 +Wire Notes Line + 10550 6050 10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/analysis b/library/SubcircuitLibrary/7485/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/7485/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/c_gate-cache.lib b/library/SubcircuitLibrary/7485/c_gate-cache.lib new file mode 100644 index 00000000..05fb44d7 --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/7485/c_gate.cir b/library/SubcircuitLibrary/7485/c_gate.cir new file mode 100644 index 00000000..1ac12515 --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and +U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT + +.end diff --git a/library/SubcircuitLibrary/7485/c_gate.cir.out b/library/SubcircuitLibrary/7485/c_gate.cir.out new file mode 100644 index 00000000..db7bb2f8 --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate.cir.out @@ -0,0 +1,42 @@ +* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir + +.include 5_and.sub +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/7485/c_gate.pro b/library/SubcircuitLibrary/7485/c_gate.pro new file mode 100644 index 00000000..f0743529 --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate.pro @@ -0,0 +1,57 @@ +update=03/26/19 19:06:59 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/7485/c_gate.sch b/library/SubcircuitLibrary/7485/c_gate.sch new file mode 100644 index 00000000..5d960c8d --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate.sch @@ -0,0 +1,246 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:c_gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5C9A2B0B +P 3300 3750 +F 0 "X1" H 4650 4550 60 0000 C CNN +F 1 "5_and" H 4700 4800 60 0000 C CNN +F 2 "" H 3300 3750 60 0000 C CNN +F 3 "" H 3300 3750 60 0000 C CNN + 1 3300 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C9A2B3E +P 5600 3300 +F 0 "U8" H 5600 3300 60 0000 C CNN +F 1 "d_and" H 5650 3400 60 0000 C CNN +F 2 "" H 5600 3300 60 0000 C CNN +F 3 "" H 5600 3300 60 0000 C CNN + 1 5600 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3200 5150 2850 +Wire Wire Line + 4150 2650 4150 2350 +Wire Wire Line + 4150 2350 3600 2350 +Wire Wire Line + 4150 2750 4050 2750 +Wire Wire Line + 4050 2750 4050 2550 +Wire Wire Line + 4050 2550 3600 2550 +Wire Wire Line + 4150 2850 3700 2850 +Wire Wire Line + 3700 2850 3700 2750 +Wire Wire Line + 3700 2750 3600 2750 +Wire Wire Line + 4150 2950 3600 2950 +Wire Wire Line + 4150 3050 4150 3150 +Wire Wire Line + 4150 3150 3600 3150 +Wire Wire Line + 5150 3300 3600 3300 +$Comp +L d_inverter U2 +U 1 1 5C9A2CDC +P 3300 2350 +F 0 "U2" H 3300 2250 60 0000 C CNN +F 1 "d_inverter" H 3300 2500 60 0000 C CNN +F 2 "" H 3350 2300 60 0000 C CNN +F 3 "" H 3350 2300 60 0000 C CNN + 1 3300 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C9A2D06 +P 3300 2550 +F 0 "U3" H 3300 2450 60 0000 C CNN +F 1 "d_inverter" H 3300 2700 60 0000 C CNN +F 2 "" H 3350 2500 60 0000 C CNN +F 3 "" H 3350 2500 60 0000 C CNN + 1 3300 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5C9A2D26 +P 3300 2750 +F 0 "U4" H 3300 2650 60 0000 C CNN +F 1 "d_inverter" H 3300 2900 60 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3300 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5C9A2D49 +P 3300 2950 +F 0 "U5" H 3300 2850 60 0000 C CNN +F 1 "d_inverter" H 3300 3100 60 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 1 3300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5C9A2D73 +P 3300 3150 +F 0 "U6" H 3300 3050 60 0000 C CNN +F 1 "d_inverter" H 3300 3300 60 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 1 3300 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5C9A2D9E +P 3300 3300 +F 0 "U7" H 3300 3200 60 0000 C CNN +F 1 "d_inverter" H 3300 3450 60 0000 C CNN +F 2 "" H 3350 3250 60 0000 C CNN +F 3 "" H 3350 3250 60 0000 C CNN + 1 3300 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2350 2000 2350 +Wire Wire Line + 3000 2550 2000 2550 +Wire Wire Line + 3000 2750 2050 2750 +Wire Wire Line + 3000 2950 2050 2950 +Wire Wire Line + 3000 3150 2050 3150 +Wire Wire Line + 3000 3300 2050 3300 +Wire Wire Line + 6050 3250 6950 3250 +$Comp +L PORT U1 +U 1 1 5C9A2F6F +P 1750 2350 +F 0 "U1" H 1800 2450 30 0000 C CNN +F 1 "PORT" H 1750 2350 30 0000 C CNN +F 2 "" H 1750 2350 60 0000 C CNN +F 3 "" H 1750 2350 60 0000 C CNN + 1 1750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A2FAB +P 1750 2550 +F 0 "U1" H 1800 2650 30 0000 C CNN +F 1 "PORT" H 1750 2550 30 0000 C CNN +F 2 "" H 1750 2550 60 0000 C CNN +F 3 "" H 1750 2550 60 0000 C CNN + 2 1750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2FDD +P 1800 2750 +F 0 "U1" H 1850 2850 30 0000 C CNN +F 1 "PORT" H 1800 2750 30 0000 C CNN +F 2 "" H 1800 2750 60 0000 C CNN +F 3 "" H 1800 2750 60 0000 C CNN + 3 1800 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A301A +P 1800 2950 +F 0 "U1" H 1850 3050 30 0000 C CNN +F 1 "PORT" H 1800 2950 30 0000 C CNN +F 2 "" H 1800 2950 60 0000 C CNN +F 3 "" H 1800 2950 60 0000 C CNN + 4 1800 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A3052 +P 1800 3150 +F 0 "U1" H 1850 3250 30 0000 C CNN +F 1 "PORT" H 1800 3150 30 0000 C CNN +F 2 "" H 1800 3150 60 0000 C CNN +F 3 "" H 1800 3150 60 0000 C CNN + 5 1800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A308D +P 1800 3300 +F 0 "U1" H 1850 3400 30 0000 C CNN +F 1 "PORT" H 1800 3300 30 0000 C CNN +F 2 "" H 1800 3300 60 0000 C CNN +F 3 "" H 1800 3300 60 0000 C CNN + 6 1800 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C9A30DD +P 7200 3250 +F 0 "U1" H 7250 3350 30 0000 C CNN +F 1 "PORT" H 7200 3250 30 0000 C CNN +F 2 "" H 7200 3250 60 0000 C CNN +F 3 "" H 7200 3250 60 0000 C CNN + 7 7200 3250 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/7485/c_gate.sub b/library/SubcircuitLibrary/7485/c_gate.sub new file mode 100644 index 00000000..c6eaa478 --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate.sub @@ -0,0 +1,36 @@ +* Subcircuit c_gate +.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ +* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir +.include 5_and.sub +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends c_gate
\ No newline at end of file diff --git a/library/SubcircuitLibrary/7485/c_gate_Previous_Values.xml b/library/SubcircuitLibrary/7485/c_gate_Previous_Values.xml new file mode 100644 index 00000000..e51d62de --- /dev/null +++ b/library/SubcircuitLibrary/7485/c_gate_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib b/library/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib new file mode 100644 index 00000000..cc25b0c9 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir b/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out b/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out new file mode 100644 index 00000000..cb2b6641 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out @@ -0,0 +1,18 @@ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u1 net-_m1-pad2_ net-_c1-pad1_ port +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +.tran 0e-03 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS.pro b/library/SubcircuitLibrary/INVCMOS/INVCMOS.pro new file mode 100644 index 00000000..b3f410b6 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS.pro @@ -0,0 +1,73 @@ +update=Sun Aug 25 15:54:56 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User +LibName37=eSim_Plot +LibName38=eSim_PSpice +LibName39=/home/saurabh/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS.sch b/library/SubcircuitLibrary/INVCMOS/INVCMOS.sch new file mode 100644 index 00000000..13a7fc09 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:INVCMOS-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 4000 5900 4150 +Connection ~ 5800 2450 +Connection ~ 5800 4150 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5050 3350 +Wire Wire Line + 4000 3350 5050 3350 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 4200 3350 +$Comp +L PORT U1 +U 1 1 5D6263BC +P 3750 3350 +F 0 "U1" H 3800 3450 30 0000 C CNN +F 1 "PORT" H 3750 3350 30 0000 C CNN +F 2 "" H 3750 3350 60 0000 C CNN +F 3 "" H 3750 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3250 5800 3250 +Connection ~ 5800 3250 +Wire Wire Line + 5800 4050 5800 4550 +$Comp +L eSim_MOS_N M1 +U 1 1 5D6265DB +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 5D626659 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2850 6050 2850 +Wire Wire Line + 6050 2850 6050 2450 +Wire Wire Line + 6050 2450 5800 2450 +Connection ~ 6000 3250 +Connection ~ 5800 4300 +$Comp +L GND #PWR1 +U 1 1 5D626C59 +P 5800 4550 +F 0 "#PWR1" H 5800 4300 50 0001 C CNN +F 1 "GND" H 5800 4400 50 0000 C CNN +F 2 "" H 5800 4550 50 0001 C CNN +F 3 "" H 5800 4550 50 0001 C CNN + 1 5800 4550 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5D626C7F +P 6250 2300 +F 0 "v1" H 6050 2400 60 0000 C CNN +F 1 "5" H 6050 2250 60 0000 C CNN +F 2 "R1" H 5950 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 1 6250 2300 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR2 +U 1 1 5D626CF6 +P 6850 2300 +F 0 "#PWR2" H 6850 2050 50 0001 C CNN +F 1 "GND" H 6850 2150 50 0000 C CNN +F 2 "" H 6850 2300 50 0001 C CNN +F 3 "" H 6850 2300 50 0001 C CNN + 1 6850 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 2300 6700 2300 +$Comp +L PORT U1 +U 2 1 5D626DCB +P 6300 3250 +F 0 "U1" H 6350 3350 30 0000 C CNN +F 1 "PORT" H 6300 3250 30 0000 C CNN +F 2 "" H 6300 3250 60 0000 C CNN +F 3 "" H 6300 3250 60 0000 C CNN + 2 6300 3250 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D62796C +P 6050 3850 +F 0 "C1" H 6075 3950 50 0000 L CNN +F 1 "1u" H 6075 3750 50 0000 L CNN +F 2 "" H 6088 3700 30 0000 C CNN +F 3 "" H 6050 3850 60 0000 C CNN + 1 6050 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3700 6050 3400 +Wire Wire Line + 6050 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 3250 +Wire Wire Line + 6050 4000 6050 4300 +Wire Wire Line + 6050 4300 5800 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS.sub b/library/SubcircuitLibrary/INVCMOS/INVCMOS.sub new file mode 100644 index 00000000..2319995c --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS.sub @@ -0,0 +1,12 @@ +* Subcircuit INVCMOS +.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +* Control Statements + +.ends INVCMOS
\ No newline at end of file diff --git a/library/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml b/library/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml new file mode 100644 index 00000000..e5bb98c7 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib b/library/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib b/library/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/INVCMOS/analysis b/library/SubcircuitLibrary/INVCMOS/analysis new file mode 100644 index 00000000..334c5333 --- /dev/null +++ b/library/SubcircuitLibrary/INVCMOS/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM7812/LM7812-cache.lib b/library/SubcircuitLibrary/LM7812/LM7812-cache.lib new file mode 100644 index 00000000..c02b3211 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812-cache.lib @@ -0,0 +1,135 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN-RESCUE-LM7812 +# +DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-LM7812 +# +DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM7812/LM7812-rescue.lib b/library/SubcircuitLibrary/LM7812/LM7812-rescue.lib new file mode 100644 index 00000000..e6cfa7d6 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812-rescue.lib @@ -0,0 +1,42 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# eSim_NPN-RESCUE-LM7812 +# +DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-LM7812 +# +DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM7812/LM7812.cir b/library/SubcircuitLibrary/LM7812/LM7812.cir new file mode 100644 index 00000000..3f0d3adf --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812.cir @@ -0,0 +1,51 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM7812/LM7812.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 10 16:26:28 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k +R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 +R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k +R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k +U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R5 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500 +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN +R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R7 Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k +Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R10 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k +Q7 Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R12 Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k +R9 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k +Q5 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP +R8 Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100 +R11 Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50 +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN +R13 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +R14 Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k +Q14 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN +R17 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k +R16 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 10.38k +R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k +U2 Net-_Q15-Pad2_ Net-_R15-Pad2_ zener +Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN +R18 Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200 +R20 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3 +R19 Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240 +U3 Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM7812/LM7812.cir.out b/library/SubcircuitLibrary/LM7812/LM7812.cir.out new file mode 100644 index 00000000..73404965 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812.cir.out @@ -0,0 +1,60 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir + +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 10.38k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +* u3 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM7812/LM7812.pro b/library/SubcircuitLibrary/LM7812/LM7812.pro new file mode 100644 index 00000000..12d08139 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812.pro @@ -0,0 +1,46 @@ +update=Mon Aug 26 14:09:03 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=LM7812-rescue +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User + diff --git a/library/SubcircuitLibrary/LM7812/LM7812.sch b/library/SubcircuitLibrary/LM7812/LM7812.sch new file mode 100644 index 00000000..ca95c2ca --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812.sch @@ -0,0 +1,758 @@ +EESchema Schematic File Version 2 +LIBS:LM7812-rescue +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:LM7812-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 5CE41429 +P 1250 1600 +F 0 "R1" V 1330 1600 50 0000 C CNN +F 1 "100k" V 1250 1600 50 0000 C CNN +F 2 "" V 1180 1600 50 0001 C CNN +F 3 "" H 1250 1600 50 0001 C CNN + 1 1250 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5CE4148B +P 1950 1600 +F 0 "R2" V 2030 1600 50 0000 C CNN +F 1 "500" V 1950 1600 50 0000 C CNN +F 2 "" V 1880 1600 50 0001 C CNN +F 3 "" H 1950 1600 50 0001 C CNN + 1 1950 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5CE414A5 +P 1950 3050 +F 0 "R3" V 2030 3050 50 0000 C CNN +F 1 "3.3k" V 1950 3050 50 0000 C CNN +F 2 "" V 1880 3050 50 0001 C CNN +F 3 "" H 1950 3050 50 0001 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5CE414CA +P 1950 3750 +F 0 "R4" V 2030 3750 50 0000 C CNN +F 1 "2.7k" V 1950 3750 50 0000 C CNN +F 2 "" V 1880 3750 50 0001 C CNN +F 3 "" H 1950 3750 50 0001 C CNN + 1 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 5CE414FA +P 1250 3350 +F 0 "U1" H 1200 3250 60 0000 C CNN +F 1 "zener" H 1250 3450 60 0000 C CNN +F 2 "" H 1300 3350 60 0000 C CNN +F 3 "" H 1300 3350 60 0000 C CNN + 1 1250 3350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q1 +U 1 1 5CE41586 +P 1850 2350 +F 0 "Q1" H 1750 2400 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN +F 2 "" H 2050 2450 29 0000 C CNN +F 3 "" H 1850 2350 60 0000 C CNN + 1 1850 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5CE418C5 +P 1950 4600 +F 0 "R5" V 2030 4600 50 0000 C CNN +F 1 "500" V 1950 4600 50 0000 C CNN +F 2 "" V 1880 4600 50 0001 C CNN +F 3 "" H 1950 4600 50 0001 C CNN + 1 1950 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 1750 1250 3050 +Wire Wire Line + 1250 1450 1250 1300 +Wire Wire Line + 1250 1300 1950 1300 +Wire Wire Line + 1950 1300 1950 1450 +Wire Wire Line + 1950 2150 1950 1750 +Wire Wire Line + 1950 2550 1950 2900 +Wire Wire Line + 1950 3200 1950 3600 +Wire Wire Line + 1950 3900 1950 4450 +Wire Wire Line + 1250 3550 1250 5200 +Wire Wire Line + 1250 5200 3200 5200 +Wire Wire Line + 1950 5200 1950 4750 +Wire Wire Line + 1650 2350 1250 2350 +Connection ~ 1250 2350 +$Comp +L eSim_NPN-RESCUE-LM7812 Q2 +U 1 1 5CE41D6C +P 2650 3350 +F 0 "Q2" H 2550 3400 50 0000 R CNN +F 1 "eSim_NPN" H 2600 3500 50 0000 R CNN +F 2 "" H 2850 3450 29 0000 C CNN +F 3 "" H 2650 3350 60 0000 C CNN + 1 2650 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q4 +U 1 1 5CE41E26 +P 3100 4100 +F 0 "Q4" H 3000 4150 50 0000 R CNN +F 1 "eSim_NPN" H 3050 4250 50 0000 R CNN +F 2 "" H 3300 4200 29 0000 C CNN +F 3 "" H 3100 4100 60 0000 C CNN + 1 3100 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 5CE41EA8 +P 2750 3850 +F 0 "R6" V 2830 3850 50 0000 C CNN +F 1 "1k" V 2750 3850 50 0000 C CNN +F 2 "" V 2680 3850 50 0001 C CNN +F 3 "" H 2750 3850 50 0001 C CNN + 1 2750 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q3 +U 1 1 5CE41EFE +P 2850 4650 +F 0 "Q3" H 2750 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN +F 2 "" H 3050 4750 29 0000 C CNN +F 3 "" H 2850 4650 60 0000 C CNN + 1 2850 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3550 2750 3700 +Wire Wire Line + 2750 4000 2750 4450 +Wire Wire Line + 2900 4100 2750 4100 +Connection ~ 2750 4100 +Wire Wire Line + 3200 4300 3200 4750 +Wire Wire Line + 3050 4650 3450 4650 +Wire Wire Line + 2450 3350 1950 3350 +Connection ~ 1950 3350 +Wire Wire Line + 2750 3600 3600 3600 +Wire Wire Line + 3200 3600 3200 3900 +Connection ~ 2750 3600 +$Comp +L R R7 +U 1 1 5CE42281 +P 3200 4900 +F 0 "R7" V 3280 4900 50 0000 C CNN +F 1 "6k" V 3200 4900 50 0000 C CNN +F 2 "" V 3130 4900 50 0001 C CNN +F 3 "" H 3200 4900 50 0001 C CNN + 1 3200 4900 + 1 0 0 -1 +$EndComp +Connection ~ 3200 4650 +Wire Wire Line + 3200 5050 3200 5250 +Connection ~ 1950 5200 +Wire Wire Line + 2750 4850 2750 5200 +Connection ~ 2750 5200 +$Comp +L eSim_NPN-RESCUE-LM7812 Q6 +U 1 1 5CE424FB +P 3650 4650 +F 0 "Q6" H 3550 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3600 4800 50 0000 R CNN +F 2 "" H 3850 4750 29 0000 C CNN +F 3 "" H 3650 4650 60 0000 C CNN + 1 3650 4650 + 1 0 0 -1 +$EndComp +$Comp +L R R10 +U 1 1 5CE42584 +P 3750 5100 +F 0 "R10" V 3830 5100 50 0000 C CNN +F 1 "1k" V 3750 5100 50 0000 C CNN +F 2 "" V 3680 5100 50 0001 C CNN +F 3 "" H 3750 5100 50 0001 C CNN + 1 3750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4850 3750 4950 +Wire Wire Line + 3200 5250 3750 5250 +Connection ~ 3200 5200 +$Comp +L eSim_NPN-RESCUE-LM7812 Q7 +U 1 1 5CE427DA +P 3700 2750 +F 0 "Q7" H 3600 2800 50 0000 R CNN +F 1 "eSim_NPN" H 3650 2900 50 0000 R CNN +F 2 "" H 3900 2850 29 0000 C CNN +F 3 "" H 3700 2750 60 0000 C CNN + 1 3700 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q8 +U 1 1 5CE428D0 +P 3700 3400 +F 0 "Q8" H 3600 3450 50 0000 R CNN +F 1 "eSim_NPN" H 3650 3550 50 0000 R CNN +F 2 "" H 3900 3500 29 0000 C CNN +F 3 "" H 3700 3400 60 0000 C CNN + 1 3700 3400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q12 +U 1 1 5CE4293A +P 4350 3000 +F 0 "Q12" H 4250 3050 50 0000 R CNN +F 1 "eSim_NPN" H 4300 3150 50 0000 R CNN +F 2 "" H 4550 3100 29 0000 C CNN +F 3 "" H 4350 3000 60 0000 C CNN + 1 4350 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2950 3600 3200 +Wire Wire Line + 4250 3200 4250 3400 +Wire Wire Line + 4250 3400 3900 3400 +Wire Wire Line + 4250 2750 4250 2800 +Wire Wire Line + 3900 2750 4250 2750 +Connection ~ 3200 3600 +$Comp +L R R12 +U 1 1 5CE42C4F +P 4350 3450 +F 0 "R12" V 4430 3450 50 0000 C CNN +F 1 "6k" V 4350 3450 50 0000 C CNN +F 2 "" V 4280 3450 50 0001 C CNN +F 3 "" H 4350 3450 50 0001 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 3300 4250 3300 +Connection ~ 4250 3300 +Wire Wire Line + 3700 3600 4350 3600 +Wire Wire Line + 3700 3600 3700 3650 +Wire Wire Line + 3700 3650 3550 3650 +Wire Wire Line + 3550 3650 3550 3600 +Connection ~ 3550 3600 +$Comp +L R R9 +U 1 1 5CE42EA3 +P 3750 3950 +F 0 "R9" V 3830 3950 50 0000 C CNN +F 1 "20k" V 3750 3950 50 0000 C CNN +F 2 "" V 3680 3950 50 0001 C CNN +F 3 "" H 3750 3950 50 0001 C CNN + 1 3750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4100 3750 4450 +Wire Wire Line + 3750 3800 3750 3600 +Connection ~ 3750 3600 +Wire Wire Line + 2750 3150 2750 2450 +Wire Wire Line + 2750 2450 3600 2450 +Wire Wire Line + 3600 2450 3600 2550 +$Comp +L eSim_PNP-RESCUE-LM7812 Q5 +U 1 1 5CE43397 +P 3450 1700 +F 0 "Q5" H 3350 1750 50 0000 R CNN +F 1 "eSim_PNP" H 3400 1850 50 0000 R CNN +F 2 "" H 3650 1800 29 0000 C CNN +F 3 "" H 3450 1700 60 0000 C CNN + 1 3450 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP-RESCUE-LM7812 Q9 +U 1 1 5CE4353C +P 4100 1700 +F 0 "Q9" H 4000 1750 50 0000 R CNN +F 1 "eSim_PNP" H 4050 1850 50 0000 R CNN +F 2 "" H 4300 1800 29 0000 C CNN +F 3 "" H 4100 1700 60 0000 C CNN + 1 4100 1700 + 1 0 0 1 +$EndComp +$Comp +L R R8 +U 1 1 5CE435B8 +P 3350 1250 +F 0 "R8" V 3430 1250 50 0000 C CNN +F 1 "100" V 3350 1250 50 0000 C CNN +F 2 "" V 3280 1250 50 0001 C CNN +F 3 "" H 3350 1250 50 0001 C CNN + 1 3350 1250 + 1 0 0 -1 +$EndComp +$Comp +L R R11 +U 1 1 5CE4368E +P 4200 1250 +F 0 "R11" V 4280 1250 50 0000 C CNN +F 1 "50" V 4200 1250 50 0000 C CNN +F 2 "" V 4130 1250 50 0001 C CNN +F 3 "" H 4200 1250 50 0001 C CNN + 1 4200 1250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q10 +U 1 1 5CE43705 +P 4100 2200 +F 0 "Q10" H 4000 2250 50 0000 R CNN +F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN +F 2 "" H 4300 2300 29 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 1400 3350 1500 +Wire Wire Line + 3650 1700 3900 1700 +Wire Wire Line + 4200 1400 4200 1500 +Wire Wire Line + 3350 1100 3350 1050 +Wire Wire Line + 1650 1050 7800 1050 +Wire Wire Line + 4200 1050 4200 1100 +Wire Wire Line + 4200 1900 4200 2000 +Wire Wire Line + 3750 1700 3750 2000 +Wire Wire Line + 3750 2000 3350 2000 +Wire Wire Line + 3350 1900 3350 2450 +Connection ~ 3750 1700 +Connection ~ 3350 2450 +Connection ~ 3350 2000 +Wire Wire Line + 2300 2200 3900 2200 +Wire Wire Line + 2300 2200 2300 4200 +Wire Wire Line + 2300 4200 1950 4200 +Connection ~ 1950 4200 +Wire Wire Line + 2200 2400 4200 2400 +Wire Wire Line + 2200 2400 2200 5200 +Connection ~ 2200 5200 +$Comp +L eSim_NPN-RESCUE-LM7812 Q11 +U 1 1 5CE4439E +P 4300 4400 +F 0 "Q11" H 4200 4450 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4550 50 0000 R CNN +F 2 "" H 4500 4500 29 0000 C CNN +F 3 "" H 4300 4400 60 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q13 +U 1 1 5CE44419 +P 4600 4800 +F 0 "Q13" H 4500 4850 50 0000 R CNN +F 1 "eSim_NPN" H 4550 4950 50 0000 R CNN +F 2 "" H 4800 4900 29 0000 C CNN +F 3 "" H 4600 4800 60 0000 C CNN + 1 4600 4800 + 1 0 0 -1 +$EndComp +$Comp +L R R13 +U 1 1 5CE444B9 +P 4400 5050 +F 0 "R13" V 4480 5050 50 0000 C CNN +F 1 "6k" V 4400 5050 50 0000 C CNN +F 2 "" V 4330 5050 50 0001 C CNN +F 3 "" H 4400 5050 50 0001 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE4451D +P 4050 4150 +F 0 "C1" H 4075 4250 50 0000 L CNN +F 1 "30p" H 4075 4050 50 0000 L CNN +F 2 "" H 4088 4000 30 0000 C CNN +F 3 "" H 4050 4150 60 0000 C CNN + 1 4050 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4100 4400 3750 4400 +Connection ~ 3750 4400 +Wire Wire Line + 3900 4150 3750 4150 +Connection ~ 3750 4150 +Wire Wire Line + 4700 4150 4200 4150 +Wire Wire Line + 4400 4150 4400 4200 +Wire Wire Line + 4400 4600 4400 4900 +Connection ~ 4400 4800 +Wire Wire Line + 4400 5200 4400 5300 +Wire Wire Line + 3650 5300 6400 5300 +Wire Wire Line + 3650 5300 3650 5250 +Connection ~ 3650 5250 +Wire Wire Line + 4700 5300 4700 5000 +Connection ~ 4400 5300 +Wire Wire Line + 4700 3800 4700 4600 +Connection ~ 4400 4150 +$Comp +L R R14 +U 1 1 5CE44FFF +P 4700 3650 +F 0 "R14" V 4780 3650 50 0000 C CNN +F 1 "6k" V 4700 3650 50 0000 C CNN +F 2 "" V 4630 3650 50 0001 C CNN +F 3 "" H 4700 3650 50 0001 C CNN + 1 4700 3650 + 1 0 0 -1 +$EndComp +Connection ~ 4700 4150 +$Comp +L eSim_PNP-RESCUE-LM7812 Q14 +U 1 1 5CE45652 +P 5050 3950 +F 0 "Q14" H 4950 4000 50 0000 R CNN +F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN +F 2 "" H 5250 4050 29 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5050 3950 + 1 0 0 1 +$EndComp +Wire Wire Line + 4850 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4700 3500 4700 3450 +Wire Wire Line + 4700 3450 5150 3450 +Wire Wire Line + 5150 3450 5150 3750 +Wire Wire Line + 5150 5300 5150 4150 +Connection ~ 4700 5300 +Wire Wire Line + 4750 3450 4750 1950 +Wire Wire Line + 4200 1950 5300 1950 +Connection ~ 4200 1950 +Connection ~ 4750 3450 +$Comp +L eSim_NPN-RESCUE-LM7812 Q15 +U 1 1 5CE463AD +P 5400 2150 +F 0 "Q15" H 5300 2200 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN +F 2 "" H 5600 2250 29 0000 C CNN +F 3 "" H 5400 2150 60 0000 C CNN + 1 5400 2150 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1950 +Wire Wire Line + 4150 2750 4150 2600 +Wire Wire Line + 4150 2600 6100 2600 +Wire Wire Line + 5300 2600 5300 2350 +Connection ~ 4150 2750 +$Comp +L R R17 +U 1 1 5CE46DDE +P 6050 4250 +F 0 "R17" V 6130 4250 50 0000 C CNN +F 1 "5k" V 6050 4250 50 0000 C CNN +F 2 "" V 5980 4250 50 0001 C CNN +F 3 "" H 6050 4250 50 0001 C CNN + 1 6050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R16 +U 1 1 5CE46F8E +P 6050 3050 +F 0 "R16" V 6130 3050 50 0000 C CNN +F 1 "10.38k" V 6050 3050 50 0000 C CNN +F 2 "" V 5980 3050 50 0001 C CNN +F 3 "" H 6050 3050 50 0001 C CNN + 1 6050 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3200 6050 4100 +Wire Wire Line + 6050 5300 6050 4400 +Connection ~ 5150 5300 +Wire Wire Line + 6050 2600 6050 2900 +Connection ~ 5300 2600 +Wire Wire Line + 4550 3000 5100 3000 +Wire Wire Line + 5100 3000 5100 3250 +Wire Wire Line + 5100 3250 5350 3250 +Wire Wire Line + 5350 3250 5350 3600 +Wire Wire Line + 5350 3600 6050 3600 +Connection ~ 6050 3600 +Wire Wire Line + 1650 1050 1650 1300 +Connection ~ 1650 1300 +Connection ~ 3350 1050 +$Comp +L R R15 +U 1 1 5CE47F7A +P 5850 1300 +F 0 "R15" V 5930 1300 50 0000 C CNN +F 1 "10k" V 5850 1300 50 0000 C CNN +F 2 "" V 5780 1300 50 0001 C CNN +F 3 "" H 5850 1300 50 0001 C CNN + 1 5850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1050 5850 1150 +Connection ~ 4200 1050 +$Comp +L zener U2 +U 1 1 5CE48686 +P 5850 1900 +F 0 "U2" H 5800 1800 60 0000 C CNN +F 1 "zener" H 5850 2000 60 0000 C CNN +F 2 "" H 5900 1900 60 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 1450 5850 1600 +Wire Wire Line + 5850 2100 5850 2250 +Wire Wire Line + 5850 2150 5600 2150 +$Comp +L eSim_NPN-RESCUE-LM7812 Q16 +U 1 1 5CE4907A +P 6550 1600 +F 0 "Q16" H 6450 1650 50 0000 R CNN +F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN +F 2 "" H 6750 1700 29 0000 C CNN +F 3 "" H 6550 1600 60 0000 C CNN + 1 6550 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q17 +U 1 1 5CE4942E +P 7300 1950 +F 0 "Q17" H 7200 2000 50 0000 R CNN +F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN +F 2 "" H 7500 2050 29 0000 C CNN +F 3 "" H 7300 1950 60 0000 C CNN + 1 7300 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 1800 6650 2300 +Wire Wire Line + 6650 1950 7100 1950 +Wire Wire Line + 7400 1050 7400 1750 +Connection ~ 5850 1050 +Wire Wire Line + 6650 1400 6650 1050 +Connection ~ 6650 1050 +$Comp +L R R18 +U 1 1 5CE498BA +P 6650 2450 +F 0 "R18" V 6730 2450 50 0000 C CNN +F 1 "200" V 6650 2450 50 0000 C CNN +F 2 "" V 6580 2450 50 0001 C CNN +F 3 "" H 6650 2450 50 0001 C CNN + 1 6650 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R20 +U 1 1 5CE4999A +P 7400 2450 +F 0 "R20" V 7480 2450 50 0000 C CNN +F 1 "0.3" V 7400 2450 50 0000 C CNN +F 2 "" V 7330 2450 50 0001 C CNN +F 3 "" H 7400 2450 50 0001 C CNN + 1 7400 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R19 +U 1 1 5CE49AF5 +P 7000 2250 +F 0 "R19" V 7080 2250 50 0000 C CNN +F 1 "240" V 7000 2250 50 0000 C CNN +F 2 "" V 6930 2250 50 0001 C CNN +F 3 "" H 7000 2250 50 0001 C CNN + 1 7000 2250 + 0 1 1 0 +$EndComp +Connection ~ 6650 1950 +Wire Wire Line + 5850 2250 6850 2250 +Connection ~ 5850 2150 +Wire Wire Line + 7400 2150 7400 2300 +Wire Wire Line + 7150 2250 7400 2250 +Connection ~ 7400 2250 +Wire Wire Line + 6100 2600 6100 2650 +Wire Wire Line + 6100 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 2600 +Connection ~ 6050 2600 +Wire Wire Line + 6650 2600 6650 2650 +Connection ~ 6650 2650 +$Comp +L PORT U3 +U 1 1 5CE4AAF6 +P 8050 1050 +F 0 "U3" H 8100 1150 30 0000 C CNN +F 1 "PORT" H 8050 1050 30 0000 C CNN +F 2 "" H 8050 1050 60 0000 C CNN +F 3 "" H 8050 1050 60 0000 C CNN + 1 8050 1050 + -1 0 0 1 +$EndComp +Connection ~ 7400 1050 +$Comp +L PORT U3 +U 3 1 5CE4B13E +P 7700 3000 +F 0 "U3" H 7750 3100 30 0000 C CNN +F 1 "PORT" H 7700 3000 30 0000 C CNN +F 2 "" H 7700 3000 60 0000 C CNN +F 3 "" H 7700 3000 60 0000 C CNN + 3 7700 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 2 1 5CE4B701 +P 6650 5300 +F 0 "U3" H 6700 5400 30 0000 C CNN +F 1 "PORT" H 6650 5300 30 0000 C CNN +F 2 "" H 6650 5300 60 0000 C CNN +F 3 "" H 6650 5300 60 0000 C CNN + 2 6650 5300 + -1 0 0 1 +$EndComp +Connection ~ 6050 5300 +Wire Wire Line + 6350 1600 5950 1600 +Wire Wire Line + 5950 1600 5950 1550 +Wire Wire Line + 5950 1550 5000 1550 +Wire Wire Line + 5000 1550 5000 1950 +Connection ~ 5000 1950 +Wire Wire Line + 7300 2650 7300 3000 +Wire Wire Line + 7300 3000 7450 3000 +Connection ~ 7300 2650 +Connection ~ 2500 5200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM7812/LM7812.sub b/library/SubcircuitLibrary/LM7812/LM7812.sub new file mode 100644 index 00000000..0dd95154 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812.sub @@ -0,0 +1,54 @@ +* Subcircuit LM7812 +.subckt LM7812 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 10.38k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Control Statements + +.ends LM7812
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml b/library/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml new file mode 100644 index 00000000..263f360c --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM7812/NPN.lib b/library/SubcircuitLibrary/LM7812/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM7812/PNP.lib b/library/SubcircuitLibrary/LM7812/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM7812/Q_PNP.lib b/library/SubcircuitLibrary/LM7812/Q_PNP.lib new file mode 100644 index 00000000..154ed2d8 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/Q_PNP.lib @@ -0,0 +1 @@ +.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM7812/analysis b/library/SubcircuitLibrary/LM7812/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM7812/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_adder/analysis b/library/SubcircuitLibrary/full_adder/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_adder/full_adder-cache.lib b/library/SubcircuitLibrary/full_adder/full_adder-cache.lib new file mode 100644 index 00000000..623a7f41 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/full_adder/full_adder.cir b/library/SubcircuitLibrary/full_adder/full_adder.cir new file mode 100644 index 00000000..6461b5b6 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 8 7 6 2 half_adder +X2 5 6 4 3 half_adder +U1 8 7 5 4 1 PORT +U2 3 2 1 d_or + +.end diff --git a/library/SubcircuitLibrary/full_adder/full_adder.cir.out b/library/SubcircuitLibrary/full_adder/full_adder.cir.out new file mode 100644 index 00000000..b90ce70d --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 + +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u1 8 7 5 4 1 port +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/full_adder/full_adder.pro b/library/SubcircuitLibrary/full_adder/full_adder.pro new file mode 100644 index 00000000..c0db0775 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 12:19:16 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/library/SubcircuitLibrary/full_adder/full_adder.sch b/library/SubcircuitLibrary/full_adder/full_adder.sch new file mode 100644 index 00000000..8bd400f2 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.sch @@ -0,0 +1,180 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L half_adder X1 +U 1 1 558AA064 +P 3800 3350 +F 0 "X1" H 4700 3850 60 0000 C CNN +F 1 "half_adder" H 4700 3750 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L half_adder X2 +U 1 1 558AA0C1 +P 5700 3350 +F 0 "X2" H 6600 3850 60 0000 C CNN +F 1 "half_adder" H 6600 3750 60 0000 C CNN +F 2 "" H 5700 3350 60 0000 C CNN +F 3 "" H 5700 3350 60 0000 C CNN + 1 5700 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558AA277 +P 3450 2650 +F 0 "U1" H 3500 2750 30 0000 C CNN +F 1 "PORT" H 3450 2650 30 0000 C CNN +F 2 "" H 3450 2650 60 0000 C CNN +F 3 "" H 3450 2650 60 0000 C CNN + 1 3450 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558AA29E +P 3450 3250 +F 0 "U1" H 3500 3350 30 0000 C CNN +F 1 "PORT" H 3450 3250 30 0000 C CNN +F 2 "" H 3450 3250 60 0000 C CNN +F 3 "" H 3450 3250 60 0000 C CNN + 2 3450 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558AA2D8 +P 5650 2300 +F 0 "U1" H 5700 2400 30 0000 C CNN +F 1 "PORT" H 5650 2300 30 0000 C CNN +F 2 "" H 5650 2300 60 0000 C CNN +F 3 "" H 5650 2300 60 0000 C CNN + 3 5650 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 558AA378 +P 7900 2650 +F 0 "U1" H 7950 2750 30 0000 C CNN +F 1 "PORT" H 7900 2650 30 0000 C CNN +F 2 "" H 7900 2650 60 0000 C CNN +F 3 "" H 7900 2650 60 0000 C CNN + 4 7900 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 558AA3E0 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 5 8700 3400 + -1 0 0 1 +$EndComp +$Comp +L d_or U2 +U 1 1 558AA43B +P 7900 3450 +F 0 "U2" H 7900 3450 60 0000 C CNN +F 1 "d_or" H 7900 3550 60 0000 C CNN +F 2 "" H 7900 3450 60 0000 C CNN +F 3 "" H 7900 3450 60 0000 C CNN + 1 7900 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 2650 4100 2650 +Wire Wire Line + 3700 3250 4100 3250 +Wire Wire Line + 5250 2650 5650 2650 +Wire Wire Line + 5650 2650 5650 3250 +Wire Wire Line + 5650 3250 6000 3250 +Wire Wire Line + 5900 2300 5900 2650 +Wire Wire Line + 5900 2650 6000 2650 +Wire Wire Line + 7150 2650 7650 2650 +Wire Wire Line + 7150 3250 7350 3250 +Wire Wire Line + 7350 3250 7350 3350 +Wire Wire Line + 7350 3350 7450 3350 +Wire Wire Line + 5250 3250 5400 3250 +Wire Wire Line + 5400 3250 5400 3450 +Wire Wire Line + 5400 3450 7450 3450 +Wire Wire Line + 8350 3400 8450 3400 +Text Notes 3850 2500 0 60 ~ 0 +IN1 +Text Notes 3850 3150 0 60 ~ 0 +IN2 +Text Notes 6000 2350 0 60 ~ 0 +CIN +Text Notes 7350 2550 0 60 ~ 0 +SUM +Text Notes 8300 3200 0 60 ~ 0 +COUT +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/full_adder/full_adder.sub b/library/SubcircuitLibrary/full_adder/full_adder.sub new file mode 100644 index 00000000..5f261f78 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.sub @@ -0,0 +1,13 @@ +* Subcircuit full_adder +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml b/library/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml new file mode 100644 index 00000000..b63184d6 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_adder/half_adder-cache.lib b/library/SubcircuitLibrary/full_adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/full_adder/half_adder.cir b/library/SubcircuitLibrary/full_adder/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/library/SubcircuitLibrary/full_adder/half_adder.cir.out b/library/SubcircuitLibrary/full_adder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/full_adder/half_adder.pro b/library/SubcircuitLibrary/full_adder/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/library/SubcircuitLibrary/full_adder/half_adder.sch b/library/SubcircuitLibrary/full_adder/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/full_adder/half_adder.sub b/library/SubcircuitLibrary/full_adder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml b/library/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_sub/analysis b/library/SubcircuitLibrary/full_sub/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_sub/full_sub-cache.lib b/library/SubcircuitLibrary/full_sub/full_sub-cache.lib new file mode 100644 index 00000000..6949ac1a --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/full_sub/full_sub-rescue.lib b/library/SubcircuitLibrary/full_sub/full_sub-rescue.lib new file mode 100644 index 00000000..803b5ece --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub-rescue.lib @@ -0,0 +1,20 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# half_sub-RESCUE-full_sub +# +DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1450 850 1550 -1050 0 1 0 N +X A 1 -1100 850 200 R 50 50 1 1 I +X B 2 -350 850 200 R 50 50 1 1 I +X D 3 -800 -1050 200 L 50 50 1 1 O +X BORROW 4 0 -1050 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/full_sub/full_sub.cir b/library/SubcircuitLibrary/full_sub/full_sub.cir new file mode 100644 index 00000000..67359421 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.cir @@ -0,0 +1,14 @@ +* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or +U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT +X1 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub +X2 Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub + +.end diff --git a/library/SubcircuitLibrary/full_sub/full_sub.cir.out b/library/SubcircuitLibrary/full_sub/full_sub.cir.out new file mode 100644 index 00000000..5e58cc0a --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.cir.out @@ -0,0 +1,19 @@ +* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir + +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/full_sub/full_sub.pro b/library/SubcircuitLibrary/full_sub/full_sub.pro new file mode 100644 index 00000000..1a0c3543 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.pro @@ -0,0 +1,74 @@ +update=03/07/19 10:55:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=full_sub-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=device +LibName24=transistors +LibName25=conn +LibName26=linear +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_User +LibName39=eSim_Plot +LibName40=eSim_PSpice + diff --git a/library/SubcircuitLibrary/full_sub/full_sub.sch b/library/SubcircuitLibrary/full_sub/full_sub.sch new file mode 100644 index 00000000..99ca85e5 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.sch @@ -0,0 +1,211 @@ +EESchema Schematic File Version 2 +LIBS:full_sub-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:full_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U3 +U 1 1 5C80734A +P 9350 4050 +F 0 "U3" H 9350 4050 60 0000 C CNN +F 1 "d_or" H 9350 4150 60 0000 C CNN +F 2 "" H 9350 4050 60 0000 C CNN +F 3 "" H 9350 4050 60 0000 C CNN + 1 9350 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 3600 5800 3600 +Wire Wire Line + 4650 2800 8600 2800 +Wire Wire Line + 8600 2800 8600 3950 +Wire Wire Line + 8600 3950 8900 3950 +Wire Wire Line + 8100 4450 8650 4450 +Wire Wire Line + 8650 4450 8650 4050 +Wire Wire Line + 8650 4050 8900 4050 +Wire Wire Line + 2800 3450 2800 3250 +Wire Wire Line + 2800 3250 3300 3250 +Wire Wire Line + 1450 3550 3300 3550 +Wire Wire Line + 4050 5100 5200 5100 +Wire Wire Line + 5800 3600 5800 5250 +Wire Wire Line + 8250 5250 9350 5250 +Wire Wire Line + 9350 5250 9350 4900 +Wire Wire Line + 9350 4900 10750 4900 +Wire Wire Line + 9800 4000 9800 4600 +Wire Wire Line + 9800 4600 9550 4600 +Wire Wire Line + 9550 4600 9550 4800 +Wire Wire Line + 9550 4800 10750 4800 +$Comp +L PORT U5 +U 1 1 5C80A4E8 +P 1200 3450 +F 0 "U5" H 1250 3550 30 0000 C CNN +F 1 "PORT" H 1200 3450 30 0000 C CNN +F 2 "" H 1200 3450 60 0000 C CNN +F 3 "" H 1200 3450 60 0000 C CNN + 1 1200 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 2 1 5C80A51E +P 1200 3650 +F 0 "U5" H 1250 3750 30 0000 C CNN +F 1 "PORT" H 1200 3650 30 0000 C CNN +F 2 "" H 1200 3650 60 0000 C CNN +F 3 "" H 1200 3650 60 0000 C CNN + 2 1200 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 3 1 5C80A54E +P 3800 5100 +F 0 "U5" H 3850 5200 30 0000 C CNN +F 1 "PORT" H 3800 5100 30 0000 C CNN +F 2 "" H 3800 5100 60 0000 C CNN +F 3 "" H 3800 5100 60 0000 C CNN + 3 3800 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 5 1 5C80A828 +P 11000 4800 +F 0 "U5" H 11050 4900 30 0000 C CNN +F 1 "PORT" H 11000 4800 30 0000 C CNN +F 2 "" H 11000 4800 60 0000 C CNN +F 3 "" H 11000 4800 60 0000 C CNN + 5 11000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 4 1 5C80AB2A +P 11000 4950 +F 0 "U5" H 11050 5050 30 0000 C CNN +F 1 "PORT" H 11000 4950 30 0000 C CNN +F 2 "" H 11000 4950 60 0000 C CNN +F 3 "" H 11000 4950 60 0000 C CNN + 4 11000 4950 + -1 0 0 1 +$EndComp +Wire Wire Line + 1450 3450 2800 3450 +Wire Wire Line + 1450 3650 1450 3550 +Wire Wire Line + 10750 4900 10750 4950 +$Comp +L half_sub X1 +U 1 1 5C80AC4D +P 3800 3450 +F 0 "X1" H 3800 3450 60 0000 C CNN +F 1 "half_sub" H 3800 3450 60 0000 C CNN +F 2 "" H 3800 3450 60 0001 C CNN +F 3 "" H 3800 3450 60 0001 C CNN + 1 3800 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 3550 4650 3550 +Wire Wire Line + 4650 3550 4650 2800 +Wire Wire Line + 4300 3300 4850 3300 +Wire Wire Line + 4850 3300 4850 3600 +$Comp +L half_sub X2 +U 1 1 5C80AD72 +P 7300 5150 +F 0 "X2" H 7300 5150 60 0000 C CNN +F 1 "half_sub" H 7300 5150 60 0000 C CNN +F 2 "" H 7300 5150 60 0001 C CNN +F 3 "" H 7300 5150 60 0001 C CNN + 1 7300 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5800 5250 6800 5250 +Wire Wire Line + 5200 5100 5200 4950 +Wire Wire Line + 5200 4950 6800 4950 +Wire Wire Line + 7800 5000 8250 5000 +Wire Wire Line + 8250 5000 8250 5250 +Wire Wire Line + 7800 5250 8100 5250 +Wire Wire Line + 8100 5250 8100 4450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/full_sub/full_sub.sub b/library/SubcircuitLibrary/full_sub/full_sub.sub new file mode 100644 index 00000000..9c9dcc5a --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.sub @@ -0,0 +1,13 @@ +* Subcircuit full_sub +.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ +* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml b/library/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml new file mode 100644 index 00000000..fcdb63e0 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_sub/half_sub-cache.lib b/library/SubcircuitLibrary/full_sub/half_sub-cache.lib new file mode 100644 index 00000000..bd15e664 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/full_sub/half_sub.cir b/library/SubcircuitLibrary/full_sub/half_sub.cir new file mode 100644 index 00000000..f20f0368 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.cir @@ -0,0 +1,14 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/full_sub/half_sub.cir.out b/library/SubcircuitLibrary/full_sub/half_sub.cir.out new file mode 100644 index 00000000..91816956 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.cir.out @@ -0,0 +1,24 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/full_sub/half_sub.pro b/library/SubcircuitLibrary/full_sub/half_sub.pro new file mode 100644 index 00000000..90e3ded9 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.pro @@ -0,0 +1,74 @@ +update=Wed 06 Mar 2019 11:10:38 PM IST +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/library/SubcircuitLibrary/full_sub/half_sub.sch b/library/SubcircuitLibrary/full_sub/half_sub.sch new file mode 100644 index 00000000..e70b1675 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U3 +U 1 1 5C7FDDA3 +P 4400 3150 +F 0 "U3" H 4400 3150 60 0000 C CNN +F 1 "d_xor" H 4450 3250 47 0000 C CNN +F 2 "" H 4400 3150 60 0000 C CNN +F 3 "" H 4400 3150 60 0000 C CNN + 1 4400 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5C7FDDD8 +P 3400 3750 +F 0 "U2" H 3400 3650 60 0000 C CNN +F 1 "d_inverter" H 3400 3900 60 0000 C CNN +F 2 "" H 3450 3700 60 0000 C CNN +F 3 "" H 3450 3700 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FDE57 +P 4450 3750 +F 0 "U4" H 4450 3750 60 0000 C CNN +F 1 "d_and" H 4500 3850 60 0000 C CNN +F 2 "" H 4450 3750 60 0000 C CNN +F 3 "" H 4450 3750 60 0000 C CNN + 1 4450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 3150 3950 3650 +Wire Wire Line + 3950 3650 4000 3650 +Wire Wire Line + 3700 3750 4000 3750 +Wire Wire Line + 3100 3750 3100 3050 +Wire Wire Line + 2950 3050 3950 3050 +$Comp +L PORT U1 +U 1 1 5C7FDF5A +P 2700 3050 +F 0 "U1" H 2750 3150 30 0000 C CNN +F 1 "PORT" H 2700 3050 30 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FDF97 +P 3500 3350 +F 0 "U1" H 3550 3450 30 0000 C CNN +F 1 "PORT" H 3500 3350 30 0000 C CNN +F 2 "" H 3500 3350 60 0000 C CNN +F 3 "" H 3500 3350 60 0000 C CNN + 2 3500 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FE00A +P 5300 3100 +F 0 "U1" H 5350 3200 30 0000 C CNN +F 1 "PORT" H 5300 3100 30 0000 C CNN +F 2 "" H 5300 3100 60 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 3 5300 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7FE064 +P 5350 3700 +F 0 "U1" H 5400 3800 30 0000 C CNN +F 1 "PORT" H 5350 3700 30 0000 C CNN +F 2 "" H 5350 3700 60 0000 C CNN +F 3 "" H 5350 3700 60 0000 C CNN + 4 5350 3700 + -1 0 0 1 +$EndComp +Connection ~ 3100 3050 +Wire Wire Line + 3750 3350 3950 3350 +Connection ~ 3950 3350 +Wire Wire Line + 4850 3100 5050 3100 +Wire Wire Line + 4900 3700 5100 3700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/full_sub/half_sub.sub b/library/SubcircuitLibrary/full_sub/half_sub.sub new file mode 100644 index 00000000..a61a3409 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.sub @@ -0,0 +1,18 @@ +* Subcircuit half_sub +.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml b/library/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml new file mode 100644 index 00000000..115ba703 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_adder/analysis b/library/SubcircuitLibrary/half_adder/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_adder/half_adder-cache.lib b/library/SubcircuitLibrary/half_adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/half_adder/half_adder.cir b/library/SubcircuitLibrary/half_adder/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/library/SubcircuitLibrary/half_adder/half_adder.cir.out b/library/SubcircuitLibrary/half_adder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/half_adder/half_adder.pro b/library/SubcircuitLibrary/half_adder/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/library/SubcircuitLibrary/half_adder/half_adder.sch b/library/SubcircuitLibrary/half_adder/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/half_adder/half_adder.sub b/library/SubcircuitLibrary/half_adder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml b/library/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/library/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_sub/analysis b/library/SubcircuitLibrary/half_sub/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_sub/half_sub-cache.lib b/library/SubcircuitLibrary/half_sub/half_sub-cache.lib new file mode 100644 index 00000000..bd15e664 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/half_sub/half_sub.cir b/library/SubcircuitLibrary/half_sub/half_sub.cir new file mode 100644 index 00000000..f20f0368 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub.cir @@ -0,0 +1,14 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/half_sub/half_sub.cir.out b/library/SubcircuitLibrary/half_sub/half_sub.cir.out new file mode 100644 index 00000000..91816956 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub.cir.out @@ -0,0 +1,24 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/half_sub/half_sub.pro b/library/SubcircuitLibrary/half_sub/half_sub.pro new file mode 100644 index 00000000..90e3ded9 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub.pro @@ -0,0 +1,74 @@ +update=Wed 06 Mar 2019 11:10:38 PM IST +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/library/SubcircuitLibrary/half_sub/half_sub.sch b/library/SubcircuitLibrary/half_sub/half_sub.sch new file mode 100644 index 00000000..e70b1675 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U3 +U 1 1 5C7FDDA3 +P 4400 3150 +F 0 "U3" H 4400 3150 60 0000 C CNN +F 1 "d_xor" H 4450 3250 47 0000 C CNN +F 2 "" H 4400 3150 60 0000 C CNN +F 3 "" H 4400 3150 60 0000 C CNN + 1 4400 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5C7FDDD8 +P 3400 3750 +F 0 "U2" H 3400 3650 60 0000 C CNN +F 1 "d_inverter" H 3400 3900 60 0000 C CNN +F 2 "" H 3450 3700 60 0000 C CNN +F 3 "" H 3450 3700 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FDE57 +P 4450 3750 +F 0 "U4" H 4450 3750 60 0000 C CNN +F 1 "d_and" H 4500 3850 60 0000 C CNN +F 2 "" H 4450 3750 60 0000 C CNN +F 3 "" H 4450 3750 60 0000 C CNN + 1 4450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 3150 3950 3650 +Wire Wire Line + 3950 3650 4000 3650 +Wire Wire Line + 3700 3750 4000 3750 +Wire Wire Line + 3100 3750 3100 3050 +Wire Wire Line + 2950 3050 3950 3050 +$Comp +L PORT U1 +U 1 1 5C7FDF5A +P 2700 3050 +F 0 "U1" H 2750 3150 30 0000 C CNN +F 1 "PORT" H 2700 3050 30 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FDF97 +P 3500 3350 +F 0 "U1" H 3550 3450 30 0000 C CNN +F 1 "PORT" H 3500 3350 30 0000 C CNN +F 2 "" H 3500 3350 60 0000 C CNN +F 3 "" H 3500 3350 60 0000 C CNN + 2 3500 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FE00A +P 5300 3100 +F 0 "U1" H 5350 3200 30 0000 C CNN +F 1 "PORT" H 5300 3100 30 0000 C CNN +F 2 "" H 5300 3100 60 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 3 5300 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7FE064 +P 5350 3700 +F 0 "U1" H 5400 3800 30 0000 C CNN +F 1 "PORT" H 5350 3700 30 0000 C CNN +F 2 "" H 5350 3700 60 0000 C CNN +F 3 "" H 5350 3700 60 0000 C CNN + 4 5350 3700 + -1 0 0 1 +$EndComp +Connection ~ 3100 3050 +Wire Wire Line + 3750 3350 3950 3350 +Connection ~ 3950 3350 +Wire Wire Line + 4850 3100 5050 3100 +Wire Wire Line + 4900 3700 5100 3700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/half_sub/half_sub.sub b/library/SubcircuitLibrary/half_sub/half_sub.sub new file mode 100644 index 00000000..a61a3409 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub.sub @@ -0,0 +1,18 @@ +* Subcircuit half_sub +.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml b/library/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml new file mode 100644 index 00000000..115ba703 --- /dev/null +++ b/library/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm555n/NPN.lib b/library/SubcircuitLibrary/lm555n/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/lm555n/analysis b/library/SubcircuitLibrary/lm555n/analysis new file mode 100644 index 00000000..a0953567 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm555n/lm555n-cache.lib b/library/SubcircuitLibrary/lm555n/lm555n-cache.lib new file mode 100644 index 00000000..824af11e --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n-cache.lib @@ -0,0 +1,205 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND-RESCUE-lm555n +# +DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# R-RESCUE-lm555n +# +DEF R-RESCUE-lm555n R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" 0 150 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_srlatch +# +DEF d_srlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srlatch" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X EN 3 -800 0 200 R 50 50 1 1 I +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# limit +# +DEF limit U 0 40 Y Y 1 F N +F0 "U" 50 -50 60 H V C CNN +F1 "limit" 50 50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +C 300 0 0 0 1 0 N +P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N +X IN 1 -400 0 200 R 50 50 1 1 I +X OUT 2 600 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/lm555n/lm555n-rescue.lib b/library/SubcircuitLibrary/lm555n/lm555n-rescue.lib new file mode 100644 index 00000000..fffeca36 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n-rescue.lib @@ -0,0 +1,18 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# d_inverter-RESCUE-lm555n +# +DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/lm555n/lm555n.cir b/library/SubcircuitLibrary/lm555n/lm555n.cir new file mode 100644 index 00000000..682d4945 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n.cir @@ -0,0 +1,31 @@ +* /home/ash98/Downloads/lm555n/lm555n.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 24 15:58:04 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +E2 Net-_E2-Pad1_ GND /c /d 10000 +U1 Net-_Q1-Pad3_ /d Net-_U1-Pad3_ Net-_U1-Pad4_ /a /b Net-_Q1-Pad1_ Net-_R1-Pad1_ PORT +R8 Net-_R8-Pad1_ Net-_Q1-Pad2_ 1500 +R7 Net-_E2-Pad1_ Net-_R7-Pad2_ 25 +R6 Net-_E1-Pad1_ Net-_R6-Pad2_ 25 +E1 Net-_E1-Pad1_ GND /b /a 10000 +R4 /b /a 2E6 +R5 /c /d 2E6 +R3 /c Net-_Q1-Pad3_ 5000 +R2 /a /c 5000 +R1 Net-_R1-Pad1_ /a 5000 +U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U7-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad6_ Net-_U10-Pad1_ d_srlatch +U7 Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ adc_bridge_1 +U4 Net-_U3-Pad2_ Net-_U4-Pad2_ adc_bridge_1 +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ adc_bridge_1 +U3 Net-_R7-Pad2_ Net-_U3-Pad2_ limit +U2 Net-_R6-Pad2_ Net-_U2-Pad2_ limit +U9 Net-_U8-Pad6_ Net-_U1-Pad3_ dac_bridge_1 +U10 Net-_U10-Pad1_ Net-_R8-Pad1_ dac_bridge_1 +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN + +.end diff --git a/library/SubcircuitLibrary/lm555n/lm555n.cir.out b/library/SubcircuitLibrary/lm555n/lm555n.cir.out new file mode 100644 index 00000000..a81070a1 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n.cir.out @@ -0,0 +1,42 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +.include npn_1.lib +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 npn_1 +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/lm555n/lm555n.pro b/library/SubcircuitLibrary/lm555n/lm555n.pro new file mode 100644 index 00000000..0a5408b6 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n.pro @@ -0,0 +1,57 @@ +update=Tue Apr 2 17:35:59 2019 +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +[eeschema/libraries] +LibName1=lm555n-rescue +LibName2=power +LibName3=device +LibName4=transistors +LibName5=conn +LibName6=linear +LibName7=regul +LibName8=74xx +LibName9=cmos4000 +LibName10=adc-dac +LibName11=memory +LibName12=xilinx +LibName13=special +LibName14=microcontrollers +LibName15=dsp +LibName16=microchip +LibName17=analog_switches +LibName18=motorola +LibName19=texas +LibName20=intel +LibName21=audio +LibName22=interface +LibName23=digital-audio +LibName24=philips +LibName25=display +LibName26=cypress +LibName27=siliconi +LibName28=opto +LibName29=atmel +LibName30=contrib +LibName31=valves +LibName32=analogSpice +LibName33=analogXSpice +LibName34=converterSpice +LibName35=digitalSpice +LibName36=linearSpice +LibName37=measurementSpice +LibName38=portSpice +LibName39=sourcesSpice +LibName40=digitalXSpice +LibName41=eSim_User +LibName42=eSim_Subckt +LibName43=eSim_Sources +LibName44=eSim_PSpice +LibName45=eSim_Power +LibName46=eSim_Plot +LibName47=eSim_Miscellaneous +LibName48=eSim_Hybrid +LibName49=eSim_Digital +LibName50=eSim_Devices +LibName51=eSim_Analog diff --git a/library/SubcircuitLibrary/lm555n/lm555n.sch b/library/SubcircuitLibrary/lm555n/lm555n.sch new file mode 100644 index 00000000..28110b13 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n.sch @@ -0,0 +1,518 @@ +EESchema Schematic File Version 2 +LIBS:lm555n-rescue +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3700 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 2650 3000 2850 3000 +Wire Wire Line + 2650 4750 2650 4650 +Connection ~ 2350 3550 +Connection ~ 2350 4900 +Wire Wire Line + 2350 4100 2350 4200 +Wire Wire Line + 9100 4900 9100 4800 +Wire Wire Line + 8500 4600 8500 4250 +Wire Wire Line + 3350 3250 3050 3250 +Wire Wire Line + 3050 3250 3050 3750 +Wire Wire Line + 3500 4350 3500 4500 +Wire Wire Line + 3650 3550 4200 3550 +Wire Wire Line + 3850 3250 4200 3250 +Wire Wire Line + 3150 3550 3150 3700 +Wire Wire Line + 3150 3700 3500 3700 +Wire Wire Line + 3500 3700 3500 3750 +Connection ~ 3500 4450 +Wire Wire Line + 3700 4450 3700 4400 +Wire Wire Line + 3050 4350 3050 4450 +Wire Wire Line + 3050 4450 3700 4450 +Wire Wire Line + 9100 4250 9000 4250 +Wire Wire Line + 9100 4400 9100 4350 +Wire Wire Line + 9100 4350 9200 4350 +Wire Wire Line + 10100 2950 10350 2950 +Wire Wire Line + 2350 4900 2350 4700 +Wire Wire Line + 2350 3500 2350 3600 +Wire Wire Line + 2250 3000 2350 3000 +Wire Wire Line + 2350 4150 2650 4150 +Connection ~ 2350 4150 +Wire Wire Line + 2250 3550 2650 3550 +Wire Wire Line + 2650 3550 2650 3500 +Wire Wire Line + 4300 4750 4300 4650 +Text Label 2800 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 3000 4050 +F 0 "E2" H 2800 4150 50 0000 C CNN +F 1 "10000" H 2800 4000 50 0000 C CNN +F 2 "" H 3000 4050 60 0001 C CNN +F 3 "" H 3000 4050 60 0001 C CNN + 1 3000 4050 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 3700 4400 +F 0 "#FLG01" H 3700 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 3700 4630 30 0000 C CNN +F 2 "" H 3700 4400 60 0001 C CNN +F 3 "" H 3700 4400 60 0001 C CNN + 1 3700 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 2000 3550 +F 0 "U1" H 2000 3500 30 0000 C CNN +F 1 "PORT" H 2000 3550 30 0000 C CNN +F 2 "" H 2000 3550 60 0001 C CNN +F 3 "" H 2000 3550 60 0001 C CNN + 5 2000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 2000 4900 +F 0 "U1" H 2000 4850 30 0000 C CNN +F 1 "PORT" H 2000 4900 30 0000 C CNN +F 2 "" H 2000 4900 60 0001 C CNN +F 3 "" H 2000 4900 60 0001 C CNN + 1 2000 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 2650 5000 +F 0 "U1" H 2650 4950 30 0000 C CNN +F 1 "PORT" H 2650 5000 30 0000 C CNN +F 2 "" H 2650 5000 60 0001 C CNN +F 3 "" H 2650 5000 60 0001 C CNN + 2 2650 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 4300 5000 +F 0 "U1" H 4300 4950 30 0000 C CNN +F 1 "PORT" H 4300 5000 30 0000 C CNN +F 2 "" H 4300 5000 60 0001 C CNN +F 3 "" H 4300 5000 60 0001 C CNN + 4 4300 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 9450 4350 +F 0 "U1" H 9450 4300 30 0000 C CNN +F 1 "PORT" H 9450 4350 30 0000 C CNN +F 2 "" H 9450 4350 60 0001 C CNN +F 3 "" H 9450 4350 60 0001 C CNN + 7 9450 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 10600 2950 +F 0 "U1" H 10600 2900 30 0000 C CNN +F 1 "PORT" H 10600 2950 30 0000 C CNN +F 2 "" H 10600 2950 60 0001 C CNN +F 3 "" H 10600 2950 60 0001 C CNN + 3 10600 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 3100 3000 +F 0 "U1" H 3100 2950 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0001 C CNN +F 3 "" H 3100 3000 60 0001 C CNN + 6 3100 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 2000 3000 +F 0 "U1" H 2000 2950 30 0000 C CNN +F 1 "PORT" H 2000 3000 30 0000 C CNN +F 2 "" H 2000 3000 60 0001 C CNN +F 3 "" H 2000 3000 60 0001 C CNN + 8 2000 3000 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R8 +U 1 1 50AA20DA +P 8750 4250 +F 0 "R8" V 8830 4250 50 0000 C CNN +F 1 "1500" V 8750 4250 50 0000 C CNN +F 2 "" H 8750 4250 60 0001 C CNN +F 3 "" H 8750 4250 60 0001 C CNN + 1 8750 4250 + 0 1 1 0 +$EndComp +$Comp +L GND-RESCUE-lm555n #PWR02 +U 1 1 50AA140C +P 3500 4500 +F 0 "#PWR02" H 3500 4500 30 0001 C CNN +F 1 "GND" H 3500 4430 30 0001 C CNN +F 2 "" H 3500 4500 60 0001 C CNN +F 3 "" H 3500 4500 60 0001 C CNN + 1 3500 4500 + 1 0 0 -1 +$EndComp +Text Label 2800 4000 0 60 ~ 0 +c +Text Label 2650 4650 0 60 ~ 0 +d +Text Label 2650 4150 0 60 ~ 0 +c +$Comp +L R-RESCUE-lm555n R7 +U 1 1 50AA12F7 +P 3600 3250 +F 0 "R7" V 3680 3250 50 0000 C CNN +F 1 "25" V 3600 3250 50 0000 C CNN +F 2 "" H 3600 3250 60 0001 C CNN +F 3 "" H 3600 3250 60 0001 C CNN + 1 3600 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R6 +U 1 1 50AA12B0 +P 3400 3550 +F 0 "R6" V 3480 3550 50 0000 C CNN +F 1 "25" V 3400 3550 50 0000 C CNN +F 2 "" H 3400 3550 60 0001 C CNN +F 3 "" H 3400 3550 60 0001 C CNN + 1 3400 3550 + 0 -1 -1 0 +$EndComp +Text Label 3250 4000 0 60 ~ 0 +b +Text Label 3250 4100 0 60 ~ 0 +a +Text Label 2650 3000 0 60 ~ 0 +b +Text Label 2650 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 3450 4050 +F 0 "E1" H 3250 4150 50 0000 C CNN +F 1 "10000" H 3250 4000 50 0000 C CNN +F 2 "" H 3450 4050 60 0001 C CNN +F 3 "" H 3450 4050 60 0001 C CNN + 1 3450 4050 + 0 1 1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R4 +U 1 1 50A9E00B +P 2650 3250 +F 0 "R4" V 2730 3250 50 0000 C CNN +F 1 "2E6" V 2650 3250 50 0000 C CNN +F 2 "" H 2650 3250 60 0001 C CNN +F 3 "" H 2650 3250 60 0001 C CNN + 1 2650 3250 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R5 +U 1 1 50A9E001 +P 2650 4400 +F 0 "R5" V 2730 4400 50 0000 C CNN +F 1 "2E6" V 2650 4400 50 0000 C CNN +F 2 "" H 2650 4400 60 0001 C CNN +F 3 "" H 2650 4400 60 0001 C CNN + 1 2650 4400 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R3 +U 1 1 50A9DF09 +P 2350 4450 +F 0 "R3" V 2430 4450 50 0000 C CNN +F 1 "5000" V 2350 4450 50 0000 C CNN +F 2 "" H 2350 4450 60 0001 C CNN +F 3 "" H 2350 4450 60 0001 C CNN + 1 2350 4450 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R2 +U 1 1 50A9DF03 +P 2350 3850 +F 0 "R2" V 2430 3850 50 0000 C CNN +F 1 "5000" V 2350 3850 50 0000 C CNN +F 2 "" H 2350 3850 60 0001 C CNN +F 3 "" H 2350 3850 60 0001 C CNN + 1 2350 3850 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R1 +U 1 1 50A9DEFE +P 2350 3250 +F 0 "R1" V 2430 3250 50 0000 C CNN +F 1 "5000" V 2350 3250 50 0000 C CNN +F 2 "" H 2350 3250 60 0001 C CNN +F 3 "" H 2350 3250 60 0001 C CNN + 1 2350 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_srlatch U8 +U 1 1 5E01E563 +P 8000 3350 +F 0 "U8" H 8000 3350 60 0000 C CNN +F 1 "d_srlatch" H 8050 3500 60 0000 C CNN +F 2 "" H 8000 3350 60 0000 C CNN +F 3 "" H 8000 3350 60 0000 C CNN + 1 8000 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5E01F10F +P 7450 4400 +F 0 "U7" H 7450 4300 60 0000 C CNN +F 1 "d_inverter" H 7450 4550 60 0000 C CNN +F 2 "" H 7500 4350 60 0000 C CNN +F 3 "" H 7500 4350 60 0000 C CNN + 1 7450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 4400 8150 4400 +Wire Wire Line + 8000 4400 8000 4150 +$Comp +L adc_bridge_1 U5 +U 1 1 5E01F2C7 +P 6350 3400 +F 0 "U5" H 6350 3400 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3550 60 0000 C CNN +F 2 "" H 6350 3400 60 0000 C CNN +F 3 "" H 6350 3400 60 0000 C CNN + 1 6350 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3350 7200 3350 +Wire Wire Line + 4300 4650 5600 4650 +Wire Wire Line + 5600 4650 5600 3350 +Wire Wire Line + 5600 3350 5750 3350 +$Comp +L adc_bridge_1 U4 +U 1 1 5E01F3F2 +P 6350 3000 +F 0 "U4" H 6350 3000 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3150 60 0000 C CNN +F 2 "" H 6350 3000 60 0000 C CNN +F 3 "" H 6350 3000 60 0000 C CNN + 1 6350 3000 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U6 +U 1 1 5E01F469 +P 6350 3850 +F 0 "U6" H 6350 3850 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 4000 60 0000 C CNN +F 2 "" H 6350 3850 60 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3800 7200 3800 +Wire Wire Line + 7200 2950 6900 2950 +$Comp +L limit U3 +U 1 1 5E01F5DC +P 4900 2950 +F 0 "U3" H 4950 2900 60 0000 C CNN +F 1 "limit" H 4950 3000 60 0000 C CNN +F 2 "" H 4900 3000 60 0000 C CNN +F 3 "" H 4900 3000 60 0000 C CNN + 1 4900 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 2950 5750 2950 +Wire Wire Line + 4200 3250 4200 2950 +Wire Wire Line + 4200 2950 4500 2950 +$Comp +L limit U2 +U 1 1 5E01F79D +P 4800 3800 +F 0 "U2" H 4850 3750 60 0000 C CNN +F 1 "limit" H 4850 3850 60 0000 C CNN +F 2 "" H 4800 3850 60 0000 C CNN +F 3 "" H 4800 3850 60 0000 C CNN + 1 4800 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 3800 5750 3800 +Wire Wire Line + 4200 3550 4200 3800 +Wire Wire Line + 4200 3800 4400 3800 +Wire Wire Line + 7050 3350 7050 4400 +Wire Wire Line + 7050 4400 7150 4400 +Connection ~ 7050 3350 +Wire Wire Line + 8000 2600 8150 2600 +Wire Wire Line + 8150 2600 8150 4400 +Connection ~ 8000 4400 +$Comp +L dac_bridge_1 U9 +U 1 1 5E01FCD2 +P 9550 3000 +F 0 "U9" H 9550 3000 60 0000 C CNN +F 1 "dac_bridge_1" H 9550 3150 60 0000 C CNN +F 2 "" H 9550 3000 60 0000 C CNN +F 3 "" H 9550 3000 60 0000 C CNN + 1 9550 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 2950 8950 2950 +$Comp +L dac_bridge_1 U10 +U 1 1 5E01FE8E +P 9600 3850 +F 0 "U10" H 9600 3850 60 0000 C CNN +F 1 "dac_bridge_1" H 9600 4000 60 0000 C CNN +F 2 "" H 9600 3850 60 0000 C CNN +F 3 "" H 9600 3850 60 0000 C CNN + 1 9600 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 3800 8800 3800 +Wire Wire Line + 9100 4000 9100 4250 +Wire Wire Line + 9100 4000 10300 4000 +Wire Wire Line + 10300 4000 10300 3800 +Wire Wire Line + 10300 3800 10150 3800 +$Comp +L eSim_NPN Q1 +U 1 1 5E01E782 +P 9000 4600 +F 0 "Q1" H 8900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 8950 4750 50 0000 R CNN +F 2 "" H 9200 4700 29 0000 C CNN +F 3 "" H 9000 4600 60 0000 C CNN + 1 9000 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 4600 8500 4600 +Wire Wire Line + 2250 4900 9100 4900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/lm555n/lm555n.sub b/library/SubcircuitLibrary/lm555n/lm555n.sub new file mode 100644 index 00000000..b524f5c6 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n.sub @@ -0,0 +1,39 @@ +* Subcircuit lm555n +.subckt lm555n 22 14 7 6 15 16 3 13 +.include npn_1.lib +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +r8 9 2 1500 +q1 3 2 22 npn_1 +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) +*control statements + +.ends lm555n diff --git a/library/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml b/library/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml new file mode 100644 index 00000000..58d33ec5 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">false</field2><field3 name="Oct">true</field3><field4 name="Start Frequency">kjadsfh</field4><field5 name="Stop Frequency">jhdsakj</field5><field6 name="No. of points">897897</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm555n/npn_1.lib b/library/SubcircuitLibrary/lm555n/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/lm555n/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm7805/NPN.lib b/library/SubcircuitLibrary/lm7805/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/lm7805/PNP.lib b/library/SubcircuitLibrary/lm7805/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/lm7805/Q_PNP.lib b/library/SubcircuitLibrary/lm7805/Q_PNP.lib new file mode 100644 index 00000000..154ed2d8 --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/Q_PNP.lib @@ -0,0 +1 @@ +.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm7805/analysis b/library/SubcircuitLibrary/lm7805/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm7805/lm7805-cache.lib b/library/SubcircuitLibrary/lm7805/lm7805-cache.lib new file mode 100644 index 00000000..aaf8454e --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805-cache.lib @@ -0,0 +1,136 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/lm7805/lm7805.cir b/library/SubcircuitLibrary/lm7805/lm7805.cir new file mode 100644 index 00000000..081b4920 --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805.cir @@ -0,0 +1,51 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm7805\lm7805.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/26/19 17:24:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k +R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 +R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k +R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k +U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R5 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500 +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN +R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R7 Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k +Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R10 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k +Q7 Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R12 Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k +R9 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k +Q5 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP +R8 Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100 +R11 Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50 +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN +R13 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +R14 Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k +Q14 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN +R17 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k +R16 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 1.385k +R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k +U2 Net-_Q15-Pad2_ Net-_R15-Pad2_ zener +Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN +R18 Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200 +R20 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3 +R19 Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240 +U3 Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/lm7805/lm7805.cir.out b/library/SubcircuitLibrary/lm7805/lm7805.cir.out new file mode 100644 index 00000000..f122fba6 --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805.cir.out @@ -0,0 +1,60 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir + +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 1.385k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +* u3 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/lm7805/lm7805.pro b/library/SubcircuitLibrary/lm7805/lm7805.pro new file mode 100644 index 00000000..d410e2fa --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805.pro @@ -0,0 +1,45 @@ +update=Mon Aug 26 14:34:23 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User + diff --git a/library/SubcircuitLibrary/lm7805/lm7805.sch b/library/SubcircuitLibrary/lm7805/lm7805.sch new file mode 100644 index 00000000..701d163d --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805.sch @@ -0,0 +1,757 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm7805-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 5CE41429 +P 1250 1600 +F 0 "R1" V 1330 1600 50 0000 C CNN +F 1 "100k" V 1250 1600 50 0000 C CNN +F 2 "" V 1180 1600 50 0001 C CNN +F 3 "" H 1250 1600 50 0001 C CNN + 1 1250 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5CE4148B +P 1950 1600 +F 0 "R2" V 2030 1600 50 0000 C CNN +F 1 "500" V 1950 1600 50 0000 C CNN +F 2 "" V 1880 1600 50 0001 C CNN +F 3 "" H 1950 1600 50 0001 C CNN + 1 1950 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5CE414A5 +P 1950 3050 +F 0 "R3" V 2030 3050 50 0000 C CNN +F 1 "3.3k" V 1950 3050 50 0000 C CNN +F 2 "" V 1880 3050 50 0001 C CNN +F 3 "" H 1950 3050 50 0001 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5CE414CA +P 1950 3750 +F 0 "R4" V 2030 3750 50 0000 C CNN +F 1 "2.7k" V 1950 3750 50 0000 C CNN +F 2 "" V 1880 3750 50 0001 C CNN +F 3 "" H 1950 3750 50 0001 C CNN + 1 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 5CE414FA +P 1250 3350 +F 0 "U1" H 1200 3250 60 0000 C CNN +F 1 "zener" H 1250 3450 60 0000 C CNN +F 2 "" H 1300 3350 60 0000 C CNN +F 3 "" H 1300 3350 60 0000 C CNN + 1 1250 3350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 5CE41586 +P 1850 2350 +F 0 "Q1" H 1750 2400 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN +F 2 "" H 2050 2450 29 0000 C CNN +F 3 "" H 1850 2350 60 0000 C CNN + 1 1850 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5CE418C5 +P 1950 4600 +F 0 "R5" V 2030 4600 50 0000 C CNN +F 1 "500" V 1950 4600 50 0000 C CNN +F 2 "" V 1880 4600 50 0001 C CNN +F 3 "" H 1950 4600 50 0001 C CNN + 1 1950 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 1750 1250 3050 +Wire Wire Line + 1250 1450 1250 1300 +Wire Wire Line + 1250 1300 1950 1300 +Wire Wire Line + 1950 1300 1950 1450 +Wire Wire Line + 1950 2150 1950 1750 +Wire Wire Line + 1950 2550 1950 2900 +Wire Wire Line + 1950 3200 1950 3600 +Wire Wire Line + 1950 3900 1950 4450 +Wire Wire Line + 1250 3550 1250 5200 +Wire Wire Line + 1250 5200 3200 5200 +Wire Wire Line + 1950 5200 1950 4750 +Wire Wire Line + 1650 2350 1250 2350 +Connection ~ 1250 2350 +$Comp +L eSim_NPN Q2 +U 1 1 5CE41D6C +P 2650 3350 +F 0 "Q2" H 2550 3400 50 0000 R CNN +F 1 "eSim_NPN" H 2600 3500 50 0000 R CNN +F 2 "" H 2850 3450 29 0000 C CNN +F 3 "" H 2650 3350 60 0000 C CNN + 1 2650 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 5CE41E26 +P 3100 4100 +F 0 "Q4" H 3000 4150 50 0000 R CNN +F 1 "eSim_NPN" H 3050 4250 50 0000 R CNN +F 2 "" H 3300 4200 29 0000 C CNN +F 3 "" H 3100 4100 60 0000 C CNN + 1 3100 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 5CE41EA8 +P 2750 3850 +F 0 "R6" V 2830 3850 50 0000 C CNN +F 1 "1k" V 2750 3850 50 0000 C CNN +F 2 "" V 2680 3850 50 0001 C CNN +F 3 "" H 2750 3850 50 0001 C CNN + 1 2750 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE41EFE +P 2850 4650 +F 0 "Q3" H 2750 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN +F 2 "" H 3050 4750 29 0000 C CNN +F 3 "" H 2850 4650 60 0000 C CNN + 1 2850 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3550 2750 3700 +Wire Wire Line + 2750 4000 2750 4450 +Wire Wire Line + 2900 4100 2750 4100 +Connection ~ 2750 4100 +Wire Wire Line + 3200 4300 3200 4750 +Wire Wire Line + 3050 4650 3450 4650 +Wire Wire Line + 2450 3350 1950 3350 +Connection ~ 1950 3350 +Wire Wire Line + 2750 3600 3600 3600 +Wire Wire Line + 3200 3600 3200 3900 +Connection ~ 2750 3600 +$Comp +L R R7 +U 1 1 5CE42281 +P 3200 4900 +F 0 "R7" V 3280 4900 50 0000 C CNN +F 1 "6k" V 3200 4900 50 0000 C CNN +F 2 "" V 3130 4900 50 0001 C CNN +F 3 "" H 3200 4900 50 0001 C CNN + 1 3200 4900 + 1 0 0 -1 +$EndComp +Connection ~ 3200 4650 +Wire Wire Line + 3200 5050 3200 5250 +Connection ~ 1950 5200 +Wire Wire Line + 2750 4850 2750 5200 +Connection ~ 2750 5200 +$Comp +L eSim_NPN Q6 +U 1 1 5CE424FB +P 3650 4650 +F 0 "Q6" H 3550 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3600 4800 50 0000 R CNN +F 2 "" H 3850 4750 29 0000 C CNN +F 3 "" H 3650 4650 60 0000 C CNN + 1 3650 4650 + 1 0 0 -1 +$EndComp +$Comp +L R R10 +U 1 1 5CE42584 +P 3750 5100 +F 0 "R10" V 3830 5100 50 0000 C CNN +F 1 "1k" V 3750 5100 50 0000 C CNN +F 2 "" V 3680 5100 50 0001 C CNN +F 3 "" H 3750 5100 50 0001 C CNN + 1 3750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4850 3750 4950 +Wire Wire Line + 3200 5250 3750 5250 +Connection ~ 3200 5200 +$Comp +L eSim_NPN Q7 +U 1 1 5CE427DA +P 3700 2750 +F 0 "Q7" H 3600 2800 50 0000 R CNN +F 1 "eSim_NPN" H 3650 2900 50 0000 R CNN +F 2 "" H 3900 2850 29 0000 C CNN +F 3 "" H 3700 2750 60 0000 C CNN + 1 3700 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE428D0 +P 3700 3400 +F 0 "Q8" H 3600 3450 50 0000 R CNN +F 1 "eSim_NPN" H 3650 3550 50 0000 R CNN +F 2 "" H 3900 3500 29 0000 C CNN +F 3 "" H 3700 3400 60 0000 C CNN + 1 3700 3400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE4293A +P 4350 3000 +F 0 "Q12" H 4250 3050 50 0000 R CNN +F 1 "eSim_NPN" H 4300 3150 50 0000 R CNN +F 2 "" H 4550 3100 29 0000 C CNN +F 3 "" H 4350 3000 60 0000 C CNN + 1 4350 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2950 3600 3200 +Wire Wire Line + 4250 3200 4250 3400 +Wire Wire Line + 4250 3400 3900 3400 +Wire Wire Line + 4250 2750 4250 2800 +Wire Wire Line + 3900 2750 4250 2750 +Connection ~ 3200 3600 +$Comp +L R R12 +U 1 1 5CE42C4F +P 4350 3450 +F 0 "R12" V 4430 3450 50 0000 C CNN +F 1 "6k" V 4350 3450 50 0000 C CNN +F 2 "" V 4280 3450 50 0001 C CNN +F 3 "" H 4350 3450 50 0001 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 3300 4250 3300 +Connection ~ 4250 3300 +Wire Wire Line + 3700 3600 4350 3600 +Wire Wire Line + 3700 3600 3700 3650 +Wire Wire Line + 3700 3650 3550 3650 +Wire Wire Line + 3550 3650 3550 3600 +Connection ~ 3550 3600 +$Comp +L R R9 +U 1 1 5CE42EA3 +P 3750 3950 +F 0 "R9" V 3830 3950 50 0000 C CNN +F 1 "20k" V 3750 3950 50 0000 C CNN +F 2 "" V 3680 3950 50 0001 C CNN +F 3 "" H 3750 3950 50 0001 C CNN + 1 3750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4100 3750 4450 +Wire Wire Line + 3750 3800 3750 3600 +Connection ~ 3750 3600 +Wire Wire Line + 2750 3150 2750 2450 +Wire Wire Line + 2750 2450 3600 2450 +Wire Wire Line + 3600 2450 3600 2550 +$Comp +L eSim_PNP Q5 +U 1 1 5CE43397 +P 3450 1700 +F 0 "Q5" H 3350 1750 50 0000 R CNN +F 1 "eSim_PNP" H 3400 1850 50 0000 R CNN +F 2 "" H 3650 1800 29 0000 C CNN +F 3 "" H 3450 1700 60 0000 C CNN + 1 3450 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE4353C +P 4100 1700 +F 0 "Q9" H 4000 1750 50 0000 R CNN +F 1 "eSim_PNP" H 4050 1850 50 0000 R CNN +F 2 "" H 4300 1800 29 0000 C CNN +F 3 "" H 4100 1700 60 0000 C CNN + 1 4100 1700 + 1 0 0 1 +$EndComp +$Comp +L R R8 +U 1 1 5CE435B8 +P 3350 1250 +F 0 "R8" V 3430 1250 50 0000 C CNN +F 1 "100" V 3350 1250 50 0000 C CNN +F 2 "" V 3280 1250 50 0001 C CNN +F 3 "" H 3350 1250 50 0001 C CNN + 1 3350 1250 + 1 0 0 -1 +$EndComp +$Comp +L R R11 +U 1 1 5CE4368E +P 4200 1250 +F 0 "R11" V 4280 1250 50 0000 C CNN +F 1 "50" V 4200 1250 50 0000 C CNN +F 2 "" V 4130 1250 50 0001 C CNN +F 3 "" H 4200 1250 50 0001 C CNN + 1 4200 1250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 5CE43705 +P 4100 2200 +F 0 "Q10" H 4000 2250 50 0000 R CNN +F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN +F 2 "" H 4300 2300 29 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 1400 3350 1500 +Wire Wire Line + 3650 1700 3900 1700 +Wire Wire Line + 4200 1400 4200 1500 +Wire Wire Line + 3350 1100 3350 1050 +Wire Wire Line + 1650 1050 7800 1050 +Wire Wire Line + 4200 1050 4200 1100 +Wire Wire Line + 4200 1900 4200 2000 +Wire Wire Line + 3750 1700 3750 2000 +Wire Wire Line + 3750 2000 3350 2000 +Wire Wire Line + 3350 1900 3350 2450 +Connection ~ 3750 1700 +Connection ~ 3350 2450 +Connection ~ 3350 2000 +Wire Wire Line + 2300 2200 3900 2200 +Wire Wire Line + 2300 2200 2300 4200 +Wire Wire Line + 2300 4200 1950 4200 +Connection ~ 1950 4200 +Wire Wire Line + 2200 2400 4200 2400 +Wire Wire Line + 2200 2400 2200 5200 +Connection ~ 2200 5200 +$Comp +L eSim_NPN Q11 +U 1 1 5CE4439E +P 4300 4400 +F 0 "Q11" H 4200 4450 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4550 50 0000 R CNN +F 2 "" H 4500 4500 29 0000 C CNN +F 3 "" H 4300 4400 60 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE44419 +P 4600 4800 +F 0 "Q13" H 4500 4850 50 0000 R CNN +F 1 "eSim_NPN" H 4550 4950 50 0000 R CNN +F 2 "" H 4800 4900 29 0000 C CNN +F 3 "" H 4600 4800 60 0000 C CNN + 1 4600 4800 + 1 0 0 -1 +$EndComp +$Comp +L R R13 +U 1 1 5CE444B9 +P 4400 5050 +F 0 "R13" V 4480 5050 50 0000 C CNN +F 1 "6k" V 4400 5050 50 0000 C CNN +F 2 "" V 4330 5050 50 0001 C CNN +F 3 "" H 4400 5050 50 0001 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE4451D +P 4050 4150 +F 0 "C1" H 4075 4250 50 0000 L CNN +F 1 "30p" H 4075 4050 50 0000 L CNN +F 2 "" H 4088 4000 30 0000 C CNN +F 3 "" H 4050 4150 60 0000 C CNN + 1 4050 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4100 4400 3750 4400 +Connection ~ 3750 4400 +Wire Wire Line + 3900 4150 3750 4150 +Connection ~ 3750 4150 +Wire Wire Line + 4700 4150 4200 4150 +Wire Wire Line + 4400 4150 4400 4200 +Wire Wire Line + 4400 4600 4400 4900 +Connection ~ 4400 4800 +Wire Wire Line + 4400 5200 4400 5300 +Wire Wire Line + 3650 5300 6400 5300 +Wire Wire Line + 3650 5300 3650 5250 +Connection ~ 3650 5250 +Wire Wire Line + 4700 5300 4700 5000 +Connection ~ 4400 5300 +Wire Wire Line + 4700 3800 4700 4600 +Connection ~ 4400 4150 +$Comp +L R R14 +U 1 1 5CE44FFF +P 4700 3650 +F 0 "R14" V 4780 3650 50 0000 C CNN +F 1 "6k" V 4700 3650 50 0000 C CNN +F 2 "" V 4630 3650 50 0001 C CNN +F 3 "" H 4700 3650 50 0001 C CNN + 1 4700 3650 + 1 0 0 -1 +$EndComp +Connection ~ 4700 4150 +$Comp +L eSim_PNP Q14 +U 1 1 5CE45652 +P 5050 3950 +F 0 "Q14" H 4950 4000 50 0000 R CNN +F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN +F 2 "" H 5250 4050 29 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5050 3950 + 1 0 0 1 +$EndComp +Wire Wire Line + 4850 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4700 3500 4700 3450 +Wire Wire Line + 4700 3450 5150 3450 +Wire Wire Line + 5150 3450 5150 3750 +Wire Wire Line + 5150 5300 5150 4150 +Connection ~ 4700 5300 +Wire Wire Line + 4750 3450 4750 1950 +Wire Wire Line + 4200 1950 5300 1950 +Connection ~ 4200 1950 +Connection ~ 4750 3450 +$Comp +L eSim_NPN Q15 +U 1 1 5CE463AD +P 5400 2150 +F 0 "Q15" H 5300 2200 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN +F 2 "" H 5600 2250 29 0000 C CNN +F 3 "" H 5400 2150 60 0000 C CNN + 1 5400 2150 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1950 +Wire Wire Line + 4150 2750 4150 2600 +Wire Wire Line + 4150 2600 6100 2600 +Wire Wire Line + 5300 2600 5300 2350 +Connection ~ 4150 2750 +$Comp +L R R17 +U 1 1 5CE46DDE +P 6050 4250 +F 0 "R17" V 6130 4250 50 0000 C CNN +F 1 "5k" V 6050 4250 50 0000 C CNN +F 2 "" V 5980 4250 50 0001 C CNN +F 3 "" H 6050 4250 50 0001 C CNN + 1 6050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R16 +U 1 1 5CE46F8E +P 6050 3050 +F 0 "R16" V 6130 3050 50 0000 C CNN +F 1 "1.385k" V 6050 3050 50 0000 C CNN +F 2 "" V 5980 3050 50 0001 C CNN +F 3 "" H 6050 3050 50 0001 C CNN + 1 6050 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3200 6050 4100 +Wire Wire Line + 6050 5300 6050 4400 +Connection ~ 5150 5300 +Wire Wire Line + 6050 2600 6050 2900 +Connection ~ 5300 2600 +Wire Wire Line + 4550 3000 5100 3000 +Wire Wire Line + 5100 3000 5100 3250 +Wire Wire Line + 5100 3250 5350 3250 +Wire Wire Line + 5350 3250 5350 3600 +Wire Wire Line + 5350 3600 6050 3600 +Connection ~ 6050 3600 +Wire Wire Line + 1650 1050 1650 1300 +Connection ~ 1650 1300 +Connection ~ 3350 1050 +$Comp +L R R15 +U 1 1 5CE47F7A +P 5850 1300 +F 0 "R15" V 5930 1300 50 0000 C CNN +F 1 "10k" V 5850 1300 50 0000 C CNN +F 2 "" V 5780 1300 50 0001 C CNN +F 3 "" H 5850 1300 50 0001 C CNN + 1 5850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1050 5850 1150 +Connection ~ 4200 1050 +$Comp +L zener U2 +U 1 1 5CE48686 +P 5850 1900 +F 0 "U2" H 5800 1800 60 0000 C CNN +F 1 "zener" H 5850 2000 60 0000 C CNN +F 2 "" H 5900 1900 60 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 1450 5850 1600 +Wire Wire Line + 5850 2100 5850 2250 +Wire Wire Line + 5850 2150 5600 2150 +$Comp +L eSim_NPN Q16 +U 1 1 5CE4907A +P 6550 1600 +F 0 "Q16" H 6450 1650 50 0000 R CNN +F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN +F 2 "" H 6750 1700 29 0000 C CNN +F 3 "" H 6550 1600 60 0000 C CNN + 1 6550 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE4942E +P 7300 1950 +F 0 "Q17" H 7200 2000 50 0000 R CNN +F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN +F 2 "" H 7500 2050 29 0000 C CNN +F 3 "" H 7300 1950 60 0000 C CNN + 1 7300 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 1800 6650 2300 +Wire Wire Line + 6650 1950 7100 1950 +Wire Wire Line + 7400 1050 7400 1750 +Connection ~ 5850 1050 +Wire Wire Line + 6650 1400 6650 1050 +Connection ~ 6650 1050 +$Comp +L R R18 +U 1 1 5CE498BA +P 6650 2450 +F 0 "R18" V 6730 2450 50 0000 C CNN +F 1 "200" V 6650 2450 50 0000 C CNN +F 2 "" V 6580 2450 50 0001 C CNN +F 3 "" H 6650 2450 50 0001 C CNN + 1 6650 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R20 +U 1 1 5CE4999A +P 7400 2450 +F 0 "R20" V 7480 2450 50 0000 C CNN +F 1 "0.3" V 7400 2450 50 0000 C CNN +F 2 "" V 7330 2450 50 0001 C CNN +F 3 "" H 7400 2450 50 0001 C CNN + 1 7400 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R19 +U 1 1 5CE49AF5 +P 7000 2250 +F 0 "R19" V 7080 2250 50 0000 C CNN +F 1 "240" V 7000 2250 50 0000 C CNN +F 2 "" V 6930 2250 50 0001 C CNN +F 3 "" H 7000 2250 50 0001 C CNN + 1 7000 2250 + 0 1 1 0 +$EndComp +Connection ~ 6650 1950 +Wire Wire Line + 5850 2250 6850 2250 +Connection ~ 5850 2150 +Wire Wire Line + 7400 2150 7400 2300 +Wire Wire Line + 7150 2250 7400 2250 +Connection ~ 7400 2250 +Wire Wire Line + 6100 2600 6100 2650 +Wire Wire Line + 6100 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 2600 +Connection ~ 6050 2600 +Wire Wire Line + 6650 2600 6650 2650 +Connection ~ 6650 2650 +$Comp +L PORT U3 +U 1 1 5CE4AAF6 +P 8050 1050 +F 0 "U3" H 8100 1150 30 0000 C CNN +F 1 "PORT" H 8050 1050 30 0000 C CNN +F 2 "" H 8050 1050 60 0000 C CNN +F 3 "" H 8050 1050 60 0000 C CNN + 1 8050 1050 + -1 0 0 1 +$EndComp +Connection ~ 7400 1050 +$Comp +L PORT U3 +U 3 1 5CE4B13E +P 7700 3000 +F 0 "U3" H 7750 3100 30 0000 C CNN +F 1 "PORT" H 7700 3000 30 0000 C CNN +F 2 "" H 7700 3000 60 0000 C CNN +F 3 "" H 7700 3000 60 0000 C CNN + 3 7700 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 2 1 5CE4B701 +P 6650 5300 +F 0 "U3" H 6700 5400 30 0000 C CNN +F 1 "PORT" H 6650 5300 30 0000 C CNN +F 2 "" H 6650 5300 60 0000 C CNN +F 3 "" H 6650 5300 60 0000 C CNN + 2 6650 5300 + -1 0 0 1 +$EndComp +Connection ~ 6050 5300 +Wire Wire Line + 6350 1600 5950 1600 +Wire Wire Line + 5950 1600 5950 1550 +Wire Wire Line + 5950 1550 5000 1550 +Wire Wire Line + 5000 1550 5000 1950 +Connection ~ 5000 1950 +Wire Wire Line + 7300 2650 7300 3000 +Wire Wire Line + 7300 3000 7450 3000 +Connection ~ 7300 2650 +Connection ~ 2500 5200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/lm7805/lm7805.sub b/library/SubcircuitLibrary/lm7805/lm7805.sub new file mode 100644 index 00000000..7ee1489c --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805.sub @@ -0,0 +1,54 @@ +* Subcircuit lm7805 +.subckt lm7805 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ +* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 1.385k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Control Statements + +.ends lm7805
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml b/library/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml new file mode 100644 index 00000000..7395bd7c --- /dev/null +++ b/library/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm_741/NPN.lib b/library/SubcircuitLibrary/lm_741/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/lm_741/PNP.lib b/library/SubcircuitLibrary/lm_741/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/lm_741/analysis b/library/SubcircuitLibrary/lm_741/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm_741/lm_741-cache.lib b/library/SubcircuitLibrary/lm_741/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/lm_741/lm_741.cir b/library/SubcircuitLibrary/lm_741/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/lm_741/lm_741.cir.out b/library/SubcircuitLibrary/lm_741/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/lm_741/lm_741.pro b/library/SubcircuitLibrary/lm_741/lm_741.pro new file mode 100644 index 00000000..cbe83f35 --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741.pro @@ -0,0 +1,45 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/library/SubcircuitLibrary/lm_741/lm_741.sch b/library/SubcircuitLibrary/lm_741/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 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+$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/lm_741/lm_741.sub b/library/SubcircuitLibrary/lm_741/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm_741/npn_1.lib b/library/SubcircuitLibrary/lm_741/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/lm_741/pnp_1.lib b/library/SubcircuitLibrary/lm_741/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/library/SubcircuitLibrary/lm_741/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/scr/D.lib b/library/SubcircuitLibrary/scr/D.lib new file mode 100644 index 00000000..ef18bb50 --- /dev/null +++ b/library/SubcircuitLibrary/scr/D.lib @@ -0,0 +1,20 @@ +.MODEL D1N750 D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ Bv=8.1 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=880.5E-18 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/scr/PowerDiode.lib b/library/SubcircuitLibrary/scr/PowerDiode.lib new file mode 100644 index 00000000..a2f61dce --- /dev/null +++ b/library/SubcircuitLibrary/scr/PowerDiode.lib @@ -0,0 +1,20 @@ +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/scr/analysis b/library/SubcircuitLibrary/scr/analysis new file mode 100644 index 00000000..687c71ec --- /dev/null +++ b/library/SubcircuitLibrary/scr/analysis @@ -0,0 +1 @@ +.tran 0e-12 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/scr/scr-cache.lib b/library/SubcircuitLibrary/scr/scr-cache.lib new file mode 100644 index 00000000..0a685b80 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr-cache.lib @@ -0,0 +1,150 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# CCCS +# +DEF CCCS F 0 40 Y Y 1 F N +F0 "F" 0 150 50 H V C CNN +F1 "CCCS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R-RESCUE-scr +# +DEF R-RESCUE-scr R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R-RESCUE-scr" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# aswitch +# +DEF aswitch U 0 40 Y Y 1 F N +F0 "U" 450 300 60 H V C CNN +F1 "aswitch" 450 200 60 H V C CNN +F2 "" 450 100 60 H V C CNN +F3 "" 450 100 60 H V C CNN +DRAW +S 200 250 650 100 0 1 0 N +X ~ 2 0 150 200 R 50 50 1 1 O +X ~ 3 850 150 200 L 50 50 1 1 O +X ~ 1_IN 450 -100 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +# dc-RESCUE-scr +# +DEF dc-RESCUE-scr v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/scr/scr-rescue.lib b/library/SubcircuitLibrary/scr/scr-rescue.lib new file mode 100644 index 00000000..64237b7d --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr-rescue.lib @@ -0,0 +1,39 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# R-RESCUE-scr +# +DEF R-RESCUE-scr R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R-RESCUE-scr" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# dc-RESCUE-scr +# +DEF dc-RESCUE-scr v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/scr/scr.cir b/library/SubcircuitLibrary/scr/scr.cir new file mode 100644 index 00000000..4b279764 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr.cir @@ -0,0 +1,20 @@ +* /opt/eSim/src/SubcircuitLibrary/scr/scr.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:47:20 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 3 7 1 PORT +F2 3 9 2 3 100 +D1 5 2 D +C1 3 9 10u +F1 3 9 4 3 10 +v1 8 4 dc +v2 6 5 dc +U1 9 1 6 aswitch +R1 7 8 50 +R2 3 9 1 + +.end diff --git a/library/SubcircuitLibrary/scr/scr.cir.out b/library/SubcircuitLibrary/scr/scr.cir.out new file mode 100644 index 00000000..d600f25d --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr.cir.out @@ -0,0 +1,29 @@ +* /opt/esim/src/subcircuitlibrary/scr/scr.cir + +.include PowerDiode.lib +* u2 3 7 1 port +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +.tran 0e-12 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/scr/scr.pro b/library/SubcircuitLibrary/scr/scr.pro new file mode 100644 index 00000000..ca0df803 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr.pro @@ -0,0 +1,45 @@ +update=Wed Jul 31 19:51:09 2019 +last_client=kicad +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=scr-rescue +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Sources +LibName8=eSim_Subckt +LibName9=eSim_User +LibName10=power +LibName11=device +LibName12=transistors +LibName13=conn +LibName14=linear +LibName15=regul +LibName16=74xx +LibName17=cmos4000 +LibName18=adc-dac +LibName19=memory +LibName20=xilinx +LibName21=special +LibName22=microcontrollers +LibName23=dsp +LibName24=microchip +LibName25=analog_switches +LibName26=motorola +LibName27=texas +LibName28=intel +LibName29=audio +LibName30=interface +LibName31=digital-audio +LibName32=philips +LibName33=display +LibName34=cypress +LibName35=siliconi +LibName36=opto +LibName37=atmel +LibName38=contrib +LibName39=valves diff --git a/library/SubcircuitLibrary/scr/scr.sch b/library/SubcircuitLibrary/scr/scr.sch new file mode 100644 index 00000000..69244f56 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr.sch @@ -0,0 +1,242 @@ +EESchema Schematic File Version 2 +LIBS:scr-rescue +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:scr-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "21 aug 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3600 3250 3600 3150 +Connection ~ 5550 4950 +Wire Wire Line + 5800 3900 5800 3850 +Wire Wire Line + 5800 3850 6150 3850 +Wire Wire Line + 6150 3850 6150 4950 +Wire Wire Line + 6150 4950 3600 4950 +Connection ~ 4300 4950 +Wire Wire Line + 4300 4950 4300 4050 +Wire Wire Line + 4300 4050 3850 4050 +Wire Wire Line + 4700 5400 4700 5950 +Wire Wire Line + 4250 5950 4250 5500 +Connection ~ 4250 4950 +Wire Wire Line + 4250 4950 4250 5200 +Wire Wire Line + 5550 3600 5550 3450 +Wire Wire Line + 5550 4950 5550 4250 +Wire Wire Line + 3600 4950 3600 4400 +Wire Wire Line + 3600 2300 3600 2850 +Wire Wire Line + 3600 2300 3150 2300 +Wire Wire Line + 3600 4150 3600 4300 +Wire Wire Line + 5550 4150 5550 4000 +Wire Wire Line + 5550 2550 5550 2250 +Wire Wire Line + 4700 4950 4700 5100 +Connection ~ 4700 4950 +Wire Wire Line + 6650 2000 6650 5950 +Connection ~ 4700 5950 +Wire Wire Line + 3850 4650 3850 5950 +Wire Wire Line + 3850 5950 6650 5950 +Connection ~ 4250 5950 +Wire Wire Line + 5800 4500 5800 5950 +Connection ~ 5800 5950 +$Comp +L PORT U2 +U 3 1 53F4C93D +P 6650 2250 +F 0 "U2" H 6650 2200 30 0000 C CNN +F 1 "PORT" H 6650 2250 30 0000 C CNN +F 2 "" H 6650 2250 60 0001 C CNN +F 3 "" H 6650 2250 60 0001 C CNN + 3 6650 2250 + -1 0 0 1 +$EndComp +$Comp +L PORT U2 +U 2 1 53F4C934 +P 2900 2300 +F 0 "U2" H 2900 2250 30 0000 C CNN +F 1 "PORT" H 2900 2300 30 0000 C CNN +F 2 "" H 2900 2300 60 0001 C CNN +F 3 "" H 2900 2300 60 0001 C CNN + 2 2900 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 1 1 53F4C92A +P 6400 4950 +F 0 "U2" H 6400 4900 30 0000 C CNN +F 1 "PORT" H 6400 4950 30 0000 C CNN +F 2 "" H 6400 4950 60 0001 C CNN +F 3 "" H 6400 4950 60 0001 C CNN + 1 6400 4950 + -1 0 0 1 +$EndComp +$Comp +L CCCS F2 +U 1 1 53F4C735 +P 5750 4200 +F 0 "F2" H 5550 4300 50 0000 C CNN +F 1 "100" H 5550 4150 50 0000 C CNN +F 2 "" H 5750 4200 60 0001 C CNN +F 3 "" H 5750 4200 60 0001 C CNN + 1 5750 4200 + 0 1 1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 53F4C6D9 +P 5550 3800 +F 0 "D1" H 5550 3900 40 0000 C CNN +F 1 "D" H 5550 3700 40 0000 C CNN +F 2 "" H 5550 3800 60 0001 C CNN +F 3 "" H 5550 3800 60 0001 C CNN + 1 5550 3800 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 53F4C6C2 +P 4700 5250 +F 0 "C1" H 4750 5350 50 0000 L CNN +F 1 "10u" H 4750 5150 50 0000 L CNN +F 2 "" H 4700 5250 60 0001 C CNN +F 3 "" H 4700 5250 60 0001 C CNN + 1 4700 5250 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F1 +U 1 1 53F4C67F +P 3800 4350 +F 0 "F1" H 3600 4450 50 0000 C CNN +F 1 "10" H 3600 4300 50 0000 C CNN +F 2 "" H 3800 4350 60 0001 C CNN +F 3 "" H 3800 4350 60 0001 C CNN + 1 3800 4350 + 0 1 1 0 +$EndComp +$Comp +L dc-RESCUE-scr v1 +U 1 1 565DBF58 +P 3600 3700 +F 0 "v1" H 3400 3800 60 0000 C CNN +F 1 "dc" H 3400 3650 60 0000 C CNN +F 2 "R1" H 3300 3700 60 0000 C CNN +F 3 "" H 3600 3700 60 0000 C CNN + 1 3600 3700 + 1 0 0 -1 +$EndComp +$Comp +L dc-RESCUE-scr v2 +U 1 1 565DC066 +P 5550 3000 +F 0 "v2" H 5350 3100 60 0000 C CNN +F 1 "dc" H 5350 2950 60 0000 C CNN +F 2 "R1" H 5250 3000 60 0000 C CNN +F 3 "" H 5550 3000 60 0000 C CNN + 1 5550 3000 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U1 +U 1 1 565DC87E +P 6400 2100 +F 0 "U1" H 6850 2400 60 0000 C CNN +F 1 "aswitch" H 6850 2300 60 0000 C CNN +F 2 "" H 6850 2200 60 0000 C CNN +F 3 "" H 6850 2200 60 0000 C CNN + 1 6400 2100 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2000 6650 2000 +$Comp +L R-RESCUE-scr R1 +U 1 1 5666B019 +P 3550 2950 +F 0 "R1" H 3600 3080 50 0000 C CNN +F 1 "50" H 3600 3000 50 0000 C CNN +F 2 "" H 3600 2930 30 0000 C CNN +F 3 "" V 3600 3000 30 0000 C CNN + 1 3550 2950 + 0 1 1 0 +$EndComp +$Comp +L R-RESCUE-scr R2 +U 1 1 5666B17A +P 4200 5300 +F 0 "R2" H 4250 5430 50 0000 C CNN +F 1 "1" H 4250 5350 50 0000 C CNN +F 2 "" H 4250 5280 30 0000 C CNN +F 3 "" V 4250 5350 30 0000 C CNN + 1 4200 5300 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/scr/scr.sub b/library/SubcircuitLibrary/scr/scr.sub new file mode 100644 index 00000000..398c8921 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr.sub @@ -0,0 +1,23 @@ +* Subcircuit scr +.subckt scr 3 7 1 +* /opt/esim/src/subcircuitlibrary/scr/scr.cir +.include PowerDiode.lib +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +* Control Statements + +.ends scr diff --git a/library/SubcircuitLibrary/scr/scr_Previous_Values.xml b/library/SubcircuitLibrary/scr/scr_Previous_Values.xml new file mode 100644 index 00000000..8ff6e8d3 --- /dev/null +++ b/library/SubcircuitLibrary/scr/scr_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)" /><field3 name="Enter OFF Resistance (default=1.0e12)" /><field4 name="Enter ON Resistance (default=1.0)" /><field5 name="Enter Control ON value(default=1.0)" /></u1></model><devicemodel><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ps</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ua741/analysis b/library/SubcircuitLibrary/ua741/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/library/SubcircuitLibrary/ua741/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ua741/ua741.cir b/library/SubcircuitLibrary/ua741/ua741.cir new file mode 100644 index 00000000..de797429 --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/library/SubcircuitLibrary/ua741/ua741.cir.out b/library/SubcircuitLibrary/ua741/ua741.cir.out new file mode 100644 index 00000000..72e68514 --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +* u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ua741/ua741.pro b/library/SubcircuitLibrary/ua741/ua741.pro new file mode 100644 index 00000000..5dbb81a5 --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/library/SubcircuitLibrary/ua741/ua741.sch b/library/SubcircuitLibrary/ua741/ua741.sch new file mode 100644 index 00000000..7dfc5e1a --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ua741/ua741.sub b/library/SubcircuitLibrary/ua741/ua741.sub new file mode 100644 index 00000000..ad26c001 --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741.sub @@ -0,0 +1,12 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +* Control Statements + +.ends ua741
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ujt/D.lib b/library/SubcircuitLibrary/ujt/D.lib new file mode 100644 index 00000000..8a7fb4da --- /dev/null +++ b/library/SubcircuitLibrary/ujt/D.lib @@ -0,0 +1,2 @@ +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/ujt/analysis b/library/SubcircuitLibrary/ujt/analysis new file mode 100644 index 00000000..ffc57a6b --- /dev/null +++ b/library/SubcircuitLibrary/ujt/analysis @@ -0,0 +1 @@ +.tran 5e-03 100e-03 0e-03
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ujt/emitter.lib b/library/SubcircuitLibrary/ujt/emitter.lib new file mode 100644 index 00000000..3e78b1ee --- /dev/null +++ b/library/SubcircuitLibrary/ujt/emitter.lib @@ -0,0 +1,11 @@ +.model emitter D( ++ Vj=1 ++ Cjo=1.700E-12 ++ Rs=4.755E-01 ++ Is=21.3P ++ M=1.959E-01 ++ N=1.8 ++ Bv=1.000E+02 ++ tt=3.030E-09 ++ Ibv=1.000E-04 +) diff --git a/library/SubcircuitLibrary/ujt/plot_data_i.txt b/library/SubcircuitLibrary/ujt/plot_data_i.txt new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/library/SubcircuitLibrary/ujt/plot_data_i.txt diff --git a/library/SubcircuitLibrary/ujt/plot_data_v.txt b/library/SubcircuitLibrary/ujt/plot_data_v.txt new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/library/SubcircuitLibrary/ujt/plot_data_v.txt diff --git a/library/SubcircuitLibrary/ujt/ujt-cache.lib b/library/SubcircuitLibrary/ujt/ujt-cache.lib new file mode 100644 index 00000000..ff75f664 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt-cache.lib @@ -0,0 +1,137 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# CCVS +# +DEF CCVS H 0 40 Y Y 1 F N +F0 "H" 0 150 50 H V C CNN +F1 "CCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# NLDS +# +DEF NLDS BB 0 40 Y Y 1 F N +F0 "BB" 0 0 60 H V C CNN +F1 "NLDS" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 0 141 0 1 0 N +X 1 1 0 350 200 D 50 50 1 1 B +X 2 2 0 -350 200 U 50 50 1 1 B +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ujt/ujt.cir b/library/SubcircuitLibrary/ujt/ujt.cir new file mode 100644 index 00000000..e0e911d7 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt.cir @@ -0,0 +1,18 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/ujt/ujt.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 15 12:43:54 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R3 /0 /6 1000k +H1 /6 /0 /4 /5 1k +C1 /5 /7 35p +R1 /7 /2 38.15k +R2 /3 /5 2.518k +U1 /1 /2 /3 PORT +B1 /5 /7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6) +D1 /1 /4 eSim_Diode + +.end diff --git a/library/SubcircuitLibrary/ujt/ujt.cir.out b/library/SubcircuitLibrary/ujt/ujt.cir.out new file mode 100644 index 00000000..2045c539 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt.cir.out @@ -0,0 +1,22 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir + +.include emitter.lib +r3 /0 /6 1000k +* h1 +c1 /5 /7 35p +r1 /7 /2 38.15k +r2 /3 /5 2.518k +* u1 /1 /2 /3 port +b1 /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) +d1 /1 /4 emitter +Vh1 /4 /5 0 +h1 /6 /0 Vh1 1k +.tran 5e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ujt/ujt.pro b/library/SubcircuitLibrary/ujt/ujt.pro new file mode 100644 index 00000000..24c5e186 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt.pro @@ -0,0 +1,44 @@ +update=Tue Jun 11 16:36:40 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User +LibName3=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName4=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName5=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName6=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName7=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName8=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName9=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName10=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName11=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog diff --git a/library/SubcircuitLibrary/ujt/ujt.sch b/library/SubcircuitLibrary/ujt/ujt.sch new file mode 100644 index 00000000..a82bddf7 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt.sch @@ -0,0 +1,199 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:ujt-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R3 +U 1 1 5CF5F733 +P 6650 3400 +F 0 "R3" H 6700 3530 50 0000 C CNN +F 1 "1000k" H 6700 3450 50 0000 C CNN +F 2 "" H 6700 3380 30 0000 C CNN +F 3 "" V 6700 3450 30 0000 C CNN + 1 6650 3400 + 0 1 -1 0 +$EndComp +$Comp +L CCVS H1 +U 1 1 5CF5F77B +P 6150 3350 +F 0 "H1" H 6150 3500 50 0000 C CNN +F 1 "1k" H 5950 3300 50 0000 C CNN +F 2 "" H 6150 3350 60 0000 C CNN +F 3 "" H 6150 3350 60 0000 C CNN + 1 6150 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CF61B3A +P 5150 4700 +F 0 "C1" H 5175 4800 50 0000 L CNN +F 1 "35p" H 5175 4600 50 0000 L CNN +F 2 "" H 5188 4550 30 0000 C CNN +F 3 "" H 5150 4700 60 0000 C CNN + 1 5150 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CF6211F +P 4300 4850 +F 0 "R1" H 4350 4980 50 0000 C CNN +F 1 "38.15k" H 4350 4900 50 0000 C CNN +F 2 "" H 4350 4830 30 0000 C CNN +F 3 "" V 4350 4900 30 0000 C CNN + 1 4300 4850 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CF6218A +P 4550 3650 +F 0 "R2" H 4600 3780 50 0000 C CNN +F 1 "2.518k" H 4600 3700 50 0000 C CNN +F 2 "" H 4600 3630 30 0000 C CNN +F 3 "" V 4600 3700 30 0000 C CNN + 1 4550 3650 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF6830A +P 4250 4150 +F 0 "U1" H 4300 4250 30 0000 C CNN +F 1 "PORT" H 4250 4150 30 0000 C CNN +F 2 "" H 4250 4150 60 0000 C CNN +F 3 "" H 4250 4150 60 0000 C CNN + 2 4250 4150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF689AD +P 5950 2200 +F 0 "U1" H 6000 2300 30 0000 C CNN +F 1 "PORT" H 5950 2200 30 0000 C CNN +F 2 "" H 5950 2200 60 0000 C CNN +F 3 "" H 5950 2200 60 0000 C CNN + 1 5950 2200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF69586 +P 4600 3000 +F 0 "U1" H 4650 3100 30 0000 C CNN +F 1 "PORT" H 4600 3000 30 0000 C CNN +F 2 "" H 4600 3000 60 0000 C CNN +F 3 "" H 4600 3000 60 0000 C CNN + 3 4600 3000 + 0 1 1 0 +$EndComp +Text Label 5600 4100 0 60 ~ 0 +5 +Text Label 5950 3150 0 60 ~ 0 +4 +Text Label 5950 2600 0 60 ~ 0 +1 +Text Label 6450 3050 0 60 ~ 0 +6 +Text Label 6450 3650 0 60 ~ 0 +0 +$Comp +L NLDS B1 +U 1 1 5CFD2C88 +P 5950 4800 +F 0 "B1" H 5950 4800 60 0000 C CNN +F 1 "I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)" H 7050 4900 60 0000 C CNN +F 2 "" H 5950 4800 60 0000 C CNN +F 3 "" H 5950 4800 60 0000 C CNN + 1 5950 4800 + 1 0 0 -1 +$EndComp +Text Label 5350 5250 0 60 ~ 0 +7 +Text Label 4600 3450 0 60 ~ 0 +3 +Text Label 4250 4500 0 60 ~ 0 +2 +$Comp +L eSim_Diode D1 +U 1 1 5CFF8BB7 +P 5950 2850 +F 0 "D1" H 5950 2950 50 0000 C CNN +F 1 "eSim_Diode" H 5950 2750 50 0000 C CNN +F 2 "" H 5950 2850 60 0000 C CNN +F 3 "" H 5950 2850 60 0000 C CNN + 1 5950 2850 + 0 1 1 0 +$EndComp +Wire Wire Line + 6200 3050 6700 3050 +Wire Wire Line + 6700 3050 6700 3200 +Wire Wire Line + 6200 3650 6300 3650 +Wire Wire Line + 6300 3650 6700 3650 +Wire Wire Line + 5950 2450 5950 2700 +Wire Wire Line + 5950 3000 5950 3300 +Wire Wire Line + 5950 3400 5950 3850 +Wire Wire Line + 5950 3850 5950 4100 +Wire Wire Line + 5950 4100 5950 4450 +Wire Wire Line + 5150 4100 5150 4550 +Wire Wire Line + 4600 4100 5150 4100 +Wire Wire Line + 5150 4100 5950 4100 +Connection ~ 5950 4100 +Wire Wire Line + 5150 4850 5150 5250 +Wire Wire Line + 4250 5250 5150 5250 +Wire Wire Line + 5150 5250 5950 5250 +Wire Wire Line + 4250 5250 4250 4950 +Wire Wire Line + 4600 4100 4600 3850 +Connection ~ 5150 4100 +Wire Wire Line + 4250 4650 4250 4400 +Wire Wire Line + 4600 3550 4600 3250 +Wire Wire Line + 5950 5250 5950 5150 +Connection ~ 5150 5250 +Wire Wire Line + 6700 3650 6700 3500 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ujt/ujt.sub b/library/SubcircuitLibrary/ujt/ujt.sub new file mode 100644 index 00000000..2fb1db35 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt.sub @@ -0,0 +1,16 @@ +* Subcircuit ujt +.subckt ujt /1 /2 /3 +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir +.include emitter.lib +r3 /0 /6 1000k +* h1 +c1 /5 /7 35p +r1 /7 /2 38.15k +r2 /3 /5 2.518k +b1 /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) +d1 /1 /4 emitter +Vh1 /4 /5 0 +h1 /6 /0 Vh1 1k +* Control Statements + +.ends ujt
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ujt/ujt_Previous_Values.xml b/library/SubcircuitLibrary/ujt/ujt_Previous_Values.xml new file mode 100644 index 00000000..4468b395 --- /dev/null +++ b/library/SubcircuitLibrary/ujt/ujt_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">0</v1><ve1 name="Source type">0</ve1><i1 name="Source type">dc<field1 name="Value">0.000001m</field1></i1><v2 name="Source type">0</v2></source><model /><devicemodel><d1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Diode/emitter.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file |