summaryrefslogtreecommitdiff
path: root/library/SubcircuitLibrary/sn7445/sn7445.cir.out
diff options
context:
space:
mode:
Diffstat (limited to 'library/SubcircuitLibrary/sn7445/sn7445.cir.out')
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.cir.out180
1 files changed, 180 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.cir.out b/library/SubcircuitLibrary/sn7445/sn7445.cir.out
new file mode 100644
index 00000000..e53a66ee
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.cir.out
@@ -0,0 +1,180 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn7445\sn7445.cir
+
+* u34 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad1_ d_nand
+* u35 net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ d_nand
+* u36 net-_u18-pad3_ net-_u19-pad3_ net-_u1-pad3_ d_nand
+* u43 net-_u32-pad3_ net-_u33-pad3_ net-_u1-pad10_ d_nand
+* u37 net-_u23-pad3_ net-_u24-pad3_ net-_u1-pad4_ d_nand
+* u38 net-_u20-pad3_ net-_u25-pad3_ net-_u1-pad5_ d_nand
+* u39 net-_u21-pad3_ net-_u22-pad3_ net-_u1-pad6_ d_nand
+* u40 net-_u26-pad3_ net-_u30-pad3_ net-_u1-pad7_ d_nand
+* u41 net-_u31-pad3_ net-_u27-pad3_ net-_u1-pad8_ d_nand
+* u42 net-_u28-pad3_ net-_u29-pad3_ net-_u1-pad9_ d_nand
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and
+* u16 net-_u10-pad2_ net-_u14-pad2_ net-_u16-pad3_ d_and
+* u17 net-_u15-pad1_ net-_u15-pad2_ net-_u17-pad3_ d_and
+* u18 net-_u14-pad1_ net-_u11-pad2_ net-_u18-pad3_ d_and
+* u19 net-_u15-pad1_ net-_u15-pad2_ net-_u19-pad3_ d_and
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_and
+* u24 net-_u15-pad1_ net-_u15-pad2_ net-_u24-pad3_ d_and
+* u20 net-_u14-pad1_ net-_u14-pad2_ net-_u20-pad3_ d_and
+* u25 net-_u13-pad2_ net-_u15-pad2_ net-_u25-pad3_ d_and
+* u21 net-_u10-pad2_ net-_u14-pad2_ net-_u21-pad3_ d_and
+* u22 net-_u13-pad2_ net-_u15-pad2_ net-_u22-pad3_ d_and
+* u26 net-_u14-pad1_ net-_u11-pad2_ net-_u26-pad3_ d_and
+* u30 net-_u13-pad2_ net-_u15-pad2_ net-_u30-pad3_ d_and
+* u31 net-_u10-pad2_ net-_u11-pad2_ net-_u31-pad3_ d_and
+* u27 net-_u13-pad2_ net-_u15-pad2_ net-_u27-pad3_ d_and
+* u28 net-_u14-pad1_ net-_u14-pad2_ net-_u28-pad3_ d_and
+* u29 net-_u15-pad1_ net-_u12-pad2_ net-_u29-pad3_ d_and
+* u32 net-_u10-pad2_ net-_u14-pad2_ net-_u32-pad3_ d_and
+* u33 net-_u15-pad1_ net-_u12-pad2_ net-_u33-pad3_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_buffer
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_buffer
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_buffer
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer
+* u8 net-_u15-pad2_ net-_u12-pad1_ d_inverter
+* u5 net-_u1-pad11_ net-_u15-pad2_ d_inverter
+* u9 net-_u15-pad1_ net-_u13-pad1_ d_inverter
+* u4 net-_u1-pad12_ net-_u15-pad1_ d_inverter
+* u7 net-_u14-pad2_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u14-pad2_ d_inverter
+* u6 net-_u14-pad1_ net-_u10-pad1_ d_inverter
+* u2 net-_u1-pad14_ net-_u14-pad1_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u1-pad1_ u34
+a2 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u1-pad2_ u35
+a3 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u1-pad3_ u36
+a4 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u1-pad10_ u43
+a5 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u1-pad4_ u37
+a6 [net-_u20-pad3_ net-_u25-pad3_ ] net-_u1-pad5_ u38
+a7 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u1-pad6_ u39
+a8 [net-_u26-pad3_ net-_u30-pad3_ ] net-_u1-pad7_ u40
+a9 [net-_u31-pad3_ net-_u27-pad3_ ] net-_u1-pad8_ u41
+a10 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u1-pad9_ u42
+a11 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a13 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u16-pad3_ u16
+a14 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u17-pad3_ u17
+a15 [net-_u14-pad1_ net-_u11-pad2_ ] net-_u18-pad3_ u18
+a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u19-pad3_ u19
+a17 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a18 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u24-pad3_ u24
+a19 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u20-pad3_ u20
+a20 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u25-pad3_ u25
+a21 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u21-pad3_ u21
+a22 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u22-pad3_ u22
+a23 [net-_u14-pad1_ net-_u11-pad2_ ] net-_u26-pad3_ u26
+a24 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u30-pad3_ u30
+a25 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u31-pad3_ u31
+a26 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u27-pad3_ u27
+a27 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u28-pad3_ u28
+a28 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u29-pad3_ u29
+a29 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u32-pad3_ u32
+a30 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u33-pad3_ u33
+a31 net-_u10-pad1_ net-_u10-pad2_ u10
+a32 net-_u11-pad1_ net-_u11-pad2_ u11
+a33 net-_u13-pad1_ net-_u13-pad2_ u13
+a34 net-_u12-pad1_ net-_u12-pad2_ u12
+a35 net-_u15-pad2_ net-_u12-pad1_ u8
+a36 net-_u1-pad11_ net-_u15-pad2_ u5
+a37 net-_u15-pad1_ net-_u13-pad1_ u9
+a38 net-_u1-pad12_ net-_u15-pad1_ u4
+a39 net-_u14-pad2_ net-_u11-pad1_ u7
+a40 net-_u1-pad13_ net-_u14-pad2_ u3
+a41 net-_u14-pad1_ net-_u10-pad1_ u6
+a42 net-_u1-pad14_ net-_u14-pad1_ u2
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u13 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
generated by cgit (git 2.34.1) at 2024-12-19 17:46:06 +0000