diff options
Diffstat (limited to 'library/SubcircuitLibrary/full_sub/half_sub.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/full_sub/half_sub.cir.out | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/full_sub/half_sub.cir.out b/library/SubcircuitLibrary/full_sub/half_sub.cir.out new file mode 100644 index 00000000..91816956 --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/half_sub.cir.out @@ -0,0 +1,24 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |