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diff --git a/library/SubcircuitLibrary/SN74ALS520N/74520N.cir.out b/library/SubcircuitLibrary/SN74ALS520N/74520N.cir.out
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+* c:\users\pt710\esim-workspace\74520n\74520n.cir
+
+.include 7421.sub
+.include CD4077.sub
+x1 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x1-pad9_ net-_x1-pad10_ net-_x1-pad11_ net-_x1-pad12_ CD4077
+x2 net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_x2-pad9_ net-_x2-pad10_ net-_x2-pad11_ net-_x2-pad12_ CD4077
+x3 net-_x1-pad9_ net-_x1-pad10_ net-_x1-pad11_ net-_x1-pad12_ net-_u3-pad1_ net-_x2-pad12_ net-_x2-pad11_ net-_x2-pad10_ net-_x2-pad9_ net-_u3-pad2_ 7421
+* u1 net-_u1-pad1_ net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ adc_bridge_8
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8
+r1 out gnd 10k
+* u5 out plot_v1
+v1 net-_u1-pad1_ gnd dc 5
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_and
+v2 net-_u1-pad3_ gnd dc 5
+v3 net-_u1-pad5_ gnd dc 5
+v4 net-_u1-pad8_ gnd dc 5
+v5 net-_u2-pad1_ gnd dc 5
+v6 net-_u2-pad2_ gnd dc 5
+v7 net-_u2-pad3_ gnd dc 5
+v8 net-_u2-pad4_ gnd dc 5
+v9 net-_u2-pad5_ gnd dc 5
+v10 net-_u2-pad6_ gnd dc 5
+v11 net-_u2-pad7_ gnd dc 5
+v12 net-_u2-pad8_ gnd dc 5
+* u4 net-_u3-pad3_ out dac_bridge_1
+a1 [net-_u1-pad1_ net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad5_ net-_u1-pad8_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ ] u1
+a2 [net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2
+a3 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
+a4 [net-_u3-pad3_ ] [out ] u4
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 1e-06 10e-03 1e-06
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out)
+.endc
+.end