diff options
Diffstat (limited to 'library/SubcircuitLibrary/SN54180/SN54180.sub')
| -rw-r--r-- | library/SubcircuitLibrary/SN54180/SN54180.sub | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN54180/SN54180.sub b/library/SubcircuitLibrary/SN54180/SN54180.sub new file mode 100644 index 00000000..34693793 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.sub @@ -0,0 +1,62 @@ +* Subcircuit SN54180 +.subckt SN54180 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54180\sn54180.cir +* u2 net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_xnor +* u3 net-_u1-pad10_ net-_u1-pad11_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor +* u9 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor +a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a8 net-_u10-pad1_ net-_u11-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13 +a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u2 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends SN54180
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