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-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT-cache.lib158
-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.cir58
-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.cir.out71
-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.pro73
-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.sch852
-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.sub65
-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/NJF.lib4
-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/LM7905_SUB/analysis1
11 files changed, 1291 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT-cache.lib b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT-cache.lib
new file mode 100644
index 00000000..c28cbe9d
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT-cache.lib
@@ -0,0 +1,158 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NJF
+#
+DEF eSim_NJF J 0 0 Y N 1 F N
+F0 "J" -100 50 50 H V R CNN
+F1 "eSim_NJF" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS jfet_n
+DRAW
+C 50 0 111 0 1 10 N
+P 3 0 1 10 10 75 10 -75 10 -75 N
+P 3 0 1 0 100 -100 100 -50 10 -50 N
+P 3 0 1 0 100 100 100 55 10 55 N
+P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 210 R 50 50 1 1 P
+X S 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.cir b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.cir
new file mode 100644
index 00000000..49c0467c
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.cir
@@ -0,0 +1,58 @@
+* C:\FOSSEE2\eSim\library\SubcircuitLibrary\LM7905-PORT\LM7905-PORT.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/28/24 11:00:08
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+J1 Net-_J1-Pad1_ Net-_J1-Pad1_ Net-_J1-Pad3_ jfet_n
+U2 Net-_J1-Pad3_ Net-_Q14-Pad1_ zener
+U3 Net-_Q1-Pad3_ Net-_Q14-Pad1_ zener
+Q1 Net-_J1-Pad1_ Net-_J1-Pad3_ Net-_Q1-Pad3_ eSim_PNP
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad1_ Net-_Q3-Pad3_ eSim_NPN
+R2 Net-_Q14-Pad1_ Net-_Q3-Pad1_ 1.4k
+R3 Net-_Q3-Pad3_ Net-_Q9-Pad2_ 7k
+R4 Net-_Q9-Pad2_ Net-_Q4-Pad3_ 15k
+Q4 Net-_Q2-Pad2_ Net-_Q1-Pad3_ Net-_Q4-Pad3_ eSim_PNP
+Q2 Net-_Q1-Pad3_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN
+Q5 Net-_Q2-Pad2_ Net-_Q2-Pad2_ Net-_Q5-Pad3_ eSim_NPN
+R1 Net-_Q2-Pad3_ Net-_J1-Pad1_ 750
+R5 Net-_Q5-Pad3_ Net-_J1-Pad1_ 1k
+Q6 Net-_Q10-Pad2_ Net-_Q2-Pad2_ Net-_Q6-Pad3_ eSim_NPN
+R6 Net-_Q6-Pad3_ Net-_J1-Pad1_ 6k
+R7 Net-_Q7-Pad1_ Net-_J1-Pad1_ 20k
+Q8 Net-_C1-Pad1_ Net-_Q7-Pad1_ Net-_Q10-Pad1_ eSim_NPN
+Q7 Net-_Q7-Pad1_ Net-_Q3-Pad1_ Net-_Q14-Pad1_ eSim_PNP
+Q9 Net-_Q14-Pad1_ Net-_Q9-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_PNP
+Q11 Net-_Q10-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_NPN
+R8 Net-_Q11-Pad2_ Net-_Q10-Pad1_ 20k
+R9 Net-_Q10-Pad1_ Net-_C1-Pad2_ 20k
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 20p
+Q13 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_J1-Pad1_ eSim_NPN
+Q14 Net-_Q14-Pad1_ Net-_Q14-Pad2_ Net-_Q12-Pad3_ eSim_NPN
+Q12 Net-_C1-Pad1_ Net-_Q10-Pad2_ Net-_Q12-Pad3_ eSim_PNP
+Q16 Net-_Q15-Pad3_ Net-_C2-Pad2_ Net-_J1-Pad1_ eSim_NPN
+Q15 Net-_C1-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN
+R10 Net-_Q15-Pad2_ Net-_Q15-Pad3_ 3k
+C2 Net-_C1-Pad1_ Net-_C2-Pad2_ 10p
+R11 Net-_C2-Pad2_ Net-_Q18-Pad1_ 5k
+R12 Net-_Q14-Pad1_ Net-_Q17-Pad1_ 4k
+Q17 Net-_Q17-Pad1_ Net-_C1-Pad1_ Net-_Q15-Pad2_ eSim_NPN
+R13 Net-_Q15-Pad2_ Net-_R13-Pad2_ 10k
+R14 Net-_R13-Pad2_ Net-_Q18-Pad1_ 600
+Q18 Net-_Q18-Pad1_ Net-_Q18-Pad2_ Net-_Q18-Pad3_ eSim_NPN
+R15 Net-_R13-Pad2_ Net-_Q18-Pad2_ 15k
+Q19 Net-_Q19-Pad1_ Net-_Q15-Pad2_ Net-_Q19-Pad3_ eSim_NPN
+Q20 Net-_Q19-Pad1_ Net-_Q19-Pad3_ Net-_Q20-Pad3_ eSim_NPN
+R16 Net-_Q19-Pad3_ Net-_Q20-Pad3_ 2k
+R18 Net-_Q14-Pad2_ Net-_Q19-Pad1_ 10k
+R17 Net-_Q14-Pad1_ Net-_Q14-Pad2_ 5k
+R20 Net-_R20-Pad1_ Net-_Q18-Pad3_ 20k
+R19 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 150
+U4 Net-_R20-Pad1_ Net-_Q19-Pad1_ zener
+R21 Net-_Q20-Pad3_ Net-_J1-Pad1_ 1.07k
+U1 Net-_Q14-Pad1_ Net-_J1-Pad1_ Net-_Q19-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.cir.out b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.cir.out
new file mode 100644
index 00000000..6a227891
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.cir.out
@@ -0,0 +1,71 @@
+* c:\fossee2\esim\library\subcircuitlibrary\lm7905-port\lm7905-port.cir
+
+.include NPN.lib
+.include NJF.lib
+.include PNP.lib
+j1 net-_j1-pad1_ net-_j1-pad1_ net-_j1-pad3_ J2N3819
+* u2 net-_j1-pad3_ net-_q14-pad1_ zener
+* u3 net-_q1-pad3_ net-_q14-pad1_ zener
+q1 net-_j1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2907A
+q3 net-_q3-pad1_ net-_q3-pad1_ net-_q3-pad3_ Q2N2222
+r2 net-_q14-pad1_ net-_q3-pad1_ 1.4k
+r3 net-_q3-pad3_ net-_q9-pad2_ 7k
+r4 net-_q9-pad2_ net-_q4-pad3_ 15k
+q4 net-_q2-pad2_ net-_q1-pad3_ net-_q4-pad3_ Q2N2907A
+q2 net-_q1-pad3_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q5 net-_q2-pad2_ net-_q2-pad2_ net-_q5-pad3_ Q2N2222
+r1 net-_q2-pad3_ net-_j1-pad1_ 750
+r5 net-_q5-pad3_ net-_j1-pad1_ 1k
+q6 net-_q10-pad2_ net-_q2-pad2_ net-_q6-pad3_ Q2N2222
+r6 net-_q6-pad3_ net-_j1-pad1_ 6k
+r7 net-_q7-pad1_ net-_j1-pad1_ 20k
+q8 net-_c1-pad1_ net-_q7-pad1_ net-_q10-pad1_ Q2N2222
+q7 net-_q7-pad1_ net-_q3-pad1_ net-_q14-pad1_ Q2N2907A
+q9 net-_q14-pad1_ net-_q9-pad2_ net-_q10-pad3_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A
+q11 net-_q10-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2222
+r8 net-_q11-pad2_ net-_q10-pad1_ 20k
+r9 net-_q10-pad1_ net-_c1-pad2_ 20k
+c1 net-_c1-pad1_ net-_c1-pad2_ 20p
+q13 net-_c1-pad1_ net-_c1-pad2_ net-_j1-pad1_ Q2N2222
+q14 net-_q14-pad1_ net-_q14-pad2_ net-_q12-pad3_ Q2N2222
+q12 net-_c1-pad1_ net-_q10-pad2_ net-_q12-pad3_ Q2N2907A
+q16 net-_q15-pad3_ net-_c2-pad2_ net-_j1-pad1_ Q2N2222
+q15 net-_c1-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222
+r10 net-_q15-pad2_ net-_q15-pad3_ 3k
+c2 net-_c1-pad1_ net-_c2-pad2_ 10p
+r11 net-_c2-pad2_ net-_q18-pad1_ 5k
+r12 net-_q14-pad1_ net-_q17-pad1_ 4k
+q17 net-_q17-pad1_ net-_c1-pad1_ net-_q15-pad2_ Q2N2222
+r13 net-_q15-pad2_ net-_r13-pad2_ 10k
+r14 net-_r13-pad2_ net-_q18-pad1_ 600
+q18 net-_q18-pad1_ net-_q18-pad2_ net-_q18-pad3_ Q2N2222
+r15 net-_r13-pad2_ net-_q18-pad2_ 15k
+q19 net-_q19-pad1_ net-_q15-pad2_ net-_q19-pad3_ Q2N2222
+q20 net-_q19-pad1_ net-_q19-pad3_ net-_q20-pad3_ Q2N2222
+r16 net-_q19-pad3_ net-_q20-pad3_ 2k
+r18 net-_q14-pad2_ net-_q19-pad1_ 10k
+r17 net-_q14-pad1_ net-_q14-pad2_ 5k
+r20 net-_r20-pad1_ net-_q18-pad3_ 20k
+r19 net-_q18-pad3_ net-_q20-pad3_ 150
+* u4 net-_r20-pad1_ net-_q19-pad1_ zener
+r21 net-_q20-pad3_ net-_j1-pad1_ 1.07k
+* u1 net-_q14-pad1_ net-_j1-pad1_ net-_q19-pad1_ port
+a1 net-_j1-pad3_ net-_q14-pad1_ u2
+a2 net-_q1-pad3_ net-_q14-pad1_ u3
+a3 net-_r20-pad1_ net-_q19-pad1_ u4
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u4 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.pro b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.sch b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.sch
new file mode 100644
index 00000000..d92d78d0
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.sch
@@ -0,0 +1,852 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:LM7905-PORT-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L jfet_n J1
+U 1 1 66506AB4
+P 1950 4400
+F 0 "J1" H 1850 4450 50 0000 R CNN
+F 1 "jfet_n" H 1900 4550 50 0000 R CNN
+F 2 "" H 2150 4500 29 0000 C CNN
+F 3 "" H 1950 4400 60 0000 C CNN
+ 1 1950 4400
+ -1 0 0 1
+$EndComp
+$Comp
+L zener U2
+U 1 1 66506AB5
+P 1850 1450
+F 0 "U2" H 1800 1350 60 0000 C CNN
+F 1 "zener" H 1850 1550 60 0000 C CNN
+F 2 "" H 1900 1450 60 0000 C CNN
+F 3 "" H 1900 1450 60 0000 C CNN
+ 1 1850 1450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L zener U3
+U 1 1 66506AB6
+P 2400 1450
+F 0 "U3" H 2350 1350 60 0000 C CNN
+F 1 "zener" H 2400 1550 60 0000 C CNN
+F 2 "" H 2450 1450 60 0000 C CNN
+F 3 "" H 2450 1450 60 0000 C CNN
+ 1 2400 1450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_PNP Q1
+U 1 1 66506AB7
+P 2050 3400
+F 0 "Q1" H 1950 3450 50 0000 R CNN
+F 1 "eSim_PNP" H 2000 3550 50 0000 R CNN
+F 2 "" H 2250 3500 29 0000 C CNN
+F 3 "" H 2050 3400 60 0000 C CNN
+ 1 2050 3400
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 66506AB8
+P 3000 1900
+F 0 "Q3" H 2900 1950 50 0000 R CNN
+F 1 "eSim_NPN" H 2950 2050 50 0000 R CNN
+F 2 "" H 3200 2000 29 0000 C CNN
+F 3 "" H 3000 1900 60 0000 C CNN
+ 1 3000 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 66506AB9
+P 3050 1050
+F 0 "R2" H 3100 1180 50 0000 C CNN
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+ 0 1 1 0
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+ 1 7800 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R13
+U 1 1 66506AD6
+P 7850 4200
+F 0 "R13" H 7900 4330 50 0000 C CNN
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+ 0 1 1 0
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+$Comp
+L resistor R14
+U 1 1 66506AD7
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+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 1850 1650 1850 4200
+Connection ~ 1850 3400
+Wire Wire Line
+ 1850 1150 1850 750
+Wire Wire Line
+ 1850 750 9650 750
+Wire Wire Line
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+Wire Wire Line
+ 3100 750 3100 950
+Connection ~ 2400 750
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 3100 2650 3100 2800
+Wire Wire Line
+ 3100 3100 3100 3250
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 3100 6100 3100 5500
+Connection ~ 2400 6100
+Wire Wire Line
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+Connection ~ 2150 6100
+Connection ~ 2150 4400
+Wire Wire Line
+ 2300 3450 2800 3450
+Connection ~ 2400 3450
+Wire Wire Line
+ 2150 3200 2300 3200
+Wire Wire Line
+ 2300 3200 2300 3450
+Wire Wire Line
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+Connection ~ 3100 750
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 2700 4850 2700 4450
+Wire Wire Line
+ 2700 4450 3300 4450
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2800 4450
+Wire Wire Line
+ 3100 4100 2800 4100
+Connection ~ 3100 4100
+Wire Wire Line
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+Connection ~ 3100 6100
+Wire Wire Line
+ 3950 1700 3950 5250
+Wire Wire Line
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+Connection ~ 3600 6100
+Wire Wire Line
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+Connection ~ 3950 4850
+Wire Wire Line
+ 4550 2950 4650 2950
+Wire Wire Line
+ 4650 2950 4650 3050
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 3950 750
+Wire Wire Line
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+Connection ~ 3950 6100
+Wire Wire Line
+ 4950 5350 5050 5350
+Wire Wire Line
+ 5350 5350 5500 5350
+Wire Wire Line
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+Connection ~ 3100 2750
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4550 750
+Wire Wire Line
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+Connection ~ 4650 6100
+Wire Wire Line
+ 5800 5350 5950 5350
+Connection ~ 5900 5350
+Wire Wire Line
+ 4350 5050 5450 5050
+Connection ~ 4650 5050
+Wire Wire Line
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+Connection ~ 5450 5350
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 7150 5350
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 6250 4950
+Wire Wire Line
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+Connection ~ 6250 4650
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 6600 3700 6600 3550
+Wire Wire Line
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+Connection ~ 6250 3550
+Connection ~ 6600 3550
+Wire Wire Line
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+Wire Wire Line
+ 7150 4500 6600 4500
+Connection ~ 6600 4500
+Wire Wire Line
+ 7150 4100 7150 3900
+Wire Wire Line
+ 6900 3900 8000 3900
+Wire Wire Line
+ 7900 750 7900 1200
+Connection ~ 6250 750
+$Comp
+L eSim_NPN Q18
+U 1 1 66506AD8
+P 8400 5250
+F 0 "Q18" H 8300 5300 50 0000 R CNN
+F 1 "eSim_NPN" H 8350 5400 50 0000 R CNN
+F 2 "" H 8600 5350 29 0000 C CNN
+F 3 "" H 8400 5250 60 0000 C CNN
+ 1 8400 5250
+ 0 -1 1 0
+$EndComp
+$Comp
+L resistor R15
+U 1 1 66506AD9
+P 8350 4650
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+ 1 8350 4650
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q19
+U 1 1 66506ADA
+P 8500 4100
+F 0 "Q19" H 8400 4150 50 0000 R CNN
+F 1 "eSim_NPN" H 8450 4250 50 0000 R CNN
+F 2 "" H 8700 4200 29 0000 C CNN
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+ 1 8500 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q20
+U 1 1 66506ADB
+P 9150 4300
+F 0 "Q20" H 9050 4350 50 0000 R CNN
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+F 2 "" H 9350 4400 29 0000 C CNN
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+ 1 9150 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R16
+U 1 1 66506ADC
+P 8750 4550
+F 0 "R16" H 8800 4680 50 0000 C CNN
+F 1 "2k" H 8800 4500 50 0000 C CNN
+F 2 "" H 8800 4530 30 0000 C CNN
+F 3 "" V 8800 4600 30 0000 C CNN
+ 1 8750 4550
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R18
+U 1 1 66506ADD
+P 9200 3150
+F 0 "R18" H 9250 3280 50 0000 C CNN
+F 1 "10k" H 9250 3100 50 0000 C CNN
+F 2 "" H 9250 3130 30 0000 C CNN
+F 3 "" V 9250 3200 30 0000 C CNN
+ 1 9200 3150
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R17
+U 1 1 66506ADE
+P 9200 1400
+F 0 "R17" H 9250 1530 50 0000 C CNN
+F 1 "5k" H 9250 1350 50 0000 C CNN
+F 2 "" H 9250 1380 30 0000 C CNN
+F 3 "" V 9250 1450 30 0000 C CNN
+ 1 9200 1400
+ 0 1 1 0
+$EndComp
+Connection ~ 7900 5350
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 7900 4500
+Wire Wire Line
+ 8300 4100 8000 4100
+Wire Wire Line
+ 8000 4100 8000 3900
+Connection ~ 7900 3900
+Connection ~ 7150 3900
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 8800 4300
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 9250 3900
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 7900 750
+Wire Wire Line
+ 6550 2750 9250 2750
+Connection ~ 9250 2750
+Wire Wire Line
+ 8800 4750 8800 4950
+Wire Wire Line
+ 8800 4950 9600 4950
+Wire Wire Line
+ 9250 4950 9250 4500
+$Comp
+L resistor R20
+U 1 1 66506ADF
+P 9850 4850
+F 0 "R20" H 9900 4980 50 0000 C CNN
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+F 3 "" V 9900 4900 30 0000 C CNN
+ 1 9850 4850
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R19
+U 1 1 66506AE0
+P 9200 5400
+F 0 "R19" H 9250 5530 50 0000 C CNN
+F 1 "150" H 9250 5350 50 0000 C CNN
+F 2 "" H 9250 5380 30 0000 C CNN
+F 3 "" V 9250 5450 30 0000 C CNN
+ 1 9200 5400
+ 1 0 0 -1
+$EndComp
+$Comp
+L zener U4
+U 1 1 66506AE1
+P 9900 4400
+F 0 "U4" H 9850 4300 60 0000 C CNN
+F 1 "zener" H 9900 4500 60 0000 C CNN
+F 2 "" H 9950 4400 60 0000 C CNN
+F 3 "" H 9950 4400 60 0000 C CNN
+ 1 9900 4400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R21
+U 1 1 66506AE2
+P 9850 5700
+F 0 "R21" H 9900 5830 50 0000 C CNN
+F 1 "1.07k" H 9900 5650 50 0000 C CNN
+F 2 "" H 9900 5680 30 0000 C CNN
+F 3 "" V 9900 5750 30 0000 C CNN
+ 1 9850 5700
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 8600 5350 9100 5350
+Wire Wire Line
+ 9900 5600 9600 5600
+Wire Wire Line
+ 9600 5600 9600 4950
+Connection ~ 9250 4950
+Wire Wire Line
+ 9900 6100 9900 5900
+Connection ~ 6600 6100
+Wire Wire Line
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+Connection ~ 9600 5350
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 8950 5350
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 3100 1500
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 5450 3900 5450 3250
+Connection ~ 5450 3250
+Connection ~ 9250 750
+Connection ~ 1850 6100
+Connection ~ 9900 3900
+$Comp
+L PORT U1
+U 3 1 66506EB6
+P 10500 3900
+F 0 "U1" H 10550 4000 30 0000 C CNN
+F 1 "PORT" H 10500 3900 30 0000 C CNN
+F 2 "" H 10500 3900 60 0000 C CNN
+F 3 "" H 10500 3900 60 0000 C CNN
+ 3 10500 3900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 66559197
+P 1850 6500
+F 0 "U1" H 1900 6600 30 0000 C CNN
+F 1 "PORT" H 1850 6500 30 0000 C CNN
+F 2 "" H 1850 6500 60 0000 C CNN
+F 3 "" H 1850 6500 60 0000 C CNN
+ 2 1850 6500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6655A4E3
+P 9650 1000
+F 0 "U1" H 9700 1100 30 0000 C CNN
+F 1 "PORT" H 9650 1000 30 0000 C CNN
+F 2 "" H 9650 1000 60 0000 C CNN
+F 3 "" H 9650 1000 60 0000 C CNN
+ 1 9650 1000
+ 0 -1 -1 0
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.sub b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.sub
new file mode 100644
index 00000000..0aa65e24
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT.sub
@@ -0,0 +1,65 @@
+* Subcircuit LM7905-PORT
+.subckt LM7905-PORT net-_q14-pad1_ net-_j1-pad1_ net-_q19-pad1_
+* c:\fossee2\esim\library\subcircuitlibrary\lm7905-port\lm7905-port.cir
+.include NPN.lib
+.include NJF.lib
+.include PNP.lib
+j1 net-_j1-pad1_ net-_j1-pad1_ net-_j1-pad3_ J2N3819
+* u2 net-_j1-pad3_ net-_q14-pad1_ zener
+* u3 net-_q1-pad3_ net-_q14-pad1_ zener
+q1 net-_j1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2907A
+q3 net-_q3-pad1_ net-_q3-pad1_ net-_q3-pad3_ Q2N2222
+r2 net-_q14-pad1_ net-_q3-pad1_ 1.4k
+r3 net-_q3-pad3_ net-_q9-pad2_ 7k
+r4 net-_q9-pad2_ net-_q4-pad3_ 15k
+q4 net-_q2-pad2_ net-_q1-pad3_ net-_q4-pad3_ Q2N2907A
+q2 net-_q1-pad3_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q5 net-_q2-pad2_ net-_q2-pad2_ net-_q5-pad3_ Q2N2222
+r1 net-_q2-pad3_ net-_j1-pad1_ 750
+r5 net-_q5-pad3_ net-_j1-pad1_ 1k
+q6 net-_q10-pad2_ net-_q2-pad2_ net-_q6-pad3_ Q2N2222
+r6 net-_q6-pad3_ net-_j1-pad1_ 6k
+r7 net-_q7-pad1_ net-_j1-pad1_ 20k
+q8 net-_c1-pad1_ net-_q7-pad1_ net-_q10-pad1_ Q2N2222
+q7 net-_q7-pad1_ net-_q3-pad1_ net-_q14-pad1_ Q2N2907A
+q9 net-_q14-pad1_ net-_q9-pad2_ net-_q10-pad3_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A
+q11 net-_q10-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2222
+r8 net-_q11-pad2_ net-_q10-pad1_ 20k
+r9 net-_q10-pad1_ net-_c1-pad2_ 20k
+c1 net-_c1-pad1_ net-_c1-pad2_ 20p
+q13 net-_c1-pad1_ net-_c1-pad2_ net-_j1-pad1_ Q2N2222
+q14 net-_q14-pad1_ net-_q14-pad2_ net-_q12-pad3_ Q2N2222
+q12 net-_c1-pad1_ net-_q10-pad2_ net-_q12-pad3_ Q2N2907A
+q16 net-_q15-pad3_ net-_c2-pad2_ net-_j1-pad1_ Q2N2222
+q15 net-_c1-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222
+r10 net-_q15-pad2_ net-_q15-pad3_ 3k
+c2 net-_c1-pad1_ net-_c2-pad2_ 10p
+r11 net-_c2-pad2_ net-_q18-pad1_ 5k
+r12 net-_q14-pad1_ net-_q17-pad1_ 4k
+q17 net-_q17-pad1_ net-_c1-pad1_ net-_q15-pad2_ Q2N2222
+r13 net-_q15-pad2_ net-_r13-pad2_ 10k
+r14 net-_r13-pad2_ net-_q18-pad1_ 600
+q18 net-_q18-pad1_ net-_q18-pad2_ net-_q18-pad3_ Q2N2222
+r15 net-_r13-pad2_ net-_q18-pad2_ 15k
+q19 net-_q19-pad1_ net-_q15-pad2_ net-_q19-pad3_ Q2N2222
+q20 net-_q19-pad1_ net-_q19-pad3_ net-_q20-pad3_ Q2N2222
+r16 net-_q19-pad3_ net-_q20-pad3_ 2k
+r18 net-_q14-pad2_ net-_q19-pad1_ 10k
+r17 net-_q14-pad1_ net-_q14-pad2_ 5k
+r20 net-_r20-pad1_ net-_q18-pad3_ 20k
+r19 net-_q18-pad3_ net-_q20-pad3_ 150
+* u4 net-_r20-pad1_ net-_q19-pad1_ zener
+r21 net-_q20-pad3_ net-_j1-pad1_ 1.07k
+a1 net-_j1-pad3_ net-_q14-pad1_ u2
+a2 net-_q1-pad3_ net-_q14-pad1_ u3
+a3 net-_r20-pad1_ net-_q19-pad1_ u4
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u4 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Control Statements
+
+.ends LM7905-PORT \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT_Previous_Values.xml b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT_Previous_Values.xml
new file mode 100644
index 00000000..dcde328e
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/LM7905-PORT_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u3 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u3><u4 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)">6.2</field11><field12 name="Enter Breakdown Current (default=2.0e-2)" /><field13 name="Enter Saturation Current (default=1.0e-12)" /><field14 name="Enter Forward Emission Coefficient (default=1.0)" /><field15 name="Enter Switch for Limiting (default=FALSE)" /></u4><u2 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><j1><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q1><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q3><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q4><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q2><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q5><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q8><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q7><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q9><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q10><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><q11><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q13><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q14><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q12><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12><q16><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q15><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q17><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q18><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q19><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q20><field>C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM7905_SUB/NJF.lib b/library/SubcircuitLibrary/LM7905_SUB/NJF.lib
new file mode 100644
index 00000000..dbb2cbae
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/NJF.lib
@@ -0,0 +1,4 @@
+.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
++ Af=1)
diff --git a/library/SubcircuitLibrary/LM7905_SUB/NPN.lib b/library/SubcircuitLibrary/LM7905_SUB/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/LM7905_SUB/PNP.lib b/library/SubcircuitLibrary/LM7905_SUB/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/LM7905_SUB/analysis b/library/SubcircuitLibrary/LM7905_SUB/analysis
new file mode 100644
index 00000000..660a46cc
--- /dev/null
+++ b/library/SubcircuitLibrary/LM7905_SUB/analysis
@@ -0,0 +1 @@
+.tran 10e-03 100e-03 0e-03 \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-21 12:12:54 +0000